drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #ifdef CONFIG_OMAP54XX
  38 #include <asm/arch/mux_dra7xx.h>
  39 #include <asm/arch/dra7xx_iodelay.h>
  40 #endif
  41 #if !defined(CONFIG_SOC_KEYSTONE)
  42 #include <asm/gpio.h>
  43 #include <asm/arch/sys_proto.h>
  44 #endif
  45 #ifdef CONFIG_MMC_OMAP36XX_PINS
  46 #include <asm/arch/mux.h>
  47 #endif
  48 #include <dm.h>
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  53 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  54         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  55 #define OMAP_HSMMC_USE_GPIO
  56 #else
  57 #undef OMAP_HSMMC_USE_GPIO
  58 #endif
  59
  60 /* common definitions for all OMAPs */
  61 #define SYSCTL_SRC      (1 << 25)
  62 #define SYSCTL_SRD      (1 << 26)
  63
  64 #ifdef CONFIG_IODELAY_RECALIBRATION
  65 struct omap_hsmmc_pinctrl_state {
  66         struct pad_conf_entry *padconf;
  67         int npads;
  68         struct iodelay_cfg_entry *iodelay;
  69         int niodelays;
  70 };
  71 #endif
  72
  73 struct omap_hsmmc_data {
  74         struct hsmmc *base_addr;
  75 #if !CONFIG_IS_ENABLED(DM_MMC)
  76         struct mmc_config cfg;
  77 #endif
  78         uint bus_width;
  79         uint clock;
  80 #ifdef OMAP_HSMMC_USE_GPIO
  81 #if CONFIG_IS_ENABLED(DM_MMC)
  82         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  83         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  84         bool cd_inverted;
  85 #else
  86         int cd_gpio;
  87         int wp_gpio;
  88 #endif
  89 #endif
  90 #if CONFIG_IS_ENABLED(DM_MMC)
  91         uint iov;
  92         enum bus_mode mode;
  93 #endif
  94         u8 controller_flags;
  95 #ifndef CONFIG_OMAP34XX
  96         struct omap_hsmmc_adma_desc *adma_desc_table;
  97         uint desc_slot;
  98 #endif
  99 #ifdef CONFIG_IODELAY_RECALIBRATION
 100         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 101         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 102         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 103         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 104         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 105         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 106         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 107         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 109 #endif
 110 };
 111
 112 struct omap_mmc_of_data {
 113         u8 controller_flags;
 114 };
 115
 116 #ifndef CONFIG_OMAP34XX
 117 struct omap_hsmmc_adma_desc {
 118         u8 attr;
 119         u8 reserved;
 120         u16 len;
 121         u32 addr;
 122 };
 123
 124 #define ADMA_MAX_LEN    63488
 125
 126 /* Decriptor table defines */
 127 #define ADMA_DESC_ATTR_VALID            BIT(0)
 128 #define ADMA_DESC_ATTR_END              BIT(1)
 129 #define ADMA_DESC_ATTR_INT              BIT(2)
 130 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 131 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 132
 133 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 134 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 135 #endif
 136
 137 /* If we fail after 1 second wait, something is really bad */
 138 #define MAX_RETRY_MS    1000
 139 #define MMC_TIMEOUT_MS  20
 140
 141 /* DMA transfers can take a long time if a lot a data is transferred.
 142  * The timeout must take in account the amount of data. Let's assume
 143  * that the time will never exceed 333 ms per MB (in other word we assume
 144  * that the bandwidth is always above 3MB/s).
 145  */
 146 #define DMA_TIMEOUT_PER_MB      333
 147 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 148 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 149 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 150 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 151
 152 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 153 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 154                         unsigned int siz);
 155 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 156 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 157 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 158
 159 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 160 {
 161 #if CONFIG_IS_ENABLED(DM_MMC)
 162         return dev_get_priv(mmc->dev);
 163 #else
 164         return (struct omap_hsmmc_data *)mmc->priv;
 165 #endif
 166 }
 167 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 168 {
 169 #if CONFIG_IS_ENABLED(DM_MMC)
 170         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 171         return &plat->cfg;
 172 #else
 173         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 174 #endif
 175 }
 176
 177 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 178 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 179 {
 180         int ret;
 181
 182 #ifndef CONFIG_DM_GPIO
 183         if (!gpio_is_valid(gpio))
 184                 return -1;
 185 #endif
 186         ret = gpio_request(gpio, label);
 187         if (ret)
 188                 return ret;
 189
 190         ret = gpio_direction_input(gpio);
 191         if (ret)
 192                 return ret;
 193
 194         return gpio;
 195 }
 196 #endif
 197
 198 static unsigned char mmc_board_init(struct mmc *mmc)
 199 {
 200 #if defined(CONFIG_OMAP34XX)
 201         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 202         t2_t *t2_base = (t2_t *)T2_BASE;
 203         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 204         u32 pbias_lite;
 205 #ifdef CONFIG_MMC_OMAP36XX_PINS
 206         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 207 #endif
 208
 209         pbias_lite = readl(&t2_base->pbias_lite);
 210         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 211 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 212         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 213         pbias_lite &= ~PBIASLITEVMODE0;
 214 #endif
 215 #ifdef CONFIG_MMC_OMAP36XX_PINS
 216         if (get_cpu_family() == CPU_OMAP36XX) {
 217                 /* Disable extended drain IO before changing PBIAS */
 218                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 219                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 220         }
 221 #endif
 222         writel(pbias_lite, &t2_base->pbias_lite);
 223
 224         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 225                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 226                 &t2_base->pbias_lite);
 227
 228 #ifdef CONFIG_MMC_OMAP36XX_PINS
 229         if (get_cpu_family() == CPU_OMAP36XX)
 230                 /* Enable extended drain IO after changing PBIAS */
 231                 writel(wkup_ctrl |
 232                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 233                                 OMAP34XX_CTRL_WKUP_CTRL);
 234 #endif
 235         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 236                 &t2_base->devconf0);
 237
 238         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 239                 &t2_base->devconf1);
 240
 241         /* Change from default of 52MHz to 26MHz if necessary */
 242         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 243                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 244                         &t2_base->ctl_prog_io1);
 245
 246         writel(readl(&prcm_base->fclken1_core) |
 247                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 248                 &prcm_base->fclken1_core);
 249
 250         writel(readl(&prcm_base->iclken1_core) |
 251                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 252                 &prcm_base->iclken1_core);
 253 #endif
 254
 255 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 256         /* PBIAS config needed for MMC1 only */
 257         if (mmc_get_blk_desc(mmc)->devnum == 0)
 258                 vmmc_pbias_config(LDO_VOLT_3V0);
 259 #endif
 260
 261         return 0;
 262 }
 263
 264 void mmc_init_stream(struct hsmmc *mmc_base)
 265 {
 266         ulong start;
 267
 268         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 269
 270         writel(MMC_CMD0, &mmc_base->cmd);
 271         start = get_timer(0);
 272         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 273                 if (get_timer(0) - start > MAX_RETRY_MS) {
 274                         printf("%s: timedout waiting for cc!\n", __func__);
 275                         return;
 276                 }
 277         }
 278         writel(CC_MASK, &mmc_base->stat)
 279                 ;
 280         writel(MMC_CMD0, &mmc_base->cmd)
 281                 ;
 282         start = get_timer(0);
 283         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 284                 if (get_timer(0) - start > MAX_RETRY_MS) {
 285                         printf("%s: timedout waiting for cc2!\n", __func__);
 286                         return;
 287                 }
 288         }
 289         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 290 }
 291
 292 #if CONFIG_IS_ENABLED(DM_MMC)
 293 #ifdef CONFIG_IODELAY_RECALIBRATION
 294 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 295 {
 296         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 297         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 298
 299         switch (priv->mode) {
 300         case MMC_HS_200:
 301                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 302                 break;
 303         case UHS_SDR104:
 304                 pinctrl_state = priv->sdr104_pinctrl_state;
 305                 break;
 306         case UHS_SDR50:
 307                 pinctrl_state = priv->sdr50_pinctrl_state;
 308                 break;
 309         case UHS_DDR50:
 310                 pinctrl_state = priv->ddr50_pinctrl_state;
 311                 break;
 312         case UHS_SDR25:
 313                 pinctrl_state = priv->sdr25_pinctrl_state;
 314                 break;
 315         case UHS_SDR12:
 316                 pinctrl_state = priv->sdr12_pinctrl_state;
 317                 break;
 318         case SD_HS:
 319         case MMC_HS:
 320         case MMC_HS_52:
 321                 pinctrl_state = priv->hs_pinctrl_state;
 322                 break;
 323         case MMC_DDR_52:
 324                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 325         default:
 326                 pinctrl_state = priv->default_pinctrl_state;
 327                 break;
 328         }
 329
 330         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 331                 if (pinctrl_state->iodelay)
 332                         late_recalibrate_iodelay(pinctrl_state->padconf,
 333                                                  pinctrl_state->npads,
 334                                                  pinctrl_state->iodelay,
 335                                                  pinctrl_state->niodelays);
 336                 else
 337                         do_set_mux32((*ctrl)->control_padconf_core_base,
 338                                      pinctrl_state->padconf,
 339                                      pinctrl_state->npads);
 340         }
 341 }
 342 #endif
 343 static void omap_hsmmc_set_timing(struct mmc *mmc)
 344 {
 345         u32 val;
 346         struct hsmmc *mmc_base;
 347         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 348
 349         mmc_base = priv->base_addr;
 350
 351         omap_hsmmc_stop_clock(mmc_base);
 352         val = readl(&mmc_base->ac12);
 353         val &= ~AC12_UHSMC_MASK;
 354         priv->mode = mmc->selected_mode;
 355
 356         if (mmc_is_mode_ddr(priv->mode))
 357                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 358         else
 359                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 360
 361         switch (priv->mode) {
 362         case MMC_HS_200:
 363         case UHS_SDR104:
 364                 val |= AC12_UHSMC_SDR104;
 365                 break;
 366         case UHS_SDR50:
 367                 val |= AC12_UHSMC_SDR50;
 368                 break;
 369         case MMC_DDR_52:
 370         case UHS_DDR50:
 371                 val |= AC12_UHSMC_DDR50;
 372                 break;
 373         case SD_HS:
 374         case MMC_HS_52:
 375         case UHS_SDR25:
 376                 val |= AC12_UHSMC_SDR25;
 377                 break;
 378         case MMC_LEGACY:
 379         case MMC_HS:
 380         case SD_LEGACY:
 381         case UHS_SDR12:
 382                 val |= AC12_UHSMC_SDR12;
 383                 break;
 384         default:
 385                 val |= AC12_UHSMC_RES;
 386                 break;
 387         }
 388         writel(val, &mmc_base->ac12);
 389
 390 #ifdef CONFIG_IODELAY_RECALIBRATION
 391         omap_hsmmc_io_recalibrate(mmc);
 392 #endif
 393         omap_hsmmc_start_clock(mmc_base);
 394 }
 395
 396 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
 397 {
 398         struct hsmmc *mmc_base;
 399         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 400         u32 val;
 401
 402         mmc_base = priv->base_addr;
 403
 404         val = readl(&mmc_base->hctl) & ~SDVS_MASK;
 405
 406         switch (priv->iov) {
 407         case IOV_3V3:
 408                 val |= SDVS_3V3;
 409                 break;
 410         case IOV_3V0:
 411                 val |= SDVS_3V0;
 412                 break;
 413         case IOV_1V8:
 414                 val |= SDVS_1V8;
 415                 break;
 416         }
 417
 418         writel(val, &mmc_base->hctl);
 419 }
 420
 421 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
 422 {
 423         struct hsmmc *mmc_base;
 424         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 425         u32 val;
 426
 427         mmc_base = priv->base_addr;
 428         val = readl(&mmc_base->capa);
 429
 430         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 431                 val |= (VS30_3V0SUP | VS18_1V8SUP);
 432                 priv->iov = IOV_3V0;
 433         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 434                 val |= VS30_3V0SUP;
 435                 val &= ~VS18_1V8SUP;
 436                 priv->iov = IOV_3V0;
 437         } else {
 438                 val |= VS18_1V8SUP;
 439                 val &= ~VS30_3V0SUP;
 440                 priv->iov = IOV_1V8;
 441         }
 442
 443         writel(val, &mmc_base->capa);
 444 }
 445
 446 #ifdef MMC_SUPPORTS_TUNING
 447 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 448 {
 449         struct hsmmc *mmc_base;
 450         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 451         u32 val;
 452
 453         mmc_base = priv->base_addr;
 454         val = readl(&mmc_base->ac12);
 455         val &= ~(AC12_SCLK_SEL);
 456         writel(val, &mmc_base->ac12);
 457
 458         val = readl(&mmc_base->dll);
 459         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 460         writel(val, &mmc_base->dll);
 461 }
 462
 463 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 464 {
 465         int i;
 466         struct hsmmc *mmc_base;
 467         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 468         u32 val;
 469
 470         mmc_base = priv->base_addr;
 471         val = readl(&mmc_base->dll);
 472         val |= DLL_FORCE_VALUE;
 473         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 474         val |= (count << DLL_FORCE_SR_C_SHIFT);
 475         writel(val, &mmc_base->dll);
 476
 477         val |= DLL_CALIB;
 478         writel(val, &mmc_base->dll);
 479         for (i = 0; i < 1000; i++) {
 480                 if (readl(&mmc_base->dll) & DLL_CALIB)
 481                         break;
 482         }
 483         val &= ~DLL_CALIB;
 484         writel(val, &mmc_base->dll);
 485 }
 486
 487 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 488 {
 489         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 490         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 491         struct mmc *mmc = upriv->mmc;
 492         struct hsmmc *mmc_base;
 493         u32 val;
 494         u8 cur_match, prev_match = 0;
 495         int ret;
 496         u32 phase_delay = 0;
 497         u32 start_window = 0, max_window = 0;
 498         u32 length = 0, max_len = 0;
 499
 500         mmc_base = priv->base_addr;
 501         val = readl(&mmc_base->capa2);
 502
 503         /* clock tuning is not needed for upto 52MHz */
 504         if (!((mmc->selected_mode == MMC_HS_200) ||
 505               (mmc->selected_mode == UHS_SDR104) ||
 506               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 507                 return 0;
 508
 509         val = readl(&mmc_base->dll);
 510         val |= DLL_SWT;
 511         writel(val, &mmc_base->dll);
 512         while (phase_delay <= MAX_PHASE_DELAY) {
 513                 omap_hsmmc_set_dll(mmc, phase_delay);
 514
 515                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 516
 517                 if (cur_match) {
 518                         if (prev_match) {
 519                                 length++;
 520                         } else {
 521                                 start_window = phase_delay;
 522                                 length = 1;
 523                         }
 524                 }
 525
 526                 if (length > max_len) {
 527                         max_window = start_window;
 528                         max_len = length;
 529                 }
 530
 531                 prev_match = cur_match;
 532                 phase_delay += 4;
 533         }
 534
 535         if (!max_len) {
 536                 ret = -EIO;
 537                 goto tuning_error;
 538         }
 539
 540         val = readl(&mmc_base->ac12);
 541         if (!(val & AC12_SCLK_SEL)) {
 542                 ret = -EIO;
 543                 goto tuning_error;
 544         }
 545
 546         phase_delay = max_window + 4 * ((3 * max_len) >> 2);
 547         omap_hsmmc_set_dll(mmc, phase_delay);
 548
 549         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 550         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 551
 552         return 0;
 553
 554 tuning_error:
 555
 556         omap_hsmmc_disable_tuning(mmc);
 557         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 558         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 559
 560         return ret;
 561 }
 562 #endif
 563 #endif
 564
 565 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 566 {
 567         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 568         struct hsmmc *mmc_base = priv->base_addr;
 569         u32 irq_mask = INT_EN_MASK;
 570
 571         /*
 572          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 573          * tuning procedure and DCRC should be disabled. But see occurences
 574          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 575          * interrupts occur along with BRR, so the data is actually in the
 576          * buffer. It has to be debugged why these interrutps occur
 577          */
 578         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 579                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 580
 581         writel(irq_mask, &mmc_base->ie);
 582 }
 583
 584 static int omap_hsmmc_init_setup(struct mmc *mmc)
 585 {
 586         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 587         struct hsmmc *mmc_base;
 588         unsigned int reg_val;
 589         unsigned int dsor;
 590         ulong start;
 591
 592         mmc_base = priv->base_addr;
 593         mmc_board_init(mmc);
 594
 595         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 596                 &mmc_base->sysconfig);
 597         start = get_timer(0);
 598         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 599                 if (get_timer(0) - start > MAX_RETRY_MS) {
 600                         printf("%s: timedout waiting for cc2!\n", __func__);
 601                         return -ETIMEDOUT;
 602                 }
 603         }
 604         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 605         start = get_timer(0);
 606         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 607                 if (get_timer(0) - start > MAX_RETRY_MS) {
 608                         printf("%s: timedout waiting for softresetall!\n",
 609                                 __func__);
 610                         return -ETIMEDOUT;
 611                 }
 612         }
 613 #ifndef CONFIG_OMAP34XX
 614         reg_val = readl(&mmc_base->hl_hwinfo);
 615         if (reg_val & MADMA_EN)
 616                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 617 #endif
 618
 619 #if CONFIG_IS_ENABLED(DM_MMC)
 620         omap_hsmmc_set_capabilities(mmc);
 621         omap_hsmmc_conf_bus_power(mmc);
 622 #else
 623         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 624         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 625                 &mmc_base->capa);
 626 #endif
 627
 628         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 629
 630         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 631                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 632                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 633
 634         dsor = 240;
 635         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 636                 (ICE_STOP | DTO_15THDTO));
 637         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 638                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 639         start = get_timer(0);
 640         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 641                 if (get_timer(0) - start > MAX_RETRY_MS) {
 642                         printf("%s: timedout waiting for ics!\n", __func__);
 643                         return -ETIMEDOUT;
 644                 }
 645         }
 646         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 647
 648         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 649
 650         mmc_enable_irq(mmc, NULL);
 651         mmc_init_stream(mmc_base);
 652
 653         return 0;
 654 }
 655
 656 /*
 657  * MMC controller internal finite state machine reset
 658  *
 659  * Used to reset command or data internal state machines, using respectively
 660  * SRC or SRD bit of SYSCTL register
 661  */
 662 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 663 {
 664         ulong start;
 665
 666         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 667
 668         /*
 669          * CMD(DAT) lines reset procedures are slightly different
 670          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 671          * According to OMAP3 TRM:
 672          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 673          * returns to 0x0.
 674          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 675          * procedure steps must be as follows:
 676          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 677          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 678          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 679          * 3. Wait until the SRC (SRD) bit returns to 0x0
 680          *    (reset procedure is completed).
 681          */
 682 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 683         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 684         if (!(readl(&mmc_base->sysctl) & bit)) {
 685                 start = get_timer(0);
 686                 while (!(readl(&mmc_base->sysctl) & bit)) {
 687                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 688                                 return;
 689                 }
 690         }
 691 #endif
 692         start = get_timer(0);
 693         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 694                 if (get_timer(0) - start > MAX_RETRY_MS) {
 695                         printf("%s: timedout waiting for sysctl %x to clear\n",
 696                                 __func__, bit);
 697                         return;
 698                 }
 699         }
 700 }
 701
 702 #ifndef CONFIG_OMAP34XX
 703 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 704 {
 705         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 706         struct omap_hsmmc_adma_desc *desc;
 707         u8 attr;
 708
 709         desc = &priv->adma_desc_table[priv->desc_slot];
 710
 711         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 712         if (!end)
 713                 priv->desc_slot++;
 714         else
 715                 attr |= ADMA_DESC_ATTR_END;
 716
 717         desc->len = len;
 718         desc->addr = (u32)buf;
 719         desc->reserved = 0;
 720         desc->attr = attr;
 721 }
 722
 723 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 724                                           struct mmc_data *data)
 725 {
 726         uint total_len = data->blocksize * data->blocks;
 727         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 728         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 729         int i = desc_count;
 730         char *buf;
 731
 732         priv->desc_slot = 0;
 733         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 734                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 735                                 sizeof(struct omap_hsmmc_adma_desc));
 736
 737         if (data->flags & MMC_DATA_READ)
 738                 buf = data->dest;
 739         else
 740                 buf = (char *)data->src;
 741
 742         while (--i) {
 743                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 744                 buf += ADMA_MAX_LEN;
 745                 total_len -= ADMA_MAX_LEN;
 746         }
 747
 748         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 749
 750         flush_dcache_range((long)priv->adma_desc_table,
 751                            (long)priv->adma_desc_table +
 752                            ROUND(desc_count *
 753                            sizeof(struct omap_hsmmc_adma_desc),
 754                            ARCH_DMA_MINALIGN));
 755 }
 756
 757 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 758 {
 759         struct hsmmc *mmc_base;
 760         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 761         u32 val;
 762         char *buf;
 763
 764         mmc_base = priv->base_addr;
 765         omap_hsmmc_prepare_adma_table(mmc, data);
 766
 767         if (data->flags & MMC_DATA_READ)
 768                 buf = data->dest;
 769         else
 770                 buf = (char *)data->src;
 771
 772         val = readl(&mmc_base->hctl);
 773         val |= DMA_SELECT;
 774         writel(val, &mmc_base->hctl);
 775
 776         val = readl(&mmc_base->con);
 777         val |= DMA_MASTER;
 778         writel(val, &mmc_base->con);
 779
 780         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
 781
 782         flush_dcache_range((u32)buf,
 783                            (u32)buf +
 784                            ROUND(data->blocksize * data->blocks,
 785                                  ARCH_DMA_MINALIGN));
 786 }
 787
 788 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
 789 {
 790         struct hsmmc *mmc_base;
 791         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 792         u32 val;
 793
 794         mmc_base = priv->base_addr;
 795
 796         val = readl(&mmc_base->con);
 797         val &= ~DMA_MASTER;
 798         writel(val, &mmc_base->con);
 799
 800         val = readl(&mmc_base->hctl);
 801         val &= ~DMA_SELECT;
 802         writel(val, &mmc_base->hctl);
 803
 804         kfree(priv->adma_desc_table);
 805 }
 806 #else
 807 #define omap_hsmmc_adma_desc
 808 #define omap_hsmmc_prepare_adma_table
 809 #define omap_hsmmc_prepare_data
 810 #define omap_hsmmc_dma_cleanup
 811 #endif
 812
 813 #if !CONFIG_IS_ENABLED(DM_MMC)
 814 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 815                         struct mmc_data *data)
 816 {
 817         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 818 #else
 819 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 820                         struct mmc_data *data)
 821 {
 822         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 823         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 824         struct mmc *mmc = upriv->mmc;
 825 #endif
 826         struct hsmmc *mmc_base;
 827         unsigned int flags, mmc_stat;
 828         ulong start;
 829
 830         mmc_base = priv->base_addr;
 831
 832         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 833                 return 0;
 834
 835         start = get_timer(0);
 836         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 837                 if (get_timer(0) - start > MAX_RETRY_MS) {
 838                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 839                                         __func__);
 840                         return -ETIMEDOUT;
 841                 }
 842         }
 843         writel(0xFFFFFFFF, &mmc_base->stat);
 844         start = get_timer(0);
 845         while (readl(&mmc_base->stat)) {
 846                 if (get_timer(0) - start > MAX_RETRY_MS) {
 847                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 848                                 __func__, readl(&mmc_base->stat));
 849                         return -ETIMEDOUT;
 850                 }
 851         }
 852         /*
 853          * CMDREG
 854          * CMDIDX[13:8] : Command index
 855          * DATAPRNT[5]  : Data Present Select
 856          * ENCMDIDX[4]  : Command Index Check Enable
 857          * ENCMDCRC[3]  : Command CRC Check Enable
 858          * RSPTYP[1:0]
 859          *      00 = No Response
 860          *      01 = Length 136
 861          *      10 = Length 48
 862          *      11 = Length 48 Check busy after response
 863          */
 864         /* Delay added before checking the status of frq change
 865          * retry not supported by mmc.c(core file)
 866          */
 867         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 868                 udelay(50000); /* wait 50 ms */
 869
 870         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 871                 flags = 0;
 872         else if (cmd->resp_type & MMC_RSP_136)
 873                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 874         else if (cmd->resp_type & MMC_RSP_BUSY)
 875                 flags = RSP_TYPE_LGHT48B;
 876         else
 877                 flags = RSP_TYPE_LGHT48;
 878
 879         /* enable default flags */
 880         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 881                         MSBS_SGLEBLK);
 882         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
 883
 884         if (cmd->resp_type & MMC_RSP_CRC)
 885                 flags |= CCCE_CHECK;
 886         if (cmd->resp_type & MMC_RSP_OPCODE)
 887                 flags |= CICE_CHECK;
 888
 889         if (data) {
 890                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 891                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 892                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
 893                         data->blocksize = 512;
 894                         writel(data->blocksize | (data->blocks << 16),
 895                                                         &mmc_base->blk);
 896                 } else
 897                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 898
 899                 if (data->flags & MMC_DATA_READ)
 900                         flags |= (DP_DATA | DDIR_READ);
 901                 else
 902                         flags |= (DP_DATA | DDIR_WRITE);
 903
 904 #ifndef CONFIG_OMAP34XX
 905                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
 906                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
 907                         omap_hsmmc_prepare_data(mmc, data);
 908                         flags |= DE_ENABLE;
 909                 }
 910 #endif
 911         }
 912
 913         mmc_enable_irq(mmc, cmd);
 914
 915         writel(cmd->cmdarg, &mmc_base->arg);
 916         udelay(20);             /* To fix "No status update" error on eMMC */
 917         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 918
 919         start = get_timer(0);
 920         do {
 921                 mmc_stat = readl(&mmc_base->stat);
 922                 if (get_timer(start) > MAX_RETRY_MS) {
 923                         printf("%s : timeout: No status update\n", __func__);
 924                         return -ETIMEDOUT;
 925                 }
 926         } while (!mmc_stat);
 927
 928         if ((mmc_stat & IE_CTO) != 0) {
 929                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 930                 return -ETIMEDOUT;
 931         } else if ((mmc_stat & ERRI_MASK) != 0)
 932                 return -1;
 933
 934         if (mmc_stat & CC_MASK) {
 935                 writel(CC_MASK, &mmc_base->stat);
 936                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 937                         if (cmd->resp_type & MMC_RSP_136) {
 938                                 /* response type 2 */
 939                                 cmd->response[3] = readl(&mmc_base->rsp10);
 940                                 cmd->response[2] = readl(&mmc_base->rsp32);
 941                                 cmd->response[1] = readl(&mmc_base->rsp54);
 942                                 cmd->response[0] = readl(&mmc_base->rsp76);
 943                         } else
 944                                 /* response types 1, 1b, 3, 4, 5, 6 */
 945                                 cmd->response[0] = readl(&mmc_base->rsp10);
 946                 }
 947         }
 948
 949 #ifndef CONFIG_OMAP34XX
 950         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
 951             !mmc_is_tuning_cmd(cmd->cmdidx)) {
 952                 u32 sz_mb, timeout;
 953
 954                 if (mmc_stat & IE_ADMAE) {
 955                         omap_hsmmc_dma_cleanup(mmc);
 956                         return -EIO;
 957                 }
 958
 959                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
 960                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
 961                 if (timeout < MAX_RETRY_MS)
 962                         timeout = MAX_RETRY_MS;
 963
 964                 start = get_timer(0);
 965                 do {
 966                         mmc_stat = readl(&mmc_base->stat);
 967                         if (mmc_stat & TC_MASK) {
 968                                 writel(readl(&mmc_base->stat) | TC_MASK,
 969                                        &mmc_base->stat);
 970                                 break;
 971                         }
 972                         if (get_timer(start) > timeout) {
 973                                 printf("%s : DMA timeout: No status update\n",
 974                                        __func__);
 975                                 return -ETIMEDOUT;
 976                         }
 977                 } while (1);
 978
 979                 omap_hsmmc_dma_cleanup(mmc);
 980                 return 0;
 981         }
 982 #endif
 983
 984         if (data && (data->flags & MMC_DATA_READ)) {
 985                 mmc_read_data(mmc_base, data->dest,
 986                                 data->blocksize * data->blocks);
 987         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 988                 mmc_write_data(mmc_base, data->src,
 989                                 data->blocksize * data->blocks);
 990         }
 991         return 0;
 992 }
 993
 994 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 995 {
 996         unsigned int *output_buf = (unsigned int *)buf;
 997         unsigned int mmc_stat;
 998         unsigned int count;
 999
1000         /*
1001          * Start Polled Read
1002          */
1003         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1004         count /= 4;
1005
1006         while (size) {
1007                 ulong start = get_timer(0);
1008                 do {
1009                         mmc_stat = readl(&mmc_base->stat);
1010                         if (get_timer(0) - start > MAX_RETRY_MS) {
1011                                 printf("%s: timedout waiting for status!\n",
1012                                                 __func__);
1013                                 return -ETIMEDOUT;
1014                         }
1015                 } while (mmc_stat == 0);
1016
1017                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1018                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1019
1020                 if ((mmc_stat & ERRI_MASK) != 0)
1021                         return 1;
1022
1023                 if (mmc_stat & BRR_MASK) {
1024                         unsigned int k;
1025
1026                         writel(readl(&mmc_base->stat) | BRR_MASK,
1027                                 &mmc_base->stat);
1028                         for (k = 0; k < count; k++) {
1029                                 *output_buf = readl(&mmc_base->data);
1030                                 output_buf++;
1031                         }
1032                         size -= (count*4);
1033                 }
1034
1035                 if (mmc_stat & BWR_MASK)
1036                         writel(readl(&mmc_base->stat) | BWR_MASK,
1037                                 &mmc_base->stat);
1038
1039                 if (mmc_stat & TC_MASK) {
1040                         writel(readl(&mmc_base->stat) | TC_MASK,
1041                                 &mmc_base->stat);
1042                         break;
1043                 }
1044         }
1045         return 0;
1046 }
1047
1048 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1049                                 unsigned int size)
1050 {
1051         unsigned int *input_buf = (unsigned int *)buf;
1052         unsigned int mmc_stat;
1053         unsigned int count;
1054
1055         /*
1056          * Start Polled Write
1057          */
1058         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1059         count /= 4;
1060
1061         while (size) {
1062                 ulong start = get_timer(0);
1063                 do {
1064                         mmc_stat = readl(&mmc_base->stat);
1065                         if (get_timer(0) - start > MAX_RETRY_MS) {
1066                                 printf("%s: timedout waiting for status!\n",
1067                                                 __func__);
1068                                 return -ETIMEDOUT;
1069                         }
1070                 } while (mmc_stat == 0);
1071
1072                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1073                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1074
1075                 if ((mmc_stat & ERRI_MASK) != 0)
1076                         return 1;
1077
1078                 if (mmc_stat & BWR_MASK) {
1079                         unsigned int k;
1080
1081                         writel(readl(&mmc_base->stat) | BWR_MASK,
1082                                         &mmc_base->stat);
1083                         for (k = 0; k < count; k++) {
1084                                 writel(*input_buf, &mmc_base->data);
1085                                 input_buf++;
1086                         }
1087                         size -= (count*4);
1088                 }
1089
1090                 if (mmc_stat & BRR_MASK)
1091                         writel(readl(&mmc_base->stat) | BRR_MASK,
1092                                 &mmc_base->stat);
1093
1094                 if (mmc_stat & TC_MASK) {
1095                         writel(readl(&mmc_base->stat) | TC_MASK,
1096                                 &mmc_base->stat);
1097                         break;
1098                 }
1099         }
1100         return 0;
1101 }
1102
1103 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1104 {
1105         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1106 }
1107
1108 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1109 {
1110         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1111 }
1112
1113 static void omap_hsmmc_set_clock(struct mmc *mmc)
1114 {
1115         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1116         struct hsmmc *mmc_base;
1117         unsigned int dsor = 0;
1118         ulong start;
1119
1120         mmc_base = priv->base_addr;
1121         omap_hsmmc_stop_clock(mmc_base);
1122
1123         /* TODO: Is setting DTO required here? */
1124         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1125                     (ICE_STOP | DTO_15THDTO));
1126
1127         if (mmc->clock != 0) {
1128                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1129                 if (dsor > CLKD_MAX)
1130                         dsor = CLKD_MAX;
1131         } else {
1132                 dsor = CLKD_MAX;
1133         }
1134
1135         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1136                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1137
1138         start = get_timer(0);
1139         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1140                 if (get_timer(0) - start > MAX_RETRY_MS) {
1141                         printf("%s: timedout waiting for ics!\n", __func__);
1142                         return;
1143                 }
1144         }
1145
1146         priv->clock = mmc->clock;
1147         omap_hsmmc_start_clock(mmc_base);
1148 }
1149
1150 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1151 {
1152         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1153         struct hsmmc *mmc_base;
1154
1155         mmc_base = priv->base_addr;
1156         /* configue bus width */
1157         switch (mmc->bus_width) {
1158         case 8:
1159                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1160                         &mmc_base->con);
1161                 break;
1162
1163         case 4:
1164                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1165                         &mmc_base->con);
1166                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1167                         &mmc_base->hctl);
1168                 break;
1169
1170         case 1:
1171         default:
1172                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1173                         &mmc_base->con);
1174                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1175                         &mmc_base->hctl);
1176                 break;
1177         }
1178
1179         priv->bus_width = mmc->bus_width;
1180 }
1181
1182 #if !CONFIG_IS_ENABLED(DM_MMC)
1183 static int omap_hsmmc_set_ios(struct mmc *mmc)
1184 {
1185         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1186 #else
1187 static int omap_hsmmc_set_ios(struct udevice *dev)
1188 {
1189         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1190         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1191         struct mmc *mmc = upriv->mmc;
1192 #endif
1193
1194         if (priv->bus_width != mmc->bus_width)
1195                 omap_hsmmc_set_bus_width(mmc);
1196
1197         if (priv->clock != mmc->clock)
1198                 omap_hsmmc_set_clock(mmc);
1199
1200 #if CONFIG_IS_ENABLED(DM_MMC)
1201         if (priv->mode != mmc->selected_mode)
1202                 omap_hsmmc_set_timing(mmc);
1203 #endif
1204         return 0;
1205 }
1206
1207 #ifdef OMAP_HSMMC_USE_GPIO
1208 #if CONFIG_IS_ENABLED(DM_MMC)
1209 static int omap_hsmmc_getcd(struct udevice *dev)
1210 {
1211         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1212         int value;
1213
1214         value = dm_gpio_get_value(&priv->cd_gpio);
1215         /* if no CD return as 1 */
1216         if (value < 0)
1217                 return 1;
1218
1219         if (priv->cd_inverted)
1220                 return !value;
1221         return value;
1222 }
1223
1224 static int omap_hsmmc_getwp(struct udevice *dev)
1225 {
1226         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1227         int value;
1228
1229         value = dm_gpio_get_value(&priv->wp_gpio);
1230         /* if no WP return as 0 */
1231         if (value < 0)
1232                 return 0;
1233         return value;
1234 }
1235 #else
1236 static int omap_hsmmc_getcd(struct mmc *mmc)
1237 {
1238         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1239         int cd_gpio;
1240
1241         /* if no CD return as 1 */
1242         cd_gpio = priv->cd_gpio;
1243         if (cd_gpio < 0)
1244                 return 1;
1245
1246         /* NOTE: assumes card detect signal is active-low */
1247         return !gpio_get_value(cd_gpio);
1248 }
1249
1250 static int omap_hsmmc_getwp(struct mmc *mmc)
1251 {
1252         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1253         int wp_gpio;
1254
1255         /* if no WP return as 0 */
1256         wp_gpio = priv->wp_gpio;
1257         if (wp_gpio < 0)
1258                 return 0;
1259
1260         /* NOTE: assumes write protect signal is active-high */
1261         return gpio_get_value(wp_gpio);
1262 }
1263 #endif
1264 #endif
1265
1266 #if CONFIG_IS_ENABLED(DM_MMC)
1267 static const struct dm_mmc_ops omap_hsmmc_ops = {
1268         .send_cmd       = omap_hsmmc_send_cmd,
1269         .set_ios        = omap_hsmmc_set_ios,
1270 #ifdef OMAP_HSMMC_USE_GPIO
1271         .get_cd         = omap_hsmmc_getcd,
1272         .get_wp         = omap_hsmmc_getwp,
1273 #endif
1274 #ifdef MMC_SUPPORTS_TUNING
1275         .execute_tuning = omap_hsmmc_execute_tuning,
1276 #endif
1277 };
1278 #else
1279 static const struct mmc_ops omap_hsmmc_ops = {
1280         .send_cmd       = omap_hsmmc_send_cmd,
1281         .set_ios        = omap_hsmmc_set_ios,
1282         .init           = omap_hsmmc_init_setup,
1283 #ifdef OMAP_HSMMC_USE_GPIO
1284         .getcd          = omap_hsmmc_getcd,
1285         .getwp          = omap_hsmmc_getwp,
1286 #endif
1287 };
1288 #endif
1289
1290 #if !CONFIG_IS_ENABLED(DM_MMC)
1291 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1292                 int wp_gpio)
1293 {
1294         struct mmc *mmc;
1295         struct omap_hsmmc_data *priv;
1296         struct mmc_config *cfg;
1297         uint host_caps_val;
1298
1299         priv = malloc(sizeof(*priv));
1300         if (priv == NULL)
1301                 return -1;
1302
1303         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1304
1305         switch (dev_index) {
1306         case 0:
1307                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1308                 break;
1309 #ifdef OMAP_HSMMC2_BASE
1310         case 1:
1311                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1312 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1313         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1314         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1315                 defined(CONFIG_HSMMC2_8BIT)
1316                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1317                 host_caps_val |= MMC_MODE_8BIT;
1318 #endif
1319                 break;
1320 #endif
1321 #ifdef OMAP_HSMMC3_BASE
1322         case 2:
1323                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1324 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1325                 /* Enable 8-bit interface for eMMC on DRA7XX */
1326                 host_caps_val |= MMC_MODE_8BIT;
1327 #endif
1328                 break;
1329 #endif
1330         default:
1331                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1332                 return 1;
1333         }
1334 #ifdef OMAP_HSMMC_USE_GPIO
1335         /* on error gpio values are set to -1, which is what we want */
1336         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1337         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1338 #endif
1339
1340         cfg = &priv->cfg;
1341
1342         cfg->name = "OMAP SD/MMC";
1343         cfg->ops = &omap_hsmmc_ops;
1344
1345         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1346         cfg->host_caps = host_caps_val & ~host_caps_mask;
1347
1348         cfg->f_min = 400000;
1349
1350         if (f_max != 0)
1351                 cfg->f_max = f_max;
1352         else {
1353                 if (cfg->host_caps & MMC_MODE_HS) {
1354                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1355                                 cfg->f_max = 52000000;
1356                         else
1357                                 cfg->f_max = 26000000;
1358                 } else
1359                         cfg->f_max = 20000000;
1360         }
1361
1362         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1363
1364 #if defined(CONFIG_OMAP34XX)
1365         /*
1366          * Silicon revs 2.1 and older do not support multiblock transfers.
1367          */
1368         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1369                 cfg->b_max = 1;
1370 #endif
1371         mmc = mmc_create(cfg, priv);
1372         if (mmc == NULL)
1373                 return -1;
1374
1375         return 0;
1376 }
1377 #else
1378
1379 #ifdef CONFIG_IODELAY_RECALIBRATION
1380 static struct pad_conf_entry *
1381 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1382 {
1383         int index = 0;
1384         struct pad_conf_entry *padconf;
1385
1386         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1387         if (!padconf) {
1388                 debug("failed to allocate memory\n");
1389                 return 0;
1390         }
1391
1392         while (index < count) {
1393                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1394                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1395                 index++;
1396         }
1397
1398         return padconf;
1399 }
1400
1401 static struct iodelay_cfg_entry *
1402 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1403 {
1404         int index = 0;
1405         struct iodelay_cfg_entry *iodelay;
1406
1407         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1408         if (!iodelay) {
1409                 debug("failed to allocate memory\n");
1410                 return 0;
1411         }
1412
1413         while (index < count) {
1414                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1415                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1416                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1417                 index++;
1418         }
1419
1420         return iodelay;
1421 }
1422
1423 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1424                                                    const char *name, int *len)
1425 {
1426         const void *fdt = gd->fdt_blob;
1427         int offset;
1428         const fdt32_t *pinctrl;
1429
1430         offset = fdt_node_offset_by_phandle(fdt, phandle);
1431         if (offset < 0) {
1432                 debug("failed to get pinctrl node %s.\n",
1433                       fdt_strerror(offset));
1434                 return 0;
1435         }
1436
1437         pinctrl = fdt_getprop(fdt, offset, name, len);
1438         if (!pinctrl) {
1439                 debug("failed to get property %s\n", name);
1440                 return 0;
1441         }
1442
1443         return pinctrl;
1444 }
1445
1446 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1447                                                 char *prop_name)
1448 {
1449         const void *fdt = gd->fdt_blob;
1450         const __be32 *phandle;
1451         int node = dev_of_offset(mmc->dev);
1452
1453         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1454         if (!phandle) {
1455                 debug("failed to get property %s\n", prop_name);
1456                 return 0;
1457         }
1458
1459         return fdt32_to_cpu(*phandle);
1460 }
1461
1462 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1463                                                char *prop_name)
1464 {
1465         const void *fdt = gd->fdt_blob;
1466         const __be32 *phandle;
1467         int len;
1468         int count;
1469         int node = dev_of_offset(mmc->dev);
1470
1471         phandle = fdt_getprop(fdt, node, prop_name, &len);
1472         if (!phandle) {
1473                 debug("failed to get property %s\n", prop_name);
1474                 return 0;
1475         }
1476
1477         /* No manual mode iodelay values if count < 2 */
1478         count = len / sizeof(*phandle);
1479         if (count < 2)
1480                 return 0;
1481
1482         return fdt32_to_cpu(*(phandle + 1));
1483 }
1484
1485 static struct pad_conf_entry *
1486 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1487 {
1488         int len;
1489         int count;
1490         struct pad_conf_entry *padconf;
1491         u32 phandle;
1492         const fdt32_t *pinctrl;
1493
1494         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1495         if (!phandle)
1496                 return ERR_PTR(-EINVAL);
1497
1498         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1499                                                &len);
1500         if (!pinctrl)
1501                 return ERR_PTR(-EINVAL);
1502
1503         count = (len / sizeof(*pinctrl)) / 2;
1504         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1505         if (!padconf)
1506                 return ERR_PTR(-EINVAL);
1507
1508         *npads = count;
1509
1510         return padconf;
1511 }
1512
1513 static struct iodelay_cfg_entry *
1514 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1515 {
1516         int len;
1517         int count;
1518         struct iodelay_cfg_entry *iodelay;
1519         u32 phandle;
1520         const fdt32_t *pinctrl;
1521
1522         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1523         /* Not all modes have manual mode iodelay values. So its not fatal */
1524         if (!phandle)
1525                 return 0;
1526
1527         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1528                                                &len);
1529         if (!pinctrl)
1530                 return ERR_PTR(-EINVAL);
1531
1532         count = (len / sizeof(*pinctrl)) / 3;
1533         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1534         if (!iodelay)
1535                 return ERR_PTR(-EINVAL);
1536
1537         *niodelay = count;
1538
1539         return iodelay;
1540 }
1541
1542 static struct omap_hsmmc_pinctrl_state *
1543 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1544 {
1545         int index;
1546         int npads = 0;
1547         int niodelays = 0;
1548         const void *fdt = gd->fdt_blob;
1549         int node = dev_of_offset(mmc->dev);
1550         char prop_name[11];
1551         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1552
1553         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1554                          malloc(sizeof(*pinctrl_state));
1555         if (!pinctrl_state) {
1556                 debug("failed to allocate memory\n");
1557                 return 0;
1558         }
1559
1560         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1561         if (index < 0) {
1562                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1563                 goto err_pinctrl_state;
1564         }
1565
1566         sprintf(prop_name, "pinctrl-%d", index);
1567
1568         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1569                                                          &npads);
1570         if (IS_ERR(pinctrl_state->padconf))
1571                 goto err_pinctrl_state;
1572         pinctrl_state->npads = npads;
1573
1574         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1575                                                         &niodelays);
1576         if (IS_ERR(pinctrl_state->iodelay))
1577                 goto err_padconf;
1578         pinctrl_state->niodelays = niodelays;
1579
1580         return pinctrl_state;
1581
1582 err_padconf:
1583         kfree(pinctrl_state->padconf);
1584
1585 err_pinctrl_state:
1586         kfree(pinctrl_state);
1587         return 0;
1588 }
1589
1590 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode)                 \
1591         do {                                                    \
1592                 struct omap_hsmmc_pinctrl_state *s;             \
1593                 if (!(cfg->host_caps & capmask))                \
1594                         break;                                  \
1595                                                                 \
1596                 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1597                 if (!s) {                                       \
1598                         debug("%s: no pinctrl for %s\n",        \
1599                               mmc->dev->name, #mode);           \
1600                         cfg->host_caps &= ~(capmask);           \
1601                 } else {                                        \
1602                         priv->mode##_pinctrl_state = s;         \
1603                 }                                               \
1604         } while (0)
1605
1606 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1607 {
1608         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1609         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1610         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1611
1612         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1613                 return 0;
1614
1615         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1616         if (!default_pinctrl) {
1617                 printf("no pinctrl state for default mode\n");
1618                 return -EINVAL;
1619         }
1620
1621         priv->default_pinctrl_state = default_pinctrl;
1622
1623         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104);
1624         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50);
1625         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50);
1626         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25);
1627         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12);
1628
1629         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v);
1630         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v);
1631         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs);
1632
1633         return 0;
1634 }
1635 #endif
1636
1637 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1638 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1639 {
1640         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1641         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1642
1643         struct mmc_config *cfg = &plat->cfg;
1644         const void *fdt = gd->fdt_blob;
1645         int node = dev_of_offset(dev);
1646         int ret;
1647
1648         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1649                                       sizeof(struct hsmmc *),
1650                                       MAP_NOCACHE);
1651
1652         ret = mmc_of_parse(dev, cfg);
1653         if (ret < 0)
1654                 return ret;
1655
1656         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1657         cfg->f_min = 400000;
1658         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1659         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1660         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1661                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1662         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1663                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1664         if (of_data)
1665                 plat->controller_flags |= of_data->controller_flags;
1666
1667 #ifdef OMAP_HSMMC_USE_GPIO
1668         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1669 #endif
1670
1671         return 0;
1672 }
1673 #endif
1674
1675 #ifdef CONFIG_BLK
1676
1677 static int omap_hsmmc_bind(struct udevice *dev)
1678 {
1679         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1680
1681         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1682 }
1683 #endif
1684 static int omap_hsmmc_probe(struct udevice *dev)
1685 {
1686         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1687         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1688         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1689         struct mmc_config *cfg = &plat->cfg;
1690         struct mmc *mmc;
1691 #ifdef CONFIG_IODELAY_RECALIBRATION
1692         int ret;
1693 #endif
1694
1695         cfg->name = "OMAP SD/MMC";
1696         priv->base_addr = plat->base_addr;
1697         priv->controller_flags = plat->controller_flags;
1698 #ifdef OMAP_HSMMC_USE_GPIO
1699         priv->cd_inverted = plat->cd_inverted;
1700 #endif
1701
1702 #ifdef CONFIG_BLK
1703         mmc = &plat->mmc;
1704 #else
1705         mmc = mmc_create(cfg, priv);
1706         if (mmc == NULL)
1707                 return -1;
1708 #endif
1709
1710 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1711         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1712         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1713 #endif
1714
1715         mmc->dev = dev;
1716         upriv->mmc = mmc;
1717
1718 #ifdef CONFIG_IODELAY_RECALIBRATION
1719         ret = omap_hsmmc_get_pinctrl_state(mmc);
1720         /*
1721          * disable high speed modes for the platforms that require IO delay
1722          * and for which we don't have this information
1723          */
1724         if ((ret < 0) &&
1725             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1726                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1727                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1728                                     UHS_CAPS);
1729         }
1730 #endif
1731
1732         return omap_hsmmc_init_setup(mmc);
1733 }
1734
1735 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1736
1737 static const struct omap_mmc_of_data dra7_mmc_of_data = {
1738         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
1739 };
1740
1741 static const struct udevice_id omap_hsmmc_ids[] = {
1742         { .compatible = "ti,omap3-hsmmc" },
1743         { .compatible = "ti,omap4-hsmmc" },
1744         { .compatible = "ti,am33xx-hsmmc" },
1745         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
1746         { }
1747 };
1748 #endif
1749
1750 U_BOOT_DRIVER(omap_hsmmc) = {
1751         .name   = "omap_hsmmc",
1752         .id     = UCLASS_MMC,
1753 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1754         .of_match = omap_hsmmc_ids,
1755         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1756         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1757 #endif
1758 #ifdef CONFIG_BLK
1759         .bind = omap_hsmmc_bind,
1760 #endif
1761         .ops = &omap_hsmmc_ops,
1762         .probe  = omap_hsmmc_probe,
1763         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1764         .flags  = DM_FLAG_PRE_RELOC,
1765 };
1766 #endif