drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <cpu_func.h>
  28 #include <malloc.h>
  29 #include <memalign.h>
  30 #include <mmc.h>
  31 #include <part.h>
  32 #include <i2c.h>
  33 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  34 #include <palmas.h>
  35 #endif
  36 #include <asm/io.h>
  37 #include <asm/arch/mmc_host_def.h>
  38 #ifdef CONFIG_OMAP54XX
  39 #include <asm/arch/mux_dra7xx.h>
  40 #include <asm/arch/dra7xx_iodelay.h>
  41 #endif
  42 #if !defined(CONFIG_SOC_KEYSTONE)
  43 #include <asm/gpio.h>
  44 #include <asm/arch/sys_proto.h>
  45 #endif
  46 #ifdef CONFIG_MMC_OMAP36XX_PINS
  47 #include <asm/arch/mux.h>
  48 #endif
  49 #include <dm.h>
  50 #include <dm/devres.h>
  51 #include <linux/err.h>
  52 #include <power/regulator.h>
  53 #include <thermal.h>
  54
  55 DECLARE_GLOBAL_DATA_PTR;
  56
  57 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  58 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  59         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  60 #define OMAP_HSMMC_USE_GPIO
  61 #else
  62 #undef OMAP_HSMMC_USE_GPIO
  63 #endif
  64
  65 /* common definitions for all OMAPs */
  66 #define SYSCTL_SRC      (1 << 25)
  67 #define SYSCTL_SRD      (1 << 26)
  68
  69 #ifdef CONFIG_IODELAY_RECALIBRATION
  70 struct omap_hsmmc_pinctrl_state {
  71         struct pad_conf_entry *padconf;
  72         int npads;
  73         struct iodelay_cfg_entry *iodelay;
  74         int niodelays;
  75 };
  76 #endif
  77
  78 struct omap_hsmmc_data {
  79         struct hsmmc *base_addr;
  80 #if !CONFIG_IS_ENABLED(DM_MMC)
  81         struct mmc_config cfg;
  82 #endif
  83         uint bus_width;
  84         uint clock;
  85         ushort last_cmd;
  86 #ifdef OMAP_HSMMC_USE_GPIO
  87 #if CONFIG_IS_ENABLED(DM_MMC)
  88         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  89         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  90 #else
  91         int cd_gpio;
  92         int wp_gpio;
  93 #endif
  94 #endif
  95 #if CONFIG_IS_ENABLED(DM_MMC)
  96         enum bus_mode mode;
  97 #endif
  98         u8 controller_flags;
  99 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 100         struct omap_hsmmc_adma_desc *adma_desc_table;
 101         uint desc_slot;
 102 #endif
 103         const char *hw_rev;
 104         struct udevice *pbias_supply;
 105         uint signal_voltage;
 106 #ifdef CONFIG_IODELAY_RECALIBRATION
 107         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 110         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 113         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 114         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 115         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 116 #endif
 117 };
 118
 119 struct omap_mmc_of_data {
 120         u8 controller_flags;
 121 };
 122
 123 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 124 struct omap_hsmmc_adma_desc {
 125         u8 attr;
 126         u8 reserved;
 127         u16 len;
 128         u32 addr;
 129 };
 130
 131 #define ADMA_MAX_LEN    63488
 132
 133 /* Decriptor table defines */
 134 #define ADMA_DESC_ATTR_VALID            BIT(0)
 135 #define ADMA_DESC_ATTR_END              BIT(1)
 136 #define ADMA_DESC_ATTR_INT              BIT(2)
 137 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 138 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 139
 140 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 141 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 142 #endif
 143
 144 /* If we fail after 1 second wait, something is really bad */
 145 #define MAX_RETRY_MS    1000
 146 #define MMC_TIMEOUT_MS  20
 147
 148 /* DMA transfers can take a long time if a lot a data is transferred.
 149  * The timeout must take in account the amount of data. Let's assume
 150  * that the time will never exceed 333 ms per MB (in other word we assume
 151  * that the bandwidth is always above 3MB/s).
 152  */
 153 #define DMA_TIMEOUT_PER_MB      333
 154 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 155 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 156 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 157 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 158
 159 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 160 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 161                         unsigned int siz);
 162 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 163 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 164 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 165
 166 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 167 {
 168 #if CONFIG_IS_ENABLED(DM_MMC)
 169         return dev_get_priv(mmc->dev);
 170 #else
 171         return (struct omap_hsmmc_data *)mmc->priv;
 172 #endif
 173 }
 174 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 175 {
 176 #if CONFIG_IS_ENABLED(DM_MMC)
 177         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 178         return &plat->cfg;
 179 #else
 180         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 181 #endif
 182 }
 183
 184 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 185 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 186 {
 187         int ret;
 188
 189 #if !CONFIG_IS_ENABLED(DM_GPIO)
 190         if (!gpio_is_valid(gpio))
 191                 return -1;
 192 #endif
 193         ret = gpio_request(gpio, label);
 194         if (ret)
 195                 return ret;
 196
 197         ret = gpio_direction_input(gpio);
 198         if (ret)
 199                 return ret;
 200
 201         return gpio;
 202 }
 203 #endif
 204
 205 static unsigned char mmc_board_init(struct mmc *mmc)
 206 {
 207 #if defined(CONFIG_OMAP34XX)
 208         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 209         t2_t *t2_base = (t2_t *)T2_BASE;
 210         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 211         u32 pbias_lite;
 212 #ifdef CONFIG_MMC_OMAP36XX_PINS
 213         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 214 #endif
 215
 216         pbias_lite = readl(&t2_base->pbias_lite);
 217         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 218 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 219         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 220         pbias_lite &= ~PBIASLITEVMODE0;
 221 #endif
 222 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 223         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 224         pbias_lite &= ~PBIASLITEVMODE1;
 225 #endif
 226 #ifdef CONFIG_MMC_OMAP36XX_PINS
 227         if (get_cpu_family() == CPU_OMAP36XX) {
 228                 /* Disable extended drain IO before changing PBIAS */
 229                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 230                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 231         }
 232 #endif
 233         writel(pbias_lite, &t2_base->pbias_lite);
 234
 235         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 236                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 237                 &t2_base->pbias_lite);
 238
 239 #ifdef CONFIG_MMC_OMAP36XX_PINS
 240         if (get_cpu_family() == CPU_OMAP36XX)
 241                 /* Enable extended drain IO after changing PBIAS */
 242                 writel(wkup_ctrl |
 243                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 244                                 OMAP34XX_CTRL_WKUP_CTRL);
 245 #endif
 246         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 247                 &t2_base->devconf0);
 248
 249         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 250                 &t2_base->devconf1);
 251
 252         /* Change from default of 52MHz to 26MHz if necessary */
 253         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 254                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 255                         &t2_base->ctl_prog_io1);
 256
 257         writel(readl(&prcm_base->fclken1_core) |
 258                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 259                 &prcm_base->fclken1_core);
 260
 261         writel(readl(&prcm_base->iclken1_core) |
 262                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 263                 &prcm_base->iclken1_core);
 264 #endif
 265
 266 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 267         !CONFIG_IS_ENABLED(DM_REGULATOR)
 268         /* PBIAS config needed for MMC1 only */
 269         if (mmc_get_blk_desc(mmc)->devnum == 0)
 270                 vmmc_pbias_config(LDO_VOLT_3V3);
 271 #endif
 272
 273         return 0;
 274 }
 275
 276 void mmc_init_stream(struct hsmmc *mmc_base)
 277 {
 278         ulong start;
 279
 280         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 281
 282         writel(MMC_CMD0, &mmc_base->cmd);
 283         start = get_timer(0);
 284         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 285                 if (get_timer(0) - start > MAX_RETRY_MS) {
 286                         printf("%s: timedout waiting for cc!\n", __func__);
 287                         return;
 288                 }
 289         }
 290         writel(CC_MASK, &mmc_base->stat)
 291                 ;
 292         writel(MMC_CMD0, &mmc_base->cmd)
 293                 ;
 294         start = get_timer(0);
 295         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 296                 if (get_timer(0) - start > MAX_RETRY_MS) {
 297                         printf("%s: timedout waiting for cc2!\n", __func__);
 298                         return;
 299                 }
 300         }
 301         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 302 }
 303
 304 #if CONFIG_IS_ENABLED(DM_MMC)
 305 #ifdef CONFIG_IODELAY_RECALIBRATION
 306 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 307 {
 308         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 309         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 310
 311         switch (priv->mode) {
 312         case MMC_HS_200:
 313                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 314                 break;
 315         case UHS_SDR104:
 316                 pinctrl_state = priv->sdr104_pinctrl_state;
 317                 break;
 318         case UHS_SDR50:
 319                 pinctrl_state = priv->sdr50_pinctrl_state;
 320                 break;
 321         case UHS_DDR50:
 322                 pinctrl_state = priv->ddr50_pinctrl_state;
 323                 break;
 324         case UHS_SDR25:
 325                 pinctrl_state = priv->sdr25_pinctrl_state;
 326                 break;
 327         case UHS_SDR12:
 328                 pinctrl_state = priv->sdr12_pinctrl_state;
 329                 break;
 330         case SD_HS:
 331         case MMC_HS:
 332         case MMC_HS_52:
 333                 pinctrl_state = priv->hs_pinctrl_state;
 334                 break;
 335         case MMC_DDR_52:
 336                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 337         default:
 338                 pinctrl_state = priv->default_pinctrl_state;
 339                 break;
 340         }
 341
 342         if (!pinctrl_state)
 343                 pinctrl_state = priv->default_pinctrl_state;
 344
 345         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 346                 if (pinctrl_state->iodelay)
 347                         late_recalibrate_iodelay(pinctrl_state->padconf,
 348                                                  pinctrl_state->npads,
 349                                                  pinctrl_state->iodelay,
 350                                                  pinctrl_state->niodelays);
 351                 else
 352                         do_set_mux32((*ctrl)->control_padconf_core_base,
 353                                      pinctrl_state->padconf,
 354                                      pinctrl_state->npads);
 355         }
 356 }
 357 #endif
 358 static void omap_hsmmc_set_timing(struct mmc *mmc)
 359 {
 360         u32 val;
 361         struct hsmmc *mmc_base;
 362         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 363
 364         mmc_base = priv->base_addr;
 365
 366         omap_hsmmc_stop_clock(mmc_base);
 367         val = readl(&mmc_base->ac12);
 368         val &= ~AC12_UHSMC_MASK;
 369         priv->mode = mmc->selected_mode;
 370
 371         if (mmc_is_mode_ddr(priv->mode))
 372                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 373         else
 374                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 375
 376         switch (priv->mode) {
 377         case MMC_HS_200:
 378         case UHS_SDR104:
 379                 val |= AC12_UHSMC_SDR104;
 380                 break;
 381         case UHS_SDR50:
 382                 val |= AC12_UHSMC_SDR50;
 383                 break;
 384         case MMC_DDR_52:
 385         case UHS_DDR50:
 386                 val |= AC12_UHSMC_DDR50;
 387                 break;
 388         case SD_HS:
 389         case MMC_HS_52:
 390         case UHS_SDR25:
 391                 val |= AC12_UHSMC_SDR25;
 392                 break;
 393         case MMC_LEGACY:
 394         case MMC_HS:
 395         case UHS_SDR12:
 396                 val |= AC12_UHSMC_SDR12;
 397                 break;
 398         default:
 399                 val |= AC12_UHSMC_RES;
 400                 break;
 401         }
 402         writel(val, &mmc_base->ac12);
 403
 404 #ifdef CONFIG_IODELAY_RECALIBRATION
 405         omap_hsmmc_io_recalibrate(mmc);
 406 #endif
 407         omap_hsmmc_start_clock(mmc_base);
 408 }
 409
 410 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 411 {
 412         struct hsmmc *mmc_base;
 413         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 414         u32 hctl, ac12;
 415
 416         mmc_base = priv->base_addr;
 417
 418         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 419         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 420
 421         switch (signal_voltage) {
 422         case MMC_SIGNAL_VOLTAGE_330:
 423                 hctl |= SDVS_3V3;
 424                 break;
 425         case MMC_SIGNAL_VOLTAGE_180:
 426                 hctl |= SDVS_1V8;
 427                 ac12 |= AC12_V1V8_SIGEN;
 428                 break;
 429         }
 430
 431         writel(hctl, &mmc_base->hctl);
 432         writel(ac12, &mmc_base->ac12);
 433 }
 434
 435 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
 436 {
 437         int ret = -ETIMEDOUT;
 438         u32 con;
 439         bool dat0_high;
 440         bool target_dat0_high = !!state;
 441         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 442         struct hsmmc *mmc_base = priv->base_addr;
 443
 444         con = readl(&mmc_base->con);
 445         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 446
 447         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 448         while (timeout_us--) {
 449                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 450                 if (dat0_high == target_dat0_high) {
 451                         ret = 0;
 452                         break;
 453                 }
 454                 udelay(10);
 455         }
 456         writel(con, &mmc_base->con);
 457
 458         return ret;
 459 }
 460
 461 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 462 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 463 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 464 {
 465         int ret = 0;
 466         int uV = mV * 1000;
 467
 468         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 469
 470         if (!mmc->vqmmc_supply)
 471                 return 0;
 472
 473         /* Disable PBIAS */
 474         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 475         if (ret)
 476                 return ret;
 477
 478         /* Turn off IO voltage */
 479         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 480         if (ret)
 481                 return ret;
 482         /* Program a new IO voltage value */
 483         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 484         if (ret)
 485                 return ret;
 486         /* Turn on IO voltage */
 487         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 488         if (ret)
 489                 return ret;
 490
 491         /* Program PBIAS voltage*/
 492         ret = regulator_set_value(priv->pbias_supply, uV);
 493         if (ret && ret != -ENOSYS)
 494                 return ret;
 495         /* Enable PBIAS */
 496         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 497         if (ret)
 498                 return ret;
 499
 500         return 0;
 501 }
 502 #endif
 503
 504 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 505 {
 506         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 507         struct hsmmc *mmc_base = priv->base_addr;
 508         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 509         u32 capa_mask;
 510         __maybe_unused u8 palmas_ldo_volt;
 511         u32 val;
 512
 513         if (mv < 0)
 514                 return -EINVAL;
 515
 516         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 517                 mv = 3300;
 518                 capa_mask = VS33_3V3SUP;
 519                 palmas_ldo_volt = LDO_VOLT_3V3;
 520         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 521                 capa_mask = VS18_1V8SUP;
 522                 palmas_ldo_volt = LDO_VOLT_1V8;
 523         } else {
 524                 return -EOPNOTSUPP;
 525         }
 526
 527         val = readl(&mmc_base->capa);
 528         if (!(val & capa_mask))
 529                 return -EOPNOTSUPP;
 530
 531         priv->signal_voltage = mmc->signal_voltage;
 532
 533         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 534
 535 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 536         return omap_hsmmc_set_io_regulator(mmc, mv);
 537 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 538         defined(CONFIG_PALMAS_POWER)
 539         if (mmc_get_blk_desc(mmc)->devnum == 0)
 540                 vmmc_pbias_config(palmas_ldo_volt);
 541         return 0;
 542 #else
 543         return 0;
 544 #endif
 545 }
 546 #endif
 547
 548 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 549 {
 550         struct hsmmc *mmc_base;
 551         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 552         u32 val;
 553
 554         mmc_base = priv->base_addr;
 555         val = readl(&mmc_base->capa);
 556
 557         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 558                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 559         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 560                 val |= VS33_3V3SUP;
 561                 val &= ~VS18_1V8SUP;
 562         } else {
 563                 val |= VS18_1V8SUP;
 564                 val &= ~VS33_3V3SUP;
 565         }
 566
 567         writel(val, &mmc_base->capa);
 568
 569         return val;
 570 }
 571
 572 #ifdef MMC_SUPPORTS_TUNING
 573 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 574 {
 575         struct hsmmc *mmc_base;
 576         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 577         u32 val;
 578
 579         mmc_base = priv->base_addr;
 580         val = readl(&mmc_base->ac12);
 581         val &= ~(AC12_SCLK_SEL);
 582         writel(val, &mmc_base->ac12);
 583
 584         val = readl(&mmc_base->dll);
 585         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 586         writel(val, &mmc_base->dll);
 587 }
 588
 589 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 590 {
 591         int i;
 592         struct hsmmc *mmc_base;
 593         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 594         u32 val;
 595
 596         mmc_base = priv->base_addr;
 597         val = readl(&mmc_base->dll);
 598         val |= DLL_FORCE_VALUE;
 599         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 600         val |= (count << DLL_FORCE_SR_C_SHIFT);
 601         writel(val, &mmc_base->dll);
 602
 603         val |= DLL_CALIB;
 604         writel(val, &mmc_base->dll);
 605         for (i = 0; i < 1000; i++) {
 606                 if (readl(&mmc_base->dll) & DLL_CALIB)
 607                         break;
 608         }
 609         val &= ~DLL_CALIB;
 610         writel(val, &mmc_base->dll);
 611 }
 612
 613 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 614 {
 615         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 616         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 617         struct mmc *mmc = upriv->mmc;
 618         struct hsmmc *mmc_base;
 619         u32 val;
 620         u8 cur_match, prev_match = 0;
 621         int ret;
 622         u32 phase_delay = 0;
 623         u32 start_window = 0, max_window = 0;
 624         u32 length = 0, max_len = 0;
 625         bool single_point_failure = false;
 626         struct udevice *thermal_dev;
 627         int temperature;
 628         int i;
 629
 630         mmc_base = priv->base_addr;
 631         val = readl(&mmc_base->capa2);
 632
 633         /* clock tuning is not needed for upto 52MHz */
 634         if (!((mmc->selected_mode == MMC_HS_200) ||
 635               (mmc->selected_mode == UHS_SDR104) ||
 636               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 637                 return 0;
 638
 639         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 640         if (ret) {
 641                 printf("Couldn't get thermal device for tuning\n");
 642                 return ret;
 643         }
 644         ret = thermal_get_temp(thermal_dev, &temperature);
 645         if (ret) {
 646                 printf("Couldn't get temperature for tuning\n");
 647                 return ret;
 648         }
 649         val = readl(&mmc_base->dll);
 650         val |= DLL_SWT;
 651         writel(val, &mmc_base->dll);
 652
 653         /*
 654          * Stage 1: Search for a maximum pass window ignoring any
 655          * any single point failures. If the tuning value ends up
 656          * near it, move away from it in stage 2 below
 657          */
 658         while (phase_delay <= MAX_PHASE_DELAY) {
 659                 omap_hsmmc_set_dll(mmc, phase_delay);
 660
 661                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 662
 663                 if (cur_match) {
 664                         if (prev_match) {
 665                                 length++;
 666                         } else if (single_point_failure) {
 667                                 /* ignore single point failure */
 668                                 length++;
 669                                 single_point_failure = false;
 670                         } else {
 671                                 start_window = phase_delay;
 672                                 length = 1;
 673                         }
 674                 } else {
 675                         single_point_failure = prev_match;
 676                 }
 677
 678                 if (length > max_len) {
 679                         max_window = start_window;
 680                         max_len = length;
 681                 }
 682
 683                 prev_match = cur_match;
 684                 phase_delay += 4;
 685         }
 686
 687         if (!max_len) {
 688                 ret = -EIO;
 689                 goto tuning_error;
 690         }
 691
 692         val = readl(&mmc_base->ac12);
 693         if (!(val & AC12_SCLK_SEL)) {
 694                 ret = -EIO;
 695                 goto tuning_error;
 696         }
 697         /*
 698          * Assign tuning value as a ratio of maximum pass window based
 699          * on temperature
 700          */
 701         if (temperature < -20000)
 702                 phase_delay = min(max_window + 4 * max_len - 24,
 703                                   max_window +
 704                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 705         else if (temperature < 20000)
 706                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 707         else if (temperature < 40000)
 708                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 709         else if (temperature < 70000)
 710                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 711         else if (temperature < 90000)
 712                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 713         else if (temperature < 120000)
 714                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 715         else
 716                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 717
 718         /*
 719          * Stage 2: Search for a single point failure near the chosen tuning
 720          * value in two steps. First in the +3 to +10 range and then in the
 721          * +2 to -10 range. If found, move away from it in the appropriate
 722          * direction by the appropriate amount depending on the temperature.
 723          */
 724         for (i = 3; i <= 10; i++) {
 725                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 726                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 727                         if (temperature < 10000)
 728                                 phase_delay += i + 6;
 729                         else if (temperature < 20000)
 730                                 phase_delay += i - 12;
 731                         else if (temperature < 70000)
 732                                 phase_delay += i - 8;
 733                         else if (temperature < 90000)
 734                                 phase_delay += i - 6;
 735                         else
 736                                 phase_delay += i - 6;
 737
 738                         goto single_failure_found;
 739                 }
 740         }
 741
 742         for (i = 2; i >= -10; i--) {
 743                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 744                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 745                         if (temperature < 10000)
 746                                 phase_delay += i + 12;
 747                         else if (temperature < 20000)
 748                                 phase_delay += i + 8;
 749                         else if (temperature < 70000)
 750                                 phase_delay += i + 8;
 751                         else if (temperature < 90000)
 752                                 phase_delay += i + 10;
 753                         else
 754                                 phase_delay += i + 12;
 755
 756                         goto single_failure_found;
 757                 }
 758         }
 759
 760 single_failure_found:
 761
 762         omap_hsmmc_set_dll(mmc, phase_delay);
 763
 764         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 765         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 766
 767         return 0;
 768
 769 tuning_error:
 770
 771         omap_hsmmc_disable_tuning(mmc);
 772         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 773         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 774
 775         return ret;
 776 }
 777 #endif
 778 #endif
 779
 780 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 781 {
 782         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 783         struct hsmmc *mmc_base = priv->base_addr;
 784         u32 irq_mask = INT_EN_MASK;
 785
 786         /*
 787          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 788          * tuning procedure and DCRC should be disabled. But see occurences
 789          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 790          * interrupts occur along with BRR, so the data is actually in the
 791          * buffer. It has to be debugged why these interrutps occur
 792          */
 793         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 794                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 795
 796         writel(irq_mask, &mmc_base->ie);
 797 }
 798
 799 static int omap_hsmmc_init_setup(struct mmc *mmc)
 800 {
 801         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 802         struct hsmmc *mmc_base;
 803         unsigned int reg_val;
 804         unsigned int dsor;
 805         ulong start;
 806
 807         mmc_base = priv->base_addr;
 808         mmc_board_init(mmc);
 809
 810         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 811                 &mmc_base->sysconfig);
 812         start = get_timer(0);
 813         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 814                 if (get_timer(0) - start > MAX_RETRY_MS) {
 815                         printf("%s: timedout waiting for cc2!\n", __func__);
 816                         return -ETIMEDOUT;
 817                 }
 818         }
 819         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 820         start = get_timer(0);
 821         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 822                 if (get_timer(0) - start > MAX_RETRY_MS) {
 823                         printf("%s: timedout waiting for softresetall!\n",
 824                                 __func__);
 825                         return -ETIMEDOUT;
 826                 }
 827         }
 828 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 829         reg_val = readl(&mmc_base->hl_hwinfo);
 830         if (reg_val & MADMA_EN)
 831                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 832 #endif
 833
 834 #if CONFIG_IS_ENABLED(DM_MMC)
 835         reg_val = omap_hsmmc_set_capabilities(mmc);
 836         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 837                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 838 #else
 839         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 840         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 841                 &mmc_base->capa);
 842 #endif
 843
 844         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 845
 846         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 847                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 848                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 849
 850         dsor = 240;
 851         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 852                 (ICE_STOP | DTO_15THDTO));
 853         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 854                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 855         start = get_timer(0);
 856         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 857                 if (get_timer(0) - start > MAX_RETRY_MS) {
 858                         printf("%s: timedout waiting for ics!\n", __func__);
 859                         return -ETIMEDOUT;
 860                 }
 861         }
 862         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 863
 864         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 865
 866         mmc_enable_irq(mmc, NULL);
 867
 868 #if !CONFIG_IS_ENABLED(DM_MMC)
 869         mmc_init_stream(mmc_base);
 870 #endif
 871
 872         return 0;
 873 }
 874
 875 /*
 876  * MMC controller internal finite state machine reset
 877  *
 878  * Used to reset command or data internal state machines, using respectively
 879  * SRC or SRD bit of SYSCTL register
 880  */
 881 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 882 {
 883         ulong start;
 884
 885         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 886
 887         /*
 888          * CMD(DAT) lines reset procedures are slightly different
 889          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 890          * According to OMAP3 TRM:
 891          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 892          * returns to 0x0.
 893          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 894          * procedure steps must be as follows:
 895          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 896          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 897          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 898          * 3. Wait until the SRC (SRD) bit returns to 0x0
 899          *    (reset procedure is completed).
 900          */
 901 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 902         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 903         if (!(readl(&mmc_base->sysctl) & bit)) {
 904                 start = get_timer(0);
 905                 while (!(readl(&mmc_base->sysctl) & bit)) {
 906                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 907                                 return;
 908                 }
 909         }
 910 #endif
 911         start = get_timer(0);
 912         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 913                 if (get_timer(0) - start > MAX_RETRY_MS) {
 914                         printf("%s: timedout waiting for sysctl %x to clear\n",
 915                                 __func__, bit);
 916                         return;
 917                 }
 918         }
 919 }
 920
 921 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 922 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 923 {
 924         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 925         struct omap_hsmmc_adma_desc *desc;
 926         u8 attr;
 927
 928         desc = &priv->adma_desc_table[priv->desc_slot];
 929
 930         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 931         if (!end)
 932                 priv->desc_slot++;
 933         else
 934                 attr |= ADMA_DESC_ATTR_END;
 935
 936         desc->len = len;
 937         desc->addr = (u32)buf;
 938         desc->reserved = 0;
 939         desc->attr = attr;
 940 }
 941
 942 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 943                                           struct mmc_data *data)
 944 {
 945         uint total_len = data->blocksize * data->blocks;
 946         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 947         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 948         int i = desc_count;
 949         char *buf;
 950
 951         priv->desc_slot = 0;
 952         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 953                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 954                                 sizeof(struct omap_hsmmc_adma_desc));
 955
 956         if (data->flags & MMC_DATA_READ)
 957                 buf = data->dest;
 958         else
 959                 buf = (char *)data->src;
 960
 961         while (--i) {
 962                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 963                 buf += ADMA_MAX_LEN;
 964                 total_len -= ADMA_MAX_LEN;
 965         }
 966
 967         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 968
 969         flush_dcache_range((long)priv->adma_desc_table,
 970                            (long)priv->adma_desc_table +
 971                            ROUND(desc_count *
 972                            sizeof(struct omap_hsmmc_adma_desc),
 973                            ARCH_DMA_MINALIGN));
 974 }
 975
 976 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 977 {
 978         struct hsmmc *mmc_base;
 979         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 980         u32 val;
 981         char *buf;
 982
 983         mmc_base = priv->base_addr;
 984         omap_hsmmc_prepare_adma_table(mmc, data);
 985
 986         if (data->flags & MMC_DATA_READ)
 987                 buf = data->dest;
 988         else
 989                 buf = (char *)data->src;
 990
 991         val = readl(&mmc_base->hctl);
 992         val |= DMA_SELECT;
 993         writel(val, &mmc_base->hctl);
 994
 995         val = readl(&mmc_base->con);
 996         val |= DMA_MASTER;
 997         writel(val, &mmc_base->con);
 998
 999         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1000
1001         flush_dcache_range((u32)buf,
1002                            (u32)buf +
1003                            ROUND(data->blocksize * data->blocks,
1004                                  ARCH_DMA_MINALIGN));
1005 }
1006
1007 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1008 {
1009         struct hsmmc *mmc_base;
1010         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1011         u32 val;
1012
1013         mmc_base = priv->base_addr;
1014
1015         val = readl(&mmc_base->con);
1016         val &= ~DMA_MASTER;
1017         writel(val, &mmc_base->con);
1018
1019         val = readl(&mmc_base->hctl);
1020         val &= ~DMA_SELECT;
1021         writel(val, &mmc_base->hctl);
1022
1023         kfree(priv->adma_desc_table);
1024 }
1025 #else
1026 #define omap_hsmmc_adma_desc
1027 #define omap_hsmmc_prepare_adma_table
1028 #define omap_hsmmc_prepare_data
1029 #define omap_hsmmc_dma_cleanup
1030 #endif
1031
1032 #if !CONFIG_IS_ENABLED(DM_MMC)
1033 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1034                         struct mmc_data *data)
1035 {
1036         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1037 #else
1038 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1039                         struct mmc_data *data)
1040 {
1041         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1042         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1043         struct mmc *mmc = upriv->mmc;
1044 #endif
1045         struct hsmmc *mmc_base;
1046         unsigned int flags, mmc_stat;
1047         ulong start;
1048         priv->last_cmd = cmd->cmdidx;
1049
1050         mmc_base = priv->base_addr;
1051
1052         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1053                 return 0;
1054
1055         start = get_timer(0);
1056         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1057                 if (get_timer(0) - start > MAX_RETRY_MS) {
1058                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1059                                         __func__);
1060                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1061                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1062                         return -ETIMEDOUT;
1063                 }
1064         }
1065         writel(0xFFFFFFFF, &mmc_base->stat);
1066         if (readl(&mmc_base->stat)) {
1067                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1068                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1069         }
1070
1071         /*
1072          * CMDREG
1073          * CMDIDX[13:8] : Command index
1074          * DATAPRNT[5]  : Data Present Select
1075          * ENCMDIDX[4]  : Command Index Check Enable
1076          * ENCMDCRC[3]  : Command CRC Check Enable
1077          * RSPTYP[1:0]
1078          *      00 = No Response
1079          *      01 = Length 136
1080          *      10 = Length 48
1081          *      11 = Length 48 Check busy after response
1082          */
1083         /* Delay added before checking the status of frq change
1084          * retry not supported by mmc.c(core file)
1085          */
1086         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1087                 udelay(50000); /* wait 50 ms */
1088
1089         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1090                 flags = 0;
1091         else if (cmd->resp_type & MMC_RSP_136)
1092                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1093         else if (cmd->resp_type & MMC_RSP_BUSY)
1094                 flags = RSP_TYPE_LGHT48B;
1095         else
1096                 flags = RSP_TYPE_LGHT48;
1097
1098         /* enable default flags */
1099         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1100                         MSBS_SGLEBLK);
1101         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1102
1103         if (cmd->resp_type & MMC_RSP_CRC)
1104                 flags |= CCCE_CHECK;
1105         if (cmd->resp_type & MMC_RSP_OPCODE)
1106                 flags |= CICE_CHECK;
1107
1108         if (data) {
1109                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1110                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1111                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1112                         data->blocksize = 512;
1113                         writel(data->blocksize | (data->blocks << 16),
1114                                                         &mmc_base->blk);
1115                 } else
1116                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1117
1118                 if (data->flags & MMC_DATA_READ)
1119                         flags |= (DP_DATA | DDIR_READ);
1120                 else
1121                         flags |= (DP_DATA | DDIR_WRITE);
1122
1123 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1124                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1125                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1126                         omap_hsmmc_prepare_data(mmc, data);
1127                         flags |= DE_ENABLE;
1128                 }
1129 #endif
1130         }
1131
1132         mmc_enable_irq(mmc, cmd);
1133
1134         writel(cmd->cmdarg, &mmc_base->arg);
1135         udelay(20);             /* To fix "No status update" error on eMMC */
1136         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1137
1138         start = get_timer(0);
1139         do {
1140                 mmc_stat = readl(&mmc_base->stat);
1141                 if (get_timer(start) > MAX_RETRY_MS) {
1142                         printf("%s : timeout: No status update\n", __func__);
1143                         return -ETIMEDOUT;
1144                 }
1145         } while (!mmc_stat);
1146
1147         if ((mmc_stat & IE_CTO) != 0) {
1148                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1149                 return -ETIMEDOUT;
1150         } else if ((mmc_stat & ERRI_MASK) != 0)
1151                 return -1;
1152
1153         if (mmc_stat & CC_MASK) {
1154                 writel(CC_MASK, &mmc_base->stat);
1155                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1156                         if (cmd->resp_type & MMC_RSP_136) {
1157                                 /* response type 2 */
1158                                 cmd->response[3] = readl(&mmc_base->rsp10);
1159                                 cmd->response[2] = readl(&mmc_base->rsp32);
1160                                 cmd->response[1] = readl(&mmc_base->rsp54);
1161                                 cmd->response[0] = readl(&mmc_base->rsp76);
1162                         } else
1163                                 /* response types 1, 1b, 3, 4, 5, 6 */
1164                                 cmd->response[0] = readl(&mmc_base->rsp10);
1165                 }
1166         }
1167
1168 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1169         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1170             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1171                 u32 sz_mb, timeout;
1172
1173                 if (mmc_stat & IE_ADMAE) {
1174                         omap_hsmmc_dma_cleanup(mmc);
1175                         return -EIO;
1176                 }
1177
1178                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1179                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1180                 if (timeout < MAX_RETRY_MS)
1181                         timeout = MAX_RETRY_MS;
1182
1183                 start = get_timer(0);
1184                 do {
1185                         mmc_stat = readl(&mmc_base->stat);
1186                         if (mmc_stat & TC_MASK) {
1187                                 writel(readl(&mmc_base->stat) | TC_MASK,
1188                                        &mmc_base->stat);
1189                                 break;
1190                         }
1191                         if (get_timer(start) > timeout) {
1192                                 printf("%s : DMA timeout: No status update\n",
1193                                        __func__);
1194                                 return -ETIMEDOUT;
1195                         }
1196                 } while (1);
1197
1198                 omap_hsmmc_dma_cleanup(mmc);
1199                 return 0;
1200         }
1201 #endif
1202
1203         if (data && (data->flags & MMC_DATA_READ)) {
1204                 mmc_read_data(mmc_base, data->dest,
1205                                 data->blocksize * data->blocks);
1206         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1207                 mmc_write_data(mmc_base, data->src,
1208                                 data->blocksize * data->blocks);
1209         }
1210         return 0;
1211 }
1212
1213 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1214 {
1215         unsigned int *output_buf = (unsigned int *)buf;
1216         unsigned int mmc_stat;
1217         unsigned int count;
1218
1219         /*
1220          * Start Polled Read
1221          */
1222         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1223         count /= 4;
1224
1225         while (size) {
1226                 ulong start = get_timer(0);
1227                 do {
1228                         mmc_stat = readl(&mmc_base->stat);
1229                         if (get_timer(0) - start > MAX_RETRY_MS) {
1230                                 printf("%s: timedout waiting for status!\n",
1231                                                 __func__);
1232                                 return -ETIMEDOUT;
1233                         }
1234                 } while (mmc_stat == 0);
1235
1236                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1237                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1238
1239                 if ((mmc_stat & ERRI_MASK) != 0)
1240                         return 1;
1241
1242                 if (mmc_stat & BRR_MASK) {
1243                         unsigned int k;
1244
1245                         writel(readl(&mmc_base->stat) | BRR_MASK,
1246                                 &mmc_base->stat);
1247                         for (k = 0; k < count; k++) {
1248                                 *output_buf = readl(&mmc_base->data);
1249                                 output_buf++;
1250                         }
1251                         size -= (count*4);
1252                 }
1253
1254                 if (mmc_stat & BWR_MASK)
1255                         writel(readl(&mmc_base->stat) | BWR_MASK,
1256                                 &mmc_base->stat);
1257
1258                 if (mmc_stat & TC_MASK) {
1259                         writel(readl(&mmc_base->stat) | TC_MASK,
1260                                 &mmc_base->stat);
1261                         break;
1262                 }
1263         }
1264         return 0;
1265 }
1266
1267 #if CONFIG_IS_ENABLED(MMC_WRITE)
1268 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1269                           unsigned int size)
1270 {
1271         unsigned int *input_buf = (unsigned int *)buf;
1272         unsigned int mmc_stat;
1273         unsigned int count;
1274
1275         /*
1276          * Start Polled Write
1277          */
1278         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1279         count /= 4;
1280
1281         while (size) {
1282                 ulong start = get_timer(0);
1283                 do {
1284                         mmc_stat = readl(&mmc_base->stat);
1285                         if (get_timer(0) - start > MAX_RETRY_MS) {
1286                                 printf("%s: timedout waiting for status!\n",
1287                                                 __func__);
1288                                 return -ETIMEDOUT;
1289                         }
1290                 } while (mmc_stat == 0);
1291
1292                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1293                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1294
1295                 if ((mmc_stat & ERRI_MASK) != 0)
1296                         return 1;
1297
1298                 if (mmc_stat & BWR_MASK) {
1299                         unsigned int k;
1300
1301                         writel(readl(&mmc_base->stat) | BWR_MASK,
1302                                         &mmc_base->stat);
1303                         for (k = 0; k < count; k++) {
1304                                 writel(*input_buf, &mmc_base->data);
1305                                 input_buf++;
1306                         }
1307                         size -= (count*4);
1308                 }
1309
1310                 if (mmc_stat & BRR_MASK)
1311                         writel(readl(&mmc_base->stat) | BRR_MASK,
1312                                 &mmc_base->stat);
1313
1314                 if (mmc_stat & TC_MASK) {
1315                         writel(readl(&mmc_base->stat) | TC_MASK,
1316                                 &mmc_base->stat);
1317                         break;
1318                 }
1319         }
1320         return 0;
1321 }
1322 #else
1323 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1324                           unsigned int size)
1325 {
1326         return -ENOTSUPP;
1327 }
1328 #endif
1329 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1330 {
1331         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1332 }
1333
1334 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1335 {
1336         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1337 }
1338
1339 static void omap_hsmmc_set_clock(struct mmc *mmc)
1340 {
1341         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1342         struct hsmmc *mmc_base;
1343         unsigned int dsor = 0;
1344         ulong start;
1345
1346         mmc_base = priv->base_addr;
1347         omap_hsmmc_stop_clock(mmc_base);
1348
1349         /* TODO: Is setting DTO required here? */
1350         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1351                     (ICE_STOP | DTO_15THDTO));
1352
1353         if (mmc->clock != 0) {
1354                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1355                 if (dsor > CLKD_MAX)
1356                         dsor = CLKD_MAX;
1357         } else {
1358                 dsor = CLKD_MAX;
1359         }
1360
1361         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1362                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1363
1364         start = get_timer(0);
1365         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1366                 if (get_timer(0) - start > MAX_RETRY_MS) {
1367                         printf("%s: timedout waiting for ics!\n", __func__);
1368                         return;
1369                 }
1370         }
1371
1372         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1373         mmc->clock = priv->clock;
1374         omap_hsmmc_start_clock(mmc_base);
1375 }
1376
1377 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1378 {
1379         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1380         struct hsmmc *mmc_base;
1381
1382         mmc_base = priv->base_addr;
1383         /* configue bus width */
1384         switch (mmc->bus_width) {
1385         case 8:
1386                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1387                         &mmc_base->con);
1388                 break;
1389
1390         case 4:
1391                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1392                         &mmc_base->con);
1393                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1394                         &mmc_base->hctl);
1395                 break;
1396
1397         case 1:
1398         default:
1399                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1400                         &mmc_base->con);
1401                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1402                         &mmc_base->hctl);
1403                 break;
1404         }
1405
1406         priv->bus_width = mmc->bus_width;
1407 }
1408
1409 #if !CONFIG_IS_ENABLED(DM_MMC)
1410 static int omap_hsmmc_set_ios(struct mmc *mmc)
1411 {
1412         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1413 #else
1414 static int omap_hsmmc_set_ios(struct udevice *dev)
1415 {
1416         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1417         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1418         struct mmc *mmc = upriv->mmc;
1419 #endif
1420         struct hsmmc *mmc_base = priv->base_addr;
1421         int ret = 0;
1422
1423         if (priv->bus_width != mmc->bus_width)
1424                 omap_hsmmc_set_bus_width(mmc);
1425
1426         if (priv->clock != mmc->clock)
1427                 omap_hsmmc_set_clock(mmc);
1428
1429         if (mmc->clk_disable)
1430                 omap_hsmmc_stop_clock(mmc_base);
1431         else
1432                 omap_hsmmc_start_clock(mmc_base);
1433
1434 #if CONFIG_IS_ENABLED(DM_MMC)
1435         if (priv->mode != mmc->selected_mode)
1436                 omap_hsmmc_set_timing(mmc);
1437
1438 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1439         if (priv->signal_voltage != mmc->signal_voltage)
1440                 ret = omap_hsmmc_set_signal_voltage(mmc);
1441 #endif
1442 #endif
1443         return ret;
1444 }
1445
1446 #ifdef OMAP_HSMMC_USE_GPIO
1447 #if CONFIG_IS_ENABLED(DM_MMC)
1448 static int omap_hsmmc_getcd(struct udevice *dev)
1449 {
1450         int value = -1;
1451 #if CONFIG_IS_ENABLED(DM_GPIO)
1452         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1453         value = dm_gpio_get_value(&priv->cd_gpio);
1454 #endif
1455         /* if no CD return as 1 */
1456         if (value < 0)
1457                 return 1;
1458
1459         return value;
1460 }
1461
1462 static int omap_hsmmc_getwp(struct udevice *dev)
1463 {
1464         int value = 0;
1465 #if CONFIG_IS_ENABLED(DM_GPIO)
1466         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1467         value = dm_gpio_get_value(&priv->wp_gpio);
1468 #endif
1469         /* if no WP return as 0 */
1470         if (value < 0)
1471                 return 0;
1472         return value;
1473 }
1474 #else
1475 static int omap_hsmmc_getcd(struct mmc *mmc)
1476 {
1477         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1478         int cd_gpio;
1479
1480         /* if no CD return as 1 */
1481         cd_gpio = priv->cd_gpio;
1482         if (cd_gpio < 0)
1483                 return 1;
1484
1485         /* NOTE: assumes card detect signal is active-low */
1486         return !gpio_get_value(cd_gpio);
1487 }
1488
1489 static int omap_hsmmc_getwp(struct mmc *mmc)
1490 {
1491         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1492         int wp_gpio;
1493
1494         /* if no WP return as 0 */
1495         wp_gpio = priv->wp_gpio;
1496         if (wp_gpio < 0)
1497                 return 0;
1498
1499         /* NOTE: assumes write protect signal is active-high */
1500         return gpio_get_value(wp_gpio);
1501 }
1502 #endif
1503 #endif
1504
1505 #if CONFIG_IS_ENABLED(DM_MMC)
1506 static const struct dm_mmc_ops omap_hsmmc_ops = {
1507         .send_cmd       = omap_hsmmc_send_cmd,
1508         .set_ios        = omap_hsmmc_set_ios,
1509 #ifdef OMAP_HSMMC_USE_GPIO
1510         .get_cd         = omap_hsmmc_getcd,
1511         .get_wp         = omap_hsmmc_getwp,
1512 #endif
1513 #ifdef MMC_SUPPORTS_TUNING
1514         .execute_tuning = omap_hsmmc_execute_tuning,
1515 #endif
1516         .wait_dat0      = omap_hsmmc_wait_dat0,
1517 };
1518 #else
1519 static const struct mmc_ops omap_hsmmc_ops = {
1520         .send_cmd       = omap_hsmmc_send_cmd,
1521         .set_ios        = omap_hsmmc_set_ios,
1522         .init           = omap_hsmmc_init_setup,
1523 #ifdef OMAP_HSMMC_USE_GPIO
1524         .getcd          = omap_hsmmc_getcd,
1525         .getwp          = omap_hsmmc_getwp,
1526 #endif
1527 };
1528 #endif
1529
1530 #if !CONFIG_IS_ENABLED(DM_MMC)
1531 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1532                 int wp_gpio)
1533 {
1534         struct mmc *mmc;
1535         struct omap_hsmmc_data *priv;
1536         struct mmc_config *cfg;
1537         uint host_caps_val;
1538
1539         priv = calloc(1, sizeof(*priv));
1540         if (priv == NULL)
1541                 return -1;
1542
1543         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1544
1545         switch (dev_index) {
1546         case 0:
1547                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1548                 break;
1549 #ifdef OMAP_HSMMC2_BASE
1550         case 1:
1551                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1552 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1553         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1554         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1555                 defined(CONFIG_HSMMC2_8BIT)
1556                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1557                 host_caps_val |= MMC_MODE_8BIT;
1558 #endif
1559                 break;
1560 #endif
1561 #ifdef OMAP_HSMMC3_BASE
1562         case 2:
1563                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1564 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1565                 /* Enable 8-bit interface for eMMC on DRA7XX */
1566                 host_caps_val |= MMC_MODE_8BIT;
1567 #endif
1568                 break;
1569 #endif
1570         default:
1571                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1572                 return 1;
1573         }
1574 #ifdef OMAP_HSMMC_USE_GPIO
1575         /* on error gpio values are set to -1, which is what we want */
1576         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1577         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1578 #endif
1579
1580         cfg = &priv->cfg;
1581
1582         cfg->name = "OMAP SD/MMC";
1583         cfg->ops = &omap_hsmmc_ops;
1584
1585         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1586         cfg->host_caps = host_caps_val & ~host_caps_mask;
1587
1588         cfg->f_min = 400000;
1589
1590         if (f_max != 0)
1591                 cfg->f_max = f_max;
1592         else {
1593                 if (cfg->host_caps & MMC_MODE_HS) {
1594                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1595                                 cfg->f_max = 52000000;
1596                         else
1597                                 cfg->f_max = 26000000;
1598                 } else
1599                         cfg->f_max = 20000000;
1600         }
1601
1602         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1603
1604 #if defined(CONFIG_OMAP34XX)
1605         /*
1606          * Silicon revs 2.1 and older do not support multiblock transfers.
1607          */
1608         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1609                 cfg->b_max = 1;
1610 #endif
1611
1612         mmc = mmc_create(cfg, priv);
1613         if (mmc == NULL)
1614                 return -1;
1615
1616         return 0;
1617 }
1618 #else
1619
1620 #ifdef CONFIG_IODELAY_RECALIBRATION
1621 static struct pad_conf_entry *
1622 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1623 {
1624         int index = 0;
1625         struct pad_conf_entry *padconf;
1626
1627         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1628         if (!padconf) {
1629                 debug("failed to allocate memory\n");
1630                 return 0;
1631         }
1632
1633         while (index < count) {
1634                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1635                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1636                 index++;
1637         }
1638
1639         return padconf;
1640 }
1641
1642 static struct iodelay_cfg_entry *
1643 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1644 {
1645         int index = 0;
1646         struct iodelay_cfg_entry *iodelay;
1647
1648         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1649         if (!iodelay) {
1650                 debug("failed to allocate memory\n");
1651                 return 0;
1652         }
1653
1654         while (index < count) {
1655                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1656                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1657                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1658                 index++;
1659         }
1660
1661         return iodelay;
1662 }
1663
1664 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1665                                                    const char *name, int *len)
1666 {
1667         const void *fdt = gd->fdt_blob;
1668         int offset;
1669         const fdt32_t *pinctrl;
1670
1671         offset = fdt_node_offset_by_phandle(fdt, phandle);
1672         if (offset < 0) {
1673                 debug("failed to get pinctrl node %s.\n",
1674                       fdt_strerror(offset));
1675                 return 0;
1676         }
1677
1678         pinctrl = fdt_getprop(fdt, offset, name, len);
1679         if (!pinctrl) {
1680                 debug("failed to get property %s\n", name);
1681                 return 0;
1682         }
1683
1684         return pinctrl;
1685 }
1686
1687 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1688                                                 char *prop_name)
1689 {
1690         const void *fdt = gd->fdt_blob;
1691         const __be32 *phandle;
1692         int node = dev_of_offset(mmc->dev);
1693
1694         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1695         if (!phandle) {
1696                 debug("failed to get property %s\n", prop_name);
1697                 return 0;
1698         }
1699
1700         return fdt32_to_cpu(*phandle);
1701 }
1702
1703 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1704                                                char *prop_name)
1705 {
1706         const void *fdt = gd->fdt_blob;
1707         const __be32 *phandle;
1708         int len;
1709         int count;
1710         int node = dev_of_offset(mmc->dev);
1711
1712         phandle = fdt_getprop(fdt, node, prop_name, &len);
1713         if (!phandle) {
1714                 debug("failed to get property %s\n", prop_name);
1715                 return 0;
1716         }
1717
1718         /* No manual mode iodelay values if count < 2 */
1719         count = len / sizeof(*phandle);
1720         if (count < 2)
1721                 return 0;
1722
1723         return fdt32_to_cpu(*(phandle + 1));
1724 }
1725
1726 static struct pad_conf_entry *
1727 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1728 {
1729         int len;
1730         int count;
1731         struct pad_conf_entry *padconf;
1732         u32 phandle;
1733         const fdt32_t *pinctrl;
1734
1735         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1736         if (!phandle)
1737                 return ERR_PTR(-EINVAL);
1738
1739         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1740                                                &len);
1741         if (!pinctrl)
1742                 return ERR_PTR(-EINVAL);
1743
1744         count = (len / sizeof(*pinctrl)) / 2;
1745         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1746         if (!padconf)
1747                 return ERR_PTR(-EINVAL);
1748
1749         *npads = count;
1750
1751         return padconf;
1752 }
1753
1754 static struct iodelay_cfg_entry *
1755 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1756 {
1757         int len;
1758         int count;
1759         struct iodelay_cfg_entry *iodelay;
1760         u32 phandle;
1761         const fdt32_t *pinctrl;
1762
1763         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1764         /* Not all modes have manual mode iodelay values. So its not fatal */
1765         if (!phandle)
1766                 return 0;
1767
1768         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1769                                                &len);
1770         if (!pinctrl)
1771                 return ERR_PTR(-EINVAL);
1772
1773         count = (len / sizeof(*pinctrl)) / 3;
1774         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1775         if (!iodelay)
1776                 return ERR_PTR(-EINVAL);
1777
1778         *niodelay = count;
1779
1780         return iodelay;
1781 }
1782
1783 static struct omap_hsmmc_pinctrl_state *
1784 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1785 {
1786         int index;
1787         int npads = 0;
1788         int niodelays = 0;
1789         const void *fdt = gd->fdt_blob;
1790         int node = dev_of_offset(mmc->dev);
1791         char prop_name[11];
1792         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1793
1794         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1795                          malloc(sizeof(*pinctrl_state));
1796         if (!pinctrl_state) {
1797                 debug("failed to allocate memory\n");
1798                 return 0;
1799         }
1800
1801         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1802         if (index < 0) {
1803                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1804                 goto err_pinctrl_state;
1805         }
1806
1807         sprintf(prop_name, "pinctrl-%d", index);
1808
1809         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1810                                                          &npads);
1811         if (IS_ERR(pinctrl_state->padconf))
1812                 goto err_pinctrl_state;
1813         pinctrl_state->npads = npads;
1814
1815         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1816                                                         &niodelays);
1817         if (IS_ERR(pinctrl_state->iodelay))
1818                 goto err_padconf;
1819         pinctrl_state->niodelays = niodelays;
1820
1821         return pinctrl_state;
1822
1823 err_padconf:
1824         kfree(pinctrl_state->padconf);
1825
1826 err_pinctrl_state:
1827         kfree(pinctrl_state);
1828         return 0;
1829 }
1830
1831 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1832         do {                                                            \
1833                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1834                 char str[20];                                           \
1835                 if (!(cfg->host_caps & capmask))                        \
1836                         break;                                          \
1837                                                                         \
1838                 if (priv->hw_rev) {                                     \
1839                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1840                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1841                 }                                                       \
1842                                                                         \
1843                 if (!s)                                                 \
1844                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1845                                                                         \
1846                 if (!s && !optional) {                                  \
1847                         debug("%s: no pinctrl for %s\n",                \
1848                               mmc->dev->name, #mode);                   \
1849                         cfg->host_caps &= ~(capmask);                   \
1850                 } else {                                                \
1851                         priv->mode##_pinctrl_state = s;                 \
1852                 }                                                       \
1853         } while (0)
1854
1855 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1856 {
1857         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1858         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1859         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1860
1861         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1862                 return 0;
1863
1864         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1865         if (!default_pinctrl) {
1866                 printf("no pinctrl state for default mode\n");
1867                 return -EINVAL;
1868         }
1869
1870         priv->default_pinctrl_state = default_pinctrl;
1871
1872         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1873         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1874         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1875         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1876         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1877
1878         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1879         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1880         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1881
1882         return 0;
1883 }
1884 #endif
1885
1886 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1887 #ifdef CONFIG_OMAP54XX
1888 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1889 {
1890         return NULL;
1891 }
1892 #endif
1893
1894 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1895 {
1896         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1897         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1898
1899         struct mmc_config *cfg = &plat->cfg;
1900 #ifdef CONFIG_OMAP54XX
1901         const struct mmc_platform_fixups *fixups;
1902 #endif
1903         const void *fdt = gd->fdt_blob;
1904         int node = dev_of_offset(dev);
1905         int ret;
1906
1907         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1908                                       sizeof(struct hsmmc *),
1909                                       MAP_NOCACHE);
1910
1911         ret = mmc_of_parse(dev, cfg);
1912         if (ret < 0)
1913                 return ret;
1914
1915         if (!cfg->f_max)
1916                 cfg->f_max = 52000000;
1917         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1918         cfg->f_min = 400000;
1919         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1920         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1921         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1922                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1923         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1924                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1925         if (of_data)
1926                 plat->controller_flags |= of_data->controller_flags;
1927
1928 #ifdef CONFIG_OMAP54XX
1929         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1930         if (fixups) {
1931                 plat->hw_rev = fixups->hw_rev;
1932                 cfg->host_caps &= ~fixups->unsupported_caps;
1933                 cfg->f_max = fixups->max_freq;
1934         }
1935 #endif
1936
1937         return 0;
1938 }
1939 #endif
1940
1941 #ifdef CONFIG_BLK
1942
1943 static int omap_hsmmc_bind(struct udevice *dev)
1944 {
1945         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1946         plat->mmc = calloc(1, sizeof(struct mmc));
1947         return mmc_bind(dev, plat->mmc, &plat->cfg);
1948 }
1949 #endif
1950 static int omap_hsmmc_probe(struct udevice *dev)
1951 {
1952         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1953         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1954         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1955         struct mmc_config *cfg = &plat->cfg;
1956         struct mmc *mmc;
1957 #ifdef CONFIG_IODELAY_RECALIBRATION
1958         int ret;
1959 #endif
1960
1961         cfg->name = "OMAP SD/MMC";
1962         priv->base_addr = plat->base_addr;
1963         priv->controller_flags = plat->controller_flags;
1964         priv->hw_rev = plat->hw_rev;
1965
1966 #ifdef CONFIG_BLK
1967         mmc = plat->mmc;
1968 #else
1969         mmc = mmc_create(cfg, priv);
1970         if (mmc == NULL)
1971                 return -1;
1972 #endif
1973 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1974         device_get_supply_regulator(dev, "pbias-supply",
1975                                     &priv->pbias_supply);
1976 #endif
1977 #if defined(OMAP_HSMMC_USE_GPIO)
1978 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1979         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1980         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1981 #endif
1982 #endif
1983
1984         mmc->dev = dev;
1985         upriv->mmc = mmc;
1986
1987 #ifdef CONFIG_IODELAY_RECALIBRATION
1988         ret = omap_hsmmc_get_pinctrl_state(mmc);
1989         /*
1990          * disable high speed modes for the platforms that require IO delay
1991          * and for which we don't have this information
1992          */
1993         if ((ret < 0) &&
1994             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1995                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1996                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1997                                     UHS_CAPS);
1998         }
1999 #endif
2000
2001         return omap_hsmmc_init_setup(mmc);
2002 }
2003
2004 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2005
2006 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2007         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2008 };
2009
2010 static const struct udevice_id omap_hsmmc_ids[] = {
2011         { .compatible = "ti,omap3-hsmmc" },
2012         { .compatible = "ti,omap4-hsmmc" },
2013         { .compatible = "ti,am33xx-hsmmc" },
2014         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2015         { }
2016 };
2017 #endif
2018
2019 U_BOOT_DRIVER(omap_hsmmc) = {
2020         .name   = "omap_hsmmc",
2021         .id     = UCLASS_MMC,
2022 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2023         .of_match = omap_hsmmc_ids,
2024         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2025         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2026 #endif
2027 #ifdef CONFIG_BLK
2028         .bind = omap_hsmmc_bind,
2029 #endif
2030         .ops = &omap_hsmmc_ops,
2031         .probe  = omap_hsmmc_probe,
2032         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2033 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2034         .flags  = DM_FLAG_PRE_RELOC,
2035 #endif
2036 };
2037 #endif