3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/mmc_host_def.h>
36 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/arch/sys_proto.h>
40 #ifdef CONFIG_MMC_OMAP36XX_PINS
41 #include <asm/arch/mux.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 /* simplify defines to OMAP_HSMMC_USE_GPIO */
48 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
49 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
50 #define OMAP_HSMMC_USE_GPIO
52 #undef OMAP_HSMMC_USE_GPIO
55 /* common definitions for all OMAPs */
56 #define SYSCTL_SRC (1 << 25)
57 #define SYSCTL_SRD (1 << 26)
59 struct omap_hsmmc_plat {
60 struct mmc_config cfg;
64 struct omap2_mmc_platform_config {
68 struct omap_hsmmc_data {
69 struct hsmmc *base_addr;
71 struct mmc_config cfg;
73 #ifdef OMAP_HSMMC_USE_GPIO
75 struct gpio_desc cd_gpio; /* Change Detect GPIO */
76 struct gpio_desc wp_gpio; /* Write Protect GPIO */
85 /* If we fail after 1 second wait, something is really bad */
86 #define MAX_RETRY_MS 1000
88 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
89 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
92 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
95 return dev_get_priv(mmc->dev);
97 return (struct omap_hsmmc_data *)mmc->priv;
100 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
103 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
106 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
110 #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
111 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
115 #ifndef CONFIG_DM_GPIO
116 if (!gpio_is_valid(gpio))
119 ret = gpio_request(gpio, label);
123 ret = gpio_direction_input(gpio);
131 static unsigned char mmc_board_init(struct mmc *mmc)
133 #if defined(CONFIG_OMAP34XX)
134 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
135 t2_t *t2_base = (t2_t *)T2_BASE;
136 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
138 #ifdef CONFIG_MMC_OMAP36XX_PINS
139 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
142 pbias_lite = readl(&t2_base->pbias_lite);
143 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
144 #ifdef CONFIG_TARGET_OMAP3_CAIRO
145 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
146 pbias_lite &= ~PBIASLITEVMODE0;
148 #ifdef CONFIG_MMC_OMAP36XX_PINS
149 if (get_cpu_family() == CPU_OMAP36XX) {
150 /* Disable extended drain IO before changing PBIAS */
151 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
152 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
155 writel(pbias_lite, &t2_base->pbias_lite);
157 writel(pbias_lite | PBIASLITEPWRDNZ1 |
158 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
159 &t2_base->pbias_lite);
161 #ifdef CONFIG_MMC_OMAP36XX_PINS
162 if (get_cpu_family() == CPU_OMAP36XX)
163 /* Enable extended drain IO after changing PBIAS */
165 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
166 OMAP34XX_CTRL_WKUP_CTRL);
168 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
171 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
174 /* Change from default of 52MHz to 26MHz if necessary */
175 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
176 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
177 &t2_base->ctl_prog_io1);
179 writel(readl(&prcm_base->fclken1_core) |
180 EN_MMC1 | EN_MMC2 | EN_MMC3,
181 &prcm_base->fclken1_core);
183 writel(readl(&prcm_base->iclken1_core) |
184 EN_MMC1 | EN_MMC2 | EN_MMC3,
185 &prcm_base->iclken1_core);
188 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
189 /* PBIAS config needed for MMC1 only */
190 if (mmc_get_blk_desc(mmc)->devnum == 0)
191 vmmc_pbias_config(LDO_VOLT_3V0);
197 void mmc_init_stream(struct hsmmc *mmc_base)
201 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
203 writel(MMC_CMD0, &mmc_base->cmd);
204 start = get_timer(0);
205 while (!(readl(&mmc_base->stat) & CC_MASK)) {
206 if (get_timer(0) - start > MAX_RETRY_MS) {
207 printf("%s: timedout waiting for cc!\n", __func__);
211 writel(CC_MASK, &mmc_base->stat)
213 writel(MMC_CMD0, &mmc_base->cmd)
215 start = get_timer(0);
216 while (!(readl(&mmc_base->stat) & CC_MASK)) {
217 if (get_timer(0) - start > MAX_RETRY_MS) {
218 printf("%s: timedout waiting for cc2!\n", __func__);
222 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
225 static int omap_hsmmc_init_setup(struct mmc *mmc)
227 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
228 struct hsmmc *mmc_base;
229 unsigned int reg_val;
233 mmc_base = priv->base_addr;
236 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
237 &mmc_base->sysconfig);
238 start = get_timer(0);
239 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
240 if (get_timer(0) - start > MAX_RETRY_MS) {
241 printf("%s: timedout waiting for cc2!\n", __func__);
245 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
246 start = get_timer(0);
247 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
248 if (get_timer(0) - start > MAX_RETRY_MS) {
249 printf("%s: timedout waiting for softresetall!\n",
254 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
255 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
258 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
260 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
261 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
262 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
265 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
266 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
267 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
268 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
269 start = get_timer(0);
270 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
271 if (get_timer(0) - start > MAX_RETRY_MS) {
272 printf("%s: timedout waiting for ics!\n", __func__);
276 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
278 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
280 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
281 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
284 mmc_init_stream(mmc_base);
290 * MMC controller internal finite state machine reset
292 * Used to reset command or data internal state machines, using respectively
293 * SRC or SRD bit of SYSCTL register
295 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
299 mmc_reg_out(&mmc_base->sysctl, bit, bit);
302 * CMD(DAT) lines reset procedures are slightly different
303 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
304 * According to OMAP3 TRM:
305 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
307 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
308 * procedure steps must be as follows:
309 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
310 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
311 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
312 * 3. Wait until the SRC (SRD) bit returns to 0x0
313 * (reset procedure is completed).
315 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
316 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
317 if (!(readl(&mmc_base->sysctl) & bit)) {
318 start = get_timer(0);
319 while (!(readl(&mmc_base->sysctl) & bit)) {
320 if (get_timer(0) - start > MAX_RETRY_MS)
325 start = get_timer(0);
326 while ((readl(&mmc_base->sysctl) & bit) != 0) {
327 if (get_timer(0) - start > MAX_RETRY_MS) {
328 printf("%s: timedout waiting for sysctl %x to clear\n",
335 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
336 struct mmc_data *data)
338 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
339 struct hsmmc *mmc_base;
340 unsigned int flags, mmc_stat;
343 mmc_base = priv->base_addr;
344 start = get_timer(0);
345 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
346 if (get_timer(0) - start > MAX_RETRY_MS) {
347 printf("%s: timedout waiting on cmd inhibit to clear\n",
352 writel(0xFFFFFFFF, &mmc_base->stat);
353 start = get_timer(0);
354 while (readl(&mmc_base->stat)) {
355 if (get_timer(0) - start > MAX_RETRY_MS) {
356 printf("%s: timedout waiting for STAT (%x) to clear\n",
357 __func__, readl(&mmc_base->stat));
363 * CMDIDX[13:8] : Command index
364 * DATAPRNT[5] : Data Present Select
365 * ENCMDIDX[4] : Command Index Check Enable
366 * ENCMDCRC[3] : Command CRC Check Enable
371 * 11 = Length 48 Check busy after response
373 /* Delay added before checking the status of frq change
374 * retry not supported by mmc.c(core file)
376 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
377 udelay(50000); /* wait 50 ms */
379 if (!(cmd->resp_type & MMC_RSP_PRESENT))
381 else if (cmd->resp_type & MMC_RSP_136)
382 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
383 else if (cmd->resp_type & MMC_RSP_BUSY)
384 flags = RSP_TYPE_LGHT48B;
386 flags = RSP_TYPE_LGHT48;
388 /* enable default flags */
389 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
390 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
392 if (cmd->resp_type & MMC_RSP_CRC)
394 if (cmd->resp_type & MMC_RSP_OPCODE)
398 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
399 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
400 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
401 data->blocksize = 512;
402 writel(data->blocksize | (data->blocks << 16),
405 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
407 if (data->flags & MMC_DATA_READ)
408 flags |= (DP_DATA | DDIR_READ);
410 flags |= (DP_DATA | DDIR_WRITE);
413 writel(cmd->cmdarg, &mmc_base->arg);
414 udelay(20); /* To fix "No status update" error on eMMC */
415 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
417 start = get_timer(0);
419 mmc_stat = readl(&mmc_base->stat);
420 if (get_timer(0) - start > MAX_RETRY_MS) {
421 printf("%s : timeout: No status update\n", __func__);
426 if ((mmc_stat & IE_CTO) != 0) {
427 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
429 } else if ((mmc_stat & ERRI_MASK) != 0)
432 if (mmc_stat & CC_MASK) {
433 writel(CC_MASK, &mmc_base->stat);
434 if (cmd->resp_type & MMC_RSP_PRESENT) {
435 if (cmd->resp_type & MMC_RSP_136) {
436 /* response type 2 */
437 cmd->response[3] = readl(&mmc_base->rsp10);
438 cmd->response[2] = readl(&mmc_base->rsp32);
439 cmd->response[1] = readl(&mmc_base->rsp54);
440 cmd->response[0] = readl(&mmc_base->rsp76);
442 /* response types 1, 1b, 3, 4, 5, 6 */
443 cmd->response[0] = readl(&mmc_base->rsp10);
447 if (data && (data->flags & MMC_DATA_READ)) {
448 mmc_read_data(mmc_base, data->dest,
449 data->blocksize * data->blocks);
450 } else if (data && (data->flags & MMC_DATA_WRITE)) {
451 mmc_write_data(mmc_base, data->src,
452 data->blocksize * data->blocks);
457 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
459 unsigned int *output_buf = (unsigned int *)buf;
460 unsigned int mmc_stat;
466 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
470 ulong start = get_timer(0);
472 mmc_stat = readl(&mmc_base->stat);
473 if (get_timer(0) - start > MAX_RETRY_MS) {
474 printf("%s: timedout waiting for status!\n",
478 } while (mmc_stat == 0);
480 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
481 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
483 if ((mmc_stat & ERRI_MASK) != 0)
486 if (mmc_stat & BRR_MASK) {
489 writel(readl(&mmc_base->stat) | BRR_MASK,
491 for (k = 0; k < count; k++) {
492 *output_buf = readl(&mmc_base->data);
498 if (mmc_stat & BWR_MASK)
499 writel(readl(&mmc_base->stat) | BWR_MASK,
502 if (mmc_stat & TC_MASK) {
503 writel(readl(&mmc_base->stat) | TC_MASK,
511 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
514 unsigned int *input_buf = (unsigned int *)buf;
515 unsigned int mmc_stat;
521 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
525 ulong start = get_timer(0);
527 mmc_stat = readl(&mmc_base->stat);
528 if (get_timer(0) - start > MAX_RETRY_MS) {
529 printf("%s: timedout waiting for status!\n",
533 } while (mmc_stat == 0);
535 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
536 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
538 if ((mmc_stat & ERRI_MASK) != 0)
541 if (mmc_stat & BWR_MASK) {
544 writel(readl(&mmc_base->stat) | BWR_MASK,
546 for (k = 0; k < count; k++) {
547 writel(*input_buf, &mmc_base->data);
553 if (mmc_stat & BRR_MASK)
554 writel(readl(&mmc_base->stat) | BRR_MASK,
557 if (mmc_stat & TC_MASK) {
558 writel(readl(&mmc_base->stat) | TC_MASK,
566 static int omap_hsmmc_set_ios(struct mmc *mmc)
568 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
569 struct hsmmc *mmc_base;
570 unsigned int dsor = 0;
573 mmc_base = priv->base_addr;
574 /* configue bus width */
575 switch (mmc->bus_width) {
577 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
582 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
584 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
590 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
592 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
597 /* configure clock with 96Mhz system clock.
599 if (mmc->clock != 0) {
600 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
601 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
605 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
606 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
608 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
609 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
611 start = get_timer(0);
612 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
613 if (get_timer(0) - start > MAX_RETRY_MS) {
614 printf("%s: timedout waiting for ics!\n", __func__);
618 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
623 #ifdef OMAP_HSMMC_USE_GPIO
625 static int omap_hsmmc_getcd(struct mmc *mmc)
627 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
630 value = dm_gpio_get_value(&priv->cd_gpio);
631 /* if no CD return as 1 */
635 if (priv->cd_inverted)
640 static int omap_hsmmc_getwp(struct mmc *mmc)
642 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
645 value = dm_gpio_get_value(&priv->wp_gpio);
646 /* if no WP return as 0 */
652 static int omap_hsmmc_getcd(struct mmc *mmc)
654 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
657 /* if no CD return as 1 */
658 cd_gpio = priv->cd_gpio;
662 /* NOTE: assumes card detect signal is active-low */
663 return !gpio_get_value(cd_gpio);
666 static int omap_hsmmc_getwp(struct mmc *mmc)
668 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
671 /* if no WP return as 0 */
672 wp_gpio = priv->wp_gpio;
676 /* NOTE: assumes write protect signal is active-high */
677 return gpio_get_value(wp_gpio);
682 static const struct mmc_ops omap_hsmmc_ops = {
683 .send_cmd = omap_hsmmc_send_cmd,
684 .set_ios = omap_hsmmc_set_ios,
685 .init = omap_hsmmc_init_setup,
686 #ifdef OMAP_HSMMC_USE_GPIO
687 .getcd = omap_hsmmc_getcd,
688 .getwp = omap_hsmmc_getwp,
692 #ifndef CONFIG_DM_MMC
693 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
697 struct omap_hsmmc_data *priv;
698 struct mmc_config *cfg;
701 priv = malloc(sizeof(*priv));
705 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
709 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
711 #ifdef OMAP_HSMMC2_BASE
713 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
714 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
715 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
716 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
717 defined(CONFIG_HSMMC2_8BIT)
718 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
719 host_caps_val |= MMC_MODE_8BIT;
723 #ifdef OMAP_HSMMC3_BASE
725 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
726 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
727 /* Enable 8-bit interface for eMMC on DRA7XX */
728 host_caps_val |= MMC_MODE_8BIT;
733 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
736 #ifdef OMAP_HSMMC_USE_GPIO
737 /* on error gpio values are set to -1, which is what we want */
738 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
739 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
744 cfg->name = "OMAP SD/MMC";
745 cfg->ops = &omap_hsmmc_ops;
747 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
748 cfg->host_caps = host_caps_val & ~host_caps_mask;
755 if (cfg->host_caps & MMC_MODE_HS) {
756 if (cfg->host_caps & MMC_MODE_HS_52MHz)
757 cfg->f_max = 52000000;
759 cfg->f_max = 26000000;
761 cfg->f_max = 20000000;
764 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
766 #if defined(CONFIG_OMAP34XX)
768 * Silicon revs 2.1 and older do not support multiblock transfers.
770 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
773 mmc = mmc_create(cfg, priv);
780 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
782 struct omap_hsmmc_data *priv = dev_get_priv(dev);
783 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
784 struct mmc_config *cfg = &plat->cfg;
785 struct omap2_mmc_platform_config *data =
786 (struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
787 const void *fdt = gd->fdt_blob;
788 int node = dev_of_offset(dev);
791 priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
792 MAP_NOCACHE) + data->reg_offset;
794 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
795 val = fdtdec_get_int(fdt, node, "bus-width", -1);
797 printf("error: bus-width property missing\n");
803 cfg->host_caps |= MMC_MODE_8BIT;
805 cfg->host_caps |= MMC_MODE_4BIT;
808 printf("error: invalid bus-width property\n");
813 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
814 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
815 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
817 #ifdef OMAP_HSMMC_USE_GPIO
818 priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
826 static int omap_hsmmc_bind(struct udevice *dev)
828 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
830 return mmc_bind(dev, &plat->mmc, &plat->cfg);
833 static int omap_hsmmc_probe(struct udevice *dev)
835 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
836 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
837 struct omap_hsmmc_data *priv = dev_get_priv(dev);
838 struct mmc_config *cfg = &plat->cfg;
841 cfg->name = "OMAP SD/MMC";
842 cfg->ops = &omap_hsmmc_ops;
847 mmc = mmc_create(cfg, priv);
852 #ifdef OMAP_HSMMC_USE_GPIO
853 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
854 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
863 static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
867 static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
871 static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
875 static const struct udevice_id omap_hsmmc_ids[] = {
877 .compatible = "ti,omap3-hsmmc",
878 .data = (ulong)&omap3_mmc_pdata
881 .compatible = "ti,omap4-hsmmc",
882 .data = (ulong)&omap4_mmc_pdata
885 .compatible = "ti,am33xx-hsmmc",
886 .data = (ulong)&am33xx_mmc_pdata
891 U_BOOT_DRIVER(omap_hsmmc) = {
892 .name = "omap_hsmmc",
894 .of_match = omap_hsmmc_ids,
895 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
897 .bind = omap_hsmmc_bind,
899 .probe = omap_hsmmc_probe,
900 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
901 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),