3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
36 #include <asm/cache.h>
38 #include <asm/arch/mmc_host_def.h>
39 #ifdef CONFIG_OMAP54XX
40 #include <asm/arch/mux_dra7xx.h>
41 #include <asm/arch/dra7xx_iodelay.h>
43 #if !defined(CONFIG_SOC_KEYSTONE)
45 #include <asm/arch/sys_proto.h>
47 #ifdef CONFIG_MMC_OMAP36XX_PINS
48 #include <asm/arch/mux.h>
51 #include <dm/devres.h>
52 #include <linux/err.h>
53 #include <power/regulator.h>
56 DECLARE_GLOBAL_DATA_PTR;
58 /* simplify defines to OMAP_HSMMC_USE_GPIO */
59 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
60 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
61 #define OMAP_HSMMC_USE_GPIO
63 #undef OMAP_HSMMC_USE_GPIO
66 /* common definitions for all OMAPs */
67 #define SYSCTL_SRC (1 << 25)
68 #define SYSCTL_SRD (1 << 26)
70 #ifdef CONFIG_IODELAY_RECALIBRATION
71 struct omap_hsmmc_pinctrl_state {
72 struct pad_conf_entry *padconf;
74 struct iodelay_cfg_entry *iodelay;
79 struct omap_hsmmc_data {
80 struct hsmmc *base_addr;
81 #if !CONFIG_IS_ENABLED(DM_MMC)
82 struct mmc_config cfg;
87 #ifdef OMAP_HSMMC_USE_GPIO
88 #if CONFIG_IS_ENABLED(DM_MMC)
89 struct gpio_desc cd_gpio; /* Change Detect GPIO */
90 struct gpio_desc wp_gpio; /* Write Protect GPIO */
96 #if CONFIG_IS_ENABLED(DM_MMC)
100 #ifdef CONFIG_MMC_OMAP_HS_ADMA
101 struct omap_hsmmc_adma_desc *adma_desc_table;
105 struct udevice *pbias_supply;
107 #ifdef CONFIG_IODELAY_RECALIBRATION
108 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
109 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
110 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
111 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
112 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
113 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
114 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
115 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
116 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
120 struct omap_mmc_of_data {
124 #ifdef CONFIG_MMC_OMAP_HS_ADMA
125 struct omap_hsmmc_adma_desc {
132 #define ADMA_MAX_LEN 63488
134 /* Decriptor table defines */
135 #define ADMA_DESC_ATTR_VALID BIT(0)
136 #define ADMA_DESC_ATTR_END BIT(1)
137 #define ADMA_DESC_ATTR_INT BIT(2)
138 #define ADMA_DESC_ATTR_ACT1 BIT(4)
139 #define ADMA_DESC_ATTR_ACT2 BIT(5)
141 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
142 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
145 /* If we fail after 1 second wait, something is really bad */
146 #define MAX_RETRY_MS 1000
147 #define MMC_TIMEOUT_MS 20
149 /* DMA transfers can take a long time if a lot a data is transferred.
150 * The timeout must take in account the amount of data. Let's assume
151 * that the time will never exceed 333 ms per MB (in other word we assume
152 * that the bandwidth is always above 3MB/s).
154 #define DMA_TIMEOUT_PER_MB 333
155 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
156 #define OMAP_HSMMC_NO_1_8_V BIT(1)
157 #define OMAP_HSMMC_USE_ADMA BIT(2)
158 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
160 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
161 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
163 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
164 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
165 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
167 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
169 #if CONFIG_IS_ENABLED(DM_MMC)
170 return dev_get_priv(mmc->dev);
172 return (struct omap_hsmmc_data *)mmc->priv;
175 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
177 #if CONFIG_IS_ENABLED(DM_MMC)
178 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
181 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
185 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
186 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
190 #if !CONFIG_IS_ENABLED(DM_GPIO)
191 if (!gpio_is_valid(gpio))
194 ret = gpio_request(gpio, label);
198 ret = gpio_direction_input(gpio);
206 static unsigned char mmc_board_init(struct mmc *mmc)
208 #if defined(CONFIG_OMAP34XX)
209 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
210 t2_t *t2_base = (t2_t *)T2_BASE;
211 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
213 #ifdef CONFIG_MMC_OMAP36XX_PINS
214 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
217 pbias_lite = readl(&t2_base->pbias_lite);
218 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
219 #ifdef CONFIG_TARGET_OMAP3_CAIRO
220 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
221 pbias_lite &= ~PBIASLITEVMODE0;
223 #ifdef CONFIG_TARGET_OMAP3_LOGIC
224 /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
225 pbias_lite &= ~PBIASLITEVMODE1;
227 #ifdef CONFIG_MMC_OMAP36XX_PINS
228 if (get_cpu_family() == CPU_OMAP36XX) {
229 /* Disable extended drain IO before changing PBIAS */
230 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
231 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
234 writel(pbias_lite, &t2_base->pbias_lite);
236 writel(pbias_lite | PBIASLITEPWRDNZ1 |
237 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
238 &t2_base->pbias_lite);
240 #ifdef CONFIG_MMC_OMAP36XX_PINS
241 if (get_cpu_family() == CPU_OMAP36XX)
242 /* Enable extended drain IO after changing PBIAS */
244 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
245 OMAP34XX_CTRL_WKUP_CTRL);
247 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
250 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
253 /* Change from default of 52MHz to 26MHz if necessary */
254 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
255 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
256 &t2_base->ctl_prog_io1);
258 writel(readl(&prcm_base->fclken1_core) |
259 EN_MMC1 | EN_MMC2 | EN_MMC3,
260 &prcm_base->fclken1_core);
262 writel(readl(&prcm_base->iclken1_core) |
263 EN_MMC1 | EN_MMC2 | EN_MMC3,
264 &prcm_base->iclken1_core);
267 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
268 !CONFIG_IS_ENABLED(DM_REGULATOR)
269 /* PBIAS config needed for MMC1 only */
270 if (mmc_get_blk_desc(mmc)->devnum == 0)
271 vmmc_pbias_config(LDO_VOLT_3V3);
277 void mmc_init_stream(struct hsmmc *mmc_base)
281 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
283 writel(MMC_CMD0, &mmc_base->cmd);
284 start = get_timer(0);
285 while (!(readl(&mmc_base->stat) & CC_MASK)) {
286 if (get_timer(0) - start > MAX_RETRY_MS) {
287 printf("%s: timedout waiting for cc!\n", __func__);
291 writel(CC_MASK, &mmc_base->stat)
293 writel(MMC_CMD0, &mmc_base->cmd)
295 start = get_timer(0);
296 while (!(readl(&mmc_base->stat) & CC_MASK)) {
297 if (get_timer(0) - start > MAX_RETRY_MS) {
298 printf("%s: timedout waiting for cc2!\n", __func__);
302 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
305 #if CONFIG_IS_ENABLED(DM_MMC)
306 #ifdef CONFIG_IODELAY_RECALIBRATION
307 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
309 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
310 struct omap_hsmmc_pinctrl_state *pinctrl_state;
312 switch (priv->mode) {
314 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
317 pinctrl_state = priv->sdr104_pinctrl_state;
320 pinctrl_state = priv->sdr50_pinctrl_state;
323 pinctrl_state = priv->ddr50_pinctrl_state;
326 pinctrl_state = priv->sdr25_pinctrl_state;
329 pinctrl_state = priv->sdr12_pinctrl_state;
334 pinctrl_state = priv->hs_pinctrl_state;
337 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
339 pinctrl_state = priv->default_pinctrl_state;
344 pinctrl_state = priv->default_pinctrl_state;
346 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
347 if (pinctrl_state->iodelay)
348 late_recalibrate_iodelay(pinctrl_state->padconf,
349 pinctrl_state->npads,
350 pinctrl_state->iodelay,
351 pinctrl_state->niodelays);
353 do_set_mux32((*ctrl)->control_padconf_core_base,
354 pinctrl_state->padconf,
355 pinctrl_state->npads);
359 static void omap_hsmmc_set_timing(struct mmc *mmc)
362 struct hsmmc *mmc_base;
363 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
365 mmc_base = priv->base_addr;
367 omap_hsmmc_stop_clock(mmc_base);
368 val = readl(&mmc_base->ac12);
369 val &= ~AC12_UHSMC_MASK;
370 priv->mode = mmc->selected_mode;
372 if (mmc_is_mode_ddr(priv->mode))
373 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
375 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
377 switch (priv->mode) {
380 val |= AC12_UHSMC_SDR104;
383 val |= AC12_UHSMC_SDR50;
387 val |= AC12_UHSMC_DDR50;
392 val |= AC12_UHSMC_SDR25;
397 val |= AC12_UHSMC_SDR12;
400 val |= AC12_UHSMC_RES;
403 writel(val, &mmc_base->ac12);
405 #ifdef CONFIG_IODELAY_RECALIBRATION
406 omap_hsmmc_io_recalibrate(mmc);
408 omap_hsmmc_start_clock(mmc_base);
411 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
413 struct hsmmc *mmc_base;
414 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
417 mmc_base = priv->base_addr;
419 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
420 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
422 switch (signal_voltage) {
423 case MMC_SIGNAL_VOLTAGE_330:
426 case MMC_SIGNAL_VOLTAGE_180:
428 ac12 |= AC12_V1V8_SIGEN;
432 writel(hctl, &mmc_base->hctl);
433 writel(ac12, &mmc_base->ac12);
436 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
438 int ret = -ETIMEDOUT;
441 bool target_dat0_high = !!state;
442 struct omap_hsmmc_data *priv = dev_get_priv(dev);
443 struct hsmmc *mmc_base = priv->base_addr;
445 con = readl(&mmc_base->con);
446 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
448 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
449 while (timeout_us--) {
450 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
451 if (dat0_high == target_dat0_high) {
457 writel(con, &mmc_base->con);
462 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
463 #if CONFIG_IS_ENABLED(DM_REGULATOR)
464 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
469 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
471 if (!mmc->vqmmc_supply)
475 ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
479 /* Turn off IO voltage */
480 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
483 /* Program a new IO voltage value */
484 ret = regulator_set_value(mmc->vqmmc_supply, uV);
487 /* Turn on IO voltage */
488 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
492 /* Program PBIAS voltage*/
493 ret = regulator_set_value(priv->pbias_supply, uV);
494 if (ret && ret != -ENOSYS)
497 ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
505 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
507 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
508 struct hsmmc *mmc_base = priv->base_addr;
509 int mv = mmc_voltage_to_mv(mmc->signal_voltage);
511 __maybe_unused u8 palmas_ldo_volt;
517 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
519 capa_mask = VS33_3V3SUP;
520 palmas_ldo_volt = LDO_VOLT_3V3;
521 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
522 capa_mask = VS18_1V8SUP;
523 palmas_ldo_volt = LDO_VOLT_1V8;
528 val = readl(&mmc_base->capa);
529 if (!(val & capa_mask))
532 priv->signal_voltage = mmc->signal_voltage;
534 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
536 #if CONFIG_IS_ENABLED(DM_REGULATOR)
537 return omap_hsmmc_set_io_regulator(mmc, mv);
538 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
539 defined(CONFIG_PALMAS_POWER)
540 if (mmc_get_blk_desc(mmc)->devnum == 0)
541 vmmc_pbias_config(palmas_ldo_volt);
549 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
551 struct hsmmc *mmc_base;
552 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
555 mmc_base = priv->base_addr;
556 val = readl(&mmc_base->capa);
558 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
559 val |= (VS33_3V3SUP | VS18_1V8SUP);
560 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
568 writel(val, &mmc_base->capa);
573 #ifdef MMC_SUPPORTS_TUNING
574 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
576 struct hsmmc *mmc_base;
577 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
580 mmc_base = priv->base_addr;
581 val = readl(&mmc_base->ac12);
582 val &= ~(AC12_SCLK_SEL);
583 writel(val, &mmc_base->ac12);
585 val = readl(&mmc_base->dll);
586 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
587 writel(val, &mmc_base->dll);
590 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
593 struct hsmmc *mmc_base;
594 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
597 mmc_base = priv->base_addr;
598 val = readl(&mmc_base->dll);
599 val |= DLL_FORCE_VALUE;
600 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
601 val |= (count << DLL_FORCE_SR_C_SHIFT);
602 writel(val, &mmc_base->dll);
605 writel(val, &mmc_base->dll);
606 for (i = 0; i < 1000; i++) {
607 if (readl(&mmc_base->dll) & DLL_CALIB)
611 writel(val, &mmc_base->dll);
614 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
616 struct omap_hsmmc_data *priv = dev_get_priv(dev);
617 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
618 struct mmc *mmc = upriv->mmc;
619 struct hsmmc *mmc_base;
621 u8 cur_match, prev_match = 0;
624 u32 start_window = 0, max_window = 0;
625 u32 length = 0, max_len = 0;
626 bool single_point_failure = false;
627 struct udevice *thermal_dev;
631 mmc_base = priv->base_addr;
632 val = readl(&mmc_base->capa2);
634 /* clock tuning is not needed for upto 52MHz */
635 if (!((mmc->selected_mode == MMC_HS_200) ||
636 (mmc->selected_mode == UHS_SDR104) ||
637 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
640 ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
642 printf("Couldn't get thermal device for tuning\n");
645 ret = thermal_get_temp(thermal_dev, &temperature);
647 printf("Couldn't get temperature for tuning\n");
650 val = readl(&mmc_base->dll);
652 writel(val, &mmc_base->dll);
655 * Stage 1: Search for a maximum pass window ignoring any
656 * any single point failures. If the tuning value ends up
657 * near it, move away from it in stage 2 below
659 while (phase_delay <= MAX_PHASE_DELAY) {
660 omap_hsmmc_set_dll(mmc, phase_delay);
662 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
667 } else if (single_point_failure) {
668 /* ignore single point failure */
670 single_point_failure = false;
672 start_window = phase_delay;
676 single_point_failure = prev_match;
679 if (length > max_len) {
680 max_window = start_window;
684 prev_match = cur_match;
693 val = readl(&mmc_base->ac12);
694 if (!(val & AC12_SCLK_SEL)) {
699 * Assign tuning value as a ratio of maximum pass window based
702 if (temperature < -20000)
703 phase_delay = min(max_window + 4 * max_len - 24,
705 DIV_ROUND_UP(13 * max_len, 16) * 4);
706 else if (temperature < 20000)
707 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
708 else if (temperature < 40000)
709 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
710 else if (temperature < 70000)
711 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
712 else if (temperature < 90000)
713 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
714 else if (temperature < 120000)
715 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
717 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
720 * Stage 2: Search for a single point failure near the chosen tuning
721 * value in two steps. First in the +3 to +10 range and then in the
722 * +2 to -10 range. If found, move away from it in the appropriate
723 * direction by the appropriate amount depending on the temperature.
725 for (i = 3; i <= 10; i++) {
726 omap_hsmmc_set_dll(mmc, phase_delay + i);
727 if (mmc_send_tuning(mmc, opcode, NULL)) {
728 if (temperature < 10000)
729 phase_delay += i + 6;
730 else if (temperature < 20000)
731 phase_delay += i - 12;
732 else if (temperature < 70000)
733 phase_delay += i - 8;
734 else if (temperature < 90000)
735 phase_delay += i - 6;
737 phase_delay += i - 6;
739 goto single_failure_found;
743 for (i = 2; i >= -10; i--) {
744 omap_hsmmc_set_dll(mmc, phase_delay + i);
745 if (mmc_send_tuning(mmc, opcode, NULL)) {
746 if (temperature < 10000)
747 phase_delay += i + 12;
748 else if (temperature < 20000)
749 phase_delay += i + 8;
750 else if (temperature < 70000)
751 phase_delay += i + 8;
752 else if (temperature < 90000)
753 phase_delay += i + 10;
755 phase_delay += i + 12;
757 goto single_failure_found;
761 single_failure_found:
763 omap_hsmmc_set_dll(mmc, phase_delay);
765 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
766 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
772 omap_hsmmc_disable_tuning(mmc);
773 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
774 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
781 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
783 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
784 struct hsmmc *mmc_base = priv->base_addr;
785 u32 irq_mask = INT_EN_MASK;
788 * TODO: Errata i802 indicates only DCRC interrupts can occur during
789 * tuning procedure and DCRC should be disabled. But see occurences
790 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
791 * interrupts occur along with BRR, so the data is actually in the
792 * buffer. It has to be debugged why these interrutps occur
794 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
795 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
797 writel(irq_mask, &mmc_base->ie);
800 static int omap_hsmmc_init_setup(struct mmc *mmc)
802 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
803 struct hsmmc *mmc_base;
804 unsigned int reg_val;
808 mmc_base = priv->base_addr;
811 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
812 &mmc_base->sysconfig);
813 start = get_timer(0);
814 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
815 if (get_timer(0) - start > MAX_RETRY_MS) {
816 printf("%s: timedout waiting for cc2!\n", __func__);
820 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
821 start = get_timer(0);
822 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
823 if (get_timer(0) - start > MAX_RETRY_MS) {
824 printf("%s: timedout waiting for softresetall!\n",
829 #ifdef CONFIG_MMC_OMAP_HS_ADMA
830 reg_val = readl(&mmc_base->hl_hwinfo);
831 if (reg_val & MADMA_EN)
832 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
835 #if CONFIG_IS_ENABLED(DM_MMC)
836 reg_val = omap_hsmmc_set_capabilities(mmc);
837 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
838 MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
840 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
841 writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
845 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
847 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
848 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
849 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
852 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
853 (ICE_STOP | DTO_15THDTO));
854 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
855 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
856 start = get_timer(0);
857 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
858 if (get_timer(0) - start > MAX_RETRY_MS) {
859 printf("%s: timedout waiting for ics!\n", __func__);
863 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
865 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
867 mmc_enable_irq(mmc, NULL);
869 #if !CONFIG_IS_ENABLED(DM_MMC)
870 mmc_init_stream(mmc_base);
877 * MMC controller internal finite state machine reset
879 * Used to reset command or data internal state machines, using respectively
880 * SRC or SRD bit of SYSCTL register
882 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
886 mmc_reg_out(&mmc_base->sysctl, bit, bit);
889 * CMD(DAT) lines reset procedures are slightly different
890 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
891 * According to OMAP3 TRM:
892 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
894 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
895 * procedure steps must be as follows:
896 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
897 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
898 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
899 * 3. Wait until the SRC (SRD) bit returns to 0x0
900 * (reset procedure is completed).
902 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
903 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
904 if (!(readl(&mmc_base->sysctl) & bit)) {
905 start = get_timer(0);
906 while (!(readl(&mmc_base->sysctl) & bit)) {
907 if (get_timer(0) - start > MMC_TIMEOUT_MS)
912 start = get_timer(0);
913 while ((readl(&mmc_base->sysctl) & bit) != 0) {
914 if (get_timer(0) - start > MAX_RETRY_MS) {
915 printf("%s: timedout waiting for sysctl %x to clear\n",
922 #ifdef CONFIG_MMC_OMAP_HS_ADMA
923 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
925 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
926 struct omap_hsmmc_adma_desc *desc;
929 desc = &priv->adma_desc_table[priv->desc_slot];
931 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
935 attr |= ADMA_DESC_ATTR_END;
938 desc->addr = (u32)buf;
943 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
944 struct mmc_data *data)
946 uint total_len = data->blocksize * data->blocks;
947 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
948 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
953 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
954 memalign(ARCH_DMA_MINALIGN, desc_count *
955 sizeof(struct omap_hsmmc_adma_desc));
957 if (data->flags & MMC_DATA_READ)
960 buf = (char *)data->src;
963 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
965 total_len -= ADMA_MAX_LEN;
968 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
970 flush_dcache_range((long)priv->adma_desc_table,
971 (long)priv->adma_desc_table +
973 sizeof(struct omap_hsmmc_adma_desc),
977 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
979 struct hsmmc *mmc_base;
980 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
984 mmc_base = priv->base_addr;
985 omap_hsmmc_prepare_adma_table(mmc, data);
987 if (data->flags & MMC_DATA_READ)
990 buf = (char *)data->src;
992 val = readl(&mmc_base->hctl);
994 writel(val, &mmc_base->hctl);
996 val = readl(&mmc_base->con);
998 writel(val, &mmc_base->con);
1000 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1002 flush_dcache_range((u32)buf,
1004 ROUND(data->blocksize * data->blocks,
1005 ARCH_DMA_MINALIGN));
1008 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1010 struct hsmmc *mmc_base;
1011 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1014 mmc_base = priv->base_addr;
1016 val = readl(&mmc_base->con);
1018 writel(val, &mmc_base->con);
1020 val = readl(&mmc_base->hctl);
1022 writel(val, &mmc_base->hctl);
1024 kfree(priv->adma_desc_table);
1027 #define omap_hsmmc_adma_desc
1028 #define omap_hsmmc_prepare_adma_table
1029 #define omap_hsmmc_prepare_data
1030 #define omap_hsmmc_dma_cleanup
1033 #if !CONFIG_IS_ENABLED(DM_MMC)
1034 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1035 struct mmc_data *data)
1037 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1039 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1040 struct mmc_data *data)
1042 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1043 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1044 struct mmc *mmc = upriv->mmc;
1046 struct hsmmc *mmc_base;
1047 unsigned int flags, mmc_stat;
1049 priv->last_cmd = cmd->cmdidx;
1051 mmc_base = priv->base_addr;
1053 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1056 start = get_timer(0);
1057 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1058 if (get_timer(0) - start > MAX_RETRY_MS) {
1059 printf("%s: timedout waiting on cmd inhibit to clear\n",
1061 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1062 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1066 writel(0xFFFFFFFF, &mmc_base->stat);
1067 if (readl(&mmc_base->stat)) {
1068 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1069 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1074 * CMDIDX[13:8] : Command index
1075 * DATAPRNT[5] : Data Present Select
1076 * ENCMDIDX[4] : Command Index Check Enable
1077 * ENCMDCRC[3] : Command CRC Check Enable
1082 * 11 = Length 48 Check busy after response
1084 /* Delay added before checking the status of frq change
1085 * retry not supported by mmc.c(core file)
1087 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1088 udelay(50000); /* wait 50 ms */
1090 if (!(cmd->resp_type & MMC_RSP_PRESENT))
1092 else if (cmd->resp_type & MMC_RSP_136)
1093 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1094 else if (cmd->resp_type & MMC_RSP_BUSY)
1095 flags = RSP_TYPE_LGHT48B;
1097 flags = RSP_TYPE_LGHT48;
1099 /* enable default flags */
1100 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1102 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1104 if (cmd->resp_type & MMC_RSP_CRC)
1105 flags |= CCCE_CHECK;
1106 if (cmd->resp_type & MMC_RSP_OPCODE)
1107 flags |= CICE_CHECK;
1110 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1111 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1112 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1113 data->blocksize = 512;
1114 writel(data->blocksize | (data->blocks << 16),
1117 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1119 if (data->flags & MMC_DATA_READ)
1120 flags |= (DP_DATA | DDIR_READ);
1122 flags |= (DP_DATA | DDIR_WRITE);
1124 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1125 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1126 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1127 omap_hsmmc_prepare_data(mmc, data);
1133 mmc_enable_irq(mmc, cmd);
1135 writel(cmd->cmdarg, &mmc_base->arg);
1136 udelay(20); /* To fix "No status update" error on eMMC */
1137 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1139 start = get_timer(0);
1141 mmc_stat = readl(&mmc_base->stat);
1142 if (get_timer(start) > MAX_RETRY_MS) {
1143 printf("%s : timeout: No status update\n", __func__);
1146 } while (!mmc_stat);
1148 if ((mmc_stat & IE_CTO) != 0) {
1149 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1151 } else if ((mmc_stat & ERRI_MASK) != 0)
1154 if (mmc_stat & CC_MASK) {
1155 writel(CC_MASK, &mmc_base->stat);
1156 if (cmd->resp_type & MMC_RSP_PRESENT) {
1157 if (cmd->resp_type & MMC_RSP_136) {
1158 /* response type 2 */
1159 cmd->response[3] = readl(&mmc_base->rsp10);
1160 cmd->response[2] = readl(&mmc_base->rsp32);
1161 cmd->response[1] = readl(&mmc_base->rsp54);
1162 cmd->response[0] = readl(&mmc_base->rsp76);
1164 /* response types 1, 1b, 3, 4, 5, 6 */
1165 cmd->response[0] = readl(&mmc_base->rsp10);
1169 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1170 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1171 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1174 if (mmc_stat & IE_ADMAE) {
1175 omap_hsmmc_dma_cleanup(mmc);
1179 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
1180 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1181 if (timeout < MAX_RETRY_MS)
1182 timeout = MAX_RETRY_MS;
1184 start = get_timer(0);
1186 mmc_stat = readl(&mmc_base->stat);
1187 if (mmc_stat & TC_MASK) {
1188 writel(readl(&mmc_base->stat) | TC_MASK,
1192 if (get_timer(start) > timeout) {
1193 printf("%s : DMA timeout: No status update\n",
1199 omap_hsmmc_dma_cleanup(mmc);
1204 if (data && (data->flags & MMC_DATA_READ)) {
1205 mmc_read_data(mmc_base, data->dest,
1206 data->blocksize * data->blocks);
1207 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1208 mmc_write_data(mmc_base, data->src,
1209 data->blocksize * data->blocks);
1214 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1216 unsigned int *output_buf = (unsigned int *)buf;
1217 unsigned int mmc_stat;
1223 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1227 ulong start = get_timer(0);
1229 mmc_stat = readl(&mmc_base->stat);
1230 if (get_timer(0) - start > MAX_RETRY_MS) {
1231 printf("%s: timedout waiting for status!\n",
1235 } while (mmc_stat == 0);
1237 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1238 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1240 if ((mmc_stat & ERRI_MASK) != 0)
1243 if (mmc_stat & BRR_MASK) {
1246 writel(readl(&mmc_base->stat) | BRR_MASK,
1248 for (k = 0; k < count; k++) {
1249 *output_buf = readl(&mmc_base->data);
1255 if (mmc_stat & BWR_MASK)
1256 writel(readl(&mmc_base->stat) | BWR_MASK,
1259 if (mmc_stat & TC_MASK) {
1260 writel(readl(&mmc_base->stat) | TC_MASK,
1268 #if CONFIG_IS_ENABLED(MMC_WRITE)
1269 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1272 unsigned int *input_buf = (unsigned int *)buf;
1273 unsigned int mmc_stat;
1277 * Start Polled Write
1279 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1283 ulong start = get_timer(0);
1285 mmc_stat = readl(&mmc_base->stat);
1286 if (get_timer(0) - start > MAX_RETRY_MS) {
1287 printf("%s: timedout waiting for status!\n",
1291 } while (mmc_stat == 0);
1293 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1294 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1296 if ((mmc_stat & ERRI_MASK) != 0)
1299 if (mmc_stat & BWR_MASK) {
1302 writel(readl(&mmc_base->stat) | BWR_MASK,
1304 for (k = 0; k < count; k++) {
1305 writel(*input_buf, &mmc_base->data);
1311 if (mmc_stat & BRR_MASK)
1312 writel(readl(&mmc_base->stat) | BRR_MASK,
1315 if (mmc_stat & TC_MASK) {
1316 writel(readl(&mmc_base->stat) | TC_MASK,
1324 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1330 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1332 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1335 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1337 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1340 static void omap_hsmmc_set_clock(struct mmc *mmc)
1342 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1343 struct hsmmc *mmc_base;
1344 unsigned int dsor = 0;
1347 mmc_base = priv->base_addr;
1348 omap_hsmmc_stop_clock(mmc_base);
1350 /* TODO: Is setting DTO required here? */
1351 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1352 (ICE_STOP | DTO_15THDTO));
1354 if (mmc->clock != 0) {
1355 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1356 if (dsor > CLKD_MAX)
1362 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1363 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1365 start = get_timer(0);
1366 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1367 if (get_timer(0) - start > MAX_RETRY_MS) {
1368 printf("%s: timedout waiting for ics!\n", __func__);
1373 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1374 mmc->clock = priv->clock;
1375 omap_hsmmc_start_clock(mmc_base);
1378 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1380 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1381 struct hsmmc *mmc_base;
1383 mmc_base = priv->base_addr;
1384 /* configue bus width */
1385 switch (mmc->bus_width) {
1387 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1392 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1394 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1400 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1402 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1407 priv->bus_width = mmc->bus_width;
1410 #if !CONFIG_IS_ENABLED(DM_MMC)
1411 static int omap_hsmmc_set_ios(struct mmc *mmc)
1413 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1415 static int omap_hsmmc_set_ios(struct udevice *dev)
1417 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1418 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1419 struct mmc *mmc = upriv->mmc;
1421 struct hsmmc *mmc_base = priv->base_addr;
1424 if (priv->bus_width != mmc->bus_width)
1425 omap_hsmmc_set_bus_width(mmc);
1427 if (priv->clock != mmc->clock)
1428 omap_hsmmc_set_clock(mmc);
1430 if (mmc->clk_disable)
1431 omap_hsmmc_stop_clock(mmc_base);
1433 omap_hsmmc_start_clock(mmc_base);
1435 #if CONFIG_IS_ENABLED(DM_MMC)
1436 if (priv->mode != mmc->selected_mode)
1437 omap_hsmmc_set_timing(mmc);
1439 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1440 if (priv->signal_voltage != mmc->signal_voltage)
1441 ret = omap_hsmmc_set_signal_voltage(mmc);
1447 #ifdef OMAP_HSMMC_USE_GPIO
1448 #if CONFIG_IS_ENABLED(DM_MMC)
1449 static int omap_hsmmc_getcd(struct udevice *dev)
1452 #if CONFIG_IS_ENABLED(DM_GPIO)
1453 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1454 value = dm_gpio_get_value(&priv->cd_gpio);
1456 /* if no CD return as 1 */
1463 static int omap_hsmmc_getwp(struct udevice *dev)
1466 #if CONFIG_IS_ENABLED(DM_GPIO)
1467 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1468 value = dm_gpio_get_value(&priv->wp_gpio);
1470 /* if no WP return as 0 */
1476 static int omap_hsmmc_getcd(struct mmc *mmc)
1478 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1481 /* if no CD return as 1 */
1482 cd_gpio = priv->cd_gpio;
1486 /* NOTE: assumes card detect signal is active-low */
1487 return !gpio_get_value(cd_gpio);
1490 static int omap_hsmmc_getwp(struct mmc *mmc)
1492 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1495 /* if no WP return as 0 */
1496 wp_gpio = priv->wp_gpio;
1500 /* NOTE: assumes write protect signal is active-high */
1501 return gpio_get_value(wp_gpio);
1506 #if CONFIG_IS_ENABLED(DM_MMC)
1507 static const struct dm_mmc_ops omap_hsmmc_ops = {
1508 .send_cmd = omap_hsmmc_send_cmd,
1509 .set_ios = omap_hsmmc_set_ios,
1510 #ifdef OMAP_HSMMC_USE_GPIO
1511 .get_cd = omap_hsmmc_getcd,
1512 .get_wp = omap_hsmmc_getwp,
1514 #ifdef MMC_SUPPORTS_TUNING
1515 .execute_tuning = omap_hsmmc_execute_tuning,
1517 .wait_dat0 = omap_hsmmc_wait_dat0,
1520 static const struct mmc_ops omap_hsmmc_ops = {
1521 .send_cmd = omap_hsmmc_send_cmd,
1522 .set_ios = omap_hsmmc_set_ios,
1523 .init = omap_hsmmc_init_setup,
1524 #ifdef OMAP_HSMMC_USE_GPIO
1525 .getcd = omap_hsmmc_getcd,
1526 .getwp = omap_hsmmc_getwp,
1531 #if !CONFIG_IS_ENABLED(DM_MMC)
1532 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1536 struct omap_hsmmc_data *priv;
1537 struct mmc_config *cfg;
1540 priv = calloc(1, sizeof(*priv));
1544 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1546 switch (dev_index) {
1548 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1550 #ifdef OMAP_HSMMC2_BASE
1552 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1553 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1554 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1555 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1556 defined(CONFIG_HSMMC2_8BIT)
1557 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1558 host_caps_val |= MMC_MODE_8BIT;
1562 #ifdef OMAP_HSMMC3_BASE
1564 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1565 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1566 /* Enable 8-bit interface for eMMC on DRA7XX */
1567 host_caps_val |= MMC_MODE_8BIT;
1572 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1575 #ifdef OMAP_HSMMC_USE_GPIO
1576 /* on error gpio values are set to -1, which is what we want */
1577 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1578 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1583 cfg->name = "OMAP SD/MMC";
1584 cfg->ops = &omap_hsmmc_ops;
1586 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1587 cfg->host_caps = host_caps_val & ~host_caps_mask;
1589 cfg->f_min = 400000;
1594 if (cfg->host_caps & MMC_MODE_HS) {
1595 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1596 cfg->f_max = 52000000;
1598 cfg->f_max = 26000000;
1600 cfg->f_max = 20000000;
1603 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1605 #if defined(CONFIG_OMAP34XX)
1607 * Silicon revs 2.1 and older do not support multiblock transfers.
1609 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1613 mmc = mmc_create(cfg, priv);
1621 #ifdef CONFIG_IODELAY_RECALIBRATION
1622 static struct pad_conf_entry *
1623 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1626 struct pad_conf_entry *padconf;
1628 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1630 debug("failed to allocate memory\n");
1634 while (index < count) {
1635 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1636 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1643 static struct iodelay_cfg_entry *
1644 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1647 struct iodelay_cfg_entry *iodelay;
1649 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1651 debug("failed to allocate memory\n");
1655 while (index < count) {
1656 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1657 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1658 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1665 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1666 const char *name, int *len)
1668 const void *fdt = gd->fdt_blob;
1670 const fdt32_t *pinctrl;
1672 offset = fdt_node_offset_by_phandle(fdt, phandle);
1674 debug("failed to get pinctrl node %s.\n",
1675 fdt_strerror(offset));
1679 pinctrl = fdt_getprop(fdt, offset, name, len);
1681 debug("failed to get property %s\n", name);
1688 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1691 const void *fdt = gd->fdt_blob;
1692 const __be32 *phandle;
1693 int node = dev_of_offset(mmc->dev);
1695 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1697 debug("failed to get property %s\n", prop_name);
1701 return fdt32_to_cpu(*phandle);
1704 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1707 const void *fdt = gd->fdt_blob;
1708 const __be32 *phandle;
1711 int node = dev_of_offset(mmc->dev);
1713 phandle = fdt_getprop(fdt, node, prop_name, &len);
1715 debug("failed to get property %s\n", prop_name);
1719 /* No manual mode iodelay values if count < 2 */
1720 count = len / sizeof(*phandle);
1724 return fdt32_to_cpu(*(phandle + 1));
1727 static struct pad_conf_entry *
1728 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1732 struct pad_conf_entry *padconf;
1734 const fdt32_t *pinctrl;
1736 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1738 return ERR_PTR(-EINVAL);
1740 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1743 return ERR_PTR(-EINVAL);
1745 count = (len / sizeof(*pinctrl)) / 2;
1746 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1748 return ERR_PTR(-EINVAL);
1755 static struct iodelay_cfg_entry *
1756 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1760 struct iodelay_cfg_entry *iodelay;
1762 const fdt32_t *pinctrl;
1764 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1765 /* Not all modes have manual mode iodelay values. So its not fatal */
1769 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1772 return ERR_PTR(-EINVAL);
1774 count = (len / sizeof(*pinctrl)) / 3;
1775 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1777 return ERR_PTR(-EINVAL);
1784 static struct omap_hsmmc_pinctrl_state *
1785 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1790 const void *fdt = gd->fdt_blob;
1791 int node = dev_of_offset(mmc->dev);
1793 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1795 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1796 malloc(sizeof(*pinctrl_state));
1797 if (!pinctrl_state) {
1798 debug("failed to allocate memory\n");
1802 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1804 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1805 goto err_pinctrl_state;
1808 sprintf(prop_name, "pinctrl-%d", index);
1810 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1812 if (IS_ERR(pinctrl_state->padconf))
1813 goto err_pinctrl_state;
1814 pinctrl_state->npads = npads;
1816 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1818 if (IS_ERR(pinctrl_state->iodelay))
1820 pinctrl_state->niodelays = niodelays;
1822 return pinctrl_state;
1825 kfree(pinctrl_state->padconf);
1828 kfree(pinctrl_state);
1832 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1834 struct omap_hsmmc_pinctrl_state *s = NULL; \
1836 if (!(cfg->host_caps & capmask)) \
1839 if (priv->hw_rev) { \
1840 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1841 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1845 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1847 if (!s && !optional) { \
1848 debug("%s: no pinctrl for %s\n", \
1849 mmc->dev->name, #mode); \
1850 cfg->host_caps &= ~(capmask); \
1852 priv->mode##_pinctrl_state = s; \
1856 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1858 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1859 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1860 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1862 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1865 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1866 if (!default_pinctrl) {
1867 printf("no pinctrl state for default mode\n");
1871 priv->default_pinctrl_state = default_pinctrl;
1873 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1874 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1875 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1876 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1877 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1879 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1880 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1881 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1887 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1888 #ifdef CONFIG_OMAP54XX
1889 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1895 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1897 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1898 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1900 struct mmc_config *cfg = &plat->cfg;
1901 #ifdef CONFIG_OMAP54XX
1902 const struct mmc_platform_fixups *fixups;
1904 const void *fdt = gd->fdt_blob;
1905 int node = dev_of_offset(dev);
1908 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1909 sizeof(struct hsmmc *),
1912 ret = mmc_of_parse(dev, cfg);
1917 cfg->f_max = 52000000;
1918 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1919 cfg->f_min = 400000;
1920 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1921 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1922 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1923 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1924 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1925 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1927 plat->controller_flags |= of_data->controller_flags;
1929 #ifdef CONFIG_OMAP54XX
1930 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1932 plat->hw_rev = fixups->hw_rev;
1933 cfg->host_caps &= ~fixups->unsupported_caps;
1934 cfg->f_max = fixups->max_freq;
1944 static int omap_hsmmc_bind(struct udevice *dev)
1946 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1947 plat->mmc = calloc(1, sizeof(struct mmc));
1948 return mmc_bind(dev, plat->mmc, &plat->cfg);
1951 static int omap_hsmmc_probe(struct udevice *dev)
1953 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1954 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1955 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1956 struct mmc_config *cfg = &plat->cfg;
1958 #ifdef CONFIG_IODELAY_RECALIBRATION
1962 cfg->name = "OMAP SD/MMC";
1963 priv->base_addr = plat->base_addr;
1964 priv->controller_flags = plat->controller_flags;
1965 priv->hw_rev = plat->hw_rev;
1970 mmc = mmc_create(cfg, priv);
1974 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1975 device_get_supply_regulator(dev, "pbias-supply",
1976 &priv->pbias_supply);
1978 #if defined(OMAP_HSMMC_USE_GPIO)
1979 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1980 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1981 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1988 #ifdef CONFIG_IODELAY_RECALIBRATION
1989 ret = omap_hsmmc_get_pinctrl_state(mmc);
1991 * disable high speed modes for the platforms that require IO delay
1992 * and for which we don't have this information
1995 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1996 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1997 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2002 return omap_hsmmc_init_setup(mmc);
2005 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2007 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2008 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2011 static const struct udevice_id omap_hsmmc_ids[] = {
2012 { .compatible = "ti,omap3-hsmmc" },
2013 { .compatible = "ti,omap4-hsmmc" },
2014 { .compatible = "ti,am33xx-hsmmc" },
2015 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2020 U_BOOT_DRIVER(omap_hsmmc) = {
2021 .name = "omap_hsmmc",
2023 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2024 .of_match = omap_hsmmc_ids,
2025 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2026 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2029 .bind = omap_hsmmc_bind,
2031 .ops = &omap_hsmmc_ops,
2032 .probe = omap_hsmmc_probe,
2033 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2034 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2035 .flags = DM_FLAG_PRE_RELOC,