drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <cpu_func.h>
  28 #include <log.h>
  29 #include <malloc.h>
  30 #include <memalign.h>
  31 #include <mmc.h>
  32 #include <part.h>
  33 #include <i2c.h>
  34 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  35 #include <palmas.h>
  36 #endif
  37 #include <asm/cache.h>
  38 #include <asm/io.h>
  39 #include <asm/arch/mmc_host_def.h>
  40 #ifdef CONFIG_OMAP54XX
  41 #include <asm/arch/mux_dra7xx.h>
  42 #include <asm/arch/dra7xx_iodelay.h>
  43 #endif
  44 #if !defined(CONFIG_SOC_KEYSTONE)
  45 #include <asm/gpio.h>
  46 #include <asm/arch/sys_proto.h>
  47 #endif
  48 #ifdef CONFIG_MMC_OMAP36XX_PINS
  49 #include <asm/arch/mux.h>
  50 #endif
  51 #include <dm.h>
  52 #include <dm/devres.h>
  53 #include <linux/bitops.h>
  54 #include <linux/delay.h>
  55 #include <linux/err.h>
  56 #include <power/regulator.h>
  57 #include <thermal.h>
  58
  59 DECLARE_GLOBAL_DATA_PTR;
  60
  61 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  62 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  63         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  64 #define OMAP_HSMMC_USE_GPIO
  65 #else
  66 #undef OMAP_HSMMC_USE_GPIO
  67 #endif
  68
  69 /* common definitions for all OMAPs */
  70 #define SYSCTL_SRC      (1 << 25)
  71 #define SYSCTL_SRD      (1 << 26)
  72
  73 #ifdef CONFIG_IODELAY_RECALIBRATION
  74 struct omap_hsmmc_pinctrl_state {
  75         struct pad_conf_entry *padconf;
  76         int npads;
  77         struct iodelay_cfg_entry *iodelay;
  78         int niodelays;
  79 };
  80 #endif
  81
  82 struct omap_hsmmc_data {
  83         struct hsmmc *base_addr;
  84 #if !CONFIG_IS_ENABLED(DM_MMC)
  85         struct mmc_config cfg;
  86 #endif
  87         uint bus_width;
  88         uint clock;
  89         ushort last_cmd;
  90 #ifdef OMAP_HSMMC_USE_GPIO
  91 #if CONFIG_IS_ENABLED(DM_MMC)
  92         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  93         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  94 #else
  95         int cd_gpio;
  96         int wp_gpio;
  97 #endif
  98 #endif
  99 #if CONFIG_IS_ENABLED(DM_MMC)
 100         enum bus_mode mode;
 101 #endif
 102         u8 controller_flags;
 103 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 104         struct omap_hsmmc_adma_desc *adma_desc_table;
 105         uint desc_slot;
 106 #endif
 107         const char *hw_rev;
 108         struct udevice *pbias_supply;
 109         uint signal_voltage;
 110 #ifdef CONFIG_IODELAY_RECALIBRATION
 111         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 113         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 114         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 115         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 116         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 117         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 118         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 119         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 120 #endif
 121 };
 122
 123 struct omap_mmc_of_data {
 124         u8 controller_flags;
 125 };
 126
 127 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 128 struct omap_hsmmc_adma_desc {
 129         u8 attr;
 130         u8 reserved;
 131         u16 len;
 132         u32 addr;
 133 };
 134
 135 #define ADMA_MAX_LEN    63488
 136
 137 /* Decriptor table defines */
 138 #define ADMA_DESC_ATTR_VALID            BIT(0)
 139 #define ADMA_DESC_ATTR_END              BIT(1)
 140 #define ADMA_DESC_ATTR_INT              BIT(2)
 141 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 142 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 143
 144 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 145 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 146 #endif
 147
 148 /* If we fail after 1 second wait, something is really bad */
 149 #define MAX_RETRY_MS    1000
 150 #define MMC_TIMEOUT_MS  20
 151
 152 /* DMA transfers can take a long time if a lot a data is transferred.
 153  * The timeout must take in account the amount of data. Let's assume
 154  * that the time will never exceed 333 ms per MB (in other word we assume
 155  * that the bandwidth is always above 3MB/s).
 156  */
 157 #define DMA_TIMEOUT_PER_MB      333
 158 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 159 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 160 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 161 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 162
 163 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 164 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 165                         unsigned int siz);
 166 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 167 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 168 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 169
 170 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 171 {
 172 #if CONFIG_IS_ENABLED(DM_MMC)
 173         return dev_get_priv(mmc->dev);
 174 #else
 175         return (struct omap_hsmmc_data *)mmc->priv;
 176 #endif
 177 }
 178 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 179 {
 180 #if CONFIG_IS_ENABLED(DM_MMC)
 181         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 182         return &plat->cfg;
 183 #else
 184         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 185 #endif
 186 }
 187
 188 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 189 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 190 {
 191         int ret;
 192
 193 #if !CONFIG_IS_ENABLED(DM_GPIO)
 194         if (!gpio_is_valid(gpio))
 195                 return -1;
 196 #endif
 197         ret = gpio_request(gpio, label);
 198         if (ret)
 199                 return ret;
 200
 201         ret = gpio_direction_input(gpio);
 202         if (ret)
 203                 return ret;
 204
 205         return gpio;
 206 }
 207 #endif
 208
 209 static unsigned char mmc_board_init(struct mmc *mmc)
 210 {
 211 #if defined(CONFIG_OMAP34XX)
 212         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 213         t2_t *t2_base = (t2_t *)T2_BASE;
 214         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 215         u32 pbias_lite;
 216 #ifdef CONFIG_MMC_OMAP36XX_PINS
 217         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 218 #endif
 219
 220         pbias_lite = readl(&t2_base->pbias_lite);
 221         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 222 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 223         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 224         pbias_lite &= ~PBIASLITEVMODE0;
 225 #endif
 226 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 227         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 228         pbias_lite &= ~PBIASLITEVMODE1;
 229 #endif
 230 #ifdef CONFIG_MMC_OMAP36XX_PINS
 231         if (get_cpu_family() == CPU_OMAP36XX) {
 232                 /* Disable extended drain IO before changing PBIAS */
 233                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 234                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 235         }
 236 #endif
 237         writel(pbias_lite, &t2_base->pbias_lite);
 238
 239         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 240                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 241                 &t2_base->pbias_lite);
 242
 243 #ifdef CONFIG_MMC_OMAP36XX_PINS
 244         if (get_cpu_family() == CPU_OMAP36XX)
 245                 /* Enable extended drain IO after changing PBIAS */
 246                 writel(wkup_ctrl |
 247                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 248                                 OMAP34XX_CTRL_WKUP_CTRL);
 249 #endif
 250         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 251                 &t2_base->devconf0);
 252
 253         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 254                 &t2_base->devconf1);
 255
 256         /* Change from default of 52MHz to 26MHz if necessary */
 257         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 258                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 259                         &t2_base->ctl_prog_io1);
 260
 261         writel(readl(&prcm_base->fclken1_core) |
 262                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 263                 &prcm_base->fclken1_core);
 264
 265         writel(readl(&prcm_base->iclken1_core) |
 266                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 267                 &prcm_base->iclken1_core);
 268 #endif
 269
 270 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 271         !CONFIG_IS_ENABLED(DM_REGULATOR)
 272         /* PBIAS config needed for MMC1 only */
 273         if (mmc_get_blk_desc(mmc)->devnum == 0)
 274                 vmmc_pbias_config(LDO_VOLT_3V3);
 275 #endif
 276
 277         return 0;
 278 }
 279
 280 void mmc_init_stream(struct hsmmc *mmc_base)
 281 {
 282         ulong start;
 283
 284         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 285
 286         writel(MMC_CMD0, &mmc_base->cmd);
 287         start = get_timer(0);
 288         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 289                 if (get_timer(0) - start > MAX_RETRY_MS) {
 290                         printf("%s: timedout waiting for cc!\n", __func__);
 291                         return;
 292                 }
 293         }
 294         writel(CC_MASK, &mmc_base->stat)
 295                 ;
 296         writel(MMC_CMD0, &mmc_base->cmd)
 297                 ;
 298         start = get_timer(0);
 299         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 300                 if (get_timer(0) - start > MAX_RETRY_MS) {
 301                         printf("%s: timedout waiting for cc2!\n", __func__);
 302                         return;
 303                 }
 304         }
 305         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 306 }
 307
 308 #if CONFIG_IS_ENABLED(DM_MMC)
 309 #ifdef CONFIG_IODELAY_RECALIBRATION
 310 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 311 {
 312         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 313         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 314
 315         switch (priv->mode) {
 316         case MMC_HS_200:
 317                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 318                 break;
 319         case UHS_SDR104:
 320                 pinctrl_state = priv->sdr104_pinctrl_state;
 321                 break;
 322         case UHS_SDR50:
 323                 pinctrl_state = priv->sdr50_pinctrl_state;
 324                 break;
 325         case UHS_DDR50:
 326                 pinctrl_state = priv->ddr50_pinctrl_state;
 327                 break;
 328         case UHS_SDR25:
 329                 pinctrl_state = priv->sdr25_pinctrl_state;
 330                 break;
 331         case UHS_SDR12:
 332                 pinctrl_state = priv->sdr12_pinctrl_state;
 333                 break;
 334         case SD_HS:
 335         case MMC_HS:
 336         case MMC_HS_52:
 337                 pinctrl_state = priv->hs_pinctrl_state;
 338                 break;
 339         case MMC_DDR_52:
 340                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 341         default:
 342                 pinctrl_state = priv->default_pinctrl_state;
 343                 break;
 344         }
 345
 346         if (!pinctrl_state)
 347                 pinctrl_state = priv->default_pinctrl_state;
 348
 349         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 350                 if (pinctrl_state->iodelay)
 351                         late_recalibrate_iodelay(pinctrl_state->padconf,
 352                                                  pinctrl_state->npads,
 353                                                  pinctrl_state->iodelay,
 354                                                  pinctrl_state->niodelays);
 355                 else
 356                         do_set_mux32((*ctrl)->control_padconf_core_base,
 357                                      pinctrl_state->padconf,
 358                                      pinctrl_state->npads);
 359         }
 360 }
 361 #endif
 362 static void omap_hsmmc_set_timing(struct mmc *mmc)
 363 {
 364         u32 val;
 365         struct hsmmc *mmc_base;
 366         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 367
 368         mmc_base = priv->base_addr;
 369
 370         omap_hsmmc_stop_clock(mmc_base);
 371         val = readl(&mmc_base->ac12);
 372         val &= ~AC12_UHSMC_MASK;
 373         priv->mode = mmc->selected_mode;
 374
 375         if (mmc_is_mode_ddr(priv->mode))
 376                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 377         else
 378                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 379
 380         switch (priv->mode) {
 381         case MMC_HS_200:
 382         case UHS_SDR104:
 383                 val |= AC12_UHSMC_SDR104;
 384                 break;
 385         case UHS_SDR50:
 386                 val |= AC12_UHSMC_SDR50;
 387                 break;
 388         case MMC_DDR_52:
 389         case UHS_DDR50:
 390                 val |= AC12_UHSMC_DDR50;
 391                 break;
 392         case SD_HS:
 393         case MMC_HS_52:
 394         case UHS_SDR25:
 395                 val |= AC12_UHSMC_SDR25;
 396                 break;
 397         case MMC_LEGACY:
 398         case MMC_HS:
 399         case UHS_SDR12:
 400                 val |= AC12_UHSMC_SDR12;
 401                 break;
 402         default:
 403                 val |= AC12_UHSMC_RES;
 404                 break;
 405         }
 406         writel(val, &mmc_base->ac12);
 407
 408 #ifdef CONFIG_IODELAY_RECALIBRATION
 409         omap_hsmmc_io_recalibrate(mmc);
 410 #endif
 411         omap_hsmmc_start_clock(mmc_base);
 412 }
 413
 414 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 415 {
 416         struct hsmmc *mmc_base;
 417         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 418         u32 hctl, ac12;
 419
 420         mmc_base = priv->base_addr;
 421
 422         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 423         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 424
 425         switch (signal_voltage) {
 426         case MMC_SIGNAL_VOLTAGE_330:
 427                 hctl |= SDVS_3V3;
 428                 break;
 429         case MMC_SIGNAL_VOLTAGE_180:
 430                 hctl |= SDVS_1V8;
 431                 ac12 |= AC12_V1V8_SIGEN;
 432                 break;
 433         }
 434
 435         writel(hctl, &mmc_base->hctl);
 436         writel(ac12, &mmc_base->ac12);
 437 }
 438
 439 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
 440 {
 441         int ret = -ETIMEDOUT;
 442         u32 con;
 443         bool dat0_high;
 444         bool target_dat0_high = !!state;
 445         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 446         struct hsmmc *mmc_base = priv->base_addr;
 447
 448         con = readl(&mmc_base->con);
 449         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 450
 451         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 452         while (timeout_us--) {
 453                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 454                 if (dat0_high == target_dat0_high) {
 455                         ret = 0;
 456                         break;
 457                 }
 458                 udelay(10);
 459         }
 460         writel(con, &mmc_base->con);
 461
 462         return ret;
 463 }
 464
 465 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 466 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 467 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 468 {
 469         int ret = 0;
 470         int uV = mV * 1000;
 471
 472         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 473
 474         if (!mmc->vqmmc_supply)
 475                 return 0;
 476
 477         /* Disable PBIAS */
 478         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 479         if (ret)
 480                 return ret;
 481
 482         /* Turn off IO voltage */
 483         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 484         if (ret)
 485                 return ret;
 486         /* Program a new IO voltage value */
 487         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 488         if (ret)
 489                 return ret;
 490         /* Turn on IO voltage */
 491         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 492         if (ret)
 493                 return ret;
 494
 495         /* Program PBIAS voltage*/
 496         ret = regulator_set_value(priv->pbias_supply, uV);
 497         if (ret && ret != -ENOSYS)
 498                 return ret;
 499         /* Enable PBIAS */
 500         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 501         if (ret)
 502                 return ret;
 503
 504         return 0;
 505 }
 506 #endif
 507
 508 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 509 {
 510         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 511         struct hsmmc *mmc_base = priv->base_addr;
 512         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 513         u32 capa_mask;
 514         __maybe_unused u8 palmas_ldo_volt;
 515         u32 val;
 516
 517         if (mv < 0)
 518                 return -EINVAL;
 519
 520         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 521                 mv = 3300;
 522                 capa_mask = VS33_3V3SUP;
 523                 palmas_ldo_volt = LDO_VOLT_3V3;
 524         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 525                 capa_mask = VS18_1V8SUP;
 526                 palmas_ldo_volt = LDO_VOLT_1V8;
 527         } else {
 528                 return -EOPNOTSUPP;
 529         }
 530
 531         val = readl(&mmc_base->capa);
 532         if (!(val & capa_mask))
 533                 return -EOPNOTSUPP;
 534
 535         priv->signal_voltage = mmc->signal_voltage;
 536
 537         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 538
 539 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 540         return omap_hsmmc_set_io_regulator(mmc, mv);
 541 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 542         defined(CONFIG_PALMAS_POWER)
 543         if (mmc_get_blk_desc(mmc)->devnum == 0)
 544                 vmmc_pbias_config(palmas_ldo_volt);
 545         return 0;
 546 #else
 547         return 0;
 548 #endif
 549 }
 550 #endif
 551
 552 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 553 {
 554         struct hsmmc *mmc_base;
 555         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 556         u32 val;
 557
 558         mmc_base = priv->base_addr;
 559         val = readl(&mmc_base->capa);
 560
 561         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 562                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 563         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 564                 val |= VS33_3V3SUP;
 565                 val &= ~VS18_1V8SUP;
 566         } else {
 567                 val |= VS18_1V8SUP;
 568                 val &= ~VS33_3V3SUP;
 569         }
 570
 571         writel(val, &mmc_base->capa);
 572
 573         return val;
 574 }
 575
 576 #ifdef MMC_SUPPORTS_TUNING
 577 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 578 {
 579         struct hsmmc *mmc_base;
 580         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 581         u32 val;
 582
 583         mmc_base = priv->base_addr;
 584         val = readl(&mmc_base->ac12);
 585         val &= ~(AC12_SCLK_SEL);
 586         writel(val, &mmc_base->ac12);
 587
 588         val = readl(&mmc_base->dll);
 589         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 590         writel(val, &mmc_base->dll);
 591 }
 592
 593 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 594 {
 595         int i;
 596         struct hsmmc *mmc_base;
 597         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 598         u32 val;
 599
 600         mmc_base = priv->base_addr;
 601         val = readl(&mmc_base->dll);
 602         val |= DLL_FORCE_VALUE;
 603         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 604         val |= (count << DLL_FORCE_SR_C_SHIFT);
 605         writel(val, &mmc_base->dll);
 606
 607         val |= DLL_CALIB;
 608         writel(val, &mmc_base->dll);
 609         for (i = 0; i < 1000; i++) {
 610                 if (readl(&mmc_base->dll) & DLL_CALIB)
 611                         break;
 612         }
 613         val &= ~DLL_CALIB;
 614         writel(val, &mmc_base->dll);
 615 }
 616
 617 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 618 {
 619         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 620         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 621         struct mmc *mmc = upriv->mmc;
 622         struct hsmmc *mmc_base;
 623         u32 val;
 624         u8 cur_match, prev_match = 0;
 625         int ret;
 626         u32 phase_delay = 0;
 627         u32 start_window = 0, max_window = 0;
 628         u32 length = 0, max_len = 0;
 629         bool single_point_failure = false;
 630         struct udevice *thermal_dev;
 631         int temperature;
 632         int i;
 633
 634         mmc_base = priv->base_addr;
 635         val = readl(&mmc_base->capa2);
 636
 637         /* clock tuning is not needed for upto 52MHz */
 638         if (!((mmc->selected_mode == MMC_HS_200) ||
 639               (mmc->selected_mode == UHS_SDR104) ||
 640               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 641                 return 0;
 642
 643         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 644         if (ret) {
 645                 printf("Couldn't get thermal device for tuning\n");
 646                 return ret;
 647         }
 648         ret = thermal_get_temp(thermal_dev, &temperature);
 649         if (ret) {
 650                 printf("Couldn't get temperature for tuning\n");
 651                 return ret;
 652         }
 653         val = readl(&mmc_base->dll);
 654         val |= DLL_SWT;
 655         writel(val, &mmc_base->dll);
 656
 657         /*
 658          * Stage 1: Search for a maximum pass window ignoring any
 659          * any single point failures. If the tuning value ends up
 660          * near it, move away from it in stage 2 below
 661          */
 662         while (phase_delay <= MAX_PHASE_DELAY) {
 663                 omap_hsmmc_set_dll(mmc, phase_delay);
 664
 665                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 666
 667                 if (cur_match) {
 668                         if (prev_match) {
 669                                 length++;
 670                         } else if (single_point_failure) {
 671                                 /* ignore single point failure */
 672                                 length++;
 673                                 single_point_failure = false;
 674                         } else {
 675                                 start_window = phase_delay;
 676                                 length = 1;
 677                         }
 678                 } else {
 679                         single_point_failure = prev_match;
 680                 }
 681
 682                 if (length > max_len) {
 683                         max_window = start_window;
 684                         max_len = length;
 685                 }
 686
 687                 prev_match = cur_match;
 688                 phase_delay += 4;
 689         }
 690
 691         if (!max_len) {
 692                 ret = -EIO;
 693                 goto tuning_error;
 694         }
 695
 696         val = readl(&mmc_base->ac12);
 697         if (!(val & AC12_SCLK_SEL)) {
 698                 ret = -EIO;
 699                 goto tuning_error;
 700         }
 701         /*
 702          * Assign tuning value as a ratio of maximum pass window based
 703          * on temperature
 704          */
 705         if (temperature < -20000)
 706                 phase_delay = min(max_window + 4 * max_len - 24,
 707                                   max_window +
 708                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 709         else if (temperature < 20000)
 710                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 711         else if (temperature < 40000)
 712                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 713         else if (temperature < 70000)
 714                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 715         else if (temperature < 90000)
 716                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 717         else if (temperature < 120000)
 718                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 719         else
 720                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 721
 722         /*
 723          * Stage 2: Search for a single point failure near the chosen tuning
 724          * value in two steps. First in the +3 to +10 range and then in the
 725          * +2 to -10 range. If found, move away from it in the appropriate
 726          * direction by the appropriate amount depending on the temperature.
 727          */
 728         for (i = 3; i <= 10; i++) {
 729                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 730                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 731                         if (temperature < 10000)
 732                                 phase_delay += i + 6;
 733                         else if (temperature < 20000)
 734                                 phase_delay += i - 12;
 735                         else if (temperature < 70000)
 736                                 phase_delay += i - 8;
 737                         else if (temperature < 90000)
 738                                 phase_delay += i - 6;
 739                         else
 740                                 phase_delay += i - 6;
 741
 742                         goto single_failure_found;
 743                 }
 744         }
 745
 746         for (i = 2; i >= -10; i--) {
 747                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 748                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 749                         if (temperature < 10000)
 750                                 phase_delay += i + 12;
 751                         else if (temperature < 20000)
 752                                 phase_delay += i + 8;
 753                         else if (temperature < 70000)
 754                                 phase_delay += i + 8;
 755                         else if (temperature < 90000)
 756                                 phase_delay += i + 10;
 757                         else
 758                                 phase_delay += i + 12;
 759
 760                         goto single_failure_found;
 761                 }
 762         }
 763
 764 single_failure_found:
 765
 766         omap_hsmmc_set_dll(mmc, phase_delay);
 767
 768         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 769         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 770
 771         return 0;
 772
 773 tuning_error:
 774
 775         omap_hsmmc_disable_tuning(mmc);
 776         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 777         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 778
 779         return ret;
 780 }
 781 #endif
 782 #endif
 783
 784 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 785 {
 786         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 787         struct hsmmc *mmc_base = priv->base_addr;
 788         u32 irq_mask = INT_EN_MASK;
 789
 790         /*
 791          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 792          * tuning procedure and DCRC should be disabled. But see occurences
 793          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 794          * interrupts occur along with BRR, so the data is actually in the
 795          * buffer. It has to be debugged why these interrutps occur
 796          */
 797         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 798                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 799
 800         writel(irq_mask, &mmc_base->ie);
 801 }
 802
 803 static int omap_hsmmc_init_setup(struct mmc *mmc)
 804 {
 805         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 806         struct hsmmc *mmc_base;
 807         unsigned int reg_val;
 808         unsigned int dsor;
 809         ulong start;
 810
 811         mmc_base = priv->base_addr;
 812         mmc_board_init(mmc);
 813
 814         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 815                 &mmc_base->sysconfig);
 816         start = get_timer(0);
 817         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 818                 if (get_timer(0) - start > MAX_RETRY_MS) {
 819                         printf("%s: timedout waiting for cc2!\n", __func__);
 820                         return -ETIMEDOUT;
 821                 }
 822         }
 823         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 824         start = get_timer(0);
 825         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 826                 if (get_timer(0) - start > MAX_RETRY_MS) {
 827                         printf("%s: timedout waiting for softresetall!\n",
 828                                 __func__);
 829                         return -ETIMEDOUT;
 830                 }
 831         }
 832 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 833         reg_val = readl(&mmc_base->hl_hwinfo);
 834         if (reg_val & MADMA_EN)
 835                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 836 #endif
 837
 838 #if CONFIG_IS_ENABLED(DM_MMC)
 839         reg_val = omap_hsmmc_set_capabilities(mmc);
 840         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 841                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 842 #else
 843         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 844         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 845                 &mmc_base->capa);
 846 #endif
 847
 848         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 849
 850         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 851                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 852                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 853
 854         dsor = 240;
 855         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 856                 (ICE_STOP | DTO_15THDTO));
 857         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 858                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 859         start = get_timer(0);
 860         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 861                 if (get_timer(0) - start > MAX_RETRY_MS) {
 862                         printf("%s: timedout waiting for ics!\n", __func__);
 863                         return -ETIMEDOUT;
 864                 }
 865         }
 866         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 867
 868         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 869
 870         mmc_enable_irq(mmc, NULL);
 871
 872 #if !CONFIG_IS_ENABLED(DM_MMC)
 873         mmc_init_stream(mmc_base);
 874 #endif
 875
 876         return 0;
 877 }
 878
 879 /*
 880  * MMC controller internal finite state machine reset
 881  *
 882  * Used to reset command or data internal state machines, using respectively
 883  * SRC or SRD bit of SYSCTL register
 884  */
 885 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 886 {
 887         ulong start;
 888
 889         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 890
 891         /*
 892          * CMD(DAT) lines reset procedures are slightly different
 893          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 894          * According to OMAP3 TRM:
 895          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 896          * returns to 0x0.
 897          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 898          * procedure steps must be as follows:
 899          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 900          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 901          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 902          * 3. Wait until the SRC (SRD) bit returns to 0x0
 903          *    (reset procedure is completed).
 904          */
 905 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 906         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 907         if (!(readl(&mmc_base->sysctl) & bit)) {
 908                 start = get_timer(0);
 909                 while (!(readl(&mmc_base->sysctl) & bit)) {
 910                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 911                                 return;
 912                 }
 913         }
 914 #endif
 915         start = get_timer(0);
 916         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 917                 if (get_timer(0) - start > MAX_RETRY_MS) {
 918                         printf("%s: timedout waiting for sysctl %x to clear\n",
 919                                 __func__, bit);
 920                         return;
 921                 }
 922         }
 923 }
 924
 925 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 926 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 927 {
 928         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 929         struct omap_hsmmc_adma_desc *desc;
 930         u8 attr;
 931
 932         desc = &priv->adma_desc_table[priv->desc_slot];
 933
 934         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 935         if (!end)
 936                 priv->desc_slot++;
 937         else
 938                 attr |= ADMA_DESC_ATTR_END;
 939
 940         desc->len = len;
 941         desc->addr = (u32)buf;
 942         desc->reserved = 0;
 943         desc->attr = attr;
 944 }
 945
 946 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 947                                           struct mmc_data *data)
 948 {
 949         uint total_len = data->blocksize * data->blocks;
 950         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 951         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 952         int i = desc_count;
 953         char *buf;
 954
 955         priv->desc_slot = 0;
 956         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 957                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 958                                 sizeof(struct omap_hsmmc_adma_desc));
 959
 960         if (data->flags & MMC_DATA_READ)
 961                 buf = data->dest;
 962         else
 963                 buf = (char *)data->src;
 964
 965         while (--i) {
 966                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 967                 buf += ADMA_MAX_LEN;
 968                 total_len -= ADMA_MAX_LEN;
 969         }
 970
 971         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 972
 973         flush_dcache_range((long)priv->adma_desc_table,
 974                            (long)priv->adma_desc_table +
 975                            ROUND(desc_count *
 976                            sizeof(struct omap_hsmmc_adma_desc),
 977                            ARCH_DMA_MINALIGN));
 978 }
 979
 980 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 981 {
 982         struct hsmmc *mmc_base;
 983         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 984         u32 val;
 985         char *buf;
 986
 987         mmc_base = priv->base_addr;
 988         omap_hsmmc_prepare_adma_table(mmc, data);
 989
 990         if (data->flags & MMC_DATA_READ)
 991                 buf = data->dest;
 992         else
 993                 buf = (char *)data->src;
 994
 995         val = readl(&mmc_base->hctl);
 996         val |= DMA_SELECT;
 997         writel(val, &mmc_base->hctl);
 998
 999         val = readl(&mmc_base->con);
1000         val |= DMA_MASTER;
1001         writel(val, &mmc_base->con);
1002
1003         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1004
1005         flush_dcache_range((u32)buf,
1006                            (u32)buf +
1007                            ROUND(data->blocksize * data->blocks,
1008                                  ARCH_DMA_MINALIGN));
1009 }
1010
1011 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1012 {
1013         struct hsmmc *mmc_base;
1014         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1015         u32 val;
1016
1017         mmc_base = priv->base_addr;
1018
1019         val = readl(&mmc_base->con);
1020         val &= ~DMA_MASTER;
1021         writel(val, &mmc_base->con);
1022
1023         val = readl(&mmc_base->hctl);
1024         val &= ~DMA_SELECT;
1025         writel(val, &mmc_base->hctl);
1026
1027         kfree(priv->adma_desc_table);
1028 }
1029 #else
1030 #define omap_hsmmc_adma_desc
1031 #define omap_hsmmc_prepare_adma_table
1032 #define omap_hsmmc_prepare_data
1033 #define omap_hsmmc_dma_cleanup
1034 #endif
1035
1036 #if !CONFIG_IS_ENABLED(DM_MMC)
1037 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1038                         struct mmc_data *data)
1039 {
1040         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1041 #else
1042 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1043                         struct mmc_data *data)
1044 {
1045         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1046         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1047         struct mmc *mmc = upriv->mmc;
1048 #endif
1049         struct hsmmc *mmc_base;
1050         unsigned int flags, mmc_stat;
1051         ulong start;
1052         priv->last_cmd = cmd->cmdidx;
1053
1054         mmc_base = priv->base_addr;
1055
1056         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1057                 return 0;
1058
1059         start = get_timer(0);
1060         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1061                 if (get_timer(0) - start > MAX_RETRY_MS) {
1062                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1063                                         __func__);
1064                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1065                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1066                         return -ETIMEDOUT;
1067                 }
1068         }
1069         writel(0xFFFFFFFF, &mmc_base->stat);
1070         if (readl(&mmc_base->stat)) {
1071                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1072                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1073         }
1074
1075         /*
1076          * CMDREG
1077          * CMDIDX[13:8] : Command index
1078          * DATAPRNT[5]  : Data Present Select
1079          * ENCMDIDX[4]  : Command Index Check Enable
1080          * ENCMDCRC[3]  : Command CRC Check Enable
1081          * RSPTYP[1:0]
1082          *      00 = No Response
1083          *      01 = Length 136
1084          *      10 = Length 48
1085          *      11 = Length 48 Check busy after response
1086          */
1087         /* Delay added before checking the status of frq change
1088          * retry not supported by mmc.c(core file)
1089          */
1090         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1091                 udelay(50000); /* wait 50 ms */
1092
1093         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1094                 flags = 0;
1095         else if (cmd->resp_type & MMC_RSP_136)
1096                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1097         else if (cmd->resp_type & MMC_RSP_BUSY)
1098                 flags = RSP_TYPE_LGHT48B;
1099         else
1100                 flags = RSP_TYPE_LGHT48;
1101
1102         /* enable default flags */
1103         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1104                         MSBS_SGLEBLK);
1105         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1106
1107         if (cmd->resp_type & MMC_RSP_CRC)
1108                 flags |= CCCE_CHECK;
1109         if (cmd->resp_type & MMC_RSP_OPCODE)
1110                 flags |= CICE_CHECK;
1111
1112         if (data) {
1113                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1114                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1115                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1116                         data->blocksize = 512;
1117                         writel(data->blocksize | (data->blocks << 16),
1118                                                         &mmc_base->blk);
1119                 } else
1120                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1121
1122                 if (data->flags & MMC_DATA_READ)
1123                         flags |= (DP_DATA | DDIR_READ);
1124                 else
1125                         flags |= (DP_DATA | DDIR_WRITE);
1126
1127 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1128                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1129                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1130                         omap_hsmmc_prepare_data(mmc, data);
1131                         flags |= DE_ENABLE;
1132                 }
1133 #endif
1134         }
1135
1136         mmc_enable_irq(mmc, cmd);
1137
1138         writel(cmd->cmdarg, &mmc_base->arg);
1139         udelay(20);             /* To fix "No status update" error on eMMC */
1140         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1141
1142         start = get_timer(0);
1143         do {
1144                 mmc_stat = readl(&mmc_base->stat);
1145                 if (get_timer(start) > MAX_RETRY_MS) {
1146                         printf("%s : timeout: No status update\n", __func__);
1147                         return -ETIMEDOUT;
1148                 }
1149         } while (!mmc_stat);
1150
1151         if ((mmc_stat & IE_CTO) != 0) {
1152                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1153                 return -ETIMEDOUT;
1154         } else if ((mmc_stat & ERRI_MASK) != 0)
1155                 return -1;
1156
1157         if (mmc_stat & CC_MASK) {
1158                 writel(CC_MASK, &mmc_base->stat);
1159                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1160                         if (cmd->resp_type & MMC_RSP_136) {
1161                                 /* response type 2 */
1162                                 cmd->response[3] = readl(&mmc_base->rsp10);
1163                                 cmd->response[2] = readl(&mmc_base->rsp32);
1164                                 cmd->response[1] = readl(&mmc_base->rsp54);
1165                                 cmd->response[0] = readl(&mmc_base->rsp76);
1166                         } else
1167                                 /* response types 1, 1b, 3, 4, 5, 6 */
1168                                 cmd->response[0] = readl(&mmc_base->rsp10);
1169                 }
1170         }
1171
1172 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1173         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1174             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1175                 u32 sz_mb, timeout;
1176
1177                 if (mmc_stat & IE_ADMAE) {
1178                         omap_hsmmc_dma_cleanup(mmc);
1179                         return -EIO;
1180                 }
1181
1182                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1183                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1184                 if (timeout < MAX_RETRY_MS)
1185                         timeout = MAX_RETRY_MS;
1186
1187                 start = get_timer(0);
1188                 do {
1189                         mmc_stat = readl(&mmc_base->stat);
1190                         if (mmc_stat & TC_MASK) {
1191                                 writel(readl(&mmc_base->stat) | TC_MASK,
1192                                        &mmc_base->stat);
1193                                 break;
1194                         }
1195                         if (get_timer(start) > timeout) {
1196                                 printf("%s : DMA timeout: No status update\n",
1197                                        __func__);
1198                                 return -ETIMEDOUT;
1199                         }
1200                 } while (1);
1201
1202                 omap_hsmmc_dma_cleanup(mmc);
1203                 return 0;
1204         }
1205 #endif
1206
1207         if (data && (data->flags & MMC_DATA_READ)) {
1208                 mmc_read_data(mmc_base, data->dest,
1209                                 data->blocksize * data->blocks);
1210         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1211                 mmc_write_data(mmc_base, data->src,
1212                                 data->blocksize * data->blocks);
1213         }
1214         return 0;
1215 }
1216
1217 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1218 {
1219         unsigned int *output_buf = (unsigned int *)buf;
1220         unsigned int mmc_stat;
1221         unsigned int count;
1222
1223         /*
1224          * Start Polled Read
1225          */
1226         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1227         count /= 4;
1228
1229         while (size) {
1230                 ulong start = get_timer(0);
1231                 do {
1232                         mmc_stat = readl(&mmc_base->stat);
1233                         if (get_timer(0) - start > MAX_RETRY_MS) {
1234                                 printf("%s: timedout waiting for status!\n",
1235                                                 __func__);
1236                                 return -ETIMEDOUT;
1237                         }
1238                 } while (mmc_stat == 0);
1239
1240                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1241                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1242
1243                 if ((mmc_stat & ERRI_MASK) != 0)
1244                         return 1;
1245
1246                 if (mmc_stat & BRR_MASK) {
1247                         unsigned int k;
1248
1249                         writel(readl(&mmc_base->stat) | BRR_MASK,
1250                                 &mmc_base->stat);
1251                         for (k = 0; k < count; k++) {
1252                                 *output_buf = readl(&mmc_base->data);
1253                                 output_buf++;
1254                         }
1255                         size -= (count*4);
1256                 }
1257
1258                 if (mmc_stat & BWR_MASK)
1259                         writel(readl(&mmc_base->stat) | BWR_MASK,
1260                                 &mmc_base->stat);
1261
1262                 if (mmc_stat & TC_MASK) {
1263                         writel(readl(&mmc_base->stat) | TC_MASK,
1264                                 &mmc_base->stat);
1265                         break;
1266                 }
1267         }
1268         return 0;
1269 }
1270
1271 #if CONFIG_IS_ENABLED(MMC_WRITE)
1272 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1273                           unsigned int size)
1274 {
1275         unsigned int *input_buf = (unsigned int *)buf;
1276         unsigned int mmc_stat;
1277         unsigned int count;
1278
1279         /*
1280          * Start Polled Write
1281          */
1282         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1283         count /= 4;
1284
1285         while (size) {
1286                 ulong start = get_timer(0);
1287                 do {
1288                         mmc_stat = readl(&mmc_base->stat);
1289                         if (get_timer(0) - start > MAX_RETRY_MS) {
1290                                 printf("%s: timedout waiting for status!\n",
1291                                                 __func__);
1292                                 return -ETIMEDOUT;
1293                         }
1294                 } while (mmc_stat == 0);
1295
1296                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1297                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1298
1299                 if ((mmc_stat & ERRI_MASK) != 0)
1300                         return 1;
1301
1302                 if (mmc_stat & BWR_MASK) {
1303                         unsigned int k;
1304
1305                         writel(readl(&mmc_base->stat) | BWR_MASK,
1306                                         &mmc_base->stat);
1307                         for (k = 0; k < count; k++) {
1308                                 writel(*input_buf, &mmc_base->data);
1309                                 input_buf++;
1310                         }
1311                         size -= (count*4);
1312                 }
1313
1314                 if (mmc_stat & BRR_MASK)
1315                         writel(readl(&mmc_base->stat) | BRR_MASK,
1316                                 &mmc_base->stat);
1317
1318                 if (mmc_stat & TC_MASK) {
1319                         writel(readl(&mmc_base->stat) | TC_MASK,
1320                                 &mmc_base->stat);
1321                         break;
1322                 }
1323         }
1324         return 0;
1325 }
1326 #else
1327 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1328                           unsigned int size)
1329 {
1330         return -ENOTSUPP;
1331 }
1332 #endif
1333 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1334 {
1335         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1336 }
1337
1338 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1339 {
1340         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1341 }
1342
1343 static void omap_hsmmc_set_clock(struct mmc *mmc)
1344 {
1345         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1346         struct hsmmc *mmc_base;
1347         unsigned int dsor = 0;
1348         ulong start;
1349
1350         mmc_base = priv->base_addr;
1351         omap_hsmmc_stop_clock(mmc_base);
1352
1353         /* TODO: Is setting DTO required here? */
1354         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1355                     (ICE_STOP | DTO_15THDTO));
1356
1357         if (mmc->clock != 0) {
1358                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1359                 if (dsor > CLKD_MAX)
1360                         dsor = CLKD_MAX;
1361         } else {
1362                 dsor = CLKD_MAX;
1363         }
1364
1365         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1366                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1367
1368         start = get_timer(0);
1369         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1370                 if (get_timer(0) - start > MAX_RETRY_MS) {
1371                         printf("%s: timedout waiting for ics!\n", __func__);
1372                         return;
1373                 }
1374         }
1375
1376         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1377         mmc->clock = priv->clock;
1378         omap_hsmmc_start_clock(mmc_base);
1379 }
1380
1381 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1382 {
1383         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1384         struct hsmmc *mmc_base;
1385
1386         mmc_base = priv->base_addr;
1387         /* configue bus width */
1388         switch (mmc->bus_width) {
1389         case 8:
1390                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1391                         &mmc_base->con);
1392                 break;
1393
1394         case 4:
1395                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1396                         &mmc_base->con);
1397                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1398                         &mmc_base->hctl);
1399                 break;
1400
1401         case 1:
1402         default:
1403                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1404                         &mmc_base->con);
1405                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1406                         &mmc_base->hctl);
1407                 break;
1408         }
1409
1410         priv->bus_width = mmc->bus_width;
1411 }
1412
1413 #if !CONFIG_IS_ENABLED(DM_MMC)
1414 static int omap_hsmmc_set_ios(struct mmc *mmc)
1415 {
1416         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1417 #else
1418 static int omap_hsmmc_set_ios(struct udevice *dev)
1419 {
1420         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1421         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1422         struct mmc *mmc = upriv->mmc;
1423 #endif
1424         struct hsmmc *mmc_base = priv->base_addr;
1425         int ret = 0;
1426
1427         if (priv->bus_width != mmc->bus_width)
1428                 omap_hsmmc_set_bus_width(mmc);
1429
1430         if (priv->clock != mmc->clock)
1431                 omap_hsmmc_set_clock(mmc);
1432
1433         if (mmc->clk_disable)
1434                 omap_hsmmc_stop_clock(mmc_base);
1435         else
1436                 omap_hsmmc_start_clock(mmc_base);
1437
1438 #if CONFIG_IS_ENABLED(DM_MMC)
1439         if (priv->mode != mmc->selected_mode)
1440                 omap_hsmmc_set_timing(mmc);
1441
1442 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1443         if (priv->signal_voltage != mmc->signal_voltage)
1444                 ret = omap_hsmmc_set_signal_voltage(mmc);
1445 #endif
1446 #endif
1447         return ret;
1448 }
1449
1450 #ifdef OMAP_HSMMC_USE_GPIO
1451 #if CONFIG_IS_ENABLED(DM_MMC)
1452 static int omap_hsmmc_getcd(struct udevice *dev)
1453 {
1454         int value = -1;
1455 #if CONFIG_IS_ENABLED(DM_GPIO)
1456         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1457         value = dm_gpio_get_value(&priv->cd_gpio);
1458 #endif
1459         /* if no CD return as 1 */
1460         if (value < 0)
1461                 return 1;
1462
1463         return value;
1464 }
1465
1466 static int omap_hsmmc_getwp(struct udevice *dev)
1467 {
1468         int value = 0;
1469 #if CONFIG_IS_ENABLED(DM_GPIO)
1470         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1471         value = dm_gpio_get_value(&priv->wp_gpio);
1472 #endif
1473         /* if no WP return as 0 */
1474         if (value < 0)
1475                 return 0;
1476         return value;
1477 }
1478 #else
1479 static int omap_hsmmc_getcd(struct mmc *mmc)
1480 {
1481         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1482         int cd_gpio;
1483
1484         /* if no CD return as 1 */
1485         cd_gpio = priv->cd_gpio;
1486         if (cd_gpio < 0)
1487                 return 1;
1488
1489         /* NOTE: assumes card detect signal is active-low */
1490         return !gpio_get_value(cd_gpio);
1491 }
1492
1493 static int omap_hsmmc_getwp(struct mmc *mmc)
1494 {
1495         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1496         int wp_gpio;
1497
1498         /* if no WP return as 0 */
1499         wp_gpio = priv->wp_gpio;
1500         if (wp_gpio < 0)
1501                 return 0;
1502
1503         /* NOTE: assumes write protect signal is active-high */
1504         return gpio_get_value(wp_gpio);
1505 }
1506 #endif
1507 #endif
1508
1509 #if CONFIG_IS_ENABLED(DM_MMC)
1510 static const struct dm_mmc_ops omap_hsmmc_ops = {
1511         .send_cmd       = omap_hsmmc_send_cmd,
1512         .set_ios        = omap_hsmmc_set_ios,
1513 #ifdef OMAP_HSMMC_USE_GPIO
1514         .get_cd         = omap_hsmmc_getcd,
1515         .get_wp         = omap_hsmmc_getwp,
1516 #endif
1517 #ifdef MMC_SUPPORTS_TUNING
1518         .execute_tuning = omap_hsmmc_execute_tuning,
1519 #endif
1520         .wait_dat0      = omap_hsmmc_wait_dat0,
1521 };
1522 #else
1523 static const struct mmc_ops omap_hsmmc_ops = {
1524         .send_cmd       = omap_hsmmc_send_cmd,
1525         .set_ios        = omap_hsmmc_set_ios,
1526         .init           = omap_hsmmc_init_setup,
1527 #ifdef OMAP_HSMMC_USE_GPIO
1528         .getcd          = omap_hsmmc_getcd,
1529         .getwp          = omap_hsmmc_getwp,
1530 #endif
1531 };
1532 #endif
1533
1534 #if !CONFIG_IS_ENABLED(DM_MMC)
1535 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1536                 int wp_gpio)
1537 {
1538         struct mmc *mmc;
1539         struct omap_hsmmc_data *priv;
1540         struct mmc_config *cfg;
1541         uint host_caps_val;
1542
1543         priv = calloc(1, sizeof(*priv));
1544         if (priv == NULL)
1545                 return -1;
1546
1547         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1548
1549         switch (dev_index) {
1550         case 0:
1551                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1552                 break;
1553 #ifdef OMAP_HSMMC2_BASE
1554         case 1:
1555                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1556 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1557         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1558         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1559                 defined(CONFIG_HSMMC2_8BIT)
1560                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1561                 host_caps_val |= MMC_MODE_8BIT;
1562 #endif
1563                 break;
1564 #endif
1565 #ifdef OMAP_HSMMC3_BASE
1566         case 2:
1567                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1568 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1569                 /* Enable 8-bit interface for eMMC on DRA7XX */
1570                 host_caps_val |= MMC_MODE_8BIT;
1571 #endif
1572                 break;
1573 #endif
1574         default:
1575                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1576                 return 1;
1577         }
1578 #ifdef OMAP_HSMMC_USE_GPIO
1579         /* on error gpio values are set to -1, which is what we want */
1580         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1581         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1582 #endif
1583
1584         cfg = &priv->cfg;
1585
1586         cfg->name = "OMAP SD/MMC";
1587         cfg->ops = &omap_hsmmc_ops;
1588
1589         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1590         cfg->host_caps = host_caps_val & ~host_caps_mask;
1591
1592         cfg->f_min = 400000;
1593
1594         if (f_max != 0)
1595                 cfg->f_max = f_max;
1596         else {
1597                 if (cfg->host_caps & MMC_MODE_HS) {
1598                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1599                                 cfg->f_max = 52000000;
1600                         else
1601                                 cfg->f_max = 26000000;
1602                 } else
1603                         cfg->f_max = 20000000;
1604         }
1605
1606         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1607
1608 #if defined(CONFIG_OMAP34XX)
1609         /*
1610          * Silicon revs 2.1 and older do not support multiblock transfers.
1611          */
1612         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1613                 cfg->b_max = 1;
1614 #endif
1615
1616         mmc = mmc_create(cfg, priv);
1617         if (mmc == NULL)
1618                 return -1;
1619
1620         return 0;
1621 }
1622 #else
1623
1624 #ifdef CONFIG_IODELAY_RECALIBRATION
1625 static struct pad_conf_entry *
1626 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1627 {
1628         int index = 0;
1629         struct pad_conf_entry *padconf;
1630
1631         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1632         if (!padconf) {
1633                 debug("failed to allocate memory\n");
1634                 return 0;
1635         }
1636
1637         while (index < count) {
1638                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1639                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1640                 index++;
1641         }
1642
1643         return padconf;
1644 }
1645
1646 static struct iodelay_cfg_entry *
1647 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1648 {
1649         int index = 0;
1650         struct iodelay_cfg_entry *iodelay;
1651
1652         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1653         if (!iodelay) {
1654                 debug("failed to allocate memory\n");
1655                 return 0;
1656         }
1657
1658         while (index < count) {
1659                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1660                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1661                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1662                 index++;
1663         }
1664
1665         return iodelay;
1666 }
1667
1668 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1669                                                    const char *name, int *len)
1670 {
1671         const void *fdt = gd->fdt_blob;
1672         int offset;
1673         const fdt32_t *pinctrl;
1674
1675         offset = fdt_node_offset_by_phandle(fdt, phandle);
1676         if (offset < 0) {
1677                 debug("failed to get pinctrl node %s.\n",
1678                       fdt_strerror(offset));
1679                 return 0;
1680         }
1681
1682         pinctrl = fdt_getprop(fdt, offset, name, len);
1683         if (!pinctrl) {
1684                 debug("failed to get property %s\n", name);
1685                 return 0;
1686         }
1687
1688         return pinctrl;
1689 }
1690
1691 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1692                                                 char *prop_name)
1693 {
1694         const void *fdt = gd->fdt_blob;
1695         const __be32 *phandle;
1696         int node = dev_of_offset(mmc->dev);
1697
1698         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1699         if (!phandle) {
1700                 debug("failed to get property %s\n", prop_name);
1701                 return 0;
1702         }
1703
1704         return fdt32_to_cpu(*phandle);
1705 }
1706
1707 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1708                                                char *prop_name)
1709 {
1710         const void *fdt = gd->fdt_blob;
1711         const __be32 *phandle;
1712         int len;
1713         int count;
1714         int node = dev_of_offset(mmc->dev);
1715
1716         phandle = fdt_getprop(fdt, node, prop_name, &len);
1717         if (!phandle) {
1718                 debug("failed to get property %s\n", prop_name);
1719                 return 0;
1720         }
1721
1722         /* No manual mode iodelay values if count < 2 */
1723         count = len / sizeof(*phandle);
1724         if (count < 2)
1725                 return 0;
1726
1727         return fdt32_to_cpu(*(phandle + 1));
1728 }
1729
1730 static struct pad_conf_entry *
1731 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1732 {
1733         int len;
1734         int count;
1735         struct pad_conf_entry *padconf;
1736         u32 phandle;
1737         const fdt32_t *pinctrl;
1738
1739         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1740         if (!phandle)
1741                 return ERR_PTR(-EINVAL);
1742
1743         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1744                                                &len);
1745         if (!pinctrl)
1746                 return ERR_PTR(-EINVAL);
1747
1748         count = (len / sizeof(*pinctrl)) / 2;
1749         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1750         if (!padconf)
1751                 return ERR_PTR(-EINVAL);
1752
1753         *npads = count;
1754
1755         return padconf;
1756 }
1757
1758 static struct iodelay_cfg_entry *
1759 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1760 {
1761         int len;
1762         int count;
1763         struct iodelay_cfg_entry *iodelay;
1764         u32 phandle;
1765         const fdt32_t *pinctrl;
1766
1767         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1768         /* Not all modes have manual mode iodelay values. So its not fatal */
1769         if (!phandle)
1770                 return 0;
1771
1772         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1773                                                &len);
1774         if (!pinctrl)
1775                 return ERR_PTR(-EINVAL);
1776
1777         count = (len / sizeof(*pinctrl)) / 3;
1778         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1779         if (!iodelay)
1780                 return ERR_PTR(-EINVAL);
1781
1782         *niodelay = count;
1783
1784         return iodelay;
1785 }
1786
1787 static struct omap_hsmmc_pinctrl_state *
1788 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1789 {
1790         int index;
1791         int npads = 0;
1792         int niodelays = 0;
1793         const void *fdt = gd->fdt_blob;
1794         int node = dev_of_offset(mmc->dev);
1795         char prop_name[11];
1796         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1797
1798         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1799                          malloc(sizeof(*pinctrl_state));
1800         if (!pinctrl_state) {
1801                 debug("failed to allocate memory\n");
1802                 return 0;
1803         }
1804
1805         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1806         if (index < 0) {
1807                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1808                 goto err_pinctrl_state;
1809         }
1810
1811         sprintf(prop_name, "pinctrl-%d", index);
1812
1813         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1814                                                          &npads);
1815         if (IS_ERR(pinctrl_state->padconf))
1816                 goto err_pinctrl_state;
1817         pinctrl_state->npads = npads;
1818
1819         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1820                                                         &niodelays);
1821         if (IS_ERR(pinctrl_state->iodelay))
1822                 goto err_padconf;
1823         pinctrl_state->niodelays = niodelays;
1824
1825         return pinctrl_state;
1826
1827 err_padconf:
1828         kfree(pinctrl_state->padconf);
1829
1830 err_pinctrl_state:
1831         kfree(pinctrl_state);
1832         return 0;
1833 }
1834
1835 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1836         do {                                                            \
1837                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1838                 char str[20];                                           \
1839                 if (!(cfg->host_caps & capmask))                        \
1840                         break;                                          \
1841                                                                         \
1842                 if (priv->hw_rev) {                                     \
1843                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1844                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1845                 }                                                       \
1846                                                                         \
1847                 if (!s)                                                 \
1848                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1849                                                                         \
1850                 if (!s && !optional) {                                  \
1851                         debug("%s: no pinctrl for %s\n",                \
1852                               mmc->dev->name, #mode);                   \
1853                         cfg->host_caps &= ~(capmask);                   \
1854                 } else {                                                \
1855                         priv->mode##_pinctrl_state = s;                 \
1856                 }                                                       \
1857         } while (0)
1858
1859 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1860 {
1861         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1862         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1863         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1864
1865         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1866                 return 0;
1867
1868         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1869         if (!default_pinctrl) {
1870                 printf("no pinctrl state for default mode\n");
1871                 return -EINVAL;
1872         }
1873
1874         priv->default_pinctrl_state = default_pinctrl;
1875
1876         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1877         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1878         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1879         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1880         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1881
1882         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1883         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1884         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1885
1886         return 0;
1887 }
1888 #endif
1889
1890 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1891 #ifdef CONFIG_OMAP54XX
1892 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1893 {
1894         return NULL;
1895 }
1896 #endif
1897
1898 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1899 {
1900         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1901         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1902
1903         struct mmc_config *cfg = &plat->cfg;
1904 #ifdef CONFIG_OMAP54XX
1905         const struct mmc_platform_fixups *fixups;
1906 #endif
1907         const void *fdt = gd->fdt_blob;
1908         int node = dev_of_offset(dev);
1909         int ret;
1910
1911         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1912                                       sizeof(struct hsmmc *),
1913                                       MAP_NOCACHE);
1914
1915         ret = mmc_of_parse(dev, cfg);
1916         if (ret < 0)
1917                 return ret;
1918
1919         if (!cfg->f_max)
1920                 cfg->f_max = 52000000;
1921         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1922         cfg->f_min = 400000;
1923         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1924         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1925         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1926                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1927         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1928                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1929         if (of_data)
1930                 plat->controller_flags |= of_data->controller_flags;
1931
1932 #ifdef CONFIG_OMAP54XX
1933         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1934         if (fixups) {
1935                 plat->hw_rev = fixups->hw_rev;
1936                 cfg->host_caps &= ~fixups->unsupported_caps;
1937                 cfg->f_max = fixups->max_freq;
1938         }
1939 #endif
1940
1941         return 0;
1942 }
1943 #endif
1944
1945 #ifdef CONFIG_BLK
1946
1947 static int omap_hsmmc_bind(struct udevice *dev)
1948 {
1949         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1950         plat->mmc = calloc(1, sizeof(struct mmc));
1951         return mmc_bind(dev, plat->mmc, &plat->cfg);
1952 }
1953 #endif
1954 static int omap_hsmmc_probe(struct udevice *dev)
1955 {
1956         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1957         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1958         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1959         struct mmc_config *cfg = &plat->cfg;
1960         struct mmc *mmc;
1961 #ifdef CONFIG_IODELAY_RECALIBRATION
1962         int ret;
1963 #endif
1964
1965         cfg->name = "OMAP SD/MMC";
1966         priv->base_addr = plat->base_addr;
1967         priv->controller_flags = plat->controller_flags;
1968         priv->hw_rev = plat->hw_rev;
1969
1970 #ifdef CONFIG_BLK
1971         mmc = plat->mmc;
1972 #else
1973         mmc = mmc_create(cfg, priv);
1974         if (mmc == NULL)
1975                 return -1;
1976 #endif
1977 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1978         device_get_supply_regulator(dev, "pbias-supply",
1979                                     &priv->pbias_supply);
1980 #endif
1981 #if defined(OMAP_HSMMC_USE_GPIO)
1982 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1983         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1984         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1985 #endif
1986 #endif
1987
1988         mmc->dev = dev;
1989         upriv->mmc = mmc;
1990
1991 #ifdef CONFIG_IODELAY_RECALIBRATION
1992         ret = omap_hsmmc_get_pinctrl_state(mmc);
1993         /*
1994          * disable high speed modes for the platforms that require IO delay
1995          * and for which we don't have this information
1996          */
1997         if ((ret < 0) &&
1998             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1999                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2000                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2001                                     UHS_CAPS);
2002         }
2003 #endif
2004
2005         return omap_hsmmc_init_setup(mmc);
2006 }
2007
2008 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2009
2010 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2011         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2012 };
2013
2014 static const struct udevice_id omap_hsmmc_ids[] = {
2015         { .compatible = "ti,omap3-hsmmc" },
2016         { .compatible = "ti,omap4-hsmmc" },
2017         { .compatible = "ti,am33xx-hsmmc" },
2018         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2019         { }
2020 };
2021 #endif
2022
2023 U_BOOT_DRIVER(omap_hsmmc) = {
2024         .name   = "omap_hsmmc",
2025         .id     = UCLASS_MMC,
2026 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2027         .of_match = omap_hsmmc_ids,
2028         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2029         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2030 #endif
2031 #ifdef CONFIG_BLK
2032         .bind = omap_hsmmc_bind,
2033 #endif
2034         .ops = &omap_hsmmc_ops,
2035         .probe  = omap_hsmmc_probe,
2036         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2037 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2038         .flags  = DM_FLAG_PRE_RELOC,
2039 #endif
2040 };
2041 #endif