drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <mmc.h>
  29 #include <part.h>
  30 #include <i2c.h>
  31 #include <twl4030.h>
  32 #include <twl6030.h>
  33 #include <palmas.h>
  34 #include <asm/io.h>
  35 #include <asm/arch/mmc_host_def.h>
  36 #if !defined(CONFIG_SOC_KEYSTONE)
  37 #include <asm/gpio.h>
  38 #include <asm/arch/sys_proto.h>
  39 #endif
  40 #include <dm.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  45 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  46         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  47 #define OMAP_HSMMC_USE_GPIO
  48 #else
  49 #undef OMAP_HSMMC_USE_GPIO
  50 #endif
  51
  52 /* common definitions for all OMAPs */
  53 #define SYSCTL_SRC      (1 << 25)
  54 #define SYSCTL_SRD      (1 << 26)
  55
  56 struct omap_hsmmc_data {
  57         struct hsmmc *base_addr;
  58         struct mmc_config cfg;
  59 #ifdef OMAP_HSMMC_USE_GPIO
  60 #ifdef CONFIG_DM_MMC
  61         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  62         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  63         bool cd_inverted;
  64 #else
  65         int cd_gpio;
  66         int wp_gpio;
  67 #endif
  68 #endif
  69 };
  70
  71 /* If we fail after 1 second wait, something is really bad */
  72 #define MAX_RETRY_MS    1000
  73
  74 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  75 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  76                         unsigned int siz);
  77
  78 #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
  79 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  80 {
  81         int ret;
  82
  83 #ifndef CONFIG_DM_GPIO
  84         if (!gpio_is_valid(gpio))
  85                 return -1;
  86 #endif
  87         ret = gpio_request(gpio, label);
  88         if (ret)
  89                 return ret;
  90
  91         ret = gpio_direction_input(gpio);
  92         if (ret)
  93                 return ret;
  94
  95         return gpio;
  96 }
  97 #endif
  98
  99 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 100 static void omap4_vmmc_pbias_config(struct mmc *mmc)
 101 {
 102         u32 value = 0;
 103
 104         value = readl((*ctrl)->control_pbiaslite);
 105         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
 106         writel(value, (*ctrl)->control_pbiaslite);
 107         /* set VMMC to 3V */
 108         twl6030_power_mmc_init();
 109         value = readl((*ctrl)->control_pbiaslite);
 110         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 111         writel(value, (*ctrl)->control_pbiaslite);
 112 }
 113 #endif
 114
 115 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 116 static void omap5_pbias_config(struct mmc *mmc)
 117 {
 118         u32 value = 0;
 119
 120         value = readl((*ctrl)->control_pbias);
 121         value &= ~SDCARD_PWRDNZ;
 122         writel(value, (*ctrl)->control_pbias);
 123         udelay(10); /* wait 10 us */
 124         value &= ~SDCARD_BIAS_PWRDNZ;
 125         writel(value, (*ctrl)->control_pbias);
 126
 127         palmas_mmc1_poweron_ldo();
 128
 129         value = readl((*ctrl)->control_pbias);
 130         value |= SDCARD_BIAS_PWRDNZ;
 131         writel(value, (*ctrl)->control_pbias);
 132         udelay(150); /* wait 150 us */
 133         value |= SDCARD_PWRDNZ;
 134         writel(value, (*ctrl)->control_pbias);
 135         udelay(150); /* wait 150 us */
 136 }
 137 #endif
 138
 139 static unsigned char mmc_board_init(struct mmc *mmc)
 140 {
 141 #if defined(CONFIG_OMAP34XX)
 142         t2_t *t2_base = (t2_t *)T2_BASE;
 143         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 144         u32 pbias_lite;
 145
 146         pbias_lite = readl(&t2_base->pbias_lite);
 147         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 148 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 149         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 150         pbias_lite &= ~PBIASLITEVMODE0;
 151 #endif
 152         writel(pbias_lite, &t2_base->pbias_lite);
 153
 154         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 155                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 156                 &t2_base->pbias_lite);
 157
 158         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 159                 &t2_base->devconf0);
 160
 161         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 162                 &t2_base->devconf1);
 163
 164         /* Change from default of 52MHz to 26MHz if necessary */
 165         if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
 166                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 167                         &t2_base->ctl_prog_io1);
 168
 169         writel(readl(&prcm_base->fclken1_core) |
 170                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 171                 &prcm_base->fclken1_core);
 172
 173         writel(readl(&prcm_base->iclken1_core) |
 174                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 175                 &prcm_base->iclken1_core);
 176 #endif
 177
 178 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 179         /* PBIAS config needed for MMC1 only */
 180         if (mmc->block_dev.dev == 0)
 181                 omap4_vmmc_pbias_config(mmc);
 182 #endif
 183 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 184         if (mmc->block_dev.dev == 0)
 185                 omap5_pbias_config(mmc);
 186 #endif
 187
 188         return 0;
 189 }
 190
 191 void mmc_init_stream(struct hsmmc *mmc_base)
 192 {
 193         ulong start;
 194
 195         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 196
 197         writel(MMC_CMD0, &mmc_base->cmd);
 198         start = get_timer(0);
 199         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 200                 if (get_timer(0) - start > MAX_RETRY_MS) {
 201                         printf("%s: timedout waiting for cc!\n", __func__);
 202                         return;
 203                 }
 204         }
 205         writel(CC_MASK, &mmc_base->stat)
 206                 ;
 207         writel(MMC_CMD0, &mmc_base->cmd)
 208                 ;
 209         start = get_timer(0);
 210         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 211                 if (get_timer(0) - start > MAX_RETRY_MS) {
 212                         printf("%s: timedout waiting for cc2!\n", __func__);
 213                         return;
 214                 }
 215         }
 216         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 217 }
 218
 219
 220 static int omap_hsmmc_init_setup(struct mmc *mmc)
 221 {
 222         struct hsmmc *mmc_base;
 223         unsigned int reg_val;
 224         unsigned int dsor;
 225         ulong start;
 226
 227         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 228         mmc_board_init(mmc);
 229
 230         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 231                 &mmc_base->sysconfig);
 232         start = get_timer(0);
 233         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 234                 if (get_timer(0) - start > MAX_RETRY_MS) {
 235                         printf("%s: timedout waiting for cc2!\n", __func__);
 236                         return TIMEOUT;
 237                 }
 238         }
 239         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 240         start = get_timer(0);
 241         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 242                 if (get_timer(0) - start > MAX_RETRY_MS) {
 243                         printf("%s: timedout waiting for softresetall!\n",
 244                                 __func__);
 245                         return TIMEOUT;
 246                 }
 247         }
 248         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 249         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 250                 &mmc_base->capa);
 251
 252         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 253
 254         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 255                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 256                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 257
 258         dsor = 240;
 259         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 260                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 261         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 262                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 263         start = get_timer(0);
 264         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 265                 if (get_timer(0) - start > MAX_RETRY_MS) {
 266                         printf("%s: timedout waiting for ics!\n", __func__);
 267                         return TIMEOUT;
 268                 }
 269         }
 270         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 271
 272         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 273
 274         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 275                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 276                 &mmc_base->ie);
 277
 278         mmc_init_stream(mmc_base);
 279
 280         return 0;
 281 }
 282
 283 /*
 284  * MMC controller internal finite state machine reset
 285  *
 286  * Used to reset command or data internal state machines, using respectively
 287  * SRC or SRD bit of SYSCTL register
 288  */
 289 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 290 {
 291         ulong start;
 292
 293         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 294
 295         /*
 296          * CMD(DAT) lines reset procedures are slightly different
 297          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 298          * According to OMAP3 TRM:
 299          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 300          * returns to 0x0.
 301          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 302          * procedure steps must be as follows:
 303          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 304          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 305          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 306          * 3. Wait until the SRC (SRD) bit returns to 0x0
 307          *    (reset procedure is completed).
 308          */
 309 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 310         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 311         if (!(readl(&mmc_base->sysctl) & bit)) {
 312                 start = get_timer(0);
 313                 while (!(readl(&mmc_base->sysctl) & bit)) {
 314                         if (get_timer(0) - start > MAX_RETRY_MS)
 315                                 return;
 316                 }
 317         }
 318 #endif
 319         start = get_timer(0);
 320         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 321                 if (get_timer(0) - start > MAX_RETRY_MS) {
 322                         printf("%s: timedout waiting for sysctl %x to clear\n",
 323                                 __func__, bit);
 324                         return;
 325                 }
 326         }
 327 }
 328
 329 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 330                         struct mmc_data *data)
 331 {
 332         struct hsmmc *mmc_base;
 333         unsigned int flags, mmc_stat;
 334         ulong start;
 335
 336         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 337         start = get_timer(0);
 338         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 339                 if (get_timer(0) - start > MAX_RETRY_MS) {
 340                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 341                                         __func__);
 342                         return TIMEOUT;
 343                 }
 344         }
 345         writel(0xFFFFFFFF, &mmc_base->stat);
 346         start = get_timer(0);
 347         while (readl(&mmc_base->stat)) {
 348                 if (get_timer(0) - start > MAX_RETRY_MS) {
 349                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 350                                 __func__, readl(&mmc_base->stat));
 351                         return TIMEOUT;
 352                 }
 353         }
 354         /*
 355          * CMDREG
 356          * CMDIDX[13:8] : Command index
 357          * DATAPRNT[5]  : Data Present Select
 358          * ENCMDIDX[4]  : Command Index Check Enable
 359          * ENCMDCRC[3]  : Command CRC Check Enable
 360          * RSPTYP[1:0]
 361          *      00 = No Response
 362          *      01 = Length 136
 363          *      10 = Length 48
 364          *      11 = Length 48 Check busy after response
 365          */
 366         /* Delay added before checking the status of frq change
 367          * retry not supported by mmc.c(core file)
 368          */
 369         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 370                 udelay(50000); /* wait 50 ms */
 371
 372         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 373                 flags = 0;
 374         else if (cmd->resp_type & MMC_RSP_136)
 375                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 376         else if (cmd->resp_type & MMC_RSP_BUSY)
 377                 flags = RSP_TYPE_LGHT48B;
 378         else
 379                 flags = RSP_TYPE_LGHT48;
 380
 381         /* enable default flags */
 382         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 383                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 384
 385         if (cmd->resp_type & MMC_RSP_CRC)
 386                 flags |= CCCE_CHECK;
 387         if (cmd->resp_type & MMC_RSP_OPCODE)
 388                 flags |= CICE_CHECK;
 389
 390         if (data) {
 391                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 392                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 393                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 394                         data->blocksize = 512;
 395                         writel(data->blocksize | (data->blocks << 16),
 396                                                         &mmc_base->blk);
 397                 } else
 398                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 399
 400                 if (data->flags & MMC_DATA_READ)
 401                         flags |= (DP_DATA | DDIR_READ);
 402                 else
 403                         flags |= (DP_DATA | DDIR_WRITE);
 404         }
 405
 406         writel(cmd->cmdarg, &mmc_base->arg);
 407         udelay(20);             /* To fix "No status update" error on eMMC */
 408         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 409
 410         start = get_timer(0);
 411         do {
 412                 mmc_stat = readl(&mmc_base->stat);
 413                 if (get_timer(0) - start > MAX_RETRY_MS) {
 414                         printf("%s : timeout: No status update\n", __func__);
 415                         return TIMEOUT;
 416                 }
 417         } while (!mmc_stat);
 418
 419         if ((mmc_stat & IE_CTO) != 0) {
 420                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 421                 return TIMEOUT;
 422         } else if ((mmc_stat & ERRI_MASK) != 0)
 423                 return -1;
 424
 425         if (mmc_stat & CC_MASK) {
 426                 writel(CC_MASK, &mmc_base->stat);
 427                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 428                         if (cmd->resp_type & MMC_RSP_136) {
 429                                 /* response type 2 */
 430                                 cmd->response[3] = readl(&mmc_base->rsp10);
 431                                 cmd->response[2] = readl(&mmc_base->rsp32);
 432                                 cmd->response[1] = readl(&mmc_base->rsp54);
 433                                 cmd->response[0] = readl(&mmc_base->rsp76);
 434                         } else
 435                                 /* response types 1, 1b, 3, 4, 5, 6 */
 436                                 cmd->response[0] = readl(&mmc_base->rsp10);
 437                 }
 438         }
 439
 440         if (data && (data->flags & MMC_DATA_READ)) {
 441                 mmc_read_data(mmc_base, data->dest,
 442                                 data->blocksize * data->blocks);
 443         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 444                 mmc_write_data(mmc_base, data->src,
 445                                 data->blocksize * data->blocks);
 446         }
 447         return 0;
 448 }
 449
 450 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 451 {
 452         unsigned int *output_buf = (unsigned int *)buf;
 453         unsigned int mmc_stat;
 454         unsigned int count;
 455
 456         /*
 457          * Start Polled Read
 458          */
 459         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 460         count /= 4;
 461
 462         while (size) {
 463                 ulong start = get_timer(0);
 464                 do {
 465                         mmc_stat = readl(&mmc_base->stat);
 466                         if (get_timer(0) - start > MAX_RETRY_MS) {
 467                                 printf("%s: timedout waiting for status!\n",
 468                                                 __func__);
 469                                 return TIMEOUT;
 470                         }
 471                 } while (mmc_stat == 0);
 472
 473                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 474                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 475
 476                 if ((mmc_stat & ERRI_MASK) != 0)
 477                         return 1;
 478
 479                 if (mmc_stat & BRR_MASK) {
 480                         unsigned int k;
 481
 482                         writel(readl(&mmc_base->stat) | BRR_MASK,
 483                                 &mmc_base->stat);
 484                         for (k = 0; k < count; k++) {
 485                                 *output_buf = readl(&mmc_base->data);
 486                                 output_buf++;
 487                         }
 488                         size -= (count*4);
 489                 }
 490
 491                 if (mmc_stat & BWR_MASK)
 492                         writel(readl(&mmc_base->stat) | BWR_MASK,
 493                                 &mmc_base->stat);
 494
 495                 if (mmc_stat & TC_MASK) {
 496                         writel(readl(&mmc_base->stat) | TC_MASK,
 497                                 &mmc_base->stat);
 498                         break;
 499                 }
 500         }
 501         return 0;
 502 }
 503
 504 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 505                                 unsigned int size)
 506 {
 507         unsigned int *input_buf = (unsigned int *)buf;
 508         unsigned int mmc_stat;
 509         unsigned int count;
 510
 511         /*
 512          * Start Polled Write
 513          */
 514         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 515         count /= 4;
 516
 517         while (size) {
 518                 ulong start = get_timer(0);
 519                 do {
 520                         mmc_stat = readl(&mmc_base->stat);
 521                         if (get_timer(0) - start > MAX_RETRY_MS) {
 522                                 printf("%s: timedout waiting for status!\n",
 523                                                 __func__);
 524                                 return TIMEOUT;
 525                         }
 526                 } while (mmc_stat == 0);
 527
 528                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 529                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 530
 531                 if ((mmc_stat & ERRI_MASK) != 0)
 532                         return 1;
 533
 534                 if (mmc_stat & BWR_MASK) {
 535                         unsigned int k;
 536
 537                         writel(readl(&mmc_base->stat) | BWR_MASK,
 538                                         &mmc_base->stat);
 539                         for (k = 0; k < count; k++) {
 540                                 writel(*input_buf, &mmc_base->data);
 541                                 input_buf++;
 542                         }
 543                         size -= (count*4);
 544                 }
 545
 546                 if (mmc_stat & BRR_MASK)
 547                         writel(readl(&mmc_base->stat) | BRR_MASK,
 548                                 &mmc_base->stat);
 549
 550                 if (mmc_stat & TC_MASK) {
 551                         writel(readl(&mmc_base->stat) | TC_MASK,
 552                                 &mmc_base->stat);
 553                         break;
 554                 }
 555         }
 556         return 0;
 557 }
 558
 559 static void omap_hsmmc_set_ios(struct mmc *mmc)
 560 {
 561         struct hsmmc *mmc_base;
 562         unsigned int dsor = 0;
 563         ulong start;
 564
 565         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 566         /* configue bus width */
 567         switch (mmc->bus_width) {
 568         case 8:
 569                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 570                         &mmc_base->con);
 571                 break;
 572
 573         case 4:
 574                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 575                         &mmc_base->con);
 576                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 577                         &mmc_base->hctl);
 578                 break;
 579
 580         case 1:
 581         default:
 582                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 583                         &mmc_base->con);
 584                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 585                         &mmc_base->hctl);
 586                 break;
 587         }
 588
 589         /* configure clock with 96Mhz system clock.
 590          */
 591         if (mmc->clock != 0) {
 592                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 593                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 594                         dsor++;
 595         }
 596
 597         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 598                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 599
 600         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 601                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 602
 603         start = get_timer(0);
 604         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 605                 if (get_timer(0) - start > MAX_RETRY_MS) {
 606                         printf("%s: timedout waiting for ics!\n", __func__);
 607                         return;
 608                 }
 609         }
 610         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 611 }
 612
 613 #ifdef OMAP_HSMMC_USE_GPIO
 614 #ifdef CONFIG_DM_MMC
 615 static int omap_hsmmc_getcd(struct mmc *mmc)
 616 {
 617         struct omap_hsmmc_data *priv = mmc->priv;
 618         int value;
 619
 620         value = dm_gpio_get_value(&priv->cd_gpio);
 621         /* if no CD return as 1 */
 622         if (value < 0)
 623                 return 1;
 624
 625         if (priv->cd_inverted)
 626                 return !value;
 627         return value;
 628 }
 629
 630 static int omap_hsmmc_getwp(struct mmc *mmc)
 631 {
 632         struct omap_hsmmc_data *priv = mmc->priv;
 633         int value;
 634
 635         value = dm_gpio_get_value(&priv->wp_gpio);
 636         /* if no WP return as 0 */
 637         if (value < 0)
 638                 return 0;
 639         return value;
 640 }
 641 #else
 642 static int omap_hsmmc_getcd(struct mmc *mmc)
 643 {
 644         struct omap_hsmmc_data *priv_data = mmc->priv;
 645         int cd_gpio;
 646
 647         /* if no CD return as 1 */
 648         cd_gpio = priv_data->cd_gpio;
 649         if (cd_gpio < 0)
 650                 return 1;
 651
 652         /* NOTE: assumes card detect signal is active-low */
 653         return !gpio_get_value(cd_gpio);
 654 }
 655
 656 static int omap_hsmmc_getwp(struct mmc *mmc)
 657 {
 658         struct omap_hsmmc_data *priv_data = mmc->priv;
 659         int wp_gpio;
 660
 661         /* if no WP return as 0 */
 662         wp_gpio = priv_data->wp_gpio;
 663         if (wp_gpio < 0)
 664                 return 0;
 665
 666         /* NOTE: assumes write protect signal is active-high */
 667         return gpio_get_value(wp_gpio);
 668 }
 669 #endif
 670 #endif
 671
 672 static const struct mmc_ops omap_hsmmc_ops = {
 673         .send_cmd       = omap_hsmmc_send_cmd,
 674         .set_ios        = omap_hsmmc_set_ios,
 675         .init           = omap_hsmmc_init_setup,
 676 #ifdef OMAP_HSMMC_USE_GPIO
 677         .getcd          = omap_hsmmc_getcd,
 678         .getwp          = omap_hsmmc_getwp,
 679 #endif
 680 };
 681
 682 #ifndef CONFIG_DM_MMC
 683 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 684                 int wp_gpio)
 685 {
 686         struct mmc *mmc;
 687         struct omap_hsmmc_data *priv_data;
 688         struct mmc_config *cfg;
 689         uint host_caps_val;
 690
 691         priv_data = malloc(sizeof(*priv_data));
 692         if (priv_data == NULL)
 693                 return -1;
 694
 695         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 696
 697         switch (dev_index) {
 698         case 0:
 699                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 700                 break;
 701 #ifdef OMAP_HSMMC2_BASE
 702         case 1:
 703                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 704 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 705         defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
 706         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
 707                 defined(CONFIG_HSMMC2_8BIT)
 708                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
 709                 host_caps_val |= MMC_MODE_8BIT;
 710 #endif
 711                 break;
 712 #endif
 713 #ifdef OMAP_HSMMC3_BASE
 714         case 2:
 715                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
 716 #if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
 717                 /* Enable 8-bit interface for eMMC on DRA7XX */
 718                 host_caps_val |= MMC_MODE_8BIT;
 719 #endif
 720                 break;
 721 #endif
 722         default:
 723                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 724                 return 1;
 725         }
 726 #ifdef OMAP_HSMMC_USE_GPIO
 727         /* on error gpio values are set to -1, which is what we want */
 728         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 729         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 730 #endif
 731
 732         cfg = &priv_data->cfg;
 733
 734         cfg->name = "OMAP SD/MMC";
 735         cfg->ops = &omap_hsmmc_ops;
 736
 737         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 738         cfg->host_caps = host_caps_val & ~host_caps_mask;
 739
 740         cfg->f_min = 400000;
 741
 742         if (f_max != 0)
 743                 cfg->f_max = f_max;
 744         else {
 745                 if (cfg->host_caps & MMC_MODE_HS) {
 746                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
 747                                 cfg->f_max = 52000000;
 748                         else
 749                                 cfg->f_max = 26000000;
 750                 } else
 751                         cfg->f_max = 20000000;
 752         }
 753
 754         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 755
 756 #if defined(CONFIG_OMAP34XX)
 757         /*
 758          * Silicon revs 2.1 and older do not support multiblock transfers.
 759          */
 760         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 761                 cfg->b_max = 1;
 762 #endif
 763         mmc = mmc_create(cfg, priv_data);
 764         if (mmc == NULL)
 765                 return -1;
 766
 767         return 0;
 768 }
 769 #else
 770 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
 771 {
 772         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 773         const void *fdt = gd->fdt_blob;
 774         int node = dev->of_offset;
 775         struct mmc_config *cfg;
 776         int val;
 777
 778         priv->base_addr = (struct hsmmc *)dev_get_addr(dev);
 779         cfg = &priv->cfg;
 780
 781         cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 782         val = fdtdec_get_int(fdt, node, "bus-width", -1);
 783         if (val < 0) {
 784                 printf("error: bus-width property missing\n");
 785                 return -ENOENT;
 786         }
 787
 788         switch (val) {
 789         case 0x8:
 790                 cfg->host_caps |= MMC_MODE_8BIT;
 791         case 0x4:
 792                 cfg->host_caps |= MMC_MODE_4BIT;
 793                 break;
 794         default:
 795                 printf("error: invalid bus-width property\n");
 796                 return -ENOENT;
 797         }
 798
 799         cfg->f_min = 400000;
 800         cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
 801         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 802         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 803
 804         priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
 805
 806         return 0;
 807 }
 808
 809 static int omap_hsmmc_probe(struct udevice *dev)
 810 {
 811         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 812         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 813         struct mmc_config *cfg;
 814         struct mmc *mmc;
 815
 816         cfg = &priv->cfg;
 817         cfg->name = "OMAP SD/MMC";
 818         cfg->ops = &omap_hsmmc_ops;
 819
 820         mmc = mmc_create(cfg, priv);
 821         if (mmc == NULL)
 822                 return -1;
 823
 824         upriv->mmc = mmc;
 825
 826         return 0;
 827 }
 828
 829 static const struct udevice_id omap_hsmmc_ids[] = {
 830         { .compatible = "ti,omap3-hsmmc" },
 831         { .compatible = "ti,omap4-hsmmc" },
 832         { .compatible = "ti,am33xx-hsmmc" },
 833         { }
 834 };
 835
 836 U_BOOT_DRIVER(omap_hsmmc) = {
 837         .name   = "omap_hsmmc",
 838         .id     = UCLASS_MMC,
 839         .of_match = omap_hsmmc_ids,
 840         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
 841         .probe  = omap_hsmmc_probe,
 842         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
 843 };
 844 #endif