3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
36 #include <asm/arch/mmc_host_def.h>
37 #if !defined(CONFIG_SOC_KEYSTONE)
39 #include <asm/arch/sys_proto.h>
41 #ifdef CONFIG_MMC_OMAP36XX_PINS
42 #include <asm/arch/mux.h>
46 DECLARE_GLOBAL_DATA_PTR;
48 /* simplify defines to OMAP_HSMMC_USE_GPIO */
49 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51 #define OMAP_HSMMC_USE_GPIO
53 #undef OMAP_HSMMC_USE_GPIO
56 /* common definitions for all OMAPs */
57 #define SYSCTL_SRC (1 << 25)
58 #define SYSCTL_SRD (1 << 26)
60 struct omap_hsmmc_data {
61 struct hsmmc *base_addr;
62 #if !CONFIG_IS_ENABLED(DM_MMC)
63 struct mmc_config cfg;
65 #ifdef OMAP_HSMMC_USE_GPIO
66 #if CONFIG_IS_ENABLED(DM_MMC)
67 struct gpio_desc cd_gpio; /* Change Detect GPIO */
68 struct gpio_desc wp_gpio; /* Write Protect GPIO */
76 #ifndef CONFIG_OMAP34XX
77 struct omap_hsmmc_adma_desc *adma_desc_table;
82 #ifndef CONFIG_OMAP34XX
83 struct omap_hsmmc_adma_desc {
90 #define ADMA_MAX_LEN 63488
92 /* Decriptor table defines */
93 #define ADMA_DESC_ATTR_VALID BIT(0)
94 #define ADMA_DESC_ATTR_END BIT(1)
95 #define ADMA_DESC_ATTR_INT BIT(2)
96 #define ADMA_DESC_ATTR_ACT1 BIT(4)
97 #define ADMA_DESC_ATTR_ACT2 BIT(5)
99 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
100 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
103 /* If we fail after 1 second wait, something is really bad */
104 #define MAX_RETRY_MS 1000
106 /* DMA transfers can take a long time if a lot a data is transferred.
107 * The timeout must take in account the amount of data. Let's assume
108 * that the time will never exceed 333 ms per MB (in other word we assume
109 * that the bandwidth is always above 3MB/s).
111 #define DMA_TIMEOUT_PER_MB 333
112 #define OMAP_HSMMC_USE_ADMA BIT(2)
114 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
115 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
118 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
120 #if CONFIG_IS_ENABLED(DM_MMC)
121 return dev_get_priv(mmc->dev);
123 return (struct omap_hsmmc_data *)mmc->priv;
126 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
128 #if CONFIG_IS_ENABLED(DM_MMC)
129 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
132 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
136 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
137 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
141 #ifndef CONFIG_DM_GPIO
142 if (!gpio_is_valid(gpio))
145 ret = gpio_request(gpio, label);
149 ret = gpio_direction_input(gpio);
157 static unsigned char mmc_board_init(struct mmc *mmc)
159 #if defined(CONFIG_OMAP34XX)
160 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
161 t2_t *t2_base = (t2_t *)T2_BASE;
162 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
164 #ifdef CONFIG_MMC_OMAP36XX_PINS
165 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
168 pbias_lite = readl(&t2_base->pbias_lite);
169 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
170 #ifdef CONFIG_TARGET_OMAP3_CAIRO
171 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
172 pbias_lite &= ~PBIASLITEVMODE0;
174 #ifdef CONFIG_MMC_OMAP36XX_PINS
175 if (get_cpu_family() == CPU_OMAP36XX) {
176 /* Disable extended drain IO before changing PBIAS */
177 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
178 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
181 writel(pbias_lite, &t2_base->pbias_lite);
183 writel(pbias_lite | PBIASLITEPWRDNZ1 |
184 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
185 &t2_base->pbias_lite);
187 #ifdef CONFIG_MMC_OMAP36XX_PINS
188 if (get_cpu_family() == CPU_OMAP36XX)
189 /* Enable extended drain IO after changing PBIAS */
191 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
192 OMAP34XX_CTRL_WKUP_CTRL);
194 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
197 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
200 /* Change from default of 52MHz to 26MHz if necessary */
201 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
202 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
203 &t2_base->ctl_prog_io1);
205 writel(readl(&prcm_base->fclken1_core) |
206 EN_MMC1 | EN_MMC2 | EN_MMC3,
207 &prcm_base->fclken1_core);
209 writel(readl(&prcm_base->iclken1_core) |
210 EN_MMC1 | EN_MMC2 | EN_MMC3,
211 &prcm_base->iclken1_core);
214 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
215 /* PBIAS config needed for MMC1 only */
216 if (mmc_get_blk_desc(mmc)->devnum == 0)
217 vmmc_pbias_config(LDO_VOLT_3V0);
223 void mmc_init_stream(struct hsmmc *mmc_base)
227 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
229 writel(MMC_CMD0, &mmc_base->cmd);
230 start = get_timer(0);
231 while (!(readl(&mmc_base->stat) & CC_MASK)) {
232 if (get_timer(0) - start > MAX_RETRY_MS) {
233 printf("%s: timedout waiting for cc!\n", __func__);
237 writel(CC_MASK, &mmc_base->stat)
239 writel(MMC_CMD0, &mmc_base->cmd)
241 start = get_timer(0);
242 while (!(readl(&mmc_base->stat) & CC_MASK)) {
243 if (get_timer(0) - start > MAX_RETRY_MS) {
244 printf("%s: timedout waiting for cc2!\n", __func__);
248 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
251 static int omap_hsmmc_init_setup(struct mmc *mmc)
253 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
254 struct hsmmc *mmc_base;
255 unsigned int reg_val;
259 mmc_base = priv->base_addr;
262 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
263 &mmc_base->sysconfig);
264 start = get_timer(0);
265 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
266 if (get_timer(0) - start > MAX_RETRY_MS) {
267 printf("%s: timedout waiting for cc2!\n", __func__);
271 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
272 start = get_timer(0);
273 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
274 if (get_timer(0) - start > MAX_RETRY_MS) {
275 printf("%s: timedout waiting for softresetall!\n",
280 #ifndef CONFIG_OMAP34XX
281 reg_val = readl(&mmc_base->hl_hwinfo);
282 if (reg_val & MADMA_EN)
283 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
285 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
286 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
289 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
291 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
292 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
293 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
296 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
297 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
298 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
299 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
300 start = get_timer(0);
301 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
302 if (get_timer(0) - start > MAX_RETRY_MS) {
303 printf("%s: timedout waiting for ics!\n", __func__);
307 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
309 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
311 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
312 IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
313 IE_CC, &mmc_base->ie);
315 mmc_init_stream(mmc_base);
321 * MMC controller internal finite state machine reset
323 * Used to reset command or data internal state machines, using respectively
324 * SRC or SRD bit of SYSCTL register
326 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
330 mmc_reg_out(&mmc_base->sysctl, bit, bit);
333 * CMD(DAT) lines reset procedures are slightly different
334 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
335 * According to OMAP3 TRM:
336 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
338 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
339 * procedure steps must be as follows:
340 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
341 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
342 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
343 * 3. Wait until the SRC (SRD) bit returns to 0x0
344 * (reset procedure is completed).
346 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
347 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
348 if (!(readl(&mmc_base->sysctl) & bit)) {
349 start = get_timer(0);
350 while (!(readl(&mmc_base->sysctl) & bit)) {
351 if (get_timer(0) - start > MAX_RETRY_MS)
356 start = get_timer(0);
357 while ((readl(&mmc_base->sysctl) & bit) != 0) {
358 if (get_timer(0) - start > MAX_RETRY_MS) {
359 printf("%s: timedout waiting for sysctl %x to clear\n",
366 #ifndef CONFIG_OMAP34XX
367 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
369 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
370 struct omap_hsmmc_adma_desc *desc;
373 desc = &priv->adma_desc_table[priv->desc_slot];
375 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
379 attr |= ADMA_DESC_ATTR_END;
382 desc->addr = (u32)buf;
387 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
388 struct mmc_data *data)
390 uint total_len = data->blocksize * data->blocks;
391 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
392 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
397 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
398 memalign(ARCH_DMA_MINALIGN, desc_count *
399 sizeof(struct omap_hsmmc_adma_desc));
401 if (data->flags & MMC_DATA_READ)
404 buf = (char *)data->src;
407 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
409 total_len -= ADMA_MAX_LEN;
412 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
414 flush_dcache_range((long)priv->adma_desc_table,
415 (long)priv->adma_desc_table +
417 sizeof(struct omap_hsmmc_adma_desc),
421 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
423 struct hsmmc *mmc_base;
424 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
428 mmc_base = priv->base_addr;
429 omap_hsmmc_prepare_adma_table(mmc, data);
431 if (data->flags & MMC_DATA_READ)
434 buf = (char *)data->src;
436 val = readl(&mmc_base->hctl);
438 writel(val, &mmc_base->hctl);
440 val = readl(&mmc_base->con);
442 writel(val, &mmc_base->con);
444 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
446 flush_dcache_range((u32)buf,
448 ROUND(data->blocksize * data->blocks,
452 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
454 struct hsmmc *mmc_base;
455 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
458 mmc_base = priv->base_addr;
460 val = readl(&mmc_base->con);
462 writel(val, &mmc_base->con);
464 val = readl(&mmc_base->hctl);
466 writel(val, &mmc_base->hctl);
468 kfree(priv->adma_desc_table);
471 #define omap_hsmmc_adma_desc
472 #define omap_hsmmc_prepare_adma_table
473 #define omap_hsmmc_prepare_data
474 #define omap_hsmmc_dma_cleanup
477 #if !CONFIG_IS_ENABLED(DM_MMC)
478 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
479 struct mmc_data *data)
481 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
483 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
484 struct mmc_data *data)
486 struct omap_hsmmc_data *priv = dev_get_priv(dev);
487 #ifndef CONFIG_OMAP34XX
488 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
489 struct mmc *mmc = upriv->mmc;
492 struct hsmmc *mmc_base;
493 unsigned int flags, mmc_stat;
496 mmc_base = priv->base_addr;
497 start = get_timer(0);
498 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
499 if (get_timer(0) - start > MAX_RETRY_MS) {
500 printf("%s: timedout waiting on cmd inhibit to clear\n",
505 writel(0xFFFFFFFF, &mmc_base->stat);
506 start = get_timer(0);
507 while (readl(&mmc_base->stat)) {
508 if (get_timer(0) - start > MAX_RETRY_MS) {
509 printf("%s: timedout waiting for STAT (%x) to clear\n",
510 __func__, readl(&mmc_base->stat));
516 * CMDIDX[13:8] : Command index
517 * DATAPRNT[5] : Data Present Select
518 * ENCMDIDX[4] : Command Index Check Enable
519 * ENCMDCRC[3] : Command CRC Check Enable
524 * 11 = Length 48 Check busy after response
526 /* Delay added before checking the status of frq change
527 * retry not supported by mmc.c(core file)
529 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
530 udelay(50000); /* wait 50 ms */
532 if (!(cmd->resp_type & MMC_RSP_PRESENT))
534 else if (cmd->resp_type & MMC_RSP_136)
535 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
536 else if (cmd->resp_type & MMC_RSP_BUSY)
537 flags = RSP_TYPE_LGHT48B;
539 flags = RSP_TYPE_LGHT48;
541 /* enable default flags */
542 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
543 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
545 if (cmd->resp_type & MMC_RSP_CRC)
547 if (cmd->resp_type & MMC_RSP_OPCODE)
551 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
552 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
553 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
554 data->blocksize = 512;
555 writel(data->blocksize | (data->blocks << 16),
558 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
560 if (data->flags & MMC_DATA_READ)
561 flags |= (DP_DATA | DDIR_READ);
563 flags |= (DP_DATA | DDIR_WRITE);
565 #ifndef CONFIG_OMAP34XX
566 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
567 !mmc_is_tuning_cmd(cmd->cmdidx)) {
568 omap_hsmmc_prepare_data(mmc, data);
574 writel(cmd->cmdarg, &mmc_base->arg);
575 udelay(20); /* To fix "No status update" error on eMMC */
576 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
578 start = get_timer(0);
580 mmc_stat = readl(&mmc_base->stat);
581 if (get_timer(start) > MAX_RETRY_MS) {
582 printf("%s : timeout: No status update\n", __func__);
587 if ((mmc_stat & IE_CTO) != 0) {
588 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
590 } else if ((mmc_stat & ERRI_MASK) != 0)
593 if (mmc_stat & CC_MASK) {
594 writel(CC_MASK, &mmc_base->stat);
595 if (cmd->resp_type & MMC_RSP_PRESENT) {
596 if (cmd->resp_type & MMC_RSP_136) {
597 /* response type 2 */
598 cmd->response[3] = readl(&mmc_base->rsp10);
599 cmd->response[2] = readl(&mmc_base->rsp32);
600 cmd->response[1] = readl(&mmc_base->rsp54);
601 cmd->response[0] = readl(&mmc_base->rsp76);
603 /* response types 1, 1b, 3, 4, 5, 6 */
604 cmd->response[0] = readl(&mmc_base->rsp10);
608 #ifndef CONFIG_OMAP34XX
609 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
610 !mmc_is_tuning_cmd(cmd->cmdidx)) {
613 if (mmc_stat & IE_ADMAE) {
614 omap_hsmmc_dma_cleanup(mmc);
618 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
619 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
620 if (timeout < MAX_RETRY_MS)
621 timeout = MAX_RETRY_MS;
623 start = get_timer(0);
625 mmc_stat = readl(&mmc_base->stat);
626 if (mmc_stat & TC_MASK) {
627 writel(readl(&mmc_base->stat) | TC_MASK,
631 if (get_timer(start) > timeout) {
632 printf("%s : DMA timeout: No status update\n",
638 omap_hsmmc_dma_cleanup(mmc);
643 if (data && (data->flags & MMC_DATA_READ)) {
644 mmc_read_data(mmc_base, data->dest,
645 data->blocksize * data->blocks);
646 } else if (data && (data->flags & MMC_DATA_WRITE)) {
647 mmc_write_data(mmc_base, data->src,
648 data->blocksize * data->blocks);
653 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
655 unsigned int *output_buf = (unsigned int *)buf;
656 unsigned int mmc_stat;
662 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
666 ulong start = get_timer(0);
668 mmc_stat = readl(&mmc_base->stat);
669 if (get_timer(0) - start > MAX_RETRY_MS) {
670 printf("%s: timedout waiting for status!\n",
674 } while (mmc_stat == 0);
676 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
677 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
679 if ((mmc_stat & ERRI_MASK) != 0)
682 if (mmc_stat & BRR_MASK) {
685 writel(readl(&mmc_base->stat) | BRR_MASK,
687 for (k = 0; k < count; k++) {
688 *output_buf = readl(&mmc_base->data);
694 if (mmc_stat & BWR_MASK)
695 writel(readl(&mmc_base->stat) | BWR_MASK,
698 if (mmc_stat & TC_MASK) {
699 writel(readl(&mmc_base->stat) | TC_MASK,
707 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
710 unsigned int *input_buf = (unsigned int *)buf;
711 unsigned int mmc_stat;
717 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
721 ulong start = get_timer(0);
723 mmc_stat = readl(&mmc_base->stat);
724 if (get_timer(0) - start > MAX_RETRY_MS) {
725 printf("%s: timedout waiting for status!\n",
729 } while (mmc_stat == 0);
731 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
732 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
734 if ((mmc_stat & ERRI_MASK) != 0)
737 if (mmc_stat & BWR_MASK) {
740 writel(readl(&mmc_base->stat) | BWR_MASK,
742 for (k = 0; k < count; k++) {
743 writel(*input_buf, &mmc_base->data);
749 if (mmc_stat & BRR_MASK)
750 writel(readl(&mmc_base->stat) | BRR_MASK,
753 if (mmc_stat & TC_MASK) {
754 writel(readl(&mmc_base->stat) | TC_MASK,
762 #if !CONFIG_IS_ENABLED(DM_MMC)
763 static int omap_hsmmc_set_ios(struct mmc *mmc)
765 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
767 static int omap_hsmmc_set_ios(struct udevice *dev)
769 struct omap_hsmmc_data *priv = dev_get_priv(dev);
770 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
771 struct mmc *mmc = upriv->mmc;
773 struct hsmmc *mmc_base;
774 unsigned int dsor = 0;
777 mmc_base = priv->base_addr;
778 /* configue bus width */
779 switch (mmc->bus_width) {
781 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
786 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
788 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
794 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
796 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
801 /* configure clock with 96Mhz system clock.
803 if (mmc->clock != 0) {
804 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
805 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
809 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
810 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
812 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
813 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
815 start = get_timer(0);
816 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
817 if (get_timer(0) - start > MAX_RETRY_MS) {
818 printf("%s: timedout waiting for ics!\n", __func__);
822 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
827 #ifdef OMAP_HSMMC_USE_GPIO
828 #if CONFIG_IS_ENABLED(DM_MMC)
829 static int omap_hsmmc_getcd(struct udevice *dev)
831 struct omap_hsmmc_data *priv = dev_get_priv(dev);
834 value = dm_gpio_get_value(&priv->cd_gpio);
835 /* if no CD return as 1 */
839 if (priv->cd_inverted)
844 static int omap_hsmmc_getwp(struct udevice *dev)
846 struct omap_hsmmc_data *priv = dev_get_priv(dev);
849 value = dm_gpio_get_value(&priv->wp_gpio);
850 /* if no WP return as 0 */
856 static int omap_hsmmc_getcd(struct mmc *mmc)
858 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
861 /* if no CD return as 1 */
862 cd_gpio = priv->cd_gpio;
866 /* NOTE: assumes card detect signal is active-low */
867 return !gpio_get_value(cd_gpio);
870 static int omap_hsmmc_getwp(struct mmc *mmc)
872 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
875 /* if no WP return as 0 */
876 wp_gpio = priv->wp_gpio;
880 /* NOTE: assumes write protect signal is active-high */
881 return gpio_get_value(wp_gpio);
886 #if CONFIG_IS_ENABLED(DM_MMC)
887 static const struct dm_mmc_ops omap_hsmmc_ops = {
888 .send_cmd = omap_hsmmc_send_cmd,
889 .set_ios = omap_hsmmc_set_ios,
890 #ifdef OMAP_HSMMC_USE_GPIO
891 .get_cd = omap_hsmmc_getcd,
892 .get_wp = omap_hsmmc_getwp,
896 static const struct mmc_ops omap_hsmmc_ops = {
897 .send_cmd = omap_hsmmc_send_cmd,
898 .set_ios = omap_hsmmc_set_ios,
899 .init = omap_hsmmc_init_setup,
900 #ifdef OMAP_HSMMC_USE_GPIO
901 .getcd = omap_hsmmc_getcd,
902 .getwp = omap_hsmmc_getwp,
907 #if !CONFIG_IS_ENABLED(DM_MMC)
908 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
912 struct omap_hsmmc_data *priv;
913 struct mmc_config *cfg;
916 priv = malloc(sizeof(*priv));
920 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
924 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
926 #ifdef OMAP_HSMMC2_BASE
928 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
929 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
930 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
931 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
932 defined(CONFIG_HSMMC2_8BIT)
933 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
934 host_caps_val |= MMC_MODE_8BIT;
938 #ifdef OMAP_HSMMC3_BASE
940 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
941 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
942 /* Enable 8-bit interface for eMMC on DRA7XX */
943 host_caps_val |= MMC_MODE_8BIT;
948 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
951 #ifdef OMAP_HSMMC_USE_GPIO
952 /* on error gpio values are set to -1, which is what we want */
953 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
954 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
959 cfg->name = "OMAP SD/MMC";
960 cfg->ops = &omap_hsmmc_ops;
962 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
963 cfg->host_caps = host_caps_val & ~host_caps_mask;
970 if (cfg->host_caps & MMC_MODE_HS) {
971 if (cfg->host_caps & MMC_MODE_HS_52MHz)
972 cfg->f_max = 52000000;
974 cfg->f_max = 26000000;
976 cfg->f_max = 20000000;
979 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
981 #if defined(CONFIG_OMAP34XX)
983 * Silicon revs 2.1 and older do not support multiblock transfers.
985 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
988 mmc = mmc_create(cfg, priv);
995 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
996 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
998 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
999 struct mmc_config *cfg = &plat->cfg;
1000 const void *fdt = gd->fdt_blob;
1001 int node = dev_of_offset(dev);
1004 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1005 sizeof(struct hsmmc *),
1008 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1009 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1011 printf("error: bus-width property missing\n");
1017 cfg->host_caps |= MMC_MODE_8BIT;
1019 cfg->host_caps |= MMC_MODE_4BIT;
1022 printf("error: invalid bus-width property\n");
1026 cfg->f_min = 400000;
1027 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1028 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1029 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1031 #ifdef OMAP_HSMMC_USE_GPIO
1032 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1041 static int omap_hsmmc_bind(struct udevice *dev)
1043 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1045 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1048 static int omap_hsmmc_probe(struct udevice *dev)
1050 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1051 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1052 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1053 struct mmc_config *cfg = &plat->cfg;
1056 cfg->name = "OMAP SD/MMC";
1057 priv->base_addr = plat->base_addr;
1058 #ifdef OMAP_HSMMC_USE_GPIO
1059 priv->cd_inverted = plat->cd_inverted;
1065 mmc = mmc_create(cfg, priv);
1070 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1071 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1072 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1078 return omap_hsmmc_init_setup(mmc);
1081 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1082 static const struct udevice_id omap_hsmmc_ids[] = {
1083 { .compatible = "ti,omap3-hsmmc" },
1084 { .compatible = "ti,omap4-hsmmc" },
1085 { .compatible = "ti,am33xx-hsmmc" },
1090 U_BOOT_DRIVER(omap_hsmmc) = {
1091 .name = "omap_hsmmc",
1093 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1094 .of_match = omap_hsmmc_ids,
1095 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1096 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1099 .bind = omap_hsmmc_bind,
1101 .ops = &omap_hsmmc_ops,
1102 .probe = omap_hsmmc_probe,
1103 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1104 .flags = DM_FLAG_PRE_RELOC,