drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <cpu_func.h>
  28 #include <log.h>
  29 #include <malloc.h>
  30 #include <memalign.h>
  31 #include <mmc.h>
  32 #include <part.h>
  33 #include <i2c.h>
  34 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  35 #include <palmas.h>
  36 #endif
  37 #include <asm/cache.h>
  38 #include <asm/io.h>
  39 #include <asm/arch/mmc_host_def.h>
  40 #ifdef CONFIG_OMAP54XX
  41 #include <asm/arch/mux_dra7xx.h>
  42 #include <asm/arch/dra7xx_iodelay.h>
  43 #endif
  44 #if !defined(CONFIG_SOC_KEYSTONE)
  45 #include <asm/gpio.h>
  46 #include <asm/arch/sys_proto.h>
  47 #endif
  48 #ifdef CONFIG_MMC_OMAP36XX_PINS
  49 #include <asm/arch/mux.h>
  50 #endif
  51 #include <dm.h>
  52 #include <dm/devres.h>
  53 #include <linux/bitops.h>
  54 #include <linux/delay.h>
  55 #include <linux/err.h>
  56 #include <power/regulator.h>
  57 #include <thermal.h>
  58
  59 DECLARE_GLOBAL_DATA_PTR;
  60
  61 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  62 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  63         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  64 #define OMAP_HSMMC_USE_GPIO
  65 #else
  66 #undef OMAP_HSMMC_USE_GPIO
  67 #endif
  68
  69 /* common definitions for all OMAPs */
  70 #define SYSCTL_SRC      (1 << 25)
  71 #define SYSCTL_SRD      (1 << 26)
  72
  73 #ifdef CONFIG_IODELAY_RECALIBRATION
  74 struct omap_hsmmc_pinctrl_state {
  75         struct pad_conf_entry *padconf;
  76         int npads;
  77         struct iodelay_cfg_entry *iodelay;
  78         int niodelays;
  79 };
  80 #endif
  81
  82 struct omap_hsmmc_data {
  83         struct hsmmc *base_addr;
  84 #if !CONFIG_IS_ENABLED(DM_MMC)
  85         struct mmc_config cfg;
  86 #endif
  87         uint bus_width;
  88         uint clock;
  89         ushort last_cmd;
  90 #ifdef OMAP_HSMMC_USE_GPIO
  91 #if CONFIG_IS_ENABLED(DM_MMC)
  92         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  93         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  94 #else
  95         int cd_gpio;
  96         int wp_gpio;
  97 #endif
  98 #endif
  99 #if CONFIG_IS_ENABLED(DM_MMC)
 100         enum bus_mode mode;
 101 #endif
 102         u8 controller_flags;
 103 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 104         struct omap_hsmmc_adma_desc *adma_desc_table;
 105         uint desc_slot;
 106 #endif
 107         const char *hw_rev;
 108         struct udevice *pbias_supply;
 109         uint signal_voltage;
 110 #ifdef CONFIG_IODELAY_RECALIBRATION
 111         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 113         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 114         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 115         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 116         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 117         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 118         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 119         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 120 #endif
 121 };
 122
 123 struct omap_mmc_of_data {
 124         u8 controller_flags;
 125 };
 126
 127 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 128 struct omap_hsmmc_adma_desc {
 129         u8 attr;
 130         u8 reserved;
 131         u16 len;
 132         u32 addr;
 133 };
 134
 135 #define ADMA_MAX_LEN    63488
 136
 137 /* Decriptor table defines */
 138 #define ADMA_DESC_ATTR_VALID            BIT(0)
 139 #define ADMA_DESC_ATTR_END              BIT(1)
 140 #define ADMA_DESC_ATTR_INT              BIT(2)
 141 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 142 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 143
 144 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 145 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 146 #endif
 147
 148 /* If we fail after 1 second wait, something is really bad */
 149 #define MAX_RETRY_MS    1000
 150 #define MMC_TIMEOUT_MS  20
 151
 152 /* DMA transfers can take a long time if a lot a data is transferred.
 153  * The timeout must take in account the amount of data. Let's assume
 154  * that the time will never exceed 333 ms per MB (in other word we assume
 155  * that the bandwidth is always above 3MB/s).
 156  */
 157 #define DMA_TIMEOUT_PER_MB      333
 158 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 159 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 160 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 161 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 162
 163 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 164 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 165                         unsigned int siz);
 166 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 167 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 168 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 169
 170 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 171 {
 172 #if CONFIG_IS_ENABLED(DM_MMC)
 173         return dev_get_priv(mmc->dev);
 174 #else
 175         return (struct omap_hsmmc_data *)mmc->priv;
 176 #endif
 177 }
 178
 179 #if defined(CONFIG_OMAP34XX) || defined(CONFIG_IODELAY_RECALIBRATION)
 180 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 181 {
 182 #if CONFIG_IS_ENABLED(DM_MMC)
 183         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 184         return &plat->cfg;
 185 #else
 186         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 187 #endif
 188 }
 189 #endif
 190
 191 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 192 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 193 {
 194         int ret;
 195
 196 #if !CONFIG_IS_ENABLED(DM_GPIO)
 197         if (!gpio_is_valid(gpio))
 198                 return -1;
 199 #endif
 200         ret = gpio_request(gpio, label);
 201         if (ret)
 202                 return ret;
 203
 204         ret = gpio_direction_input(gpio);
 205         if (ret)
 206                 return ret;
 207
 208         return gpio;
 209 }
 210 #endif
 211
 212 static unsigned char mmc_board_init(struct mmc *mmc)
 213 {
 214 #if defined(CONFIG_OMAP34XX)
 215         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 216         t2_t *t2_base = (t2_t *)T2_BASE;
 217         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 218         u32 pbias_lite;
 219 #ifdef CONFIG_MMC_OMAP36XX_PINS
 220         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 221 #endif
 222
 223         pbias_lite = readl(&t2_base->pbias_lite);
 224         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 225 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 226         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 227         pbias_lite &= ~PBIASLITEVMODE0;
 228 #endif
 229 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 230         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 231         pbias_lite &= ~PBIASLITEVMODE1;
 232 #endif
 233 #ifdef CONFIG_MMC_OMAP36XX_PINS
 234         if (get_cpu_family() == CPU_OMAP36XX) {
 235                 /* Disable extended drain IO before changing PBIAS */
 236                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 237                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 238         }
 239 #endif
 240         writel(pbias_lite, &t2_base->pbias_lite);
 241
 242         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 243                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 244                 &t2_base->pbias_lite);
 245
 246 #ifdef CONFIG_MMC_OMAP36XX_PINS
 247         if (get_cpu_family() == CPU_OMAP36XX)
 248                 /* Enable extended drain IO after changing PBIAS */
 249                 writel(wkup_ctrl |
 250                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 251                                 OMAP34XX_CTRL_WKUP_CTRL);
 252 #endif
 253         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 254                 &t2_base->devconf0);
 255
 256         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 257                 &t2_base->devconf1);
 258
 259         /* Change from default of 52MHz to 26MHz if necessary */
 260         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 261                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 262                         &t2_base->ctl_prog_io1);
 263
 264         writel(readl(&prcm_base->fclken1_core) |
 265                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 266                 &prcm_base->fclken1_core);
 267
 268         writel(readl(&prcm_base->iclken1_core) |
 269                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 270                 &prcm_base->iclken1_core);
 271 #endif
 272
 273 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 274         !CONFIG_IS_ENABLED(DM_REGULATOR)
 275         /* PBIAS config needed for MMC1 only */
 276         if (mmc_get_blk_desc(mmc)->devnum == 0)
 277                 vmmc_pbias_config(LDO_VOLT_3V3);
 278 #endif
 279
 280         return 0;
 281 }
 282
 283 void mmc_init_stream(struct hsmmc *mmc_base)
 284 {
 285         ulong start;
 286
 287         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 288
 289         writel(MMC_CMD0, &mmc_base->cmd);
 290         start = get_timer(0);
 291         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 292                 if (get_timer(0) - start > MAX_RETRY_MS) {
 293                         printf("%s: timedout waiting for cc!\n", __func__);
 294                         return;
 295                 }
 296         }
 297         writel(CC_MASK, &mmc_base->stat)
 298                 ;
 299         writel(MMC_CMD0, &mmc_base->cmd)
 300                 ;
 301         start = get_timer(0);
 302         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 303                 if (get_timer(0) - start > MAX_RETRY_MS) {
 304                         printf("%s: timedout waiting for cc2!\n", __func__);
 305                         return;
 306                 }
 307         }
 308         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 309 }
 310
 311 #if CONFIG_IS_ENABLED(DM_MMC)
 312 #ifdef CONFIG_IODELAY_RECALIBRATION
 313 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 314 {
 315         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 316         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 317
 318         switch (priv->mode) {
 319         case MMC_HS_200:
 320                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 321                 break;
 322         case UHS_SDR104:
 323                 pinctrl_state = priv->sdr104_pinctrl_state;
 324                 break;
 325         case UHS_SDR50:
 326                 pinctrl_state = priv->sdr50_pinctrl_state;
 327                 break;
 328         case UHS_DDR50:
 329                 pinctrl_state = priv->ddr50_pinctrl_state;
 330                 break;
 331         case UHS_SDR25:
 332                 pinctrl_state = priv->sdr25_pinctrl_state;
 333                 break;
 334         case UHS_SDR12:
 335                 pinctrl_state = priv->sdr12_pinctrl_state;
 336                 break;
 337         case SD_HS:
 338         case MMC_HS:
 339         case MMC_HS_52:
 340                 pinctrl_state = priv->hs_pinctrl_state;
 341                 break;
 342         case MMC_DDR_52:
 343                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 344         default:
 345                 pinctrl_state = priv->default_pinctrl_state;
 346                 break;
 347         }
 348
 349         if (!pinctrl_state)
 350                 pinctrl_state = priv->default_pinctrl_state;
 351
 352         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 353                 if (pinctrl_state->iodelay)
 354                         late_recalibrate_iodelay(pinctrl_state->padconf,
 355                                                  pinctrl_state->npads,
 356                                                  pinctrl_state->iodelay,
 357                                                  pinctrl_state->niodelays);
 358                 else
 359                         do_set_mux32((*ctrl)->control_padconf_core_base,
 360                                      pinctrl_state->padconf,
 361                                      pinctrl_state->npads);
 362         }
 363 }
 364 #endif
 365 static void omap_hsmmc_set_timing(struct mmc *mmc)
 366 {
 367         u32 val;
 368         struct hsmmc *mmc_base;
 369         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 370
 371         mmc_base = priv->base_addr;
 372
 373         omap_hsmmc_stop_clock(mmc_base);
 374         val = readl(&mmc_base->ac12);
 375         val &= ~AC12_UHSMC_MASK;
 376         priv->mode = mmc->selected_mode;
 377
 378         if (mmc_is_mode_ddr(priv->mode))
 379                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 380         else
 381                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 382
 383         switch (priv->mode) {
 384         case MMC_HS_200:
 385         case UHS_SDR104:
 386                 val |= AC12_UHSMC_SDR104;
 387                 break;
 388         case UHS_SDR50:
 389                 val |= AC12_UHSMC_SDR50;
 390                 break;
 391         case MMC_DDR_52:
 392         case UHS_DDR50:
 393                 val |= AC12_UHSMC_DDR50;
 394                 break;
 395         case SD_HS:
 396         case MMC_HS_52:
 397         case UHS_SDR25:
 398                 val |= AC12_UHSMC_SDR25;
 399                 break;
 400         case MMC_LEGACY:
 401         case MMC_HS:
 402         case UHS_SDR12:
 403                 val |= AC12_UHSMC_SDR12;
 404                 break;
 405         default:
 406                 val |= AC12_UHSMC_RES;
 407                 break;
 408         }
 409         writel(val, &mmc_base->ac12);
 410
 411 #ifdef CONFIG_IODELAY_RECALIBRATION
 412         omap_hsmmc_io_recalibrate(mmc);
 413 #endif
 414         omap_hsmmc_start_clock(mmc_base);
 415 }
 416
 417 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 418 {
 419         struct hsmmc *mmc_base;
 420         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 421         u32 hctl, ac12;
 422
 423         mmc_base = priv->base_addr;
 424
 425         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 426         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 427
 428         switch (signal_voltage) {
 429         case MMC_SIGNAL_VOLTAGE_330:
 430                 hctl |= SDVS_3V3;
 431                 break;
 432         case MMC_SIGNAL_VOLTAGE_180:
 433                 hctl |= SDVS_1V8;
 434                 ac12 |= AC12_V1V8_SIGEN;
 435                 break;
 436         }
 437
 438         writel(hctl, &mmc_base->hctl);
 439         writel(ac12, &mmc_base->ac12);
 440 }
 441
 442 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
 443 {
 444         int ret = -ETIMEDOUT;
 445         u32 con;
 446         bool dat0_high;
 447         bool target_dat0_high = !!state;
 448         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 449         struct hsmmc *mmc_base = priv->base_addr;
 450
 451         con = readl(&mmc_base->con);
 452         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 453
 454         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 455         while (timeout_us--) {
 456                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 457                 if (dat0_high == target_dat0_high) {
 458                         ret = 0;
 459                         break;
 460                 }
 461                 udelay(10);
 462         }
 463         writel(con, &mmc_base->con);
 464
 465         return ret;
 466 }
 467
 468 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 469 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 470 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 471 {
 472         int ret = 0;
 473         int uV = mV * 1000;
 474
 475         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 476
 477         if (!mmc->vqmmc_supply)
 478                 return 0;
 479
 480         /* Disable PBIAS */
 481         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 482         if (ret)
 483                 return ret;
 484
 485         /* Turn off IO voltage */
 486         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 487         if (ret)
 488                 return ret;
 489         /* Program a new IO voltage value */
 490         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 491         if (ret)
 492                 return ret;
 493         /* Turn on IO voltage */
 494         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 495         if (ret)
 496                 return ret;
 497
 498         /* Program PBIAS voltage*/
 499         ret = regulator_set_value(priv->pbias_supply, uV);
 500         if (ret && ret != -ENOSYS)
 501                 return ret;
 502         /* Enable PBIAS */
 503         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 504         if (ret)
 505                 return ret;
 506
 507         return 0;
 508 }
 509 #endif
 510
 511 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 512 {
 513         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 514         struct hsmmc *mmc_base = priv->base_addr;
 515         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 516         u32 capa_mask;
 517         __maybe_unused u8 palmas_ldo_volt;
 518         u32 val;
 519
 520         if (mv < 0)
 521                 return -EINVAL;
 522
 523         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 524                 mv = 3300;
 525                 capa_mask = VS33_3V3SUP;
 526                 palmas_ldo_volt = LDO_VOLT_3V3;
 527         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 528                 capa_mask = VS18_1V8SUP;
 529                 palmas_ldo_volt = LDO_VOLT_1V8;
 530         } else {
 531                 return -EOPNOTSUPP;
 532         }
 533
 534         val = readl(&mmc_base->capa);
 535         if (!(val & capa_mask))
 536                 return -EOPNOTSUPP;
 537
 538         priv->signal_voltage = mmc->signal_voltage;
 539
 540         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 541
 542 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 543         return omap_hsmmc_set_io_regulator(mmc, mv);
 544 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 545         defined(CONFIG_PALMAS_POWER)
 546         if (mmc_get_blk_desc(mmc)->devnum == 0)
 547                 vmmc_pbias_config(palmas_ldo_volt);
 548         return 0;
 549 #else
 550         return 0;
 551 #endif
 552 }
 553 #endif
 554
 555 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 556 {
 557         struct hsmmc *mmc_base;
 558         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 559         u32 val;
 560
 561         mmc_base = priv->base_addr;
 562         val = readl(&mmc_base->capa);
 563
 564         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 565                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 566         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 567                 val |= VS33_3V3SUP;
 568                 val &= ~VS18_1V8SUP;
 569         } else {
 570                 val |= VS18_1V8SUP;
 571                 val &= ~VS33_3V3SUP;
 572         }
 573
 574         writel(val, &mmc_base->capa);
 575
 576         return val;
 577 }
 578
 579 #ifdef MMC_SUPPORTS_TUNING
 580 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 581 {
 582         struct hsmmc *mmc_base;
 583         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 584         u32 val;
 585
 586         mmc_base = priv->base_addr;
 587         val = readl(&mmc_base->ac12);
 588         val &= ~(AC12_SCLK_SEL);
 589         writel(val, &mmc_base->ac12);
 590
 591         val = readl(&mmc_base->dll);
 592         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 593         writel(val, &mmc_base->dll);
 594 }
 595
 596 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 597 {
 598         int i;
 599         struct hsmmc *mmc_base;
 600         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 601         u32 val;
 602
 603         mmc_base = priv->base_addr;
 604         val = readl(&mmc_base->dll);
 605         val |= DLL_FORCE_VALUE;
 606         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 607         val |= (count << DLL_FORCE_SR_C_SHIFT);
 608         writel(val, &mmc_base->dll);
 609
 610         val |= DLL_CALIB;
 611         writel(val, &mmc_base->dll);
 612         for (i = 0; i < 1000; i++) {
 613                 if (readl(&mmc_base->dll) & DLL_CALIB)
 614                         break;
 615         }
 616         val &= ~DLL_CALIB;
 617         writel(val, &mmc_base->dll);
 618 }
 619
 620 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 621 {
 622         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 623         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 624         struct mmc *mmc = upriv->mmc;
 625         struct hsmmc *mmc_base;
 626         u32 val;
 627         u8 cur_match, prev_match = 0;
 628         int ret;
 629         u32 phase_delay = 0;
 630         u32 start_window = 0, max_window = 0;
 631         u32 length = 0, max_len = 0;
 632         bool single_point_failure = false;
 633         struct udevice *thermal_dev;
 634         int temperature;
 635         int i;
 636
 637         mmc_base = priv->base_addr;
 638         val = readl(&mmc_base->capa2);
 639
 640         /* clock tuning is not needed for upto 52MHz */
 641         if (!((mmc->selected_mode == MMC_HS_200) ||
 642               (mmc->selected_mode == UHS_SDR104) ||
 643               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 644                 return 0;
 645
 646         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 647         if (ret) {
 648                 printf("Couldn't get thermal device for tuning\n");
 649                 return ret;
 650         }
 651         ret = thermal_get_temp(thermal_dev, &temperature);
 652         if (ret) {
 653                 printf("Couldn't get temperature for tuning\n");
 654                 return ret;
 655         }
 656         val = readl(&mmc_base->dll);
 657         val |= DLL_SWT;
 658         writel(val, &mmc_base->dll);
 659
 660         /*
 661          * Stage 1: Search for a maximum pass window ignoring any
 662          * any single point failures. If the tuning value ends up
 663          * near it, move away from it in stage 2 below
 664          */
 665         while (phase_delay <= MAX_PHASE_DELAY) {
 666                 omap_hsmmc_set_dll(mmc, phase_delay);
 667
 668                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 669
 670                 if (cur_match) {
 671                         if (prev_match) {
 672                                 length++;
 673                         } else if (single_point_failure) {
 674                                 /* ignore single point failure */
 675                                 length++;
 676                                 single_point_failure = false;
 677                         } else {
 678                                 start_window = phase_delay;
 679                                 length = 1;
 680                         }
 681                 } else {
 682                         single_point_failure = prev_match;
 683                 }
 684
 685                 if (length > max_len) {
 686                         max_window = start_window;
 687                         max_len = length;
 688                 }
 689
 690                 prev_match = cur_match;
 691                 phase_delay += 4;
 692         }
 693
 694         if (!max_len) {
 695                 ret = -EIO;
 696                 goto tuning_error;
 697         }
 698
 699         val = readl(&mmc_base->ac12);
 700         if (!(val & AC12_SCLK_SEL)) {
 701                 ret = -EIO;
 702                 goto tuning_error;
 703         }
 704         /*
 705          * Assign tuning value as a ratio of maximum pass window based
 706          * on temperature
 707          */
 708         if (temperature < -20000)
 709                 phase_delay = min(max_window + 4 * max_len - 24,
 710                                   max_window +
 711                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 712         else if (temperature < 20000)
 713                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 714         else if (temperature < 40000)
 715                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 716         else if (temperature < 70000)
 717                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 718         else if (temperature < 90000)
 719                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 720         else if (temperature < 120000)
 721                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 722         else
 723                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 724
 725         /*
 726          * Stage 2: Search for a single point failure near the chosen tuning
 727          * value in two steps. First in the +3 to +10 range and then in the
 728          * +2 to -10 range. If found, move away from it in the appropriate
 729          * direction by the appropriate amount depending on the temperature.
 730          */
 731         for (i = 3; i <= 10; i++) {
 732                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 733                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 734                         if (temperature < 10000)
 735                                 phase_delay += i + 6;
 736                         else if (temperature < 20000)
 737                                 phase_delay += i - 12;
 738                         else if (temperature < 70000)
 739                                 phase_delay += i - 8;
 740                         else if (temperature < 90000)
 741                                 phase_delay += i - 6;
 742                         else
 743                                 phase_delay += i - 6;
 744
 745                         goto single_failure_found;
 746                 }
 747         }
 748
 749         for (i = 2; i >= -10; i--) {
 750                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 751                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 752                         if (temperature < 10000)
 753                                 phase_delay += i + 12;
 754                         else if (temperature < 20000)
 755                                 phase_delay += i + 8;
 756                         else if (temperature < 70000)
 757                                 phase_delay += i + 8;
 758                         else if (temperature < 90000)
 759                                 phase_delay += i + 10;
 760                         else
 761                                 phase_delay += i + 12;
 762
 763                         goto single_failure_found;
 764                 }
 765         }
 766
 767 single_failure_found:
 768
 769         omap_hsmmc_set_dll(mmc, phase_delay);
 770
 771         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 772         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 773
 774         return 0;
 775
 776 tuning_error:
 777
 778         omap_hsmmc_disable_tuning(mmc);
 779         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 780         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 781
 782         return ret;
 783 }
 784 #endif
 785 #endif
 786
 787 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 788 {
 789         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 790         struct hsmmc *mmc_base = priv->base_addr;
 791         u32 irq_mask = INT_EN_MASK;
 792
 793         /*
 794          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 795          * tuning procedure and DCRC should be disabled. But see occurences
 796          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 797          * interrupts occur along with BRR, so the data is actually in the
 798          * buffer. It has to be debugged why these interrutps occur
 799          */
 800         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 801                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 802
 803         writel(irq_mask, &mmc_base->ie);
 804 }
 805
 806 static int omap_hsmmc_init_setup(struct mmc *mmc)
 807 {
 808         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 809         struct hsmmc *mmc_base;
 810         unsigned int reg_val;
 811         unsigned int dsor;
 812         ulong start;
 813
 814         mmc_base = priv->base_addr;
 815         mmc_board_init(mmc);
 816
 817         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 818                 &mmc_base->sysconfig);
 819         start = get_timer(0);
 820         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 821                 if (get_timer(0) - start > MAX_RETRY_MS) {
 822                         printf("%s: timedout waiting for cc2!\n", __func__);
 823                         return -ETIMEDOUT;
 824                 }
 825         }
 826         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 827         start = get_timer(0);
 828         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 829                 if (get_timer(0) - start > MAX_RETRY_MS) {
 830                         printf("%s: timedout waiting for softresetall!\n",
 831                                 __func__);
 832                         return -ETIMEDOUT;
 833                 }
 834         }
 835 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 836         reg_val = readl(&mmc_base->hl_hwinfo);
 837         if (reg_val & MADMA_EN)
 838                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 839 #endif
 840
 841 #if CONFIG_IS_ENABLED(DM_MMC)
 842         reg_val = omap_hsmmc_set_capabilities(mmc);
 843         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 844                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 845 #else
 846         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 847         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 848                 &mmc_base->capa);
 849 #endif
 850
 851         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 852
 853         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 854                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 855                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 856
 857         dsor = 240;
 858         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 859                 (ICE_STOP | DTO_15THDTO));
 860         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 861                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 862         start = get_timer(0);
 863         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 864                 if (get_timer(0) - start > MAX_RETRY_MS) {
 865                         printf("%s: timedout waiting for ics!\n", __func__);
 866                         return -ETIMEDOUT;
 867                 }
 868         }
 869         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 870
 871         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 872
 873         mmc_enable_irq(mmc, NULL);
 874
 875 #if !CONFIG_IS_ENABLED(DM_MMC)
 876         mmc_init_stream(mmc_base);
 877 #endif
 878
 879         return 0;
 880 }
 881
 882 /*
 883  * MMC controller internal finite state machine reset
 884  *
 885  * Used to reset command or data internal state machines, using respectively
 886  * SRC or SRD bit of SYSCTL register
 887  */
 888 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 889 {
 890         ulong start;
 891
 892         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 893
 894         /*
 895          * CMD(DAT) lines reset procedures are slightly different
 896          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 897          * According to OMAP3 TRM:
 898          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 899          * returns to 0x0.
 900          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 901          * procedure steps must be as follows:
 902          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 903          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 904          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 905          * 3. Wait until the SRC (SRD) bit returns to 0x0
 906          *    (reset procedure is completed).
 907          */
 908 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 909         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 910         if (!(readl(&mmc_base->sysctl) & bit)) {
 911                 start = get_timer(0);
 912                 while (!(readl(&mmc_base->sysctl) & bit)) {
 913                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 914                                 return;
 915                 }
 916         }
 917 #endif
 918         start = get_timer(0);
 919         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 920                 if (get_timer(0) - start > MAX_RETRY_MS) {
 921                         printf("%s: timedout waiting for sysctl %x to clear\n",
 922                                 __func__, bit);
 923                         return;
 924                 }
 925         }
 926 }
 927
 928 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 929 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 930 {
 931         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 932         struct omap_hsmmc_adma_desc *desc;
 933         u8 attr;
 934
 935         desc = &priv->adma_desc_table[priv->desc_slot];
 936
 937         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 938         if (!end)
 939                 priv->desc_slot++;
 940         else
 941                 attr |= ADMA_DESC_ATTR_END;
 942
 943         desc->len = len;
 944         desc->addr = (u32)buf;
 945         desc->reserved = 0;
 946         desc->attr = attr;
 947 }
 948
 949 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 950                                           struct mmc_data *data)
 951 {
 952         uint total_len = data->blocksize * data->blocks;
 953         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 954         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 955         int i = desc_count;
 956         char *buf;
 957
 958         priv->desc_slot = 0;
 959         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 960                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 961                                 sizeof(struct omap_hsmmc_adma_desc));
 962
 963         if (data->flags & MMC_DATA_READ)
 964                 buf = data->dest;
 965         else
 966                 buf = (char *)data->src;
 967
 968         while (--i) {
 969                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 970                 buf += ADMA_MAX_LEN;
 971                 total_len -= ADMA_MAX_LEN;
 972         }
 973
 974         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 975
 976         flush_dcache_range((long)priv->adma_desc_table,
 977                            (long)priv->adma_desc_table +
 978                            ROUND(desc_count *
 979                            sizeof(struct omap_hsmmc_adma_desc),
 980                            ARCH_DMA_MINALIGN));
 981 }
 982
 983 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 984 {
 985         struct hsmmc *mmc_base;
 986         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 987         u32 val;
 988         char *buf;
 989
 990         mmc_base = priv->base_addr;
 991         omap_hsmmc_prepare_adma_table(mmc, data);
 992
 993         if (data->flags & MMC_DATA_READ)
 994                 buf = data->dest;
 995         else
 996                 buf = (char *)data->src;
 997
 998         val = readl(&mmc_base->hctl);
 999         val |= DMA_SELECT;
1000         writel(val, &mmc_base->hctl);
1001
1002         val = readl(&mmc_base->con);
1003         val |= DMA_MASTER;
1004         writel(val, &mmc_base->con);
1005
1006         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1007
1008         flush_dcache_range((u32)buf,
1009                            (u32)buf +
1010                            ROUND(data->blocksize * data->blocks,
1011                                  ARCH_DMA_MINALIGN));
1012 }
1013
1014 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1015 {
1016         struct hsmmc *mmc_base;
1017         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1018         u32 val;
1019
1020         mmc_base = priv->base_addr;
1021
1022         val = readl(&mmc_base->con);
1023         val &= ~DMA_MASTER;
1024         writel(val, &mmc_base->con);
1025
1026         val = readl(&mmc_base->hctl);
1027         val &= ~DMA_SELECT;
1028         writel(val, &mmc_base->hctl);
1029
1030         kfree(priv->adma_desc_table);
1031 }
1032 #else
1033 #define omap_hsmmc_adma_desc
1034 #define omap_hsmmc_prepare_adma_table
1035 #define omap_hsmmc_prepare_data
1036 #define omap_hsmmc_dma_cleanup
1037 #endif
1038
1039 #if !CONFIG_IS_ENABLED(DM_MMC)
1040 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1041                         struct mmc_data *data)
1042 {
1043         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1044 #else
1045 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1046                         struct mmc_data *data)
1047 {
1048         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1049         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1050         struct mmc *mmc = upriv->mmc;
1051 #endif
1052         struct hsmmc *mmc_base;
1053         unsigned int flags, mmc_stat;
1054         ulong start;
1055         priv->last_cmd = cmd->cmdidx;
1056
1057         mmc_base = priv->base_addr;
1058
1059         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1060                 return 0;
1061
1062         start = get_timer(0);
1063         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1064                 if (get_timer(0) - start > MAX_RETRY_MS) {
1065                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1066                                         __func__);
1067                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1068                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1069                         return -ETIMEDOUT;
1070                 }
1071         }
1072         writel(0xFFFFFFFF, &mmc_base->stat);
1073         if (readl(&mmc_base->stat)) {
1074                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1075                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1076         }
1077
1078         /*
1079          * CMDREG
1080          * CMDIDX[13:8] : Command index
1081          * DATAPRNT[5]  : Data Present Select
1082          * ENCMDIDX[4]  : Command Index Check Enable
1083          * ENCMDCRC[3]  : Command CRC Check Enable
1084          * RSPTYP[1:0]
1085          *      00 = No Response
1086          *      01 = Length 136
1087          *      10 = Length 48
1088          *      11 = Length 48 Check busy after response
1089          */
1090         /* Delay added before checking the status of frq change
1091          * retry not supported by mmc.c(core file)
1092          */
1093         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1094                 udelay(50000); /* wait 50 ms */
1095
1096         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1097                 flags = 0;
1098         else if (cmd->resp_type & MMC_RSP_136)
1099                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1100         else if (cmd->resp_type & MMC_RSP_BUSY)
1101                 flags = RSP_TYPE_LGHT48B;
1102         else
1103                 flags = RSP_TYPE_LGHT48;
1104
1105         /* enable default flags */
1106         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1107                         MSBS_SGLEBLK);
1108         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1109
1110         if (cmd->resp_type & MMC_RSP_CRC)
1111                 flags |= CCCE_CHECK;
1112         if (cmd->resp_type & MMC_RSP_OPCODE)
1113                 flags |= CICE_CHECK;
1114
1115         if (data) {
1116                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1117                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1118                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1119                         data->blocksize = 512;
1120                         writel(data->blocksize | (data->blocks << 16),
1121                                                         &mmc_base->blk);
1122                 } else
1123                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1124
1125                 if (data->flags & MMC_DATA_READ)
1126                         flags |= (DP_DATA | DDIR_READ);
1127                 else
1128                         flags |= (DP_DATA | DDIR_WRITE);
1129
1130 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1131                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1132                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1133                         omap_hsmmc_prepare_data(mmc, data);
1134                         flags |= DE_ENABLE;
1135                 }
1136 #endif
1137         }
1138
1139         mmc_enable_irq(mmc, cmd);
1140
1141         writel(cmd->cmdarg, &mmc_base->arg);
1142         udelay(20);             /* To fix "No status update" error on eMMC */
1143         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1144
1145         start = get_timer(0);
1146         do {
1147                 mmc_stat = readl(&mmc_base->stat);
1148                 if (get_timer(start) > MAX_RETRY_MS) {
1149                         printf("%s : timeout: No status update\n", __func__);
1150                         return -ETIMEDOUT;
1151                 }
1152         } while (!mmc_stat);
1153
1154         if ((mmc_stat & IE_CTO) != 0) {
1155                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1156                 return -ETIMEDOUT;
1157         } else if ((mmc_stat & ERRI_MASK) != 0)
1158                 return -1;
1159
1160         if (mmc_stat & CC_MASK) {
1161                 writel(CC_MASK, &mmc_base->stat);
1162                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1163                         if (cmd->resp_type & MMC_RSP_136) {
1164                                 /* response type 2 */
1165                                 cmd->response[3] = readl(&mmc_base->rsp10);
1166                                 cmd->response[2] = readl(&mmc_base->rsp32);
1167                                 cmd->response[1] = readl(&mmc_base->rsp54);
1168                                 cmd->response[0] = readl(&mmc_base->rsp76);
1169                         } else
1170                                 /* response types 1, 1b, 3, 4, 5, 6 */
1171                                 cmd->response[0] = readl(&mmc_base->rsp10);
1172                 }
1173         }
1174
1175 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1176         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1177             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1178                 u32 sz_mb, timeout;
1179
1180                 if (mmc_stat & IE_ADMAE) {
1181                         omap_hsmmc_dma_cleanup(mmc);
1182                         return -EIO;
1183                 }
1184
1185                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1186                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1187                 if (timeout < MAX_RETRY_MS)
1188                         timeout = MAX_RETRY_MS;
1189
1190                 start = get_timer(0);
1191                 do {
1192                         mmc_stat = readl(&mmc_base->stat);
1193                         if (mmc_stat & TC_MASK) {
1194                                 writel(readl(&mmc_base->stat) | TC_MASK,
1195                                        &mmc_base->stat);
1196                                 break;
1197                         }
1198                         if (get_timer(start) > timeout) {
1199                                 printf("%s : DMA timeout: No status update\n",
1200                                        __func__);
1201                                 return -ETIMEDOUT;
1202                         }
1203                 } while (1);
1204
1205                 omap_hsmmc_dma_cleanup(mmc);
1206                 return 0;
1207         }
1208 #endif
1209
1210         if (data && (data->flags & MMC_DATA_READ)) {
1211                 mmc_read_data(mmc_base, data->dest,
1212                                 data->blocksize * data->blocks);
1213         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1214                 mmc_write_data(mmc_base, data->src,
1215                                 data->blocksize * data->blocks);
1216         }
1217         return 0;
1218 }
1219
1220 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1221 {
1222         unsigned int *output_buf = (unsigned int *)buf;
1223         unsigned int mmc_stat;
1224         unsigned int count;
1225
1226         /*
1227          * Start Polled Read
1228          */
1229         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1230         count /= 4;
1231
1232         while (size) {
1233                 ulong start = get_timer(0);
1234                 do {
1235                         mmc_stat = readl(&mmc_base->stat);
1236                         if (get_timer(0) - start > MAX_RETRY_MS) {
1237                                 printf("%s: timedout waiting for status!\n",
1238                                                 __func__);
1239                                 return -ETIMEDOUT;
1240                         }
1241                 } while (mmc_stat == 0);
1242
1243                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1244                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1245
1246                 if ((mmc_stat & ERRI_MASK) != 0)
1247                         return 1;
1248
1249                 if (mmc_stat & BRR_MASK) {
1250                         unsigned int k;
1251
1252                         writel(readl(&mmc_base->stat) | BRR_MASK,
1253                                 &mmc_base->stat);
1254                         for (k = 0; k < count; k++) {
1255                                 *output_buf = readl(&mmc_base->data);
1256                                 output_buf++;
1257                         }
1258                         size -= (count*4);
1259                 }
1260
1261                 if (mmc_stat & BWR_MASK)
1262                         writel(readl(&mmc_base->stat) | BWR_MASK,
1263                                 &mmc_base->stat);
1264
1265                 if (mmc_stat & TC_MASK) {
1266                         writel(readl(&mmc_base->stat) | TC_MASK,
1267                                 &mmc_base->stat);
1268                         break;
1269                 }
1270         }
1271         return 0;
1272 }
1273
1274 #if CONFIG_IS_ENABLED(MMC_WRITE)
1275 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1276                           unsigned int size)
1277 {
1278         unsigned int *input_buf = (unsigned int *)buf;
1279         unsigned int mmc_stat;
1280         unsigned int count;
1281
1282         /*
1283          * Start Polled Write
1284          */
1285         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1286         count /= 4;
1287
1288         while (size) {
1289                 ulong start = get_timer(0);
1290                 do {
1291                         mmc_stat = readl(&mmc_base->stat);
1292                         if (get_timer(0) - start > MAX_RETRY_MS) {
1293                                 printf("%s: timedout waiting for status!\n",
1294                                                 __func__);
1295                                 return -ETIMEDOUT;
1296                         }
1297                 } while (mmc_stat == 0);
1298
1299                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1300                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1301
1302                 if ((mmc_stat & ERRI_MASK) != 0)
1303                         return 1;
1304
1305                 if (mmc_stat & BWR_MASK) {
1306                         unsigned int k;
1307
1308                         writel(readl(&mmc_base->stat) | BWR_MASK,
1309                                         &mmc_base->stat);
1310                         for (k = 0; k < count; k++) {
1311                                 writel(*input_buf, &mmc_base->data);
1312                                 input_buf++;
1313                         }
1314                         size -= (count*4);
1315                 }
1316
1317                 if (mmc_stat & BRR_MASK)
1318                         writel(readl(&mmc_base->stat) | BRR_MASK,
1319                                 &mmc_base->stat);
1320
1321                 if (mmc_stat & TC_MASK) {
1322                         writel(readl(&mmc_base->stat) | TC_MASK,
1323                                 &mmc_base->stat);
1324                         break;
1325                 }
1326         }
1327         return 0;
1328 }
1329 #else
1330 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1331                           unsigned int size)
1332 {
1333         return -ENOTSUPP;
1334 }
1335 #endif
1336 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1337 {
1338         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1339 }
1340
1341 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1342 {
1343         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1344 }
1345
1346 static void omap_hsmmc_set_clock(struct mmc *mmc)
1347 {
1348         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1349         struct hsmmc *mmc_base;
1350         unsigned int dsor = 0;
1351         ulong start;
1352
1353         mmc_base = priv->base_addr;
1354         omap_hsmmc_stop_clock(mmc_base);
1355
1356         /* TODO: Is setting DTO required here? */
1357         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1358                     (ICE_STOP | DTO_15THDTO));
1359
1360         if (mmc->clock != 0) {
1361                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1362                 if (dsor > CLKD_MAX)
1363                         dsor = CLKD_MAX;
1364         } else {
1365                 dsor = CLKD_MAX;
1366         }
1367
1368         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1369                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1370
1371         start = get_timer(0);
1372         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1373                 if (get_timer(0) - start > MAX_RETRY_MS) {
1374                         printf("%s: timedout waiting for ics!\n", __func__);
1375                         return;
1376                 }
1377         }
1378
1379         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1380         mmc->clock = priv->clock;
1381         omap_hsmmc_start_clock(mmc_base);
1382 }
1383
1384 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1385 {
1386         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1387         struct hsmmc *mmc_base;
1388
1389         mmc_base = priv->base_addr;
1390         /* configue bus width */
1391         switch (mmc->bus_width) {
1392         case 8:
1393                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1394                         &mmc_base->con);
1395                 break;
1396
1397         case 4:
1398                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1399                         &mmc_base->con);
1400                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1401                         &mmc_base->hctl);
1402                 break;
1403
1404         case 1:
1405         default:
1406                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1407                         &mmc_base->con);
1408                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1409                         &mmc_base->hctl);
1410                 break;
1411         }
1412
1413         priv->bus_width = mmc->bus_width;
1414 }
1415
1416 #if !CONFIG_IS_ENABLED(DM_MMC)
1417 static int omap_hsmmc_set_ios(struct mmc *mmc)
1418 {
1419         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1420 #else
1421 static int omap_hsmmc_set_ios(struct udevice *dev)
1422 {
1423         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1424         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1425         struct mmc *mmc = upriv->mmc;
1426 #endif
1427         struct hsmmc *mmc_base = priv->base_addr;
1428         int ret = 0;
1429
1430         if (priv->bus_width != mmc->bus_width)
1431                 omap_hsmmc_set_bus_width(mmc);
1432
1433         if (priv->clock != mmc->clock)
1434                 omap_hsmmc_set_clock(mmc);
1435
1436         if (mmc->clk_disable)
1437                 omap_hsmmc_stop_clock(mmc_base);
1438         else
1439                 omap_hsmmc_start_clock(mmc_base);
1440
1441 #if CONFIG_IS_ENABLED(DM_MMC)
1442         if (priv->mode != mmc->selected_mode)
1443                 omap_hsmmc_set_timing(mmc);
1444
1445 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1446         if (priv->signal_voltage != mmc->signal_voltage)
1447                 ret = omap_hsmmc_set_signal_voltage(mmc);
1448 #endif
1449 #endif
1450         return ret;
1451 }
1452
1453 #ifdef OMAP_HSMMC_USE_GPIO
1454 #if CONFIG_IS_ENABLED(DM_MMC)
1455 static int omap_hsmmc_getcd(struct udevice *dev)
1456 {
1457         int value = -1;
1458 #if CONFIG_IS_ENABLED(DM_GPIO)
1459         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1460         value = dm_gpio_get_value(&priv->cd_gpio);
1461 #endif
1462         /* if no CD return as 1 */
1463         if (value < 0)
1464                 return 1;
1465
1466         return value;
1467 }
1468
1469 static int omap_hsmmc_getwp(struct udevice *dev)
1470 {
1471         int value = 0;
1472 #if CONFIG_IS_ENABLED(DM_GPIO)
1473         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1474         value = dm_gpio_get_value(&priv->wp_gpio);
1475 #endif
1476         /* if no WP return as 0 */
1477         if (value < 0)
1478                 return 0;
1479         return value;
1480 }
1481 #else
1482 static int omap_hsmmc_getcd(struct mmc *mmc)
1483 {
1484         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1485         int cd_gpio;
1486
1487         /* if no CD return as 1 */
1488         cd_gpio = priv->cd_gpio;
1489         if (cd_gpio < 0)
1490                 return 1;
1491
1492         /* NOTE: assumes card detect signal is active-low */
1493         return !gpio_get_value(cd_gpio);
1494 }
1495
1496 static int omap_hsmmc_getwp(struct mmc *mmc)
1497 {
1498         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1499         int wp_gpio;
1500
1501         /* if no WP return as 0 */
1502         wp_gpio = priv->wp_gpio;
1503         if (wp_gpio < 0)
1504                 return 0;
1505
1506         /* NOTE: assumes write protect signal is active-high */
1507         return gpio_get_value(wp_gpio);
1508 }
1509 #endif
1510 #endif
1511
1512 #if CONFIG_IS_ENABLED(DM_MMC)
1513 static const struct dm_mmc_ops omap_hsmmc_ops = {
1514         .send_cmd       = omap_hsmmc_send_cmd,
1515         .set_ios        = omap_hsmmc_set_ios,
1516 #ifdef OMAP_HSMMC_USE_GPIO
1517         .get_cd         = omap_hsmmc_getcd,
1518         .get_wp         = omap_hsmmc_getwp,
1519 #endif
1520 #ifdef MMC_SUPPORTS_TUNING
1521         .execute_tuning = omap_hsmmc_execute_tuning,
1522 #endif
1523         .wait_dat0      = omap_hsmmc_wait_dat0,
1524 };
1525 #else
1526 static const struct mmc_ops omap_hsmmc_ops = {
1527         .send_cmd       = omap_hsmmc_send_cmd,
1528         .set_ios        = omap_hsmmc_set_ios,
1529         .init           = omap_hsmmc_init_setup,
1530 #ifdef OMAP_HSMMC_USE_GPIO
1531         .getcd          = omap_hsmmc_getcd,
1532         .getwp          = omap_hsmmc_getwp,
1533 #endif
1534 };
1535 #endif
1536
1537 #if !CONFIG_IS_ENABLED(DM_MMC)
1538 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1539                 int wp_gpio)
1540 {
1541         struct mmc *mmc;
1542         struct omap_hsmmc_data *priv;
1543         struct mmc_config *cfg;
1544         uint host_caps_val;
1545
1546         priv = calloc(1, sizeof(*priv));
1547         if (priv == NULL)
1548                 return -1;
1549
1550         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1551
1552         switch (dev_index) {
1553         case 0:
1554                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1555                 break;
1556 #ifdef OMAP_HSMMC2_BASE
1557         case 1:
1558                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1559 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1560         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1561         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1562                 defined(CONFIG_HSMMC2_8BIT)
1563                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1564                 host_caps_val |= MMC_MODE_8BIT;
1565 #endif
1566                 break;
1567 #endif
1568 #ifdef OMAP_HSMMC3_BASE
1569         case 2:
1570                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1571 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1572                 /* Enable 8-bit interface for eMMC on DRA7XX */
1573                 host_caps_val |= MMC_MODE_8BIT;
1574 #endif
1575                 break;
1576 #endif
1577         default:
1578                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1579                 return 1;
1580         }
1581 #ifdef OMAP_HSMMC_USE_GPIO
1582         /* on error gpio values are set to -1, which is what we want */
1583         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1584         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1585 #endif
1586
1587         cfg = &priv->cfg;
1588
1589         cfg->name = "OMAP SD/MMC";
1590         cfg->ops = &omap_hsmmc_ops;
1591
1592         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1593         cfg->host_caps = host_caps_val & ~host_caps_mask;
1594
1595         cfg->f_min = 400000;
1596
1597         if (f_max != 0)
1598                 cfg->f_max = f_max;
1599         else {
1600                 if (cfg->host_caps & MMC_MODE_HS) {
1601                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1602                                 cfg->f_max = 52000000;
1603                         else
1604                                 cfg->f_max = 26000000;
1605                 } else
1606                         cfg->f_max = 20000000;
1607         }
1608
1609         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1610
1611 #if defined(CONFIG_OMAP34XX)
1612         /*
1613          * Silicon revs 2.1 and older do not support multiblock transfers.
1614          */
1615         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1616                 cfg->b_max = 1;
1617 #endif
1618
1619         mmc = mmc_create(cfg, priv);
1620         if (mmc == NULL)
1621                 return -1;
1622
1623         return 0;
1624 }
1625 #else
1626
1627 #ifdef CONFIG_IODELAY_RECALIBRATION
1628 static struct pad_conf_entry *
1629 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1630 {
1631         int index = 0;
1632         struct pad_conf_entry *padconf;
1633
1634         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1635         if (!padconf) {
1636                 debug("failed to allocate memory\n");
1637                 return 0;
1638         }
1639
1640         while (index < count) {
1641                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1642                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1643                 index++;
1644         }
1645
1646         return padconf;
1647 }
1648
1649 static struct iodelay_cfg_entry *
1650 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1651 {
1652         int index = 0;
1653         struct iodelay_cfg_entry *iodelay;
1654
1655         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1656         if (!iodelay) {
1657                 debug("failed to allocate memory\n");
1658                 return 0;
1659         }
1660
1661         while (index < count) {
1662                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1663                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1664                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1665                 index++;
1666         }
1667
1668         return iodelay;
1669 }
1670
1671 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1672                                                    const char *name, int *len)
1673 {
1674         const void *fdt = gd->fdt_blob;
1675         int offset;
1676         const fdt32_t *pinctrl;
1677
1678         offset = fdt_node_offset_by_phandle(fdt, phandle);
1679         if (offset < 0) {
1680                 debug("failed to get pinctrl node %s.\n",
1681                       fdt_strerror(offset));
1682                 return 0;
1683         }
1684
1685         pinctrl = fdt_getprop(fdt, offset, name, len);
1686         if (!pinctrl) {
1687                 debug("failed to get property %s\n", name);
1688                 return 0;
1689         }
1690
1691         return pinctrl;
1692 }
1693
1694 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1695                                                 char *prop_name)
1696 {
1697         const void *fdt = gd->fdt_blob;
1698         const __be32 *phandle;
1699         int node = dev_of_offset(mmc->dev);
1700
1701         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1702         if (!phandle) {
1703                 debug("failed to get property %s\n", prop_name);
1704                 return 0;
1705         }
1706
1707         return fdt32_to_cpu(*phandle);
1708 }
1709
1710 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1711                                                char *prop_name)
1712 {
1713         const void *fdt = gd->fdt_blob;
1714         const __be32 *phandle;
1715         int len;
1716         int count;
1717         int node = dev_of_offset(mmc->dev);
1718
1719         phandle = fdt_getprop(fdt, node, prop_name, &len);
1720         if (!phandle) {
1721                 debug("failed to get property %s\n", prop_name);
1722                 return 0;
1723         }
1724
1725         /* No manual mode iodelay values if count < 2 */
1726         count = len / sizeof(*phandle);
1727         if (count < 2)
1728                 return 0;
1729
1730         return fdt32_to_cpu(*(phandle + 1));
1731 }
1732
1733 static struct pad_conf_entry *
1734 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1735 {
1736         int len;
1737         int count;
1738         struct pad_conf_entry *padconf;
1739         u32 phandle;
1740         const fdt32_t *pinctrl;
1741
1742         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1743         if (!phandle)
1744                 return ERR_PTR(-EINVAL);
1745
1746         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1747                                                &len);
1748         if (!pinctrl)
1749                 return ERR_PTR(-EINVAL);
1750
1751         count = (len / sizeof(*pinctrl)) / 2;
1752         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1753         if (!padconf)
1754                 return ERR_PTR(-EINVAL);
1755
1756         *npads = count;
1757
1758         return padconf;
1759 }
1760
1761 static struct iodelay_cfg_entry *
1762 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1763 {
1764         int len;
1765         int count;
1766         struct iodelay_cfg_entry *iodelay;
1767         u32 phandle;
1768         const fdt32_t *pinctrl;
1769
1770         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1771         /* Not all modes have manual mode iodelay values. So its not fatal */
1772         if (!phandle)
1773                 return 0;
1774
1775         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1776                                                &len);
1777         if (!pinctrl)
1778                 return ERR_PTR(-EINVAL);
1779
1780         count = (len / sizeof(*pinctrl)) / 3;
1781         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1782         if (!iodelay)
1783                 return ERR_PTR(-EINVAL);
1784
1785         *niodelay = count;
1786
1787         return iodelay;
1788 }
1789
1790 static struct omap_hsmmc_pinctrl_state *
1791 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1792 {
1793         int index;
1794         int npads = 0;
1795         int niodelays = 0;
1796         const void *fdt = gd->fdt_blob;
1797         int node = dev_of_offset(mmc->dev);
1798         char prop_name[11];
1799         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1800
1801         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1802                          malloc(sizeof(*pinctrl_state));
1803         if (!pinctrl_state) {
1804                 debug("failed to allocate memory\n");
1805                 return 0;
1806         }
1807
1808         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1809         if (index < 0) {
1810                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1811                 goto err_pinctrl_state;
1812         }
1813
1814         sprintf(prop_name, "pinctrl-%d", index);
1815
1816         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1817                                                          &npads);
1818         if (IS_ERR(pinctrl_state->padconf))
1819                 goto err_pinctrl_state;
1820         pinctrl_state->npads = npads;
1821
1822         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1823                                                         &niodelays);
1824         if (IS_ERR(pinctrl_state->iodelay))
1825                 goto err_padconf;
1826         pinctrl_state->niodelays = niodelays;
1827
1828         return pinctrl_state;
1829
1830 err_padconf:
1831         kfree(pinctrl_state->padconf);
1832
1833 err_pinctrl_state:
1834         kfree(pinctrl_state);
1835         return 0;
1836 }
1837
1838 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1839         do {                                                            \
1840                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1841                 char str[20];                                           \
1842                 if (!(cfg->host_caps & capmask))                        \
1843                         break;                                          \
1844                                                                         \
1845                 if (priv->hw_rev) {                                     \
1846                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1847                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1848                 }                                                       \
1849                                                                         \
1850                 if (!s)                                                 \
1851                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1852                                                                         \
1853                 if (!s && !optional) {                                  \
1854                         debug("%s: no pinctrl for %s\n",                \
1855                               mmc->dev->name, #mode);                   \
1856                         cfg->host_caps &= ~(capmask);                   \
1857                 } else {                                                \
1858                         priv->mode##_pinctrl_state = s;                 \
1859                 }                                                       \
1860         } while (0)
1861
1862 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1863 {
1864         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1865         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1866         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1867
1868         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1869                 return 0;
1870
1871         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1872         if (!default_pinctrl) {
1873                 printf("no pinctrl state for default mode\n");
1874                 return -EINVAL;
1875         }
1876
1877         priv->default_pinctrl_state = default_pinctrl;
1878
1879         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1880         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1881         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1882         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1883         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1884
1885         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1886         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1887         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1888
1889         return 0;
1890 }
1891 #endif
1892
1893 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1894 #ifdef CONFIG_OMAP54XX
1895 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1896 {
1897         return NULL;
1898 }
1899 #endif
1900
1901 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1902 {
1903         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1904         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1905
1906         struct mmc_config *cfg = &plat->cfg;
1907 #ifdef CONFIG_OMAP54XX
1908         const struct mmc_platform_fixups *fixups;
1909 #endif
1910         const void *fdt = gd->fdt_blob;
1911         int node = dev_of_offset(dev);
1912         int ret;
1913
1914         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1915                                       sizeof(struct hsmmc *),
1916                                       MAP_NOCACHE);
1917
1918         ret = mmc_of_parse(dev, cfg);
1919         if (ret < 0)
1920                 return ret;
1921
1922         if (!cfg->f_max)
1923                 cfg->f_max = 52000000;
1924         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1925         cfg->f_min = 400000;
1926         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1927         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1928         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1929                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1930         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1931                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1932         if (of_data)
1933                 plat->controller_flags |= of_data->controller_flags;
1934
1935 #ifdef CONFIG_OMAP54XX
1936         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1937         if (fixups) {
1938                 plat->hw_rev = fixups->hw_rev;
1939                 cfg->host_caps &= ~fixups->unsupported_caps;
1940                 cfg->f_max = fixups->max_freq;
1941         }
1942 #endif
1943
1944         return 0;
1945 }
1946 #endif
1947
1948 #ifdef CONFIG_BLK
1949
1950 static int omap_hsmmc_bind(struct udevice *dev)
1951 {
1952         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1953         plat->mmc = calloc(1, sizeof(struct mmc));
1954         return mmc_bind(dev, plat->mmc, &plat->cfg);
1955 }
1956 #endif
1957 static int omap_hsmmc_probe(struct udevice *dev)
1958 {
1959         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1960         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1961         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1962         struct mmc_config *cfg = &plat->cfg;
1963         struct mmc *mmc;
1964 #ifdef CONFIG_IODELAY_RECALIBRATION
1965         int ret;
1966 #endif
1967
1968         cfg->name = "OMAP SD/MMC";
1969         priv->base_addr = plat->base_addr;
1970         priv->controller_flags = plat->controller_flags;
1971         priv->hw_rev = plat->hw_rev;
1972
1973 #ifdef CONFIG_BLK
1974         mmc = plat->mmc;
1975 #else
1976         mmc = mmc_create(cfg, priv);
1977         if (mmc == NULL)
1978                 return -1;
1979 #endif
1980 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1981         device_get_supply_regulator(dev, "pbias-supply",
1982                                     &priv->pbias_supply);
1983 #endif
1984 #if defined(OMAP_HSMMC_USE_GPIO)
1985 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1986         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1987         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1988 #endif
1989 #endif
1990
1991         mmc->dev = dev;
1992         upriv->mmc = mmc;
1993
1994 #ifdef CONFIG_IODELAY_RECALIBRATION
1995         ret = omap_hsmmc_get_pinctrl_state(mmc);
1996         /*
1997          * disable high speed modes for the platforms that require IO delay
1998          * and for which we don't have this information
1999          */
2000         if ((ret < 0) &&
2001             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2002                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2003                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2004                                     UHS_CAPS);
2005         }
2006 #endif
2007
2008         return omap_hsmmc_init_setup(mmc);
2009 }
2010
2011 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2012
2013 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2014         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2015 };
2016
2017 static const struct udevice_id omap_hsmmc_ids[] = {
2018         { .compatible = "ti,omap3-hsmmc" },
2019         { .compatible = "ti,omap4-hsmmc" },
2020         { .compatible = "ti,am33xx-hsmmc" },
2021         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2022         { }
2023 };
2024 #endif
2025
2026 U_BOOT_DRIVER(omap_hsmmc) = {
2027         .name   = "omap_hsmmc",
2028         .id     = UCLASS_MMC,
2029 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2030         .of_match = omap_hsmmc_ids,
2031         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2032         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2033 #endif
2034 #ifdef CONFIG_BLK
2035         .bind = omap_hsmmc_bind,
2036 #endif
2037         .ops = &omap_hsmmc_ops,
2038         .probe  = omap_hsmmc_probe,
2039         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2040 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2041         .flags  = DM_FLAG_PRE_RELOC,
2042 #endif
2043 };
2044 #endif