1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Marvell International Ltd.
5 * https://spdx.org/licenses
7 #ifndef __OCTEONTX_HSMMC_H__
8 #define __OCTEONTX_HSMMC_H__
11 /** Name of our driver */
12 #define OCTEONTX_MMC_DRIVER_NAME "octeontx-hsmmc"
14 /** Maximum supported MMC slots */
15 #define OCTEONTX_MAX_MMC_SLOT 3
17 #define POWER_ON_TIME 40 /** See SD 4.1 spec figure 6-5 */
20 * Timeout used when waiting for commands to complete. We need to keep this
21 * above the hardware watchdog timeout which is usually limited to 1000ms
23 #define WATCHDOG_COUNT (1100) /* in msecs */
26 * Long timeout for commands which might take a while to complete.
28 #define MMC_TIMEOUT_LONG 1000
31 * Short timeout used for most commands in msecs
33 #define MMC_TIMEOUT_SHORT 20
35 #define NSEC_PER_SEC 1000000000L
37 #define MAX_NO_OF_TAPS 64
39 #define EXT_CSD_POWER_CLASS 187 /* R/W */
41 /* default HS400 tuning block number */
42 #define DEFAULT_HS400_TUNING_BLOCK 1
44 struct octeontx_mmc_host;
46 /** MMC/SD slot data structure */
47 struct octeontx_mmc_slot {
49 struct mmc_config cfg;
50 struct octeontx_mmc_host *host;
52 void *base_addr; /** Same as host base_addr */
54 int bus_id; /** slot number */
59 int hs400_tuning_block;
60 struct gpio_desc cd_gpio;
61 struct gpio_desc wp_gpio;
62 struct gpio_desc power_gpio;
64 union mio_emm_switch cached_switch;
65 union mio_emm_switch want_switch;
66 union mio_emm_rca cached_rca;
67 union mio_emm_timing taps; /* otx2: MIO_EMM_TIMING */
68 union mio_emm_timing hs200_taps;
69 union mio_emm_timing hs400_taps;
70 /* These are used to see if our tuning is still valid or not */
71 enum bus_mode last_mode;
77 uint cmd_cnt; /* otx: sample cmd in delay */
78 uint dat_cnt; /* otx: sample data in delay */
79 uint drive; /* Current drive */
80 uint slew; /* clock skew */
81 uint cmd_out_hs200_delay;
82 uint data_out_hs200_delay;
83 uint cmd_out_hs400_delay;
84 uint data_out_hs400_delay;
102 struct octeontx_mmc_cr_mods {
107 struct octeontx_mmc_cr {
112 struct octeontx_sd_mods {
113 struct octeontx_mmc_cr mmc;
114 struct octeontx_mmc_cr sd;
115 struct octeontx_mmc_cr sdacmd;
118 /** Host controller data structure */
119 struct octeontx_mmc_host {
122 struct octeontx_mmc_slot slots[OCTEONTX_MAX_MMC_SLOT + 1];
125 union mio_emm_cfg emm_cfg;
127 struct mmc *last_mmc; /** Last mmc used */
134 uint dma_wait_delay; /* Delay before polling DMA in usecs */
136 bool timing_calibrated:1;
139 bool calibrate_glitch:1;
140 bool cond_clock_glitch:1;
141 bool tap_requires_noclk:1;
142 bool hs400_skew_needed:1;
146 * NOTE: This was copied from the Linux kernel.
148 * MMC status in R1, for native mode (SPI bits are different)
152 * r:detected and set for the actual command response
153 * x:detected and set during command execution. the host must poll
154 * the card by sending status command in order to read these bits.
156 * a:according to the card state
157 * b:always related to the previous command. Reception of
158 * a valid command will clear it (with a delay of one command)
161 #define R1_OUT_OF_RANGE BIT(31) /* er, c */
162 #define R1_ADDRESS_ERROR BIT(30) /* erx, c */
163 #define R1_BLOCK_LEN_ERROR BIT(29) /* er, c */
164 #define R1_ERASE_SEQ_ERROR BIT(28) /* er, c */
165 #define R1_ERASE_PARAM BIT(27) /* ex, c */
166 #define R1_WP_VIOLATION BIT(26) /* erx, c */
167 #define R1_CARD_IS_LOCKED BIT(25) /* sx, a */
168 #define R1_LOCK_UNLOCK_FAILED BIT(24) /* erx, c */
169 #define R1_COM_CRC_ERROR BIT(23) /* er, b */
170 /*#define R1_ILLEGAL_COMMAND BIT(22)*/ /* er, b */
171 #define R1_CARD_ECC_FAILED BIT(21) /* ex, c */
172 #define R1_CC_ERROR BIT(20) /* erx, c */
173 #define R1_ERROR BIT(19) /* erx, c */
174 #define R1_UNDERRUN BIT(18) /* ex, c */
175 #define R1_OVERRUN BIT(17) /* ex, c */
176 #define R1_CID_CSD_OVERWRITE BIT(16) /* erx, c, CID/CSD overwrite */
177 #define R1_WP_ERASE_SKIP BIT(15) /* sx, c */
178 #define R1_CARD_ECC_DISABLED BIT(14) /* sx, a */
179 #define R1_ERASE_RESET BIT(13) /* sr, c */
180 #define R1_STATUS(x) ((x) & 0xFFFFE000)
181 #define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */
182 #define R1_READY_FOR_DATA BIT(8) /* sx, a */
183 #define R1_SWITCH_ERROR BIT(7) /* sx, c */
185 #define R1_BLOCK_READ_MASK R1_OUT_OF_RANGE | \
187 R1_BLOCK_LEN_ERROR | \
188 R1_CARD_IS_LOCKED | \
190 R1_ILLEGAL_COMMAND | \
191 R1_CARD_ECC_FAILED | \
194 #define R1_BLOCK_WRITE_MASK R1_OUT_OF_RANGE | \
196 R1_BLOCK_LEN_ERROR | \
198 R1_CARD_IS_LOCKED | \
200 R1_ILLEGAL_COMMAND | \
201 R1_CARD_ECC_FAILED | \
207 #endif /* __OCTEONTX_HSMMC_H__ */