1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Marvell International Ltd.
5 * https://spdx.org/licenses
25 #include <linux/delay.h>
26 #include <linux/kernel.h>
27 #include <linux/libfdt.h>
29 #include <asm/arch/board.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/csrs/csrs-mio_emm.h>
33 #include <dm/device-internal.h>
35 #include <power/regulator.h>
37 #include "octeontx_hsmmc.h"
39 #define MMC_TIMEOUT_SHORT 20 /* in ms */
40 #define MMC_TIMEOUT_LONG 1000
41 #define MMC_TIMEOUT_ERASE 10000
43 #define MMC_DEFAULT_DATA_IN_TAP 10
44 #define MMC_DEFAULT_CMD_IN_TAP 10
45 #define MMC_DEFAULT_CMD_OUT_TAP 39
46 #define MMC_DEFAULT_DATA_OUT_TAP 39
47 #define MMC_DEFAULT_HS200_CMD_IN_TAP 24
48 #define MMC_DEFAULT_HS200_DATA_IN_TAP 24
49 #define MMC_DEFAULT_HS200_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
50 #define MMC_DEFAULT_HS200_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
51 #define MMC_DEFAULT_HS400_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
52 #define MMC_DEFAULT_HS400_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 5 : 3)
53 #define MMC_DEFAULT_HS200_CMD_OUT_DLY 800 /* Delay in ps */
54 #define MMC_DEFAULT_HS200_DATA_OUT_DLY 800 /* Delay in ps */
55 #define MMC_DEFAULT_HS400_CMD_OUT_DLY 800 /* Delay in ps */
56 #define MMC_DEFAULT_HS400_DATA_OUT_DLY 400 /* Delay in ps */
57 #define MMC_DEFAULT_SD_UHS_SDR104_CMD_OUT_TAP MMC_DEFAULT_HS200_CMD_OUT_TAP
58 #define MMC_DEFAULT_SD_UHS_SDR104_DATA_OUT_TAP MMC_DEFAULT_HS200_DATA_OUT_TAP
59 #define MMC_LEGACY_DEFAULT_CMD_OUT_TAP 39
60 #define MMC_LEGACY_DEFAULT_DATA_OUT_TAP 39
61 #define MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP 63
62 #define MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP 63
63 #define MMC_HS_CMD_OUT_TAP 32
64 #define MMC_HS_DATA_OUT_TAP 32
65 #define MMC_SD_HS_CMD_OUT_TAP 26
66 #define MMC_SD_HS_DATA_OUT_TAP 26
67 #define MMC_SD_UHS_SDR25_CMD_OUT_TAP 26
68 #define MMC_SD_UHS_SDR25_DATA_OUT_TAP 26
69 #define MMC_SD_UHS_SDR50_CMD_OUT_TAP 26
70 #define MMC_SD_UHS_SDR50_DATA_OUT_TAP 26
71 #define MMC_DEFAULT_TAP_DELAY 4
72 #define TOTAL_NO_OF_TAPS 512
73 static void octeontx_mmc_switch_to(struct mmc *mmc);
74 static int octeontx_mmc_configure_delay(struct mmc *mmc);
75 static void octeontx_mmc_set_timing(struct mmc *mmc);
76 static void set_wdog(struct mmc *mmc, u64 us);
77 static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch);
78 static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
79 struct mmc_data *data);
80 static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay);
81 static int octeontx_mmc_calibrate_delay(struct mmc *mmc);
82 static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc);
83 static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc);
85 static bool host_probed;
88 * Get the slot data structure from a MMC data structure
90 static inline struct octeontx_mmc_slot *mmc_to_slot(struct mmc *mmc)
92 return container_of(mmc, struct octeontx_mmc_slot, mmc);
95 static inline struct octeontx_mmc_host *mmc_to_host(struct mmc *mmc)
97 return mmc_to_slot(mmc)->host;
100 static inline struct octeontx_mmc_slot *dev_to_mmc_slot(struct udevice *dev)
102 return dev_get_priv(dev);
105 static inline struct mmc *dev_to_mmc(struct udevice *dev)
107 return &((struct octeontx_mmc_slot *)dev_get_priv(dev))->mmc;
111 const char *mmc_reg_str(u64 reg)
113 if (reg == MIO_EMM_DMA_CFG())
114 return "MIO_EMM_DMA_CFG";
115 if (reg == MIO_EMM_DMA_ADR())
116 return "MIO_EMM_DMA_ADR";
117 if (reg == MIO_EMM_DMA_INT())
118 return "MIO_EMM_DMA_INT";
119 if (reg == MIO_EMM_CFG())
120 return "MIO_EMM_CFG";
121 if (reg == MIO_EMM_MODEX(0))
122 return "MIO_EMM_MODE0";
123 if (reg == MIO_EMM_MODEX(1))
124 return "MIO_EMM_MODE1";
125 if (reg == MIO_EMM_MODEX(2))
126 return "MIO_EMM_MODE2";
127 if (reg == MIO_EMM_MODEX(3))
128 return "MIO_EMM_MODE3";
129 if (reg == MIO_EMM_IO_CTL())
130 return "MIO_EMM_IO_CTL";
131 if (reg == MIO_EMM_SWITCH())
132 return "MIO_EMM_SWITCH";
133 if (reg == MIO_EMM_DMA())
134 return "MIO_EMM_DMA";
135 if (reg == MIO_EMM_CMD())
136 return "MIO_EMM_CMD";
137 if (reg == MIO_EMM_RSP_STS())
138 return "MIO_EMM_RSP_STS";
139 if (reg == MIO_EMM_RSP_LO())
140 return "MIO_EMM_RSP_LO";
141 if (reg == MIO_EMM_RSP_HI())
142 return "MIO_EMM_RSP_HI";
143 if (reg == MIO_EMM_INT())
144 return "MIO_EMM_INT";
145 if (reg == MIO_EMM_WDOG())
146 return "MIO_EMM_WDOG";
147 if (reg == MIO_EMM_DMA_ARG())
148 return "MIO_EMM_DMA_ARG";
149 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
150 if (reg == MIO_EMM_SAMPLE())
151 return "MIO_EMM_SAMPLE";
153 if (reg == MIO_EMM_STS_MASK())
154 return "MIO_EMM_STS_MASK";
155 if (reg == MIO_EMM_RCA())
156 return "MIO_EMM_RCA";
157 if (reg == MIO_EMM_BUF_IDX())
158 return "MIO_EMM_BUF_IDX";
159 if (reg == MIO_EMM_BUF_DAT())
160 return "MIO_EMM_BUF_DAT";
161 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
162 if (reg == MIO_EMM_CALB())
163 return "MIO_EMM_CALB";
164 if (reg == MIO_EMM_TAP())
165 return "MIO_EMM_TAP";
166 if (reg == MIO_EMM_TIMING())
167 return "MIO_EMM_TIMING";
168 if (reg == MIO_EMM_DEBUG())
169 return "MIO_EMM_DEBUG";
176 static void octeontx_print_rsp_sts(struct mmc *mmc)
179 union mio_emm_rsp_sts emm_rsp_sts;
180 const struct octeontx_mmc_host *host = mmc_to_host(mmc);
181 static const char * const ctype_xor_str[] = {
183 "Read data into Dbuf",
184 "Write data from Dbuf",
188 static const char * const rtype_xor_str[] = {
199 emm_rsp_sts.u = readq(host->base_addr + MIO_EMM_RSP_STS());
200 printf("\nMIO_EMM_RSP_STS: 0x%016llx\n", emm_rsp_sts.u);
201 printf(" 60-61: bus_id: %u\n", emm_rsp_sts.s.bus_id);
202 printf(" 59: cmd_val: %s\n",
203 emm_rsp_sts.s.cmd_val ? "yes" : "no");
204 printf(" 58: switch_val: %s\n",
205 emm_rsp_sts.s.switch_val ? "yes" : "no");
206 printf(" 57: dma_val: %s\n",
207 emm_rsp_sts.s.dma_val ? "yes" : "no");
208 printf(" 56: dma_pend: %s\n",
209 emm_rsp_sts.s.dma_pend ? "yes" : "no");
210 printf(" 28: dbuf_err: %s\n",
211 emm_rsp_sts.s.dbuf_err ? "yes" : "no");
212 printf(" 23: dbuf: %u\n", emm_rsp_sts.s.dbuf);
213 printf(" 22: blk_timeout: %s\n",
214 emm_rsp_sts.s.blk_timeout ? "yes" : "no");
215 printf(" 21: blk_crc_err: %s\n",
216 emm_rsp_sts.s.blk_crc_err ? "yes" : "no");
217 printf(" 20: rsp_busybit: %s\n",
218 emm_rsp_sts.s.rsp_busybit ? "yes" : "no");
219 printf(" 19: stp_timeout: %s\n",
220 emm_rsp_sts.s.stp_timeout ? "yes" : "no");
221 printf(" 18: stp_crc_err: %s\n",
222 emm_rsp_sts.s.stp_crc_err ? "yes" : "no");
223 printf(" 17: stp_bad_sts: %s\n",
224 emm_rsp_sts.s.stp_bad_sts ? "yes" : "no");
225 printf(" 16: stp_val: %s\n",
226 emm_rsp_sts.s.stp_val ? "yes" : "no");
227 printf(" 15: rsp_timeout: %s\n",
228 emm_rsp_sts.s.rsp_timeout ? "yes" : "no");
229 printf(" 14: rsp_crc_err: %s\n",
230 emm_rsp_sts.s.rsp_crc_err ? "yes" : "no");
231 printf(" 13: rsp_bad_sts: %s\n",
232 emm_rsp_sts.s.rsp_bad_sts ? "yes" : "no");
233 printf(" 12: rsp_val: %s\n",
234 emm_rsp_sts.s.rsp_val ? "yes" : "no");
235 printf(" 9-11: rsp_type: %s\n",
236 rtype_xor_str[emm_rsp_sts.s.rsp_type]);
237 printf(" 7-8: cmd_type: %s\n",
238 ctype_xor_str[emm_rsp_sts.s.cmd_type]);
239 printf(" 1-6: cmd_idx: %u\n",
240 emm_rsp_sts.s.cmd_idx);
241 printf(" 0: cmd_done: %s\n",
242 emm_rsp_sts.s.cmd_done ? "yes" : "no");
246 static inline u64 read_csr(struct mmc *mmc, u64 reg)
248 const struct octeontx_mmc_host *host = mmc_to_host(mmc);
249 u64 value = readq(host->base_addr + reg);
251 printf(" %s: %s(0x%p) => 0x%llx\n", __func__,
252 mmc_reg_str(reg), host->base_addr + reg,
259 * Writes to a CSR register
261 * @param[in] mmc pointer to mmc data structure
262 * @param reg register offset
263 * @param value value to write to register
265 static inline void write_csr(struct mmc *mmc, u64 reg, u64 value)
267 const struct octeontx_mmc_host *host = mmc_to_host(mmc);
268 void *addr = host->base_addr + reg;
271 printf(" %s: %s(0x%p) <= 0x%llx\n", __func__, mmc_reg_str(reg),
278 static void mmc_print_status(u32 status)
281 static const char * const state[] = {
297 "reserved" /* 15 */ };
298 if (status & R1_APP_CMD)
300 if (status & R1_SWITCH_ERROR)
301 puts("MMC switch error\n");
302 if (status & R1_READY_FOR_DATA)
303 puts("MMC ready for data\n");
304 printf("MMC %s state\n", state[R1_CURRENT_STATE(status)]);
305 if (status & R1_ERASE_RESET)
306 puts("MMC erase reset\n");
307 if (status & R1_WP_ERASE_SKIP)
308 puts("MMC partial erase due to write protected blocks\n");
309 if (status & R1_CID_CSD_OVERWRITE)
310 puts("MMC CID/CSD overwrite error\n");
311 if (status & R1_ERROR)
312 puts("MMC undefined device error\n");
313 if (status & R1_CC_ERROR)
314 puts("MMC device error\n");
315 if (status & R1_CARD_ECC_FAILED)
316 puts("MMC internal ECC failed to correct data\n");
317 if (status & R1_ILLEGAL_COMMAND)
318 puts("MMC illegal command\n");
319 if (status & R1_COM_CRC_ERROR)
320 puts("MMC CRC of previous command failed\n");
321 if (status & R1_LOCK_UNLOCK_FAILED)
322 puts("MMC sequence or password error in lock/unlock device command\n");
323 if (status & R1_CARD_IS_LOCKED)
324 puts("MMC device locked by host\n");
325 if (status & R1_WP_VIOLATION)
326 puts("MMC attempt to program write protected block\n");
327 if (status & R1_ERASE_PARAM)
328 puts("MMC invalid selection of erase groups for erase\n");
329 if (status & R1_ERASE_SEQ_ERROR)
330 puts("MMC error in sequence of erase commands\n");
331 if (status & R1_BLOCK_LEN_ERROR)
332 puts("MMC block length error\n");
333 if (status & R1_ADDRESS_ERROR)
334 puts("MMC address misalign error\n");
335 if (status & R1_OUT_OF_RANGE)
336 puts("MMC address out of range\n");
342 * Print out all of the register values where mmc is optional
344 * @param mmc MMC device (can be NULL)
345 * @param host Pointer to host data structure (can be NULL if mmc is !NULL)
347 static void octeontx_mmc_print_registers2(struct mmc *mmc,
348 struct octeontx_mmc_host *host)
350 struct octeontx_mmc_slot *slot = mmc ? mmc->priv : NULL;
351 union mio_emm_dma_cfg emm_dma_cfg;
352 union mio_emm_dma_adr emm_dma_adr;
353 union mio_emm_dma_int emm_dma_int;
354 union mio_emm_cfg emm_cfg;
355 union mio_emm_modex emm_mode;
356 union mio_emm_switch emm_switch;
357 union mio_emm_dma emm_dma;
358 union mio_emm_cmd emm_cmd;
359 union mio_emm_rsp_sts emm_rsp_sts;
360 union mio_emm_rsp_lo emm_rsp_lo;
361 union mio_emm_rsp_hi emm_rsp_hi;
362 union mio_emm_int emm_int;
363 union mio_emm_wdog emm_wdog;
364 union mio_emm_sample emm_sample;
365 union mio_emm_calb emm_calb;
366 union mio_emm_tap emm_tap;
367 union mio_emm_timing emm_timing;
368 union mio_emm_io_ctl io_ctl;
369 union mio_emm_debug emm_debug;
370 union mio_emm_sts_mask emm_sts_mask;
371 union mio_emm_rca emm_rca;
374 static const char * const bus_width_str[] = {
375 "1-bit data bus (power on)",
380 "4-bit data bus (dual data rate)",
381 "8-bit data bus (dual data rate)",
392 static const char * const ctype_xor_str[] = {
394 "Read data into Dbuf",
395 "Write data from Dbuf",
399 static const char * const rtype_xor_str[] = {
411 host = mmc_to_host(mmc);
414 printf("%s: bus id: %u\n", __func__, slot->bus_id);
415 emm_dma_cfg.u = readq(host->base_addr + MIO_EMM_DMA_CFG());
416 printf("MIO_EMM_DMA_CFG: 0x%016llx\n",
418 printf(" 63: en: %s\n",
419 emm_dma_cfg.s.en ? "enabled" : "disabled");
420 printf(" 62: rw: %s\n",
421 emm_dma_cfg.s.rw ? "write" : "read");
422 printf(" 61: clr: %s\n",
423 emm_dma_cfg.s.clr ? "clear" : "not clear");
424 printf(" 59: swap32: %s\n",
425 emm_dma_cfg.s.swap32 ? "yes" : "no");
426 printf(" 58: swap16: %s\n",
427 emm_dma_cfg.s.swap16 ? "yes" : "no");
428 printf(" 57: swap8: %s\n",
429 emm_dma_cfg.s.swap8 ? "yes" : "no");
430 printf(" 56: endian: %s\n",
431 emm_dma_cfg.s.endian ? "little" : "big");
432 printf(" 36-55: size: %u\n",
435 emm_dma_adr.u = readq(host->base_addr + MIO_EMM_DMA_ADR());
436 printf("MIO_EMM_DMA_ADR: 0x%016llx\n", emm_dma_adr.u);
437 printf(" 0-49: adr: 0x%llx\n",
438 (u64)emm_dma_adr.s.adr);
440 emm_dma_int.u = readq(host->base_addr + MIO_EMM_DMA_INT());
441 printf("\nMIO_EMM_DMA_INT: 0x%016llx\n",
443 printf(" 1: FIFO: %s\n",
444 emm_dma_int.s.fifo ? "yes" : "no");
445 printf(" 0: Done: %s\n",
446 emm_dma_int.s.done ? "yes" : "no");
447 emm_cfg.u = readq(host->base_addr + MIO_EMM_CFG());
449 printf("\nMIO_EMM_CFG: 0x%016llx\n",
451 printf(" 3: bus_ena3: %s\n",
452 emm_cfg.s.bus_ena & 0x08 ? "yes" : "no");
453 printf(" 2: bus_ena2: %s\n",
454 emm_cfg.s.bus_ena & 0x04 ? "yes" : "no");
455 printf(" 1: bus_ena1: %s\n",
456 emm_cfg.s.bus_ena & 0x02 ? "yes" : "no");
457 printf(" 0: bus_ena0: %s\n",
458 emm_cfg.s.bus_ena & 0x01 ? "yes" : "no");
459 for (bus = 0; bus < 4; bus++) {
460 emm_mode.u = readq(host->base_addr + MIO_EMM_MODEX(bus));
461 printf("\nMIO_EMM_MODE%u: 0x%016llx\n",
463 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
464 printf(" 50: hs400_timing: %s\n",
465 emm_mode.s.hs400_timing ? "yes" : "no");
466 printf(" 49: hs200_timing: %s\n",
467 emm_mode.s.hs200_timing ? "yes" : "no");
469 printf(" 48: hs_timing: %s\n",
470 emm_mode.s.hs_timing ? "yes" : "no");
471 printf(" 40-42: bus_width: %s\n",
472 bus_width_str[emm_mode.s.bus_width]);
473 printf(" 32-35: power_class %u\n",
474 emm_mode.s.power_class);
475 printf(" 16-31: clk_hi: %u\n",
477 printf(" 0-15: clk_lo: %u\n",
481 emm_switch.u = readq(host->base_addr + MIO_EMM_SWITCH());
482 printf("\nMIO_EMM_SWITCH: 0x%016llx\n", emm_switch.u);
483 printf(" 60-61: bus_id: %u\n", emm_switch.s.bus_id);
484 printf(" 59: switch_exe: %s\n",
485 emm_switch.s.switch_exe ? "yes" : "no");
486 printf(" 58: switch_err0: %s\n",
487 emm_switch.s.switch_err0 ? "yes" : "no");
488 printf(" 57: switch_err1: %s\n",
489 emm_switch.s.switch_err1 ? "yes" : "no");
490 printf(" 56: switch_err2: %s\n",
491 emm_switch.s.switch_err2 ? "yes" : "no");
492 printf(" 48: hs_timing: %s\n",
493 emm_switch.s.hs_timing ? "yes" : "no");
494 printf(" 42-40: bus_width: %s\n",
495 bus_width_str[emm_switch.s.bus_width]);
496 printf(" 32-35: power_class: %u\n",
497 emm_switch.s.power_class);
498 printf(" 16-31: clk_hi: %u\n",
499 emm_switch.s.clk_hi);
500 printf(" 0-15: clk_lo: %u\n", emm_switch.s.clk_lo);
502 emm_dma.u = readq(host->base_addr + MIO_EMM_DMA());
503 printf("\nMIO_EMM_DMA: 0x%016llx\n", emm_dma.u);
504 printf(" 60-61: bus_id: %u\n", emm_dma.s.bus_id);
505 printf(" 59: dma_val: %s\n",
506 emm_dma.s.dma_val ? "yes" : "no");
507 printf(" 58: sector: %s mode\n",
508 emm_dma.s.sector ? "sector" : "byte");
509 printf(" 57: dat_null: %s\n",
510 emm_dma.s.dat_null ? "yes" : "no");
511 printf(" 51-56: thres: %u\n", emm_dma.s.thres);
512 printf(" 50: rel_wr: %s\n",
513 emm_dma.s.rel_wr ? "yes" : "no");
514 printf(" 49: rw: %s\n",
515 emm_dma.s.rw ? "write" : "read");
516 printf(" 48: multi: %s\n",
517 emm_dma.s.multi ? "yes" : "no");
518 printf(" 32-47: block_cnt: %u\n",
519 emm_dma.s.block_cnt);
520 printf(" 0-31: card_addr: 0x%x\n",
521 emm_dma.s.card_addr);
523 emm_cmd.u = readq(host->base_addr + MIO_EMM_CMD());
524 printf("\nMIO_EMM_CMD: 0x%016llx\n", emm_cmd.u);
525 printf("\n 62: skip_busy: %s\n",
526 emm_cmd.s.skip_busy ? "yes" : "no");
527 printf(" 60-61: bus_id: %u\n", emm_cmd.s.bus_id);
528 printf(" 59: cmd_val: %s\n",
529 emm_cmd.s.cmd_val ? "yes" : "no");
530 printf(" 55: dbuf: %u\n", emm_cmd.s.dbuf);
531 printf(" 49-54: offset: %u\n", emm_cmd.s.offset);
532 printf(" 41-42: ctype_xor: %s\n",
533 ctype_xor_str[emm_cmd.s.ctype_xor]);
534 printf(" 38-40: rtype_xor: %s\n",
535 rtype_xor_str[emm_cmd.s.rtype_xor]);
536 printf(" 32-37: cmd_idx: %u\n", emm_cmd.s.cmd_idx);
537 printf(" 0-31: arg: 0x%x\n", emm_cmd.s.arg);
539 emm_rsp_sts.u = readq(host->base_addr + MIO_EMM_RSP_STS());
540 printf("\nMIO_EMM_RSP_STS: 0x%016llx\n", emm_rsp_sts.u);
541 printf(" 60-61: bus_id: %u\n", emm_rsp_sts.s.bus_id);
542 printf(" 59: cmd_val: %s\n",
543 emm_rsp_sts.s.cmd_val ? "yes" : "no");
544 printf(" 58: switch_val: %s\n",
545 emm_rsp_sts.s.switch_val ? "yes" : "no");
546 printf(" 57: dma_val: %s\n",
547 emm_rsp_sts.s.dma_val ? "yes" : "no");
548 printf(" 56: dma_pend: %s\n",
549 emm_rsp_sts.s.dma_pend ? "yes" : "no");
550 printf(" 28: dbuf_err: %s\n",
551 emm_rsp_sts.s.dbuf_err ? "yes" : "no");
552 printf(" 23: dbuf: %u\n", emm_rsp_sts.s.dbuf);
553 printf(" 22: blk_timeout: %s\n",
554 emm_rsp_sts.s.blk_timeout ? "yes" : "no");
555 printf(" 21: blk_crc_err: %s\n",
556 emm_rsp_sts.s.blk_crc_err ? "yes" : "no");
557 printf(" 20: rsp_busybit: %s\n",
558 emm_rsp_sts.s.rsp_busybit ? "yes" : "no");
559 printf(" 19: stp_timeout: %s\n",
560 emm_rsp_sts.s.stp_timeout ? "yes" : "no");
561 printf(" 18: stp_crc_err: %s\n",
562 emm_rsp_sts.s.stp_crc_err ? "yes" : "no");
563 printf(" 17: stp_bad_sts: %s\n",
564 emm_rsp_sts.s.stp_bad_sts ? "yes" : "no");
565 printf(" 16: stp_val: %s\n",
566 emm_rsp_sts.s.stp_val ? "yes" : "no");
567 printf(" 15: rsp_timeout: %s\n",
568 emm_rsp_sts.s.rsp_timeout ? "yes" : "no");
569 printf(" 14: rsp_crc_err: %s\n",
570 emm_rsp_sts.s.rsp_crc_err ? "yes" : "no");
571 printf(" 13: rsp_bad_sts: %s\n",
572 emm_rsp_sts.s.rsp_bad_sts ? "yes" : "no");
573 printf(" 12: rsp_val: %s\n",
574 emm_rsp_sts.s.rsp_val ? "yes" : "no");
575 printf(" 9-11: rsp_type: %s\n",
576 rtype_xor_str[emm_rsp_sts.s.rsp_type]);
577 printf(" 7-8: cmd_type: %s\n",
578 ctype_xor_str[emm_rsp_sts.s.cmd_type]);
579 printf(" 1-6: cmd_idx: %u\n",
580 emm_rsp_sts.s.cmd_idx);
581 printf(" 0: cmd_done: %s\n",
582 emm_rsp_sts.s.cmd_done ? "yes" : "no");
584 emm_rsp_lo.u = readq(host->base_addr + MIO_EMM_RSP_LO());
585 printf("\nMIO_EMM_RSP_STS_LO: 0x%016llx\n", emm_rsp_lo.u);
587 emm_rsp_hi.u = readq(host->base_addr + MIO_EMM_RSP_HI());
588 printf("\nMIO_EMM_RSP_STS_HI: 0x%016llx\n", emm_rsp_hi.u);
590 emm_int.u = readq(host->base_addr + MIO_EMM_INT());
591 printf("\nMIO_EMM_INT: 0x%016llx\n", emm_int.u);
592 printf(" 6: switch_err: %s\n",
593 emm_int.s.switch_err ? "yes" : "no");
594 printf(" 5: switch_done: %s\n",
595 emm_int.s.switch_done ? "yes" : "no");
596 printf(" 4: dma_err: %s\n",
597 emm_int.s.dma_err ? "yes" : "no");
598 printf(" 3: cmd_err: %s\n",
599 emm_int.s.cmd_err ? "yes" : "no");
600 printf(" 2: dma_done: %s\n",
601 emm_int.s.dma_done ? "yes" : "no");
602 printf(" 1: cmd_done: %s\n",
603 emm_int.s.cmd_done ? "yes" : "no");
604 printf(" 0: buf_done: %s\n",
605 emm_int.s.buf_done ? "yes" : "no");
607 emm_wdog.u = readq(host->base_addr + MIO_EMM_WDOG());
608 printf("\nMIO_EMM_WDOG: 0x%016llx (%u)\n",
609 emm_wdog.u, emm_wdog.s.clk_cnt);
611 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
612 emm_sample.u = readq(host->base_addr + MIO_EMM_SAMPLE());
613 printf("\nMIO_EMM_SAMPLE: 0x%016llx\n",
615 printf(" 16-25: cmd_cnt: %u\n",
616 emm_sample.s.cmd_cnt);
617 printf(" 0-9: dat_cnt: %u\n",
618 emm_sample.s.dat_cnt);
621 emm_sts_mask.u = readq(host->base_addr + MIO_EMM_STS_MASK());
622 printf("\nMIO_EMM_STS_MASK: 0x%016llx\n", emm_sts_mask.u);
624 emm_rca.u = readq(host->base_addr + MIO_EMM_RCA());
625 printf("\nMIO_EMM_RCA: 0x%016llx\n", emm_rca.u);
626 printf(" 0-15: card_rca: 0x%04x\n",
628 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
629 emm_calb.u = readq(host->base_addr + MIO_EMM_CALB());
630 printf("\nMIO_EMM_CALB: 0x%016llx\n",
632 printf(" 0: start: %u\n",
634 emm_tap.u = readq(host->base_addr + MIO_EMM_TAP());
635 printf("\nMIO_EMM_TAP: 0x%016llx\n",
637 printf(" 7-0: delay: %u\n", emm_tap.s.delay);
638 emm_timing.u = readq(host->base_addr + MIO_EMM_TIMING());
639 printf("\nMIO_EMM_TIMING: 0x%016llx\n",
641 printf(" 53-48: cmd_in_tap: %u\n",
642 emm_timing.s.cmd_in_tap);
643 printf(" 37-32: cmd_out_tap: %u\n",
644 emm_timing.s.cmd_out_tap);
645 printf(" 21-16: data_in_tap: %u\n",
646 emm_timing.s.data_in_tap);
647 printf(" 5-0: data_out_tap: %u\n",
648 emm_timing.s.data_out_tap);
649 io_ctl.u = readq(host->base_addr + MIO_EMM_IO_CTL());
650 printf("\nMIO_IO_CTL: 0x%016llx\n", io_ctl.u);
651 printf(" 3-2: drive: %u (%u mA)\n",
652 io_ctl.s.drive, 2 << io_ctl.s.drive);
653 printf(" 0: slew: %u %s\n", io_ctl.s.slew,
654 io_ctl.s.slew ? "high" : "low");
655 emm_debug.u = readq(host->base_addr + MIO_EMM_DEBUG());
656 printf("\nMIO_EMM_DEBUG: 0x%016llx\n",
658 printf(" 21: rdsync_rst 0x%x\n",
659 emm_debug.s.rdsync_rst);
660 printf(" 20: emmc_clk_disable 0x%x\n",
661 emm_debug.s.emmc_clk_disable);
662 printf(" 19-16: dma_sm: 0x%x\n",
664 printf(" 15-12: data_sm: 0x%x\n",
665 emm_debug.s.data_sm);
666 printf(" 11-8: cmd_sm: 0x%x\n",
668 printf(" 0: clk_on: 0x%x\n",
676 * Print out all of the register values
678 * @param mmc MMC device
680 static void octeontx_mmc_print_registers(struct mmc *mmc)
682 #ifdef DEBUG_REGISTERS
688 octeontx_mmc_print_registers2(mmc, mmc_to_host(mmc));
691 static const struct octeontx_sd_mods octeontx_cr_types[] = {
692 { {0, 0}, {0, 0}, {0, 0} }, /* CMD0 */
693 { {0, 3}, {0, 3}, {0, 0} }, /* CMD1 */
694 { {0, 2}, {0, 2}, {0, 0} }, /* CMD2 */
695 { {0, 1}, {0, 3}, {0, 0} }, /* CMD3 SD_CMD_SEND_RELATIVE_ADDR 0, 2 */
696 { {0, 0}, {0, 0}, {0, 0} }, /* CMD4 */
697 { {0, 1}, {0, 1}, {0, 0} }, /* CMD5 */
698 { {0, 1}, {1, 1}, {0, 1} }, /*
699 * CMD6 SD_CMD_SWITCH_FUNC 1,0
700 * (ACMD) SD_APP_SET_BUS_WIDTH
702 { {0, 1}, {0, 1}, {0, 0} }, /* CMD7 */
703 { {1, 1}, {0, 3}, {0, 0} }, /* CMD8 SD_CMD_SEND_IF_COND 1,2 */
704 { {0, 2}, {0, 2}, {0, 0} }, /* CMD9 */
705 { {0, 2}, {0, 2}, {0, 0} }, /* CMD10 */
706 { {1, 1}, {0, 1}, {1, 1} }, /* CMD11 SD_CMD_SWITCH_UHS18V 1,0 */
707 { {0, 1}, {0, 1}, {0, 0} }, /* CMD12 */
708 { {0, 1}, {0, 1}, {1, 3} }, /* CMD13 (ACMD)) SD_CMD_APP_SD_STATUS 1,2 */
709 { {1, 1}, {1, 1}, {0, 0} }, /* CMD14 */
710 { {0, 0}, {0, 0}, {0, 0} }, /* CMD15 */
711 { {0, 1}, {0, 1}, {0, 0} }, /* CMD16 */
712 { {1, 1}, {1, 1}, {0, 0} }, /* CMD17 */
713 { {1, 1}, {1, 1}, {0, 0} }, /* CMD18 */
714 { {3, 1}, {3, 1}, {0, 0} }, /* CMD19 */
715 { {2, 1}, {0, 0}, {0, 0} }, /* CMD20 */ /* SD 2,0 */
716 { {0, 0}, {0, 0}, {0, 0} }, /* CMD21 */
717 { {0, 0}, {0, 0}, {1, 1} }, /* CMD22 (ACMD) SD_APP_SEND_NUM_WR_BLKS 1,0 */
718 { {0, 1}, {0, 1}, {0, 1} }, /* CMD23 */ /* SD ACMD 1,0 */
719 { {2, 1}, {2, 1}, {2, 1} }, /* CMD24 */
720 { {2, 1}, {2, 1}, {2, 1} }, /* CMD25 */
721 { {2, 1}, {2, 1}, {2, 1} }, /* CMD26 */
722 { {2, 1}, {2, 1}, {2, 1} }, /* CMD27 */
723 { {0, 1}, {0, 1}, {0, 1} }, /* CMD28 */
724 { {0, 1}, {0, 1}, {0, 1} }, /* CMD29 */
725 { {1, 1}, {1, 1}, {1, 1} }, /* CMD30 */
726 { {1, 1}, {1, 1}, {1, 1} }, /* CMD31 */
727 { {0, 0}, {0, 1}, {0, 0} }, /* CMD32 SD_CMD_ERASE_WR_BLK_START 0,1 */
728 { {0, 0}, {0, 1}, {0, 0} }, /* CMD33 SD_CMD_ERASE_WR_BLK_END 0,1 */
729 { {0, 0}, {0, 0}, {0, 0} }, /* CMD34 */
730 { {0, 1}, {0, 1}, {0, 1} }, /* CMD35 */
731 { {0, 1}, {0, 1}, {0, 1} }, /* CMD36 */
732 { {0, 0}, {0, 0}, {0, 0} }, /* CMD37 */
733 { {0, 1}, {0, 1}, {0, 1} }, /* CMD38 */
734 { {0, 4}, {0, 4}, {0, 4} }, /* CMD39 */
735 { {0, 5}, {0, 5}, {0, 5} }, /* CMD40 */
736 { {0, 0}, {0, 0}, {0, 3} }, /* CMD41 (ACMD) SD_CMD_APP_SEND_OP_COND 0,3 */
737 { {2, 1}, {2, 1}, {2, 1} }, /* CMD42 */
738 { {0, 0}, {0, 0}, {0, 0} }, /* CMD43 */
739 { {0, 0}, {0, 0}, {0, 0} }, /* CMD44 */
740 { {0, 0}, {0, 0}, {0, 0} }, /* CMD45 */
741 { {0, 0}, {0, 0}, {0, 0} }, /* CMD46 */
742 { {0, 0}, {0, 0}, {0, 0} }, /* CMD47 */
743 { {0, 0}, {1, 0}, {0, 0} }, /* CMD48 SD_CMD_READ_EXTR_SINGLE */
744 { {0, 0}, {2, 0}, {0, 0} }, /* CMD49 SD_CMD_WRITE_EXTR_SINGLE */
745 { {0, 0}, {0, 0}, {0, 0} }, /* CMD50 */
746 { {0, 0}, {0, 0}, {1, 1} }, /* CMD51 (ACMD) SD_CMD_APP_SEND_SCR 1,1 */
747 { {0, 0}, {0, 0}, {0, 0} }, /* CMD52 */
748 { {0, 0}, {0, 0}, {0, 0} }, /* CMD53 */
749 { {0, 0}, {0, 0}, {0, 0} }, /* CMD54 */
750 { {0, 1}, {0, 1}, {0, 1} }, /* CMD55 */
751 { {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff} }, /* CMD56 */
752 { {0, 0}, {0, 0}, {0, 0} }, /* CMD57 */
753 { {0, 0}, {0, 3}, {0, 3} }, /* CMD58 SD_CMD_SPI_READ_OCR 0,3 */
754 { {0, 0}, {0, 1}, {0, 0} }, /* CMD59 SD_CMD_SPI_CRC_ON_OFF 0,1 */
755 { {0, 0}, {0, 0}, {0, 0} }, /* CMD60 */
756 { {0, 0}, {0, 0}, {0, 0} }, /* CMD61 */
757 { {0, 0}, {0, 0}, {0, 0} }, /* CMD62 */
758 { {0, 0}, {0, 0}, {0, 0} } /* CMD63 */
762 * Returns XOR values needed for SD commands and other quirks
764 * @param mmc mmc device
765 * @param cmd command information
767 * @return octeontx_mmc_cr_mods data structure with various quirks and flags
769 static struct octeontx_mmc_cr_mods
770 octeontx_mmc_get_cr_mods(struct mmc *mmc, const struct mmc_cmd *cmd,
771 const struct mmc_data *data)
773 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
774 struct octeontx_mmc_cr_mods cr = {0, 0};
775 const struct octeontx_sd_mods *sdm =
776 &octeontx_cr_types[cmd->cmdidx & 0x3f];
777 u8 c = sdm->mmc.c, r = sdm->mmc.r;
778 u8 desired_ctype = 0;
781 #ifdef MMC_SUPPORTS_TUNING
782 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
783 if (cmd->resp_type == MMC_RSP_R1)
785 if (data && data->flags & MMC_DATA_READ)
792 if (cmd->cmdidx == 56)
793 c = (cmd->cmdarg & 1) ? 1 : 2;
796 if (data->flags & MMC_DATA_READ)
798 else if (data->flags & MMC_DATA_WRITE)
802 cr.ctype_xor = c ^ desired_ctype;
804 cr.rtype_xor = r ^ sdm->sdacmd.r;
806 cr.rtype_xor = r ^ sdm->sd.r;
808 debug("%s(%s): mmc c: %d, mmc r: %d, desired c: %d, xor c: %d, xor r: %d\n",
809 __func__, mmc->dev->name, c, r, desired_ctype,
810 cr.ctype_xor, cr.rtype_xor);
815 * Keep track of switch commands internally
817 static void octeontx_mmc_track_switch(struct mmc *mmc, u32 cmd_arg)
819 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
820 u8 how = (cmd_arg >> 24) & 3;
821 u8 where = (u8)(cmd_arg >> 16);
822 u8 val = (u8)(cmd_arg >> 8);
824 slot->want_switch = slot->cached_switch;
833 case EXT_CSD_BUS_WIDTH:
834 slot->want_switch.s.bus_width = val;
836 case EXT_CSD_POWER_CLASS:
837 slot->want_switch.s.power_class = val;
839 case EXT_CSD_HS_TIMING:
840 slot->want_switch.s.hs_timing = 0;
841 slot->want_switch.s.hs200_timing = 0;
842 slot->want_switch.s.hs400_timing = 0;
847 slot->want_switch.s.hs_timing = 1;
850 if (!slot->is_asim && !slot->is_emul)
851 slot->want_switch.s.hs200_timing = 1;
854 if (!slot->is_asim && !slot->is_emul)
855 slot->want_switch.s.hs400_timing = 1;
858 pr_err("%s(%s): Unsupported timing mode 0x%x\n",
859 __func__, mmc->dev->name, val & 0xf);
868 static int octeontx_mmc_print_rsp_errors(struct mmc *mmc,
869 union mio_emm_rsp_sts rsp_sts)
872 const char *name = mmc->dev->name;
874 if (rsp_sts.s.acc_timeout) {
875 pr_warn("%s(%s): acc_timeout\n", __func__, name);
878 if (rsp_sts.s.dbuf_err) {
879 pr_warn("%s(%s): dbuf_err\n", __func__, name);
882 if (rsp_sts.s.blk_timeout) {
883 pr_warn("%s(%s): blk_timeout\n", __func__, name);
886 if (rsp_sts.s.blk_crc_err) {
887 pr_warn("%s(%s): blk_crc_err\n", __func__, name);
890 if (rsp_sts.s.stp_timeout) {
891 pr_warn("%s(%s): stp_timeout\n", __func__, name);
894 if (rsp_sts.s.stp_crc_err) {
895 pr_warn("%s(%s): stp_crc_err\n", __func__, name);
898 if (rsp_sts.s.stp_bad_sts) {
899 pr_warn("%s(%s): stp_bad_sts\n", __func__, name);
903 pr_warn(" rsp_sts: 0x%llx\n", rsp_sts.u);
909 * Starts a DMA operation for block read/write
911 * @param mmc mmc device
912 * @param write true if write operation
913 * @param clear true to clear DMA operation
914 * @param adr source or destination DMA address
915 * @param size size in blocks
916 * @param timeout timeout in ms
918 static void octeontx_mmc_start_dma(struct mmc *mmc, bool write,
919 bool clear, u32 block, dma_addr_t adr,
920 u32 size, int timeout)
922 const struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
923 union mio_emm_dma_cfg emm_dma_cfg;
924 union mio_emm_dma_adr emm_dma_adr;
925 union mio_emm_dma emm_dma;
927 /* Clear any interrupts */
928 write_csr(mmc, MIO_EMM_DMA_INT(),
929 read_csr(mmc, MIO_EMM_DMA_INT()));
932 emm_dma_cfg.s.en = 1;
933 emm_dma_cfg.s.rw = !!write;
934 emm_dma_cfg.s.clr = !!clear;
935 emm_dma_cfg.s.size = ((u64)(size * mmc->read_bl_len) / 8) - 1;
936 #if __BYTE_ORDER != __BIG_ENDIAN
937 emm_dma_cfg.s.endian = 1;
940 emm_dma_adr.s.adr = adr;
941 write_csr(mmc, MIO_EMM_DMA_ADR(), emm_dma_adr.u);
942 write_csr(mmc, MIO_EMM_DMA_CFG(), emm_dma_cfg.u);
945 emm_dma.s.bus_id = slot->bus_id;
946 emm_dma.s.dma_val = 1;
947 emm_dma.s.rw = !!write;
948 emm_dma.s.sector = mmc->high_capacity ? 1 : 0;
950 if (size > 1 && ((IS_SD(mmc) && (mmc->scr[0] & 2)) || !IS_SD(mmc)))
955 emm_dma.s.block_cnt = size;
956 if (!mmc->high_capacity)
957 block *= mmc->read_bl_len;
958 emm_dma.s.card_addr = block;
959 debug("%s(%s): card address: 0x%x, size: %d, multi: %d\n",
960 __func__, mmc->dev->name, block, size, emm_dma.s.multi);
963 timeout = (timeout * 1000) - 1000;
964 set_wdog(mmc, timeout);
966 debug(" Writing 0x%llx to mio_emm_dma\n", emm_dma.u);
967 write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
971 * Waits for a DMA operation to complete
973 * @param mmc mmc device
974 * @param timeout timeout in ms
976 * @return 0 for success (could be DMA errors), -ETIMEDOUT on timeout
980 * Cleanup DMA engine after a failure
982 * @param mmc mmc device
983 * @param rsp_sts rsp status
985 static void octeontx_mmc_cleanup_dma(struct mmc *mmc,
986 union mio_emm_rsp_sts rsp_sts)
988 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
989 union mio_emm_dma emm_dma;
994 debug("%s(%s): rsp_sts: 0x%llx, rsp_lo: 0x%llx, dma_int: 0x%llx\n",
995 __func__, mmc->dev->name, rsp_sts.u,
996 read_csr(mmc, MIO_EMM_RSP_LO()),
997 read_csr(mmc, MIO_EMM_DMA_INT()));
998 emm_dma.u = read_csr(mmc, MIO_EMM_DMA());
999 emm_dma.s.dma_val = 1;
1000 emm_dma.s.dat_null = 1;
1001 emm_dma.s.bus_id = slot->bus_id;
1002 write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
1003 start = get_timer(0);
1005 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1007 } while (get_timer(start) < 100 &&
1008 (rsp_sts.s.dma_val || rsp_sts.s.dma_pend));
1009 } while (retries-- >= 0 && rsp_sts.s.dma_pend);
1010 if (rsp_sts.s.dma_val)
1011 pr_err("%s(%s): Error: could not clean up DMA. RSP_STS: 0x%llx, RSP_LO: 0x%llx\n",
1012 __func__, mmc->dev->name, rsp_sts.u,
1013 read_csr(mmc, MIO_EMM_RSP_LO()));
1014 debug(" rsp_sts after clearing up DMA: 0x%llx\n",
1015 read_csr(mmc, MIO_EMM_RSP_STS()));
1019 * Waits for a DMA operation to complete
1021 * @param mmc mmc device
1022 * @param timeout timeout in ms
1023 * @param verbose true to print out error information
1025 * @return 0 for success (could be DMA errors), -ETIMEDOUT on timeout
1026 * or -EIO if IO error.
1028 static int octeontx_mmc_wait_dma(struct mmc *mmc, bool write, ulong timeout,
1031 struct octeontx_mmc_host *host = mmc_to_host(mmc);
1032 ulong start_time = get_timer(0);
1033 union mio_emm_dma_int emm_dma_int;
1034 union mio_emm_rsp_sts rsp_sts;
1035 union mio_emm_dma emm_dma;
1036 bool timed_out = false;
1039 debug("%s(%s, %lu, %d), delay: %uus\n", __func__, mmc->dev->name,
1040 timeout, verbose, host->dma_wait_delay);
1042 udelay(host->dma_wait_delay);
1044 emm_dma_int.u = read_csr(mmc, MIO_EMM_DMA_INT());
1045 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1047 if ((rsp_sts.s.dma_pend && !rsp_sts.s.dma_val) ||
1048 rsp_sts.s.blk_timeout ||
1049 rsp_sts.s.stp_timeout ||
1050 rsp_sts.s.rsp_timeout) {
1053 debug("%s: f1\n", __func__);
1054 octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
1059 if (rsp_sts.s.blk_crc_err ||
1060 (rsp_sts.s.dma_pend && !rsp_sts.s.dma_val)) {
1063 octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
1068 if (rsp_sts.s.dma_pend) {
1070 * If this is set then an error has occurred.
1071 * Try and restart the DMA operation.
1073 emm_dma.u = read_csr(mmc, MIO_EMM_DMA());
1075 pr_err("%s(%s): DMA pending error: rsp_sts: 0x%llx, dma_int: 0x%llx, emm_dma: 0x%llx\n",
1076 __func__, mmc->dev->name, rsp_sts.u,
1077 emm_dma_int.u, emm_dma.u);
1078 octeontx_print_rsp_sts(mmc);
1079 debug(" MIO_EMM_DEBUG: 0x%llx\n",
1080 read_csr(mmc, MIO_EMM_DEBUG()));
1081 pr_err("%s: Trying DMA resume...\n", __func__);
1083 emm_dma.s.dma_val = 1;
1084 emm_dma.s.dat_null = 1;
1085 write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
1087 } else if (!rsp_sts.s.dma_val && emm_dma_int.s.done) {
1091 timed_out = (get_timer(start_time) > timeout);
1092 } while (!timed_out);
1094 if (timed_out || err) {
1096 pr_err("%s(%s): MMC DMA %s after %lu ms, rsp_sts: 0x%llx, dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
1097 __func__, mmc->dev->name,
1098 timed_out ? "timed out" : "error",
1099 get_timer(start_time), rsp_sts.u,
1101 read_csr(mmc, MIO_EMM_RSP_LO()),
1102 read_csr(mmc, MIO_EMM_DMA()));
1103 octeontx_print_rsp_sts(mmc);
1105 if (rsp_sts.s.dma_pend)
1106 octeontx_mmc_cleanup_dma(mmc, rsp_sts);
1108 write_csr(mmc, MIO_EMM_DMA_INT(),
1109 read_csr(mmc, MIO_EMM_DMA_INT()));
1112 return timed_out ? -ETIMEDOUT : (err ? -EIO : 0);
1116 * Read blocks from the MMC/SD device
1118 * @param mmc mmc device
1119 * @param cmd command
1120 * @param data data for read
1121 * @param verbose true to print out error information
1123 * @return number of blocks read or 0 if error
1125 static int octeontx_mmc_read_blocks(struct mmc *mmc, struct mmc_cmd *cmd,
1126 struct mmc_data *data, bool verbose)
1128 struct octeontx_mmc_host *host = mmc_to_host(mmc);
1129 union mio_emm_rsp_sts rsp_sts;
1130 dma_addr_t dma_addr = (dma_addr_t)dm_pci_virt_to_mem(host->dev,
1133 ulong blkcnt = data->blocks;
1134 ulong start = cmd->cmdarg;
1135 int timeout = 1000 + blkcnt * 20;
1136 bool timed_out = false;
1137 bool multi_xfer = cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK;
1139 debug("%s(%s): dest: %p, dma address: 0x%llx, blkcnt: %lu, start: %lu\n",
1140 __func__, mmc->dev->name, data->dest, dma_addr, blkcnt, start);
1141 debug("%s: rsp_sts: 0x%llx\n", __func__,
1142 read_csr(mmc, MIO_EMM_RSP_STS()));
1143 /* use max timeout for multi-block transfers */
1147 * If we have a valid SD card in the slot, we set the response bit
1148 * mask to check for CRC errors and timeouts only.
1149 * Otherwise, use the default power on reset value.
1151 write_csr(mmc, MIO_EMM_STS_MASK(),
1152 IS_SD(mmc) ? 0x00b00000ull : 0xe4390080ull);
1153 invalidate_dcache_range((u64)data->dest,
1154 (u64)data->dest + blkcnt * data->blocksize);
1157 octeontx_mmc_start_dma(mmc, false, false, start, dma_addr,
1159 timed_out = !!octeontx_mmc_wait_dma(mmc, false, timeout,
1161 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1162 if (timed_out || rsp_sts.s.dma_val || rsp_sts.s.dma_pend) {
1166 pr_err("%s(%s): Error: DMA timed out. rsp_sts: 0x%llx, emm_int: 0x%llx, dma_int: 0x%llx, rsp_lo: 0x%llx\n",
1167 __func__, mmc->dev->name, rsp_sts.u,
1168 read_csr(mmc, MIO_EMM_INT()),
1169 read_csr(mmc, MIO_EMM_DMA_INT()),
1170 read_csr(mmc, MIO_EMM_RSP_LO()));
1171 pr_err("%s: block count: %lu, start: 0x%lx\n",
1172 __func__, blkcnt, start);
1173 octeontx_mmc_print_registers(mmc);
1180 octeontx_mmc_start_dma(mmc, false, false, start,
1181 dma_addr, 1, timeout);
1182 dma_addr += mmc->read_bl_len;
1185 timed_out = !!octeontx_mmc_wait_dma(mmc, false,
1187 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1188 if (timed_out || rsp_sts.s.dma_val ||
1189 rsp_sts.s.dma_pend) {
1191 pr_err("%s: Error: DMA timed out. rsp_sts: 0x%llx, emm_int: 0x%llx, dma_int: 0x%llx, rsp_lo: 0x%llx\n",
1192 __func__, rsp_sts.u,
1193 read_csr(mmc, MIO_EMM_INT()),
1194 read_csr(mmc, MIO_EMM_DMA_INT()),
1195 read_csr(mmc, MIO_EMM_RSP_LO()));
1196 pr_err("%s: block count: 1, start: 0x%lx\n",
1198 octeontx_mmc_print_registers(mmc);
1200 return blkcnt - count;
1206 debug("%s(%s): Read %lu (0x%lx) blocks starting at block %u (0x%x) to address %p (dma address 0x%llx)\n",
1207 __func__, mmc->dev->name, blkcnt, blkcnt,
1208 cmd->cmdarg, cmd->cmdarg, data->dest,
1209 dm_pci_virt_to_mem(host->dev, data->dest));
1210 print_buffer(0, data->dest, 1, 0x200, 0);
1215 static int octeontx_mmc_poll_ready(struct mmc *mmc, ulong timeout)
1220 bool not_ready = false;
1222 memset(&cmd, 0, sizeof(cmd));
1223 cmd.cmdidx = MMC_CMD_SEND_STATUS;
1224 cmd.cmdarg = mmc->rca << 16;
1225 cmd.resp_type = MMC_RSP_R1;
1226 start = get_timer(0);
1228 err = octeontx_mmc_send_cmd(mmc, &cmd, NULL);
1230 pr_err("%s(%s): MMC command error: %d; Retry...\n",
1231 __func__, mmc->dev->name, err);
1233 } else if (cmd.response[0] & R1_READY_FOR_DATA) {
1237 } while (get_timer(start) < timeout);
1240 pr_err("%s(%s): MMC command error; Retry timeout\n",
1241 __func__, mmc->dev->name);
1245 static ulong octeontx_mmc_write_blocks(struct mmc *mmc, struct mmc_cmd *cmd,
1246 struct mmc_data *data)
1248 struct octeontx_mmc_host *host = mmc_to_host(mmc);
1249 ulong start = cmd->cmdarg;
1250 ulong blkcnt = data->blocks;
1251 dma_addr_t dma_addr;
1252 union mio_emm_rsp_sts rsp_sts;
1253 union mio_emm_sts_mask emm_sts_mask;
1256 bool timed_out = false;
1257 bool multi_xfer = (blkcnt > 1) &&
1258 ((IS_SD(mmc) && mmc->scr[0] & 2) || !IS_SD(mmc));
1260 octeontx_mmc_switch_to(mmc);
1262 emm_sts_mask.s.sts_msk = R1_BLOCK_WRITE_MASK;
1263 write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
1265 if (octeontx_mmc_poll_ready(mmc, 10000)) {
1266 pr_err("%s(%s): Ready timed out\n", __func__, mmc->dev->name);
1269 flush_dcache_range((u64)data->src,
1270 (u64)data->src + blkcnt * mmc->write_bl_len);
1271 dma_addr = (u64)dm_pci_virt_to_mem(host->dev, (void *)data->src);
1273 timeout = 5000 + 100 * blkcnt;
1274 octeontx_mmc_start_dma(mmc, true, false, start, dma_addr,
1276 timed_out = !!octeontx_mmc_wait_dma(mmc, true, timeout, true);
1277 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1278 if (timed_out || rsp_sts.s.dma_val || rsp_sts.s.dma_pend) {
1279 pr_err("%s(%s): Error: multi-DMA timed out after %lums. rsp_sts: 0x%llx, emm_int: 0x%llx, emm_dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
1280 __func__, mmc->dev->name, timeout,
1282 read_csr(mmc, MIO_EMM_INT()),
1283 read_csr(mmc, MIO_EMM_DMA_INT()),
1284 read_csr(mmc, MIO_EMM_RSP_LO()),
1285 read_csr(mmc, MIO_EMM_DMA()));
1292 octeontx_mmc_start_dma(mmc, true, false, start,
1293 dma_addr, 1, timeout);
1294 dma_addr += mmc->read_bl_len;
1297 timed_out = !!octeontx_mmc_wait_dma(mmc, true, timeout,
1299 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1300 if (timed_out || rsp_sts.s.dma_val ||
1301 rsp_sts.s.dma_pend) {
1302 pr_err("%s(%s): Error: single-DMA timed out after %lums. rsp_sts: 0x%llx, emm_int: 0x%llx, emm_dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
1303 __func__, mmc->dev->name, timeout,
1305 read_csr(mmc, MIO_EMM_RSP_STS()),
1306 read_csr(mmc, MIO_EMM_DMA_INT()),
1307 read_csr(mmc, MIO_EMM_RSP_LO()),
1308 read_csr(mmc, MIO_EMM_DMA()));
1309 return blkcnt - count;
1319 * Send a command to the eMMC/SD device
1321 * @param mmc mmc device
1322 * @param cmd cmd to send and response
1323 * @param data additional data
1325 * @return 0 for success, otherwise error
1327 static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1328 struct mmc_data *data)
1330 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
1331 const char *name = slot->dev->name;
1332 struct octeontx_mmc_cr_mods mods = {0, 0};
1333 union mio_emm_rsp_sts rsp_sts;
1334 union mio_emm_cmd emm_cmd;
1335 union mio_emm_rsp_lo rsp_lo;
1336 union mio_emm_buf_idx emm_buf_idx;
1337 union mio_emm_buf_dat emm_buf_dat;
1343 * This constant has a 1 bit for each command which should have a short
1344 * timeout and a 0 for each bit with a long timeout. Currently the
1345 * following commands have a long timeout:
1346 * CMD6, CMD17, CMD18, CMD24, CMD25, CMD32, CMD33, CMD35, CMD36 and
1349 static const u64 timeout_short = 0xFFFFFFA4FCF9FFDFull;
1352 if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD) {
1353 union mio_emm_rca emm_rca;
1356 emm_rca.s.card_rca = mmc->rca;
1357 write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
1360 if (timeout_short & (1ull << cmd->cmdidx))
1361 timeout = MMC_TIMEOUT_SHORT;
1362 else if (cmd->cmdidx == MMC_CMD_SWITCH && IS_SD(mmc))
1364 else if (cmd->cmdidx == MMC_CMD_ERASE)
1365 timeout = MMC_TIMEOUT_ERASE;
1367 timeout = MMC_TIMEOUT_LONG;
1369 debug("%s(%s): cmd idx: %u, arg: 0x%x, resp type: 0x%x, timeout: %u\n",
1370 __func__, name, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
1373 debug(" data: addr: %p, flags: 0x%x, blocks: %u, blocksize: %u\n",
1374 data->dest, data->flags, data->blocks, data->blocksize);
1376 octeontx_mmc_switch_to(mmc);
1378 /* Clear any interrupts */
1379 write_csr(mmc, MIO_EMM_INT(), read_csr(mmc, MIO_EMM_INT()));
1382 * We need to override the default command types and response types
1383 * when dealing with SD cards.
1385 mods = octeontx_mmc_get_cr_mods(mmc, cmd, data);
1387 /* Handle block read/write/stop operations */
1388 switch (cmd->cmdidx) {
1389 case MMC_CMD_GO_IDLE_STATE:
1390 slot->tuned = false;
1391 slot->hs200_tuned = false;
1392 slot->hs400_tuned = false;
1394 case MMC_CMD_STOP_TRANSMISSION:
1396 case MMC_CMD_READ_MULTIPLE_BLOCK:
1397 case MMC_CMD_READ_SINGLE_BLOCK:
1398 pr_debug("%s(%s): Reading blocks\n", __func__, name);
1399 blkcnt = octeontx_mmc_read_blocks(mmc, cmd, data, true);
1400 return (blkcnt > 0) ? 0 : -1;
1401 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
1402 case MMC_CMD_WRITE_SINGLE_BLOCK:
1403 blkcnt = octeontx_mmc_write_blocks(mmc, cmd, data);
1404 return (blkcnt > 0) ? 0 : -1;
1405 case MMC_CMD_SELECT_CARD:
1406 /* Set the RCA register (is it set automatically?) */
1408 union mio_emm_rca emm_rca;
1411 emm_rca.s.card_rca = (cmd->cmdarg >> 16);
1412 write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
1413 debug("%s: Set SD relative address (RCA) to 0x%x\n",
1414 __func__, emm_rca.s.card_rca);
1418 case MMC_CMD_SWITCH:
1419 if (!data && !slot->is_acmd)
1420 octeontx_mmc_track_switch(mmc, cmd->cmdarg);
1425 emm_cmd.s.cmd_val = 1;
1426 emm_cmd.s.bus_id = slot->bus_id;
1427 emm_cmd.s.cmd_idx = cmd->cmdidx;
1428 emm_cmd.s.arg = cmd->cmdarg;
1429 emm_cmd.s.ctype_xor = mods.ctype_xor;
1430 emm_cmd.s.rtype_xor = mods.rtype_xor;
1431 if (data && data->blocks == 1 && data->blocksize != 512) {
1433 64 - ((data->blocks * data->blocksize) / 8);
1434 debug("%s: offset set to %u\n", __func__, emm_cmd.s.offset);
1437 if (data && data->flags & MMC_DATA_WRITE) {
1438 u8 *src = (u8 *)data->src;
1441 pr_err("%s(%s): Error: data source for cmd 0x%x is NULL!\n",
1442 __func__, name, cmd->cmdidx);
1445 if (data->blocksize > 512) {
1446 pr_err("%s(%s): Error: data for cmd 0x%x exceeds 512 bytes\n",
1447 __func__, name, cmd->cmdidx);
1451 debug("%s: Sending %d bytes data\n", __func__, data->blocksize);
1452 print_buffer(0, src, 1, data->blocksize, 0);
1455 emm_buf_idx.s.inc = 1;
1456 write_csr(mmc, MIO_EMM_BUF_IDX(), emm_buf_idx.u);
1457 for (i = 0; i < (data->blocksize + 7) / 8; i++) {
1458 memcpy(&emm_buf_dat.u, src, sizeof(emm_buf_dat.u));
1459 write_csr(mmc, MIO_EMM_BUF_DAT(),
1460 cpu_to_be64(emm_buf_dat.u));
1461 src += sizeof(emm_buf_dat.u);
1463 write_csr(mmc, MIO_EMM_BUF_IDX(), 0);
1465 debug("%s(%s): Sending command %u (emm_cmd: 0x%llx)\n", __func__,
1466 name, cmd->cmdidx, emm_cmd.u);
1467 set_wdog(mmc, timeout * 1000);
1468 write_csr(mmc, MIO_EMM_CMD(), emm_cmd.u);
1470 /* Wait for command to finish or time out */
1471 start = get_timer(0);
1473 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
1475 } while (!rsp_sts.s.cmd_done && !rsp_sts.s.rsp_timeout &&
1476 (get_timer(start) < timeout + 10));
1477 octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
1478 if (rsp_sts.s.rsp_timeout || !rsp_sts.s.cmd_done) {
1479 debug("%s(%s): Error: command %u(0x%x) timed out. rsp_sts: 0x%llx\n",
1480 __func__, name, cmd->cmdidx, cmd->cmdarg, rsp_sts.u);
1481 octeontx_mmc_print_registers(mmc);
1484 if (rsp_sts.s.rsp_crc_err) {
1485 debug("%s(%s): RSP CRC error, rsp_sts: 0x%llx, cmdidx: %u, arg: 0x%08x\n",
1486 __func__, name, rsp_sts.u, cmd->cmdidx, cmd->cmdarg);
1487 octeontx_mmc_print_registers(mmc);
1490 if (slot->bus_id != rsp_sts.s.bus_id) {
1491 pr_warn("%s(%s): bus id mismatch, got %d, expected %d for command 0x%x(0x%x)\n",
1493 rsp_sts.s.bus_id, slot->bus_id,
1494 cmd->cmdidx, cmd->cmdarg);
1497 if (rsp_sts.s.rsp_bad_sts) {
1498 rsp_lo.u = read_csr(mmc, MIO_EMM_RSP_LO());
1499 debug("%s: Bad response for bus id %d, cmd id %d:\n"
1500 " rsp_timeout: %d\n"
1501 " rsp_bad_sts: %d\n"
1502 " rsp_crc_err: %d\n",
1503 __func__, slot->bus_id, cmd->cmdidx,
1504 rsp_sts.s.rsp_timeout,
1505 rsp_sts.s.rsp_bad_sts,
1506 rsp_sts.s.rsp_crc_err);
1507 if (rsp_sts.s.rsp_type == 1 && rsp_sts.s.rsp_bad_sts) {
1508 debug(" Response status: 0x%llx\n",
1509 (rsp_lo.u >> 8) & 0xffffffff);
1511 mmc_print_status((rsp_lo.u >> 8) & 0xffffffff);
1516 if (rsp_sts.s.cmd_idx != cmd->cmdidx) {
1517 debug("%s(%s): Command response index %d does not match command index %d\n",
1518 __func__, name, rsp_sts.s.cmd_idx, cmd->cmdidx);
1519 octeontx_print_rsp_sts(mmc);
1520 debug("%s: rsp_lo: 0x%llx\n", __func__,
1521 read_csr(mmc, MIO_EMM_RSP_LO()));
1526 slot->is_acmd = (cmd->cmdidx == MMC_CMD_APP_CMD);
1528 if (!cmd->resp_type & MMC_RSP_PRESENT)
1529 debug(" Response type: 0x%x, no response expected\n",
1531 /* Get the response if present */
1532 if (rsp_sts.s.rsp_val && (cmd->resp_type & MMC_RSP_PRESENT)) {
1533 union mio_emm_rsp_hi rsp_hi;
1535 rsp_lo.u = read_csr(mmc, MIO_EMM_RSP_LO());
1537 switch (rsp_sts.s.rsp_type) {
1542 cmd->response[0] = (rsp_lo.u >> 8) & 0xffffffffull;
1543 debug(" response: 0x%08x\n",
1545 cmd->response[1] = 0;
1546 cmd->response[2] = 0;
1547 cmd->response[3] = 0;
1550 cmd->response[3] = rsp_lo.u & 0xffffffff;
1551 cmd->response[2] = (rsp_lo.u >> 32) & 0xffffffff;
1552 rsp_hi.u = read_csr(mmc, MIO_EMM_RSP_HI());
1553 cmd->response[1] = rsp_hi.u & 0xffffffff;
1554 cmd->response[0] = (rsp_hi.u >> 32) & 0xffffffff;
1555 debug(" response: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1556 cmd->response[0], cmd->response[1],
1557 cmd->response[2], cmd->response[3]);
1560 pr_err("%s(%s): Unknown response type 0x%x for command %d, arg: 0x%x, rsp_sts: 0x%llx\n",
1561 __func__, name, rsp_sts.s.rsp_type, cmd->cmdidx,
1562 cmd->cmdarg, rsp_sts.u);
1566 debug(" Response not expected\n");
1569 if (data && data->flags & MMC_DATA_READ) {
1570 u8 *dest = (u8 *)data->dest;
1573 pr_err("%s(%s): Error, destination buffer NULL!\n",
1574 __func__, mmc->dev->name);
1577 if (data->blocksize > 512) {
1578 printf("%s(%s): Error: data size %u exceeds 512\n",
1579 __func__, mmc->dev->name,
1584 emm_buf_idx.s.inc = 1;
1585 write_csr(mmc, MIO_EMM_BUF_IDX(), emm_buf_idx.u);
1586 for (i = 0; i < (data->blocksize + 7) / 8; i++) {
1587 emm_buf_dat.u = read_csr(mmc, MIO_EMM_BUF_DAT());
1588 emm_buf_dat.u = be64_to_cpu(emm_buf_dat.u);
1589 memcpy(dest, &emm_buf_dat.u, sizeof(emm_buf_dat.u));
1590 dest += sizeof(emm_buf_dat.u);
1592 write_csr(mmc, MIO_EMM_BUF_IDX(), 0);
1594 debug("%s: Received %d bytes data\n", __func__,
1596 print_buffer(0, data->dest, 1, data->blocksize, 0);
1603 octeontx_mmc_print_registers(mmc);
1608 static int octeontx_mmc_dev_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1609 struct mmc_data *data)
1611 return octeontx_mmc_send_cmd(dev_to_mmc(dev), cmd, data);
1614 #ifdef MMC_SUPPORTS_TUNING
1615 static int octeontx_mmc_test_cmd(struct mmc *mmc, u32 opcode, int *statp)
1620 memset(&cmd, 0, sizeof(cmd));
1622 debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp);
1623 cmd.cmdidx = opcode;
1624 cmd.resp_type = MMC_RSP_R1;
1625 cmd.cmdarg = mmc->rca << 16;
1627 err = octeontx_mmc_send_cmd(mmc, &cmd, NULL);
1629 debug("%s(%s, %u) returned %d\n", __func__,
1630 mmc->dev->name, opcode, err);
1632 *statp = cmd.response[0];
1636 static int octeontx_mmc_test_get_ext_csd(struct mmc *mmc, u32 opcode,
1640 struct mmc_data data;
1642 u8 ext_csd[MMC_MAX_BLOCK_LEN];
1644 debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp);
1645 memset(&cmd, 0, sizeof(cmd));
1647 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
1648 cmd.resp_type = MMC_RSP_R1;
1651 data.dest = (char *)ext_csd;
1653 data.blocksize = MMC_MAX_BLOCK_LEN;
1654 data.flags = MMC_DATA_READ;
1656 err = octeontx_mmc_send_cmd(mmc, &cmd, &data);
1658 *statp = cmd.response[0];
1664 * Wrapper to set the MIO_EMM_TIMING register
1666 * @param mmc pointer to mmc data structure
1667 * @param emm_timing New emm_timing register value
1669 * On some devices it is possible that changing the data out value can
1670 * cause a glitch on an internal fifo. This works around this problem
1671 * by performing a soft-reset immediately before setting the timing register.
1673 * Note: this function should not be called from any function that
1674 * performs DMA or block operations since not all registers are
1677 static void octeontx_mmc_set_emm_timing(struct mmc *mmc,
1678 union mio_emm_timing emm_timing)
1680 union mio_emm_cfg emm_cfg;
1681 struct octeontx_mmc_slot *slot = mmc->priv;
1682 union mio_emm_debug emm_debug;
1684 debug("%s(%s, 0x%llx) din: %u\n", __func__, mmc->dev->name,
1685 emm_timing.u, emm_timing.s.data_in_tap);
1688 if (slot->host->tap_requires_noclk) {
1689 /* Turn off the clock */
1690 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
1691 emm_debug.s.emmc_clk_disable = 1;
1692 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
1694 emm_debug.s.rdsync_rst = 1;
1695 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
1697 emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
1698 emm_cfg.s.bus_ena = 1 << 3;
1699 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
1702 write_csr(mmc, MIO_EMM_TIMING(), emm_timing.u);
1705 if (slot->host->tap_requires_noclk) {
1706 /* Turn on the clock */
1707 emm_debug.s.rdsync_rst = 0;
1708 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
1710 emm_debug.s.emmc_clk_disable = 0;
1711 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
1714 emm_cfg.s.bus_ena = 1 << mmc_to_slot(mmc)->bus_id;
1715 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
1718 static const u8 octeontx_hs400_tuning_block[512] = {
1719 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
1720 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
1721 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1722 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1723 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1724 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1725 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1726 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1727 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
1728 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
1729 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
1730 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1731 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1732 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1733 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1734 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1735 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
1736 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
1737 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1738 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1739 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1740 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1741 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1742 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1743 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
1744 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
1745 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
1746 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1747 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1748 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1749 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1750 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1751 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
1752 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
1753 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1754 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1755 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1756 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1757 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1758 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1759 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
1760 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
1761 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
1762 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1763 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1764 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1765 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1766 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1767 0xff, 0x00, 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
1768 0x00, 0xff, 0x00, 0xff, 0x55, 0xaa, 0x55, 0xaa,
1769 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
1770 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
1771 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
1772 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
1773 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
1774 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
1775 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00,
1776 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,
1777 0x01, 0xfe, 0x01, 0xfe, 0xcc, 0xcc, 0xcc, 0xff,
1778 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
1779 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
1780 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
1781 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
1782 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
1787 * Perform tuning in HS400 mode
1789 * @param[in] mmc mmc data structure
1791 * @ret 0 for success, otherwise error
1793 static int octeontx_tune_hs400(struct mmc *mmc)
1795 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
1797 struct mmc_data data;
1798 union mio_emm_timing emm_timing;
1799 u8 buffer[mmc->read_bl_len];
1806 int best_start = -1;
1807 bool prev_ok = false;
1809 char how[MAX_NO_OF_TAPS + 1] = "";
1811 if (slot->hs400_tuning_block == -1)
1814 /* The eMMC standard disables all tuning support when operating in
1815 * DDR modes like HS400. The problem with this is that there are
1816 * many cases where the HS200 tuning does not work for HS400 mode.
1817 * In order to perform this tuning, while in HS200 a block is written
1818 * to a block specified in the device tree (marvell,hs400-tuning-block)
1819 * which is used for tuning in this function by repeatedly reading
1820 * this block and comparing the data and return code. This function
1821 * chooses the data input tap in the middle of the longest run of
1822 * successful read operations.
1825 emm_timing = slot->hs200_taps;
1826 debug("%s(%s): Start ci: %d, co: %d, di: %d, do: %d\n",
1827 __func__, mmc->dev->name, emm_timing.s.cmd_in_tap,
1828 emm_timing.s.cmd_out_tap, emm_timing.s.data_in_tap,
1829 emm_timing.s.data_out_tap);
1830 memset(buffer, 0xdb, sizeof(buffer));
1832 snprintf(env_name, sizeof(env_name), "emmc%d_data_in_tap_hs400",
1834 tap = env_get_ulong(env_name, 10, -1L);
1835 if (tap >= 0 && tap < MAX_NO_OF_TAPS) {
1836 printf("Overriding data input tap for HS400 mode to %d\n", tap);
1837 emm_timing.s.data_in_tap = tap;
1838 octeontx_mmc_set_emm_timing(mmc, emm_timing);
1842 for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) {
1843 if (tap < MAX_NO_OF_TAPS) {
1844 debug("%s: Testing data in tap %d\n", __func__, tap);
1845 emm_timing.s.data_in_tap = tap;
1846 octeontx_mmc_set_emm_timing(mmc, emm_timing);
1848 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
1849 cmd.cmdarg = slot->hs400_tuning_block;
1850 cmd.resp_type = MMC_RSP_R1;
1851 data.dest = (void *)buffer;
1853 data.blocksize = mmc->read_bl_len;
1854 data.flags = MMC_DATA_READ;
1855 err = !octeontx_mmc_read_blocks(mmc, &cmd, &data,
1857 if (err || memcmp(buffer, octeontx_hs400_tuning_block,
1861 debug("%s: data mismatch. Read:\n",
1863 print_buffer(0, buffer, 1,
1865 debug("\nExpected:\n");
1867 octeontx_hs400_tuning_block, 1,
1868 sizeof(octeontx_hs400_tuning_block),
1871 debug("%s: Error %d reading block\n",
1877 debug("%s: tap %d good\n", __func__, tap);
1879 how[tap] = "-+"[!err];
1887 } else if (prev_ok) {
1888 run = tap - 1 - start_run;
1889 if (start_run >= 0 && run > best_run) {
1890 best_start = start_run;
1896 how[tap - 1] = '\0';
1897 if (best_start < 0) {
1898 printf("%s(%s): %lldMHz tuning failed for HS400\n",
1899 __func__, mmc->dev->name, slot->clock / 1000000);
1902 tap = best_start + best_run / 2;
1904 snprintf(env_name, sizeof(env_name), "emmc%d_data_in_tap_adj_hs400",
1906 tap_adj = env_get_ulong(env_name, 10, slot->hs400_tap_adj);
1908 * Keep it in range and if out of range force it back in with a small
1912 tap = tap + tap_adj;
1913 if (tap >= best_start + best_run)
1914 tap = best_start + best_run - 2;
1915 if (tap <= best_start)
1916 tap = best_start + 2;
1919 debug("Tuning: %s\n", how);
1920 debug("%s(%s): HS400 tap: best run start: %d, length: %d, tap: %d\n",
1921 __func__, mmc->dev->name, best_start, best_run, tap);
1922 slot->hs400_taps = slot->hs200_taps;
1923 slot->hs400_taps.s.data_in_tap = tap;
1924 slot->hs400_tuned = true;
1925 if (env_get_yesno("emmc_export_hs400_taps") > 0) {
1926 debug("%s(%s): Exporting HS400 taps\n",
1927 __func__, mmc->dev->name);
1928 env_set_ulong("emmc_timing_tap", slot->host->timing_taps);
1929 snprintf(env_name, sizeof(env_name),
1930 "emmc%d_hs400_data_in_tap_debug",
1932 env_set(env_name, how);
1933 snprintf(env_name, sizeof(env_name),
1934 "emmc%d_hs400_data_in_tap_val",
1936 env_set_ulong(env_name, tap);
1937 snprintf(env_name, sizeof(env_name),
1938 "emmc%d_hs400_data_in_tap_start",
1940 env_set_ulong(env_name, best_start);
1941 snprintf(env_name, sizeof(env_name),
1942 "emmc%d_hs400_data_in_tap_end",
1944 env_set_ulong(env_name, best_start + best_run);
1945 snprintf(env_name, sizeof(env_name),
1946 "emmc%d_hs400_cmd_in_tap",
1948 env_set_ulong(env_name, slot->hs400_taps.s.cmd_in_tap);
1949 snprintf(env_name, sizeof(env_name),
1950 "emmc%d_hs400_cmd_out_tap",
1952 env_set_ulong(env_name, slot->hs400_taps.s.cmd_out_tap);
1953 snprintf(env_name, sizeof(env_name),
1954 "emmc%d_hs400_cmd_out_delay",
1956 env_set_ulong(env_name, slot->cmd_out_hs400_delay);
1957 snprintf(env_name, sizeof(env_name),
1958 "emmc%d_hs400_data_out_tap",
1960 env_set_ulong(env_name, slot->hs400_taps.s.data_out_tap);
1961 snprintf(env_name, sizeof(env_name),
1962 "emmc%d_hs400_data_out_delay",
1964 env_set_ulong(env_name, slot->data_out_hs400_delay);
1966 debug("%s(%s): HS400 environment export disabled\n",
1967 __func__, mmc->dev->name);
1969 octeontx_mmc_set_timing(mmc);
1977 int (*test)(struct mmc *mmc, u32 opcode, int *error);
1981 bool not_hs200_only;
1985 struct adj adj[] = {
1986 { "CMD_IN", 48, octeontx_mmc_test_cmd, MMC_CMD_SEND_STATUS,
1987 false, false, false, 2, },
1988 /* { "CMD_OUT", 32, octeontx_mmc_test_cmd, MMC_CMD_SEND_STATUS, },*/
1989 { "DATA_IN(HS200)", 16, mmc_send_tuning,
1990 MMC_CMD_SEND_TUNING_BLOCK_HS200, false, true, false, 2, },
1991 { "DATA_IN", 16, octeontx_mmc_test_get_ext_csd, 0, false, false,
1993 /* { "DATA_OUT", 0, octeontx_mmc_test_cmd, 0, true, false},*/
1998 * Perform tuning tests to find optimal timing
2000 * @param mmc mmc device
2001 * @param adj parameter to tune
2002 * @param opcode command opcode to use
2004 * @return 0 for success, -1 if tuning failed
2006 static int octeontx_mmc_adjust_tuning(struct mmc *mmc, struct adj *adj,
2009 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2010 union mio_emm_timing timing;
2011 union mio_emm_debug emm_debug;
2018 int best_start = -1;
2019 bool prev_ok = false;
2021 const int tap_adj = slot->hs200_tap_adj;
2022 char how[MAX_NO_OF_TAPS + 1] = "";
2023 bool is_hs200 = mmc->selected_mode == MMC_HS_200;
2025 debug("%s(%s, %s, %d), hs200: %d\n", __func__, mmc->dev->name,
2026 adj->name, opcode, is_hs200);
2027 octeontx_mmc_set_emm_timing(mmc,
2028 is_hs200 ? slot->hs200_taps : slot->taps);
2031 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
2032 printf("%s(%s): Before tuning %s, opcode: %d\n",
2033 __func__, mmc->dev->name, adj->name, opcode);
2034 octeontx_mmc_print_registers2(mmc, NULL);
2039 * The algorithm to find the optimal timing is to start
2040 * at the end and work backwards and select the second
2041 * value that passes. Each test is repeated twice.
2043 for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) {
2044 if (tap < MAX_NO_OF_TAPS) {
2045 if (slot->host->tap_requires_noclk) {
2046 /* Turn off the clock */
2047 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
2048 emm_debug.s.emmc_clk_disable = 1;
2049 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2051 emm_debug.s.rdsync_rst = 1;
2052 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2056 timing.u = read_csr(mmc, MIO_EMM_TIMING());
2057 timing.u &= ~(0x3full << adj->mask_shift);
2058 timing.u |= (u64)tap << adj->mask_shift;
2059 write_csr(mmc, MIO_EMM_TIMING(), timing.u);
2060 debug("%s(%s): Testing ci: %d, co: %d, di: %d, do: %d\n",
2061 __func__, mmc->dev->name, timing.s.cmd_in_tap,
2062 timing.s.cmd_out_tap, timing.s.data_in_tap,
2063 timing.s.data_out_tap);
2065 if (slot->host->tap_requires_noclk) {
2066 /* Turn off the clock */
2067 emm_debug.s.rdsync_rst = 0;
2068 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2070 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
2071 emm_debug.s.emmc_clk_disable = 0;
2072 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2075 for (count = 0; count < 2; count++) {
2076 err = adj->test(mmc, opcode, NULL);
2078 debug("%s(%s, %s): tap %d failed, count: %d, rsp_sts: 0x%llx, rsp_lo: 0x%llx\n",
2079 __func__, mmc->dev->name,
2080 adj->name, tap, count,
2085 debug("%s(%s, %s): tap: %d, do: %d, di: %d, co: %d, ci: %d\n",
2086 __func__, mmc->dev->name,
2088 timing.s.data_out_tap,
2089 timing.s.data_in_tap,
2090 timing.s.cmd_out_tap,
2091 timing.s.cmd_in_tap);
2094 debug("%s(%s, %s): tap %d passed, count: %d, rsp_sts: 0x%llx, rsp_lo: 0x%llx\n",
2095 __func__, mmc->dev->name, adj->name, tap,
2097 read_csr(mmc, MIO_EMM_RSP_STS()),
2098 read_csr(mmc, MIO_EMM_RSP_LO()));
2100 tap_status |= (u64)(!err) << tap;
2101 how[tap] = "-+"[!err];
2104 * Putting the end+1 case in the loop simplifies
2105 * logic, allowing 'prev_ok' to process a sweet
2106 * spot in tuning which extends to the wall.
2112 * If no CRC/etc errors in the response, but previous
2113 * failed, note the start of a new run.
2115 debug(" prev_ok: %d\n", prev_ok);
2118 } else if (prev_ok) {
2119 run = tap - 1 - start_run;
2120 /* did we just exit a wider sweet spot? */
2121 if (start_run >= 0 && run > best_run) {
2122 best_start = start_run;
2127 how[tap - 1] = '\0';
2128 if (best_start < 0) {
2129 printf("%s(%s, %s): %lldMHz tuning %s failed\n", __func__,
2130 mmc->dev->name, adj->name, slot->clock / 1000000,
2135 tap = best_start + best_run / 2;
2136 debug(" tap %d is center, start: %d, run: %d\n", tap,
2137 best_start, best_run);
2139 slot->hs200_taps.u &= ~(0x3full << adj->mask_shift);
2140 slot->hs200_taps.u |= (u64)tap << adj->mask_shift;
2142 slot->taps.u &= ~(0x3full << adj->mask_shift);
2143 slot->taps.u |= (u64)tap << adj->mask_shift;
2145 if (best_start < 0) {
2146 printf("%s(%s, %s): %lldMHz tuning %s failed\n", __func__,
2147 mmc->dev->name, adj->name, slot->clock / 1000000,
2152 tap = best_start + best_run / 2;
2153 if (is_hs200 && (tap + tap_adj >= 0) && (tap + tap_adj < 64) &&
2154 tap_status & (1ULL << (tap + tap_adj))) {
2155 debug("Adjusting tap from %d by %d to %d\n",
2156 tap, tap_adj, tap + tap_adj);
2160 debug("%s/%s %d/%d/%d %s\n", mmc->dev->name,
2161 adj->name, best_start, tap, best_start + best_run, how);
2164 slot->hs200_taps.u &= ~(0x3full << adj->mask_shift);
2165 slot->hs200_taps.u |= (u64)tap << adj->mask_shift;
2167 slot->taps.u &= ~(0x3full << adj->mask_shift);
2168 slot->taps.u |= (u64)tap << adj->mask_shift;
2172 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
2173 debug("%s(%s, %s): After successful tuning\n",
2174 __func__, mmc->dev->name, adj->name);
2175 debug("%s(%s, %s): tap: %d, new do: %d, di: %d, co: %d, ci: %d\n",
2176 __func__, mmc->dev->name, adj->name, tap,
2177 slot->taps.s.data_out_tap,
2178 slot->taps.s.data_in_tap,
2179 slot->taps.s.cmd_out_tap,
2180 slot->taps.s.cmd_in_tap);
2181 debug("%s(%s, %s): tap: %d, new do HS200: %d, di: %d, co: %d, ci: %d\n",
2182 __func__, mmc->dev->name, adj->name, tap,
2183 slot->hs200_taps.s.data_out_tap,
2184 slot->hs200_taps.s.data_in_tap,
2185 slot->hs200_taps.s.cmd_out_tap,
2186 slot->hs200_taps.s.cmd_in_tap);
2189 octeontx_mmc_set_timing(mmc);
2191 if (is_hs200 && env_get_yesno("emmc_export_hs200_taps")) {
2194 env_set_ulong("emmc_timing_tap", slot->host->timing_taps);
2196 case MMC_CMD_SEND_TUNING_BLOCK:
2197 snprintf(env_name, sizeof(env_name),
2198 "emmc%d_hs200_data_in_tap_debug",
2200 env_set(env_name, how);
2201 snprintf(env_name, sizeof(env_name),
2202 "emmc%d_hs200_data_in_tap_val", slot->bus_id);
2203 env_set_ulong(env_name, tap);
2204 snprintf(env_name, sizeof(env_name),
2205 "emmc%d_hs200_data_in_tap_start",
2207 env_set_ulong(env_name, best_start);
2208 snprintf(env_name, sizeof(env_name),
2209 "emmc%d_hs200_data_in_tap_end",
2211 env_set_ulong(env_name, best_start + best_run);
2213 case MMC_CMD_SEND_STATUS:
2214 snprintf(env_name, sizeof(env_name),
2215 "emmc%d_hs200_cmd_in_tap_debug",
2217 env_set(env_name, how);
2218 snprintf(env_name, sizeof(env_name),
2219 "emmc%d_hs200_cmd_in_tap_val", slot->bus_id);
2220 env_set_ulong(env_name, tap);
2221 snprintf(env_name, sizeof(env_name),
2222 "emmc%d_hs200_cmd_in_tap_start",
2224 env_set_ulong(env_name, best_start);
2225 snprintf(env_name, sizeof(env_name),
2226 "emmc%d_hs200_cmd_in_tap_end",
2228 env_set_ulong(env_name, best_start + best_run);
2231 snprintf(env_name, sizeof(env_name),
2232 "emmc%d_hs200_data_out_tap", slot->bus_id);
2233 env_set_ulong(env_name, slot->data_out_hs200_delay);
2234 snprintf(env_name, sizeof(env_name),
2235 "emmc%d_hs200_cmd_out_tap", slot->bus_id);
2236 env_set_ulong(env_name, slot->cmd_out_hs200_delay);
2244 static int octeontx_mmc_execute_tuning(struct udevice *dev, u32 opcode)
2246 struct mmc *mmc = dev_to_mmc(dev);
2247 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2248 union mio_emm_timing emm_timing;
2254 pr_info("%s re-tuning, opcode 0x%x\n", dev->name, opcode);
2256 if (slot->is_asim || slot->is_emul)
2259 is_hs200 = (mmc->selected_mode == MMC_HS_200);
2261 slot->hs200_tuned = false;
2262 slot->hs400_tuned = false;
2264 slot->tuned = false;
2266 octeontx_mmc_set_output_bus_timing(mmc);
2267 octeontx_mmc_set_input_bus_timing(mmc);
2268 emm_timing.u = read_csr(mmc, MIO_EMM_TIMING());
2269 if (mmc->selected_mode == MMC_HS_200) {
2270 slot->hs200_taps.s.cmd_out_tap = emm_timing.s.cmd_out_tap;
2271 slot->hs200_taps.s.data_out_tap = emm_timing.s.data_out_tap;
2273 slot->taps.s.cmd_out_tap = emm_timing.s.cmd_out_tap;
2274 slot->taps.s.data_out_tap = emm_timing.s.data_out_tap;
2276 octeontx_mmc_set_input_bus_timing(mmc);
2277 octeontx_mmc_set_output_bus_timing(mmc);
2279 for (a = adj; a->name; a++) {
2282 if (!strcmp(a->name, "CMD_IN")) {
2283 snprintf(env_name, sizeof(env_name),
2284 "emmc%d_cmd_in_tap", slot->bus_id);
2285 in_tap = env_get_ulong(env_name, 10, (ulong)-1);
2286 if (in_tap != (ulong)-1) {
2287 if (mmc->selected_mode == MMC_HS_200 ||
2289 slot->hs200_taps.s.cmd_in_tap = in_tap;
2290 slot->hs400_taps.s.cmd_in_tap = in_tap;
2292 slot->taps.s.cmd_in_tap = in_tap;
2296 } else if (a->hs200_only &&
2297 !strcmp(a->name, "DATA_IN(HS200)")) {
2298 snprintf(env_name, sizeof(env_name),
2299 "emmc%d_data_in_tap_hs200", slot->bus_id);
2300 in_tap = env_get_ulong(env_name, 10, (ulong)-1);
2301 if (in_tap != (ulong)-1) {
2302 debug("%s(%s): Overriding HS200 data in tap to %d\n",
2303 __func__, dev->name, (int)in_tap);
2304 slot->hs200_taps.s.data_in_tap = in_tap;
2307 } else if (!a->hs200_only && !strcmp(a->name, "DATA_IN")) {
2308 snprintf(env_name, sizeof(env_name),
2309 "emmc%d_data_in_tap", slot->bus_id);
2310 in_tap = env_get_ulong(env_name, 10, (ulong)-1);
2311 if (in_tap != (ulong)-1) {
2312 debug("%s(%s): Overriding non-HS200 data in tap to %d\n",
2313 __func__, dev->name, (int)in_tap);
2314 slot->taps.s.data_in_tap = in_tap;
2319 debug("%s(%s): Testing: %s, mode: %s, opcode: %u\n", __func__,
2320 dev->name, a->name, mmc_mode_name(mmc->selected_mode),
2323 /* Skip DDR only test when not in DDR mode */
2324 if (a->ddr_only && !mmc->ddr_mode) {
2325 debug("%s(%s): Skipping %s due to non-DDR mode\n",
2326 __func__, dev->name, a->name);
2329 /* Skip hs200 tests in non-hs200 mode and
2330 * non-hs200 tests in hs200 mode
2333 if (a->not_hs200_only) {
2334 debug("%s(%s): Skipping %s\n", __func__,
2335 dev->name, a->name);
2339 if (a->hs200_only) {
2340 debug("%s(%s): Skipping %s\n", __func__,
2341 dev->name, a->name);
2346 err = octeontx_mmc_adjust_tuning(mmc, a, a->opcode ?
2347 a->opcode : opcode);
2349 pr_err("%s(%s, %u): tuning %s failed\n", __func__,
2350 dev->name, opcode, a->name);
2355 octeontx_mmc_set_timing(mmc);
2357 slot->hs200_tuned = true;
2361 if (slot->hs400_tuning_block != -1) {
2363 struct mmc_data data;
2364 u8 buffer[mmc->read_bl_len];
2366 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
2367 cmd.cmdarg = slot->hs400_tuning_block;
2368 cmd.resp_type = MMC_RSP_R1;
2369 data.dest = (void *)buffer;
2371 data.blocksize = mmc->read_bl_len;
2372 data.flags = MMC_DATA_READ;
2373 err = octeontx_mmc_read_blocks(mmc, &cmd, &data, true) != 1;
2376 printf("%s: Cannot read HS400 tuning block %u\n",
2377 dev->name, slot->hs400_tuning_block);
2380 if (memcmp(buffer, octeontx_hs400_tuning_block,
2382 debug("%s(%s): Writing new HS400 tuning block to block %d\n",
2383 __func__, dev->name, slot->hs400_tuning_block);
2384 cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
2385 data.src = (void *)octeontx_hs400_tuning_block;
2386 data.flags = MMC_DATA_WRITE;
2387 err = !octeontx_mmc_write_blocks(mmc, &cmd, &data);
2389 printf("%s: Cannot write HS400 tuning block %u\n",
2390 dev->name, slot->hs400_tuning_block);
2398 #else /* MMC_SUPPORTS_TUNING */
2399 static void octeontx_mmc_set_emm_timing(struct mmc *mmc,
2400 union mio_emm_timing emm_timing)
2403 #endif /* MMC_SUPPORTS_TUNING */
2406 * Calculate the clock period with rounding up
2408 * @param mmc mmc device
2409 * @return clock period in system clocks for clk_lo + clk_hi
2411 static u32 octeontx_mmc_calc_clk_period(struct mmc *mmc)
2413 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2414 struct octeontx_mmc_host *host = slot->host;
2416 return DIV_ROUND_UP(host->sys_freq, mmc->clock);
2419 static int octeontx_mmc_set_ios(struct udevice *dev)
2421 struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
2422 struct mmc *mmc = &slot->mmc;
2423 struct octeontx_mmc_host *host = slot->host;
2424 union mio_emm_switch emm_switch;
2425 union mio_emm_modex mode;
2429 int power_class = 10;
2431 bool is_hs200 = false;
2432 bool is_hs400 = false;
2434 debug("%s(%s): Entry\n", __func__, dev->name);
2435 debug(" clock: %u, bus width: %u, mode: %u\n", mmc->clock,
2436 mmc->bus_width, mmc->selected_mode);
2437 debug(" host caps: 0x%x, card caps: 0x%x\n", mmc->host_caps,
2439 octeontx_mmc_switch_to(mmc);
2443 clock = mmc->cfg->f_min;
2445 switch (mmc->bus_width) {
2456 pr_warn("%s(%s): Invalid bus width %d, defaulting to 1\n",
2457 __func__, dev->name, mmc->bus_width);
2461 /* DDR is available for 4/8 bit bus width */
2462 if (mmc->ddr_mode && bus_width)
2465 debug("%s: sys_freq: %llu\n", __func__, host->sys_freq);
2466 clk_period = octeontx_mmc_calc_clk_period(mmc);
2469 emm_switch.s.bus_width = bus_width;
2470 emm_switch.s.power_class = power_class;
2471 emm_switch.s.clk_hi = clk_period / 2;
2472 emm_switch.s.clk_lo = clk_period / 2;
2474 debug("%s: last mode: %d, mode: %d, last clock: %u, clock: %u, ddr: %d\n",
2475 __func__, slot->last_mode, mmc->selected_mode,
2476 slot->last_clock, mmc->clock, mmc->ddr_mode);
2477 switch (mmc->selected_mode) {
2483 emm_switch.s.hs_timing = 1;
2492 emm_switch.s.hs200_timing = 1;
2499 emm_switch.s.hs400_timing = 1;
2502 pr_err("%s(%s): Unsupported mode 0x%x\n", __func__, dev->name,
2503 mmc->selected_mode);
2506 emm_switch.s.bus_id = slot->bus_id;
2508 if (!is_hs200 && !is_hs400 &&
2509 (mmc->selected_mode != slot->last_mode ||
2510 mmc->clock != slot->last_clock) &&
2512 slot->tuned = false;
2513 slot->last_mode = mmc->selected_mode;
2514 slot->last_clock = mmc->clock;
2517 if (CONFIG_IS_ENABLED(MMC_VERBOSE)) {
2518 debug("%s(%s): Setting bus mode to %s\n", __func__, dev->name,
2519 mmc_mode_name(mmc->selected_mode));
2521 debug("%s(%s): Setting bus mode to 0x%x\n", __func__, dev->name,
2522 mmc->selected_mode);
2525 debug(" Trying switch 0x%llx w%d hs:%d hs200:%d hs400:%d\n",
2526 emm_switch.u, emm_switch.s.bus_width, emm_switch.s.hs_timing,
2527 emm_switch.s.hs200_timing, emm_switch.s.hs400_timing);
2529 set_wdog(mmc, 1000);
2530 do_switch(mmc, emm_switch);
2532 mode.u = read_csr(mmc, MIO_EMM_MODEX(slot->bus_id));
2533 debug("%s(%s): mode: 0x%llx w:%d, hs:%d, hs200:%d, hs400:%d\n",
2534 __func__, dev->name, mode.u, mode.s.bus_width,
2535 mode.s.hs_timing, mode.s.hs200_timing, mode.s.hs400_timing);
2537 err = octeontx_mmc_configure_delay(mmc);
2539 #ifdef MMC_SUPPORTS_TUNING
2540 if (!err && mmc->selected_mode == MMC_HS_400 && !slot->hs400_tuned) {
2541 debug("%s: Tuning HS400 mode\n", __func__);
2542 err = octeontx_tune_hs400(mmc);
2550 * Gets the status of the card detect pin
2552 static int octeontx_mmc_get_cd(struct udevice *dev)
2554 struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
2557 if (dm_gpio_is_valid(&slot->cd_gpio)) {
2558 val = dm_gpio_get_value(&slot->cd_gpio);
2559 val ^= slot->cd_inverted;
2561 debug("%s(%s): cd: %d\n", __func__, dev->name, val);
2566 * Gets the status of the write protect pin
2568 static int octeontx_mmc_get_wp(struct udevice *dev)
2570 struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
2573 if (dm_gpio_is_valid(&slot->wp_gpio)) {
2574 val = dm_gpio_get_value(&slot->wp_gpio);
2575 val ^= slot->wp_inverted;
2577 debug("%s(%s): wp: %d\n", __func__, dev->name, val);
2581 static void octeontx_mmc_set_timing(struct mmc *mmc)
2583 union mio_emm_timing timing;
2584 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2586 switch (mmc->selected_mode) {
2588 timing = slot->hs200_taps;
2591 timing = slot->hs400_tuned ?
2592 slot->hs400_taps : slot->hs200_taps;
2595 timing = slot->taps;
2599 debug("%s(%s):\n cmd_in_tap: %u\n cmd_out_tap: %u\n data_in_tap: %u\n data_out_tap: %u\n",
2600 __func__, mmc->dev->name, timing.s.cmd_in_tap,
2601 timing.s.cmd_out_tap, timing.s.data_in_tap,
2602 timing.s.data_out_tap);
2604 octeontx_mmc_set_emm_timing(mmc, timing);
2607 static int octeontx_mmc_configure_delay(struct mmc *mmc)
2609 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2610 struct octeontx_mmc_host *host __maybe_unused = slot->host;
2611 bool __maybe_unused is_hs200;
2612 bool __maybe_unused is_hs400;
2614 debug("%s(%s)\n", __func__, mmc->dev->name);
2616 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
2617 union mio_emm_sample emm_sample;
2620 emm_sample.s.cmd_cnt = slot->cmd_cnt;
2621 emm_sample.s.dat_cnt = slot->dat_cnt;
2622 write_csr(mmc, MIO_EMM_SAMPLE(), emm_sample.u);
2624 is_hs200 = (mmc->selected_mode == MMC_HS_200);
2625 is_hs400 = (mmc->selected_mode == MMC_HS_400);
2627 if ((is_hs200 && slot->hs200_tuned) ||
2628 (is_hs400 && slot->hs400_tuned) ||
2629 (!is_hs200 && !is_hs400 && slot->tuned)) {
2630 octeontx_mmc_set_output_bus_timing(mmc);
2632 int half = MAX_NO_OF_TAPS / 2;
2635 switch (mmc->selected_mode) {
2638 cout = MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP;
2639 dout = MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP;
2641 cout = MMC_LEGACY_DEFAULT_CMD_OUT_TAP;
2642 dout = MMC_LEGACY_DEFAULT_DATA_OUT_TAP;
2646 cout = MMC_HS_CMD_OUT_TAP;
2647 dout = MMC_HS_DATA_OUT_TAP;
2653 cout = MMC_SD_HS_CMD_OUT_TAP;
2654 dout = MMC_SD_HS_DATA_OUT_TAP;
2660 cout = MMC_DEFAULT_CMD_OUT_TAP;
2661 dout = MMC_DEFAULT_DATA_OUT_TAP;
2666 if (host->timing_calibrated) {
2667 cout = octeontx2_mmc_calc_delay(
2668 mmc, slot->cmd_out_hs200_delay);
2669 dout = octeontx2_mmc_calc_delay(
2671 slot->data_out_hs200_delay);
2672 debug("%s(%s): Calibrated HS200/HS400 cmd out delay: %dps tap: %d, data out delay: %d, tap: %d\n",
2673 __func__, mmc->dev->name,
2674 slot->cmd_out_hs200_delay, cout,
2675 slot->data_out_hs200_delay, dout);
2677 cout = MMC_DEFAULT_HS200_CMD_OUT_TAP;
2678 dout = MMC_DEFAULT_HS200_DATA_OUT_TAP;
2685 if (host->timing_calibrated) {
2686 if (slot->cmd_out_hs400_delay)
2687 cout = octeontx2_mmc_calc_delay(
2689 slot->cmd_out_hs400_delay);
2690 if (slot->data_out_hs400_delay)
2691 dout = octeontx2_mmc_calc_delay(
2693 slot->data_out_hs400_delay);
2694 debug("%s(%s): Calibrated HS200/HS400 cmd out delay: %dps tap: %d, data out delay: %d, tap: %d\n",
2695 __func__, mmc->dev->name,
2696 slot->cmd_out_hs400_delay, cout,
2697 slot->data_out_hs400_delay, dout);
2699 cout = MMC_DEFAULT_HS400_CMD_OUT_TAP;
2700 dout = MMC_DEFAULT_HS400_DATA_OUT_TAP;
2705 pr_err("%s(%s): Invalid mode %d\n", __func__,
2706 mmc->dev->name, mmc->selected_mode);
2709 debug("%s(%s): Not tuned, hs200: %d, hs200 tuned: %d, hs400: %d, hs400 tuned: %d, tuned: %d\n",
2710 __func__, mmc->dev->name, is_hs200,
2712 is_hs400, slot->hs400_tuned, slot->tuned);
2713 /* Set some defaults */
2715 slot->hs200_taps.u = 0;
2716 slot->hs200_taps.s.cmd_out_tap = cout;
2717 slot->hs200_taps.s.data_out_tap = dout;
2718 slot->hs200_taps.s.cmd_in_tap = half;
2719 slot->hs200_taps.s.data_in_tap = half;
2720 } else if (is_hs400) {
2721 slot->hs400_taps.u = 0;
2722 slot->hs400_taps.s.cmd_out_tap = cout;
2723 slot->hs400_taps.s.data_out_tap = dout;
2724 slot->hs400_taps.s.cmd_in_tap = half;
2725 slot->hs400_taps.s.data_in_tap = half;
2728 slot->taps.s.cmd_out_tap = cout;
2729 slot->taps.s.data_out_tap = dout;
2730 slot->taps.s.cmd_in_tap = half;
2731 slot->taps.s.data_in_tap = half;
2736 debug("%s(%s): hs200 taps: ci: %u, co: %u, di: %u, do: %u\n",
2737 __func__, mmc->dev->name,
2738 slot->hs200_taps.s.cmd_in_tap,
2739 slot->hs200_taps.s.cmd_out_tap,
2740 slot->hs200_taps.s.data_in_tap,
2741 slot->hs200_taps.s.data_out_tap);
2743 debug("%s(%s): hs400 taps: ci: %u, co: %u, di: %u, do: %u\n",
2744 __func__, mmc->dev->name,
2745 slot->hs400_taps.s.cmd_in_tap,
2746 slot->hs400_taps.s.cmd_out_tap,
2747 slot->hs400_taps.s.data_in_tap,
2748 slot->hs400_taps.s.data_out_tap);
2750 debug("%s(%s): taps: ci: %u, co: %u, di: %u, do: %u\n",
2751 __func__, mmc->dev->name, slot->taps.s.cmd_in_tap,
2752 slot->taps.s.cmd_out_tap,
2753 slot->taps.s.data_in_tap,
2754 slot->taps.s.data_out_tap);
2755 octeontx_mmc_set_timing(mmc);
2756 debug("%s: Done\n", __func__);
2763 * Sets the MMC watchdog timer in microseconds
2765 * @param mmc mmc device
2766 * @param us timeout in microseconds, 0 for maximum timeout
2768 static void set_wdog(struct mmc *mmc, u64 us)
2770 union mio_emm_wdog wdog;
2773 val = (us * mmc->clock) / 1000000;
2774 if (val >= (1 << 26) || !us) {
2776 pr_debug("%s: warning: timeout %llu exceeds max value %llu, truncating\n",
2778 (u64)(((1ULL << 26) - 1) * 1000000ULL) /
2780 val = (1 << 26) - 1;
2783 wdog.s.clk_cnt = val;
2784 write_csr(mmc, MIO_EMM_WDOG(), wdog.u);
2788 * Set the IO drive strength and slew
2790 * @param mmc mmc device
2792 static void octeontx_mmc_io_drive_setup(struct mmc *mmc)
2794 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
2795 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2796 union mio_emm_io_ctl io_ctl;
2798 if (slot->drive < 0 || slot->slew < 0)
2802 io_ctl.s.drive = slot->drive;
2803 io_ctl.s.slew = slot->slew;
2804 write_csr(mmc, MIO_EMM_IO_CTL(), io_ctl.u);
2809 * Print switch errors
2811 * @param mmc mmc device
2813 static void check_switch_errors(struct mmc *mmc)
2815 union mio_emm_switch emm_switch;
2817 emm_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
2818 if (emm_switch.s.switch_err0)
2819 pr_err("%s: Switch power class error\n", mmc->cfg->name);
2820 if (emm_switch.s.switch_err1)
2821 pr_err("%s: Switch HS timing error\n", mmc->cfg->name);
2822 if (emm_switch.s.switch_err2)
2823 pr_err("%s: Switch bus width error\n", mmc->cfg->name);
2826 static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch)
2828 union mio_emm_rsp_sts rsp_sts;
2829 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
2830 int bus_id = emm_switch.s.bus_id;
2833 if (emm_switch.s.bus_id != 0) {
2834 emm_switch.s.bus_id = 0;
2835 write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
2837 emm_switch.s.bus_id = bus_id;
2839 debug("%s(%s, 0x%llx)\n", __func__, mmc->dev->name, emm_switch.u);
2840 write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
2842 start = get_timer(0);
2844 rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
2845 if (!rsp_sts.s.switch_val)
2848 } while (get_timer(start) < 10);
2849 if (rsp_sts.s.switch_val) {
2850 pr_warn("%s(%s): Warning: writing 0x%llx to emm_switch timed out, status: 0x%llx\n",
2851 __func__, mmc->dev->name, emm_switch.u, rsp_sts.u);
2853 slot->cached_switch = emm_switch;
2854 check_switch_errors(mmc);
2855 slot->cached_switch.u = emm_switch.u;
2856 debug("%s: emm_switch: 0x%llx, rsp_lo: 0x%llx\n",
2857 __func__, read_csr(mmc, MIO_EMM_SWITCH()),
2858 read_csr(mmc, MIO_EMM_RSP_LO()));
2862 * Given a delay in ps, return the tap delay count
2864 * @param mmc mmc data structure
2865 * @param delay delay in picoseconds
2867 * @return Number of tap cycles or error if -1
2869 static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay)
2871 struct octeontx_mmc_host *host = mmc_to_host(mmc);
2873 if (host->is_asim || host->is_emul)
2876 if (!host->timing_taps) {
2877 pr_err("%s(%s): Error: host timing not calibrated\n",
2878 __func__, mmc->dev->name);
2881 debug("%s(%s, %d) timing taps: %llu\n", __func__, mmc->dev->name,
2882 delay, host->timing_taps);
2883 return min_t(int, DIV_ROUND_UP(delay, host->timing_taps), 63);
2887 * Calibrates the delay based on the internal clock
2889 * @param mmc Pointer to mmc data structure
2891 * @return 0 for success or -ETIMEDOUT on error
2893 * NOTE: On error a default value will be calculated.
2895 static int octeontx_mmc_calibrate_delay(struct mmc *mmc)
2897 union mio_emm_calb emm_calb;
2898 union mio_emm_tap emm_tap;
2899 union mio_emm_cfg emm_cfg;
2900 union mio_emm_io_ctl emm_io_ctl;
2901 union mio_emm_switch emm_switch;
2902 union mio_emm_wdog emm_wdog;
2903 union mio_emm_sts_mask emm_sts_mask;
2904 union mio_emm_debug emm_debug;
2905 union mio_emm_timing emm_timing;
2906 struct octeontx_mmc_host *host = mmc_to_host(mmc);
2910 debug("%s: Calibrating delay\n", __func__);
2911 if (host->is_asim || host->is_emul) {
2912 debug(" No calibration for ASIM\n");
2916 if (host->calibrate_glitch) {
2917 emm_tap.s.delay = MMC_DEFAULT_TAP_DELAY;
2919 /* Save registers */
2920 emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
2921 emm_io_ctl.u = read_csr(mmc, MIO_EMM_IO_CTL());
2922 emm_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
2923 emm_wdog.u = read_csr(mmc, MIO_EMM_WDOG());
2924 emm_sts_mask.u = read_csr(mmc, MIO_EMM_STS_MASK());
2925 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
2926 emm_timing.u = read_csr(mmc, MIO_EMM_TIMING());
2927 bus_ena = emm_cfg.s.bus_ena;
2928 bus_id = emm_switch.s.bus_id;
2929 emm_cfg.s.bus_ena = 0;
2930 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
2932 emm_cfg.s.bus_ena = 1ULL << 3;
2933 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
2936 write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
2937 emm_calb.s.start = 1;
2938 write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
2939 start = get_timer(0);
2940 /* This should only take 3 microseconds */
2943 emm_tap.u = read_csr(mmc, MIO_EMM_TAP());
2944 } while (!emm_tap.s.delay && get_timer(start) < 10);
2946 emm_calb.s.start = 0;
2947 write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
2949 emm_cfg.s.bus_ena = 0;
2950 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
2952 /* Restore registers */
2953 emm_cfg.s.bus_ena = bus_ena;
2954 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
2955 if (host->tap_requires_noclk) {
2956 /* Turn off the clock */
2957 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
2958 emm_debug.s.emmc_clk_disable = 1;
2959 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2961 emm_debug.s.rdsync_rst = 1;
2962 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2966 write_csr(mmc, MIO_EMM_TIMING(), emm_timing.u);
2967 if (host->tap_requires_noclk) {
2968 /* Turn the clock back on */
2970 emm_debug.s.rdsync_rst = 0;
2971 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2973 emm_debug.s.emmc_clk_disable = 0;
2974 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2977 write_csr(mmc, MIO_EMM_IO_CTL(), emm_io_ctl.u);
2978 bus_id = emm_switch.s.bus_id;
2979 emm_switch.s.bus_id = 0;
2980 write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
2981 emm_switch.s.bus_id = bus_id;
2982 write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
2983 write_csr(mmc, MIO_EMM_WDOG(), emm_wdog.u);
2984 write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
2985 write_csr(mmc, MIO_EMM_RCA(), mmc->rca);
2986 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
2988 if (!emm_tap.s.delay) {
2989 pr_err("%s: Error: delay calibration failed, timed out.\n",
2991 /* Set to default value if timed out */
2992 emm_tap.s.delay = MMC_DEFAULT_TAP_DELAY;
2997 host->timing_taps = (10 * 1000 * emm_tap.s.delay) / TOTAL_NO_OF_TAPS;
2998 debug("%s(%s): timing taps: %llu, delay: %u\n",
2999 __func__, mmc->dev->name, host->timing_taps, emm_tap.s.delay);
3000 host->timing_calibrated = true;
3004 static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc)
3006 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3008 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
3009 union mio_emm_sample sample;
3012 sample.s.cmd_cnt = slot->cmd_clk_skew;
3013 sample.s.dat_cnt = slot->dat_clk_skew;
3014 write_csr(mmc, MIO_EMM_SAMPLE(), sample.u);
3016 union mio_emm_timing timing;
3018 timing.u = read_csr(mmc, MIO_EMM_TIMING());
3019 if (mmc->selected_mode == MMC_HS_200) {
3020 if (slot->hs200_tuned) {
3021 timing.s.cmd_in_tap =
3022 slot->hs200_taps.s.cmd_in_tap;
3023 timing.s.data_in_tap =
3024 slot->hs200_taps.s.data_in_tap;
3026 pr_warn("%s(%s): Warning: hs200 timing not tuned\n",
3027 __func__, mmc->dev->name);
3028 timing.s.cmd_in_tap =
3029 MMC_DEFAULT_HS200_CMD_IN_TAP;
3030 timing.s.data_in_tap =
3031 MMC_DEFAULT_HS200_DATA_IN_TAP;
3033 } else if (mmc->selected_mode == MMC_HS_400) {
3034 if (slot->hs400_tuned) {
3035 timing.s.cmd_in_tap =
3036 slot->hs400_taps.s.cmd_in_tap;
3037 timing.s.data_in_tap =
3038 slot->hs400_taps.s.data_in_tap;
3039 } else if (slot->hs200_tuned) {
3040 timing.s.cmd_in_tap =
3041 slot->hs200_taps.s.cmd_in_tap;
3042 timing.s.data_in_tap =
3043 slot->hs200_taps.s.data_in_tap;
3045 pr_warn("%s(%s): Warning: hs400 timing not tuned\n",
3046 __func__, mmc->dev->name);
3047 timing.s.cmd_in_tap =
3048 MMC_DEFAULT_HS200_CMD_IN_TAP;
3049 timing.s.data_in_tap =
3050 MMC_DEFAULT_HS200_DATA_IN_TAP;
3052 } else if (slot->tuned) {
3053 timing.s.cmd_in_tap = slot->taps.s.cmd_in_tap;
3054 timing.s.data_in_tap = slot->taps.s.data_in_tap;
3056 timing.s.cmd_in_tap = MMC_DEFAULT_CMD_IN_TAP;
3057 timing.s.data_in_tap = MMC_DEFAULT_DATA_IN_TAP;
3059 octeontx_mmc_set_emm_timing(mmc, timing);
3066 * Sets the default bus timing for the current mode.
3068 * @param mmc mmc data structure
3070 * @return 0 for success, error otherwise
3072 static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc)
3074 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3075 union mio_emm_timing timing;
3076 int cout_bdelay, dout_bdelay;
3077 unsigned int cout_delay, dout_delay;
3080 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX))
3083 debug("%s(%s)\n", __func__, mmc->dev->name);
3084 if (slot->is_asim || slot->is_emul)
3087 octeontx_mmc_calibrate_delay(mmc);
3089 if (mmc->clock < 26000000) {
3092 } else if (mmc->clock <= 52000000) {
3095 } else if (!mmc_is_mode_ddr(mmc->selected_mode)) {
3096 cout_delay = slot->cmd_out_hs200_delay;
3097 dout_delay = slot->data_out_hs200_delay;
3099 cout_delay = slot->cmd_out_hs400_delay;
3100 dout_delay = slot->data_out_hs400_delay;
3103 snprintf(env_name, sizeof(env_name), "mmc%d_hs200_dout_delay_ps",
3105 dout_delay = env_get_ulong(env_name, 10, dout_delay);
3106 debug("%s: dout_delay: %u\n", __func__, dout_delay);
3108 cout_bdelay = octeontx2_mmc_calc_delay(mmc, cout_delay);
3109 dout_bdelay = octeontx2_mmc_calc_delay(mmc, dout_delay);
3111 debug("%s: cmd output delay: %u, data output delay: %u, cmd bdelay: %d, data bdelay: %d, clock: %d\n",
3112 __func__, cout_delay, dout_delay, cout_bdelay, dout_bdelay,
3114 if (cout_bdelay < 0 || dout_bdelay < 0) {
3115 pr_err("%s: Error: could not calculate command and/or data clock skew\n",
3119 timing.u = read_csr(mmc, MIO_EMM_TIMING());
3120 timing.s.cmd_out_tap = cout_bdelay;
3121 timing.s.data_out_tap = dout_bdelay;
3122 if (mmc->selected_mode == MMC_HS_200) {
3123 slot->hs200_taps.s.cmd_out_tap = cout_bdelay;
3124 slot->hs200_taps.s.data_out_tap = dout_bdelay;
3125 } else if (mmc->selected_mode == MMC_HS_400) {
3126 slot->hs400_taps.s.cmd_out_tap = cout_bdelay;
3127 slot->hs400_taps.s.data_out_tap = dout_bdelay;
3129 slot->taps.s.cmd_out_tap = cout_bdelay;
3130 slot->taps.s.data_out_tap = dout_bdelay;
3132 octeontx_mmc_set_emm_timing(mmc, timing);
3133 debug("%s(%s): bdelay: %d/%d, clock: %d, ddr: %s, timing taps: %llu, do: %d, di: %d, co: %d, ci: %d\n",
3134 __func__, mmc->dev->name, cout_bdelay, dout_bdelay, mmc->clock,
3135 mmc->ddr_mode ? "yes" : "no",
3136 mmc_to_host(mmc)->timing_taps,
3137 timing.s.data_out_tap,
3138 timing.s.data_in_tap,
3139 timing.s.cmd_out_tap,
3140 timing.s.cmd_in_tap);
3145 static void octeontx_mmc_set_clock(struct mmc *mmc)
3147 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3150 clock = min(mmc->cfg->f_max, (uint)slot->clock);
3151 clock = max(mmc->cfg->f_min, clock);
3152 debug("%s(%s): f_min: %u, f_max: %u, clock: %u\n", __func__,
3153 mmc->dev->name, mmc->cfg->f_min, mmc->cfg->f_max, clock);
3154 slot->clock = clock;
3159 * This switches I/O power as needed when switching between slots.
3161 * @param mmc mmc data structure
3163 static void octeontx_mmc_switch_io(struct mmc *mmc)
3165 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3166 struct octeontx_mmc_host *host = slot->host;
3167 struct mmc *last_mmc = host->last_mmc;
3168 static struct udevice *last_reg;
3169 union mio_emm_cfg emm_cfg;
3171 static bool initialized;
3174 if (!initialized || mmc != host->last_mmc) {
3177 /* Switch to bus 3 which is unused */
3178 emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
3179 emm_cfg.s.bus_ena = 1 << 3;
3180 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
3182 /* Turn off all other I/O interfaces with first initialization
3183 * if at least one supply was found.
3185 for (bus = 0; bus <= OCTEONTX_MAX_MMC_SLOT; bus++) {
3186 ommc = &host->slots[bus].mmc;
3188 /* Handle self case later */
3189 if (ommc == mmc || !ommc->vqmmc_supply)
3192 /* Skip if we're not switching regulators */
3193 if (last_reg == mmc->vqmmc_supply)
3196 /* Turn off other regulators */
3197 if (ommc->vqmmc_supply != mmc->vqmmc_supply)
3198 regulator_set_enable(ommc->vqmmc_supply, false);
3200 /* Turn ourself on */
3201 if (mmc->vqmmc_supply && last_reg != mmc->vqmmc_supply)
3202 regulator_set_enable(mmc->vqmmc_supply, true);
3203 mdelay(1); /* Settle time */
3204 /* Switch to new bus */
3205 emm_cfg.s.bus_ena = 1 << slot->bus_id;
3206 write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
3207 last_reg = mmc->vqmmc_supply;
3212 /* No change in device */
3213 if (last_mmc == mmc)
3217 pr_warn("%s(%s): No previous slot detected in IO slot switch!\n",
3218 __func__, mmc->dev->name);
3222 debug("%s(%s): last: %s, supply: %p\n", __func__, mmc->dev->name,
3223 last_mmc->dev->name, mmc->vqmmc_supply);
3225 /* The supply is the same so we do nothing */
3226 if (last_mmc->vqmmc_supply == mmc->vqmmc_supply)
3229 /* Turn off the old slot I/O supply */
3230 if (last_mmc->vqmmc_supply) {
3231 debug("%s(%s): Turning off IO to %s, supply: %s\n",
3232 __func__, mmc->dev->name, last_mmc->dev->name,
3233 last_mmc->vqmmc_supply->name);
3234 regulator_set_enable(last_mmc->vqmmc_supply, false);
3236 /* Turn on the new slot I/O supply */
3237 if (mmc->vqmmc_supply) {
3238 debug("%s(%s): Turning on IO to slot %d, supply: %s\n",
3239 __func__, mmc->dev->name, slot->bus_id,
3240 mmc->vqmmc_supply->name);
3241 regulator_set_enable(mmc->vqmmc_supply, true);
3243 /* Allow power to settle */
3248 * Called to switch between mmc devices
3250 * @param mmc new mmc device
3252 static void octeontx_mmc_switch_to(struct mmc *mmc)
3254 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3255 struct octeontx_mmc_slot *old_slot;
3256 struct octeontx_mmc_host *host = slot->host;
3257 union mio_emm_switch emm_switch;
3258 union mio_emm_sts_mask emm_sts_mask;
3259 union mio_emm_rca emm_rca;
3261 if (slot->bus_id == host->last_slotid)
3264 debug("%s(%s) switching from slot %d to slot %d\n", __func__,
3265 mmc->dev->name, host->last_slotid, slot->bus_id);
3266 octeontx_mmc_switch_io(mmc);
3268 if (host->last_slotid >= 0 && slot->valid) {
3269 old_slot = &host->slots[host->last_slotid];
3270 old_slot->cached_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
3271 old_slot->cached_rca.u = read_csr(mmc, MIO_EMM_RCA());
3274 write_csr(mmc, MIO_EMM_RCA(), mmc->rca);
3275 emm_switch = slot->cached_switch;
3276 do_switch(mmc, emm_switch);
3278 emm_rca.s.card_rca = mmc->rca;
3279 write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
3282 set_wdog(mmc, 100000);
3283 if (octeontx_mmc_set_output_bus_timing(mmc) ||
3284 octeontx_mmc_set_input_bus_timing(mmc))
3285 pr_err("%s(%s): Error setting bus timing\n", __func__,
3287 octeontx_mmc_io_drive_setup(mmc);
3290 emm_sts_mask.s.sts_msk = 1 << 7 | 1 << 22 | 1 << 23 | 1 << 19;
3291 write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
3292 host->last_slotid = slot->bus_id;
3293 host->last_mmc = mmc;
3298 * Perform initial timing configuration
3300 * @param mmc mmc device
3302 * @return 0 for success
3304 * NOTE: This will need to be updated when new silicon comes out
3306 static int octeontx_mmc_init_timing(struct mmc *mmc)
3308 union mio_emm_timing timing;
3310 if (mmc_to_slot(mmc)->is_asim || mmc_to_slot(mmc)->is_emul)
3313 debug("%s(%s)\n", __func__, mmc->dev->name);
3315 timing.s.cmd_out_tap = MMC_DEFAULT_CMD_OUT_TAP;
3316 timing.s.data_out_tap = MMC_DEFAULT_DATA_OUT_TAP;
3317 timing.s.cmd_in_tap = MMC_DEFAULT_CMD_IN_TAP;
3318 timing.s.data_in_tap = MMC_DEFAULT_DATA_IN_TAP;
3319 octeontx_mmc_set_emm_timing(mmc, timing);
3324 * Perform low-level initialization
3326 * @param mmc mmc device
3328 * @return 0 for success, error otherwise
3330 static int octeontx_mmc_init_lowlevel(struct mmc *mmc)
3332 struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
3333 struct octeontx_mmc_host *host = slot->host;
3334 union mio_emm_switch emm_switch;
3337 debug("%s(%s): lowlevel init for slot %d\n", __func__,
3338 mmc->dev->name, slot->bus_id);
3339 host->emm_cfg.s.bus_ena &= ~(1 << slot->bus_id);
3340 write_csr(mmc, MIO_EMM_CFG(), host->emm_cfg.u);
3342 host->emm_cfg.s.bus_ena |= 1 << slot->bus_id;
3343 write_csr(mmc, MIO_EMM_CFG(), host->emm_cfg.u);
3345 slot->clock = mmc->cfg->f_min;
3346 octeontx_mmc_set_clock(&slot->mmc);
3348 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
3349 if (host->cond_clock_glitch) {
3350 union mio_emm_debug emm_debug;
3352 emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
3353 emm_debug.s.clk_on = 1;
3354 write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
3356 octeontx_mmc_calibrate_delay(&slot->mmc);
3359 clk_period = octeontx_mmc_calc_clk_period(mmc);
3361 emm_switch.s.power_class = 10;
3362 emm_switch.s.clk_lo = clk_period / 2;
3363 emm_switch.s.clk_hi = clk_period / 2;
3365 emm_switch.s.bus_id = slot->bus_id;
3366 debug("%s: Performing switch\n", __func__);
3367 do_switch(mmc, emm_switch);
3368 slot->cached_switch.u = emm_switch.u;
3370 if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX))
3371 octeontx_mmc_init_timing(mmc);
3373 set_wdog(mmc, 1000000); /* Set to 1 second */
3374 write_csr(mmc, MIO_EMM_STS_MASK(), 0xe4390080ull);
3375 write_csr(mmc, MIO_EMM_RCA(), 1);
3377 debug("%s: done\n", __func__);
3382 * Translates a voltage number to bits in MMC register
3384 * @param voltage voltage in microvolts
3386 * @return MMC register value for voltage
3388 static u32 xlate_voltage(u32 voltage)
3392 /* Convert to millivolts */
3394 if (voltage >= 1650 && voltage <= 1950)
3395 volt |= MMC_VDD_165_195;
3396 if (voltage >= 2000 && voltage <= 2100)
3397 volt |= MMC_VDD_20_21;
3398 if (voltage >= 2100 && voltage <= 2200)
3399 volt |= MMC_VDD_21_22;
3400 if (voltage >= 2200 && voltage <= 2300)
3401 volt |= MMC_VDD_22_23;
3402 if (voltage >= 2300 && voltage <= 2400)
3403 volt |= MMC_VDD_23_24;
3404 if (voltage >= 2400 && voltage <= 2500)
3405 volt |= MMC_VDD_24_25;
3406 if (voltage >= 2500 && voltage <= 2600)
3407 volt |= MMC_VDD_25_26;
3408 if (voltage >= 2600 && voltage <= 2700)
3409 volt |= MMC_VDD_26_27;
3410 if (voltage >= 2700 && voltage <= 2800)
3411 volt |= MMC_VDD_27_28;
3412 if (voltage >= 2800 && voltage <= 2900)
3413 volt |= MMC_VDD_28_29;
3414 if (voltage >= 2900 && voltage <= 3000)
3415 volt |= MMC_VDD_29_30;
3416 if (voltage >= 3000 && voltage <= 3100)
3417 volt |= MMC_VDD_30_31;
3418 if (voltage >= 3100 && voltage <= 3200)
3419 volt |= MMC_VDD_31_32;
3420 if (voltage >= 3200 && voltage <= 3300)
3421 volt |= MMC_VDD_32_33;
3422 if (voltage >= 3300 && voltage <= 3400)
3423 volt |= MMC_VDD_33_34;
3424 if (voltage >= 3400 && voltage <= 3500)
3425 volt |= MMC_VDD_34_35;
3426 if (voltage >= 3500 && voltage <= 3600)
3427 volt |= MMC_VDD_35_36;
3433 * Check if a slot is valid in the device tree
3435 * @param dev slot device to check
3437 * @return true if status reports "ok" or "okay" or if no status,
3440 static bool octeontx_mmc_get_valid(struct udevice *dev)
3442 const char *stat = ofnode_read_string(dev_ofnode(dev), "status");
3444 if (!stat || !strncmp(stat, "ok", 2))
3451 * Reads slot configuration from the device tree
3453 * @param dev slot device
3455 * @return 0 on success, otherwise error
3457 static int octeontx_mmc_get_config(struct udevice *dev)
3459 struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
3464 ofnode node = dev_ofnode(dev);
3468 debug("%s(%s)", __func__, dev->name);
3469 slot->cfg.name = dev->name;
3471 slot->cfg.f_max = ofnode_read_s32_default(dev_ofnode(dev),
3474 snprintf(env_name, sizeof(env_name), "mmc_max_frequency%d",
3477 new_max_freq = env_get_ulong(env_name, 10, slot->cfg.f_max);
3478 debug("Reading %s, got %lu\n", env_name, new_max_freq);
3480 if (new_max_freq != slot->cfg.f_max) {
3481 printf("Overriding device tree MMC maximum frequency %u to %lu\n",
3482 slot->cfg.f_max, new_max_freq);
3483 slot->cfg.f_max = new_max_freq;
3485 slot->cfg.f_min = 400000;
3486 slot->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
3488 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
3489 slot->hs400_tuning_block =
3490 ofnode_read_s32_default(dev_ofnode(dev),
3491 "marvell,hs400-tuning-block",
3493 debug("%s(%s): mmc HS400 tuning block: %d\n", __func__,
3494 dev->name, slot->hs400_tuning_block);
3496 slot->hs200_tap_adj =
3497 ofnode_read_s32_default(dev_ofnode(dev),
3498 "marvell,hs200-tap-adjust", 0);
3499 debug("%s(%s): hs200-tap-adjust: %d\n", __func__, dev->name,
3500 slot->hs200_tap_adj);
3501 slot->hs400_tap_adj =
3502 ofnode_read_s32_default(dev_ofnode(dev),
3503 "marvell,hs400-tap-adjust", 0);
3504 debug("%s(%s): hs400-tap-adjust: %d\n", __func__, dev->name,
3505 slot->hs400_tap_adj);
3508 err = ofnode_read_u32_array(dev_ofnode(dev), "voltage-ranges",
3511 slot->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
3513 low = xlate_voltage(voltages[0]);
3514 high = xlate_voltage(voltages[1]);
3515 debug(" low voltage: 0x%x (%u), high: 0x%x (%u)\n",
3516 low, voltages[0], high, voltages[1]);
3517 if (low > high || !low || !high) {
3518 pr_err("Invalid MMC voltage range [%u-%u] specified for %s\n",
3519 low, high, dev->name);
3522 slot->cfg.voltages = 0;
3524 slot->cfg.voltages |= low;
3526 } while (low <= high);
3528 debug("%s: config voltages: 0x%x\n", __func__, slot->cfg.voltages);
3529 slot->slew = ofnode_read_s32_default(node, "cavium,clk-slew", -1);
3530 slot->drive = ofnode_read_s32_default(node, "cavium,drv-strength", -1);
3531 gpio_request_by_name(dev, "cd-gpios", 0, &slot->cd_gpio, GPIOD_IS_IN);
3532 slot->cd_inverted = ofnode_read_bool(node, "cd-inverted");
3533 gpio_request_by_name(dev, "wp-gpios", 0, &slot->wp_gpio, GPIOD_IS_IN);
3534 slot->wp_inverted = ofnode_read_bool(node, "wp-inverted");
3535 if (slot->cfg.voltages & MMC_VDD_165_195) {
3536 slot->is_1_8v = true;
3537 slot->is_3_3v = false;
3538 } else if (slot->cfg.voltages & (MMC_VDD_30_31 | MMC_VDD_31_32 |
3539 MMC_VDD_33_34 | MMC_VDD_34_35 |
3541 slot->is_1_8v = false;
3542 slot->is_3_3v = true;
3545 bus_width = ofnode_read_u32_default(node, "bus-width", 1);
3546 /* Note fall-through */
3547 switch (bus_width) {
3549 slot->cfg.host_caps |= MMC_MODE_8BIT;
3551 slot->cfg.host_caps |= MMC_MODE_4BIT;
3553 slot->cfg.host_caps |= MMC_MODE_1BIT;
3556 if (ofnode_read_bool(node, "no-1-8-v")) {
3557 slot->is_3_3v = true;
3558 slot->is_1_8v = false;
3559 if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34)))
3560 pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n",
3561 __func__, dev->name);
3563 if (ofnode_read_bool(node, "mmc-ddr-3-3v")) {
3564 slot->is_3_3v = true;
3565 slot->is_1_8v = false;
3566 if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34)))
3567 pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n",
3568 __func__, dev->name);
3570 if (ofnode_read_bool(node, "cap-sd-highspeed") ||
3571 ofnode_read_bool(node, "cap-mmc-highspeed") ||
3572 ofnode_read_bool(node, "sd-uhs-sdr25"))
3573 slot->cfg.host_caps |= MMC_MODE_HS;
3574 if (slot->cfg.f_max >= 50000000 &&
3575 slot->cfg.host_caps & MMC_MODE_HS)
3576 slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
3577 if (ofnode_read_bool(node, "sd-uhs-sdr50"))
3578 slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
3579 if (ofnode_read_bool(node, "sd-uhs-ddr50"))
3580 slot->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz |
3583 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
3584 if (!slot->is_asim && !slot->is_emul) {
3585 if (ofnode_read_bool(node, "mmc-hs200-1_8v"))
3586 slot->cfg.host_caps |= MMC_MODE_HS200 |
3588 if (ofnode_read_bool(node, "mmc-hs400-1_8v"))
3589 slot->cfg.host_caps |= MMC_MODE_HS400 |
3593 slot->cmd_out_hs200_delay =
3594 ofnode_read_u32_default(node,
3595 "marvell,cmd-out-hs200-dly",
3596 MMC_DEFAULT_HS200_CMD_OUT_DLY);
3597 debug("%s(%s): HS200 cmd out delay: %d\n",
3598 __func__, dev->name, slot->cmd_out_hs200_delay);
3599 slot->data_out_hs200_delay =
3600 ofnode_read_u32_default(node,
3601 "marvell,data-out-hs200-dly",
3602 MMC_DEFAULT_HS200_DATA_OUT_DLY);
3603 debug("%s(%s): HS200 data out delay: %d\n",
3604 __func__, dev->name, slot->data_out_hs200_delay);
3605 slot->cmd_out_hs400_delay =
3606 ofnode_read_u32_default(node,
3607 "marvell,cmd-out-hs400-dly",
3608 MMC_DEFAULT_HS400_CMD_OUT_DLY);
3609 debug("%s(%s): HS400 cmd out delay: %d\n",
3610 __func__, dev->name, slot->cmd_out_hs400_delay);
3611 slot->data_out_hs400_delay =
3612 ofnode_read_u32_default(node,
3613 "marvell,data-out-hs400-dly",
3614 MMC_DEFAULT_HS400_DATA_OUT_DLY);
3615 debug("%s(%s): HS400 data out delay: %d\n",
3616 __func__, dev->name, slot->data_out_hs400_delay);
3620 slot->disable_ddr = ofnode_read_bool(node, "marvell,disable-ddr");
3621 slot->non_removable = ofnode_read_bool(node, "non-removable");
3622 slot->cmd_clk_skew = ofnode_read_u32_default(node,
3623 "cavium,cmd-clk-skew", 0);
3624 slot->dat_clk_skew = ofnode_read_u32_default(node,
3625 "cavium,dat-clk-skew", 0);
3626 debug("%s(%s): host caps: 0x%x\n", __func__,
3627 dev->name, slot->cfg.host_caps);
3634 * @param dev mmc device
3636 * @return 0 for success, error otherwise
3638 static int octeontx_mmc_slot_probe(struct udevice *dev)
3640 struct octeontx_mmc_slot *slot;
3644 debug("%s(%s)\n", __func__, dev->name);
3646 pr_err("%s(%s): Error: host not probed yet\n",
3647 __func__, dev->name);
3649 slot = dev_to_mmc_slot(dev);
3653 slot->valid = false;
3654 if (!octeontx_mmc_get_valid(dev)) {
3655 debug("%s(%s): slot is invalid\n", __func__, dev->name);
3659 debug("%s(%s): Getting config\n", __func__, dev->name);
3660 err = octeontx_mmc_get_config(dev);
3662 pr_err("probe(%s): Error getting config\n", dev->name);
3666 debug("%s(%s): mmc bind, mmc: %p\n", __func__, dev->name, &slot->mmc);
3667 err = mmc_bind(dev, &slot->mmc, &slot->cfg);
3669 pr_err("%s(%s): Error binding mmc\n", __func__, dev->name);
3673 /* For some reason, mmc_bind always assigns priv to the device */
3674 slot->mmc.priv = slot;
3676 debug("%s(%s): lowlevel init\n", __func__, dev->name);
3677 err = octeontx_mmc_init_lowlevel(mmc);
3679 pr_err("probe(%s): Low-level init failed\n", dev->name);
3686 " base address : %p\n"
3687 " bus id : %d\n", __func__, dev->name,
3688 slot->base_addr, slot->bus_id);
3694 * MMC slot driver operations
3696 static const struct dm_mmc_ops octeontx_hsmmc_ops = {
3697 .send_cmd = octeontx_mmc_dev_send_cmd,
3698 .set_ios = octeontx_mmc_set_ios,
3699 .get_cd = octeontx_mmc_get_cd,
3700 .get_wp = octeontx_mmc_get_wp,
3701 #ifdef MMC_SUPPORTS_TUNING
3702 .execute_tuning = octeontx_mmc_execute_tuning,
3706 static const struct udevice_id octeontx_hsmmc_ids[] = {
3707 { .compatible = "mmc-slot" },
3711 U_BOOT_DRIVER(octeontx_hsmmc_slot) = {
3712 .name = "octeontx_hsmmc_slot",
3714 .of_match = of_match_ptr(octeontx_hsmmc_ids),
3715 .probe = octeontx_mmc_slot_probe,
3716 .ops = &octeontx_hsmmc_ops,
3719 /*****************************************************************
3722 * The PCI host driver contains the resources used by all of the
3725 * The slot drivers are pseudo drivers.
3729 * Probe the MMC host controller
3731 * @param dev mmc host controller device
3733 * @return 0 for success, -1 on error
3735 static int octeontx_mmc_host_probe(struct udevice *dev)
3737 struct octeontx_mmc_host *host = dev_get_priv(dev);
3738 union mio_emm_int emm_int;
3741 debug("%s(%s): Entry host: %p\n", __func__, dev->name, host);
3743 if (!octeontx_mmc_get_valid(dev)) {
3744 debug("%s(%s): mmc host not valid\n", __func__, dev->name);
3747 memset(host, 0, sizeof(*host));
3748 host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
3750 if (!host->base_addr) {
3751 pr_err("%s: Error: MMC base address not found\n", __func__);
3755 debug("%s(%s): Base address: %p\n", __func__, dev->name,
3757 if (!dev_has_ofnode(dev)) {
3758 pr_err("%s: No device tree information found\n", __func__);
3761 host->node = dev_ofnode(dev);
3762 host->last_slotid = -1;
3763 if (otx_is_platform(PLATFORM_ASIM))
3764 host->is_asim = true;
3765 if (otx_is_platform(PLATFORM_EMULATOR))
3766 host->is_emul = true;
3767 host->dma_wait_delay =
3768 ofnode_read_u32_default(dev_ofnode(dev),
3769 "marvell,dma-wait-delay", 1);
3770 /* Force reset of eMMC */
3771 writeq(0, host->base_addr + MIO_EMM_CFG());
3772 debug("%s: Clearing MIO_EMM_CFG\n", __func__);
3774 emm_int.u = readq(host->base_addr + MIO_EMM_INT());
3775 debug("%s: Writing 0x%llx to MIO_EMM_INT\n", __func__, emm_int.u);
3776 writeq(emm_int.u, host->base_addr + MIO_EMM_INT());
3778 debug("%s(%s): Getting I/O clock\n", __func__, dev->name);
3779 host->sys_freq = octeontx_get_io_clock();
3780 debug("%s(%s): I/O clock %llu\n", __func__, dev->name, host->sys_freq);
3782 if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
3783 /* Flags for issues to work around */
3784 dm_pci_read_config8(dev, PCI_REVISION_ID, &rev);
3785 if (otx_is_soc(CN96XX)) {
3786 debug("%s: CN96XX revision %d\n", __func__, rev);
3789 host->calibrate_glitch = true;
3790 host->cond_clock_glitch = true;
3797 host->hs400_skew_needed = true;
3798 debug("HS400 skew support enabled\n");
3801 debug("CN96XX rev C0+ detected\n");
3802 host->tap_requires_noclk = true;
3805 } else if (otx_is_soc(CN95XX)) {
3807 host->cond_clock_glitch = true;
3817 * This performs some initial setup before a probe occurs.
3819 * @param dev: MMC slot device
3821 * @return 0 for success, -1 on failure
3823 * Do some pre-initialization before probing a slot.
3825 static int octeontx_mmc_host_child_pre_probe(struct udevice *dev)
3827 struct octeontx_mmc_host *host = dev_get_priv(dev_get_parent(dev));
3828 struct octeontx_mmc_slot *slot;
3829 struct mmc_uclass_priv *upriv;
3830 ofnode node = dev_ofnode(dev);
3835 debug("%s(%s) Pre-Probe\n", __func__, dev->name);
3836 if (ofnode_read_u32(node, "reg", &bus_id)) {
3837 pr_err("%s(%s): Error: \"reg\" not found in device tree\n",
3838 __func__, dev->name);
3841 if (bus_id > OCTEONTX_MAX_MMC_SLOT) {
3842 pr_err("%s(%s): Error: \"reg\" out of range of 0..%d\n",
3843 __func__, dev->name, OCTEONTX_MAX_MMC_SLOT);
3847 slot = &host->slots[bus_id];
3848 dev_set_priv(dev, slot);
3850 slot->bus_id = bus_id;
3852 slot->base_addr = host->base_addr;
3853 slot->is_asim = host->is_asim;
3854 slot->is_emul = host->is_emul;
3856 snprintf(name, sizeof(name), "octeontx-mmc%d", bus_id);
3857 err = device_set_name(dev, name);
3859 /* FIXME: This code should not be needed */
3860 if (!dev_get_uclass_priv(dev)) {
3861 debug("%s(%s): Allocating uclass priv\n", __func__,
3863 upriv = calloc(1, sizeof(struct mmc_uclass_priv));
3868 * FIXME: This is not allowed
3869 * dev_set_uclass_priv(dev, upriv);
3870 * uclass_set_priv(dev->uclass, upriv);
3873 upriv = dev_get_uclass_priv(dev);
3876 upriv->mmc = &slot->mmc;
3877 debug("%s: uclass priv: %p, mmc: %p\n", dev->name, upriv, upriv->mmc);
3879 debug("%s: ret: %d\n", __func__, err);
3883 static const struct udevice_id octeontx_hsmmc_host_ids[] = {
3884 { .compatible = "cavium,thunder-8890-mmc" },
3888 U_BOOT_DRIVER(octeontx_hsmmc_host) = {
3889 .name = "octeontx_hsmmc_host",
3890 /* FIXME: Why is this not UCLASS_MMC? */
3892 .of_match = of_match_ptr(octeontx_hsmmc_host_ids),
3893 .probe = octeontx_mmc_host_probe,
3894 .priv_auto = sizeof(struct octeontx_mmc_host),
3895 .child_pre_probe = octeontx_mmc_host_child_pre_probe,
3896 .flags = DM_FLAG_PRE_RELOC,
3899 static struct pci_device_id octeontx_mmc_supported[] = {
3900 { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_EMMC) },
3904 U_BOOT_PCI_DEVICE(octeontx_hsmmc_host, octeontx_mmc_supported);