2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * See file CREDITS for list of people who contributed to this
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/errno.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/imx-regs.h>
43 #include <asm/arch/sys_proto.h>
44 #include <asm/arch/dma.h>
45 #include <bouncebuf.h>
49 struct mxs_ssp_regs *regs;
50 uint32_t clkseq_bypass;
51 uint32_t *clkctrl_ssp;
53 int (*mmc_is_wp)(int);
54 struct mxs_dma_desc *desc;
57 #define MXSMMC_MAX_TIMEOUT 10000
58 #define MXSMMC_SMALL_TRANSFER 512
60 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
62 struct mxs_ssp_regs *ssp_regs = priv->regs;
64 int timeout = MXSMMC_MAX_TIMEOUT;
66 uint32_t data_count = data->blocksize * data->blocks;
68 if (data->flags & MMC_DATA_READ) {
69 data_ptr = (uint32_t *)data->dest;
70 while (data_count && --timeout) {
71 reg = readl(&ssp_regs->hw_ssp_status);
72 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
73 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
75 timeout = MXSMMC_MAX_TIMEOUT;
80 data_ptr = (uint32_t *)data->src;
82 while (data_count && --timeout) {
83 reg = readl(&ssp_regs->hw_ssp_status);
84 if (!(reg & SSP_STATUS_FIFO_FULL)) {
85 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
87 timeout = MXSMMC_MAX_TIMEOUT;
93 return timeout ? 0 : COMM_ERR;
96 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
98 uint32_t data_count = data->blocksize * data->blocks;
100 struct mxs_dma_desc *desc = priv->desc;
103 struct bounce_buffer bbstate;
105 memset(desc, 0, sizeof(struct mxs_dma_desc));
106 desc->address = (dma_addr_t)desc;
108 if (data->flags & MMC_DATA_READ) {
109 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
111 flags = GEN_BB_WRITE;
113 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
114 addr = (void *)data->src;
118 bounce_buffer_start(&bbstate, addr, data_count, flags);
120 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
122 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
123 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
125 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
126 mxs_dma_desc_append(dmach, priv->desc);
127 if (mxs_dma_go(dmach)) {
128 bounce_buffer_stop(&bbstate);
132 bounce_buffer_stop(&bbstate);
138 * Sends a command out on the bus. Takes the mmc pointer,
139 * a command pointer, and an optional data pointer.
142 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
144 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
145 struct mxs_ssp_regs *ssp_regs = priv->regs;
151 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
154 timeout = MXSMMC_MAX_TIMEOUT;
157 reg = readl(&ssp_regs->hw_ssp_status);
159 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
160 SSP_STATUS_CMD_BUSY))) {
166 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
170 /* See if card is present */
171 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
172 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
176 /* Start building CTRL0 contents */
177 ctrl0 = priv->buswidth;
180 if (!(cmd->resp_type & MMC_RSP_CRC))
181 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
182 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
183 ctrl0 |= SSP_CTRL0_GET_RESP;
184 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
185 ctrl0 |= SSP_CTRL0_LONG_RESP;
187 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
188 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
190 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
193 reg = readl(&ssp_regs->hw_ssp_cmd0);
194 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
195 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
196 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
197 reg |= SSP_CMD0_APPEND_8CYC;
198 writel(reg, &ssp_regs->hw_ssp_cmd0);
200 /* Command argument */
201 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
206 if (data->flags & MMC_DATA_READ) {
207 ctrl0 |= SSP_CTRL0_READ;
208 } else if (priv->mmc_is_wp &&
209 priv->mmc_is_wp(mmc->block_dev.dev)) {
210 printf("MMC%d: Can not write a locked card!\n",
215 ctrl0 |= SSP_CTRL0_DATA_XFER;
216 reg = ((data->blocks - 1) <<
217 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
218 ((ffs(data->blocksize) - 1) <<
219 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
220 writel(reg, &ssp_regs->hw_ssp_block_size);
222 reg = data->blocksize * data->blocks;
223 writel(reg, &ssp_regs->hw_ssp_xfer_size);
226 /* Kick off the command */
227 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
228 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
230 /* Wait for the command to complete */
231 timeout = MXSMMC_MAX_TIMEOUT;
234 reg = readl(&ssp_regs->hw_ssp_status);
235 if (!(reg & SSP_STATUS_CMD_BUSY))
240 printf("MMC%d: Command %d busy\n",
241 mmc->block_dev.dev, cmd->cmdidx);
245 /* Check command timeout */
246 if (reg & SSP_STATUS_RESP_TIMEOUT) {
247 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
248 mmc->block_dev.dev, cmd->cmdidx, reg);
252 /* Check command errors */
253 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
254 printf("MMC%d: Command %d error (status 0x%08x)!\n",
255 mmc->block_dev.dev, cmd->cmdidx, reg);
259 /* Copy response to response buffer */
260 if (cmd->resp_type & MMC_RSP_136) {
261 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
262 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
263 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
264 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
266 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
268 /* Return if no data to process */
272 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
273 ret = mxsmmc_send_cmd_pio(priv, data);
275 printf("MMC%d: Data timeout with command %d "
276 "(status 0x%08x)!\n",
277 mmc->block_dev.dev, cmd->cmdidx, reg);
281 ret = mxsmmc_send_cmd_dma(priv, data);
283 printf("MMC%d: DMA transfer failed\n",
289 /* Check data errors */
290 reg = readl(&ssp_regs->hw_ssp_status);
292 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
293 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
294 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
295 mmc->block_dev.dev, cmd->cmdidx, reg);
302 static void mxsmmc_set_ios(struct mmc *mmc)
304 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
305 struct mxs_ssp_regs *ssp_regs = priv->regs;
307 /* Set the clock speed */
309 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
311 switch (mmc->bus_width) {
313 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
316 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
319 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
323 /* Set the bus width */
324 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
325 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
327 debug("MMC%d: Set %d bits bus width\n",
328 mmc->block_dev.dev, mmc->bus_width);
331 static int mxsmmc_init(struct mmc *mmc)
333 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
334 struct mxs_ssp_regs *ssp_regs = priv->regs;
337 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
339 /* 8 bits word length in MMC mode */
340 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
341 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
342 SSP_CTRL1_DMA_ENABLE,
343 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
345 /* Set initial bit clock 400 KHz */
346 mx28_set_ssp_busclock(priv->id, 400);
348 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
349 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
351 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
356 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
358 struct mxs_clkctrl_regs *clkctrl_regs =
359 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
360 struct mmc *mmc = NULL;
361 struct mxsmmc_priv *priv = NULL;
364 mmc = malloc(sizeof(struct mmc));
368 priv = malloc(sizeof(struct mxsmmc_priv));
374 priv->desc = mxs_dma_desc_alloc();
381 ret = mxs_dma_init_channel(id);
385 priv->mmc_is_wp = wp;
389 priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
390 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
391 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
394 priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
395 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
396 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
399 priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
400 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
401 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
404 priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
405 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
406 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
410 sprintf(mmc->name, "MXS MMC");
411 mmc->send_cmd = mxsmmc_send_cmd;
412 mmc->set_ios = mxsmmc_set_ios;
413 mmc->init = mxsmmc_init;
417 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
419 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
420 MMC_MODE_HS_52MHz | MMC_MODE_HS;
423 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
424 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
425 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
426 * CLOCK_RATE could be any integer from 0 to 255.
429 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;