mmc: mtk-sd: fix hang when data read quickly
[platform/kernel/u-boot.git] / drivers / mmc / mtk-sd.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MediaTek SD/MMC Card Interface driver
4  *
5  * Copyright (C) 2018 MediaTek Inc.
6  * Author: Weijie Gao <weijie.gao@mediatek.com>
7  */
8
9 #include <clk.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <mmc.h>
13 #include <errno.h>
14 #include <malloc.h>
15 #include <mapmem.h>
16 #include <stdbool.h>
17 #include <asm/gpio.h>
18 #include <dm/pinctrl.h>
19 #include <linux/bitops.h>
20 #include <linux/io.h>
21 #include <linux/iopoll.h>
22
23 /* MSDC_CFG */
24 #define MSDC_CFG_HS400_CK_MODE_EXT      BIT(22)
25 #define MSDC_CFG_CKMOD_EXT_M            0x300000
26 #define MSDC_CFG_CKMOD_EXT_S            20
27 #define MSDC_CFG_CKDIV_EXT_M            0xfff00
28 #define MSDC_CFG_CKDIV_EXT_S            8
29 #define MSDC_CFG_HS400_CK_MODE          BIT(18)
30 #define MSDC_CFG_CKMOD_M                0x30000
31 #define MSDC_CFG_CKMOD_S                16
32 #define MSDC_CFG_CKDIV_M                0xff00
33 #define MSDC_CFG_CKDIV_S                8
34 #define MSDC_CFG_CKSTB                  BIT(7)
35 #define MSDC_CFG_PIO                    BIT(3)
36 #define MSDC_CFG_RST                    BIT(2)
37 #define MSDC_CFG_CKPDN                  BIT(1)
38 #define MSDC_CFG_MODE                   BIT(0)
39
40 /* MSDC_IOCON */
41 #define MSDC_IOCON_W_DSPL               BIT(8)
42 #define MSDC_IOCON_DSPL                 BIT(2)
43 #define MSDC_IOCON_RSPL                 BIT(1)
44
45 /* MSDC_PS */
46 #define MSDC_PS_DAT0                    BIT(16)
47 #define MSDC_PS_CDDBCE_M                0xf000
48 #define MSDC_PS_CDDBCE_S                12
49 #define MSDC_PS_CDSTS                   BIT(1)
50 #define MSDC_PS_CDEN                    BIT(0)
51
52 /* #define MSDC_INT(EN) */
53 #define MSDC_INT_ACMDRDY                BIT(3)
54 #define MSDC_INT_ACMDTMO                BIT(4)
55 #define MSDC_INT_ACMDCRCERR             BIT(5)
56 #define MSDC_INT_CMDRDY                 BIT(8)
57 #define MSDC_INT_CMDTMO                 BIT(9)
58 #define MSDC_INT_RSPCRCERR              BIT(10)
59 #define MSDC_INT_XFER_COMPL             BIT(12)
60 #define MSDC_INT_DATTMO                 BIT(14)
61 #define MSDC_INT_DATCRCERR              BIT(15)
62
63 /* MSDC_FIFOCS */
64 #define MSDC_FIFOCS_CLR                 BIT(31)
65 #define MSDC_FIFOCS_TXCNT_M             0xff0000
66 #define MSDC_FIFOCS_TXCNT_S             16
67 #define MSDC_FIFOCS_RXCNT_M             0xff
68 #define MSDC_FIFOCS_RXCNT_S             0
69
70 /* #define SDC_CFG */
71 #define SDC_CFG_DTOC_M                  0xff000000
72 #define SDC_CFG_DTOC_S                  24
73 #define SDC_CFG_SDIOIDE                 BIT(20)
74 #define SDC_CFG_SDIO                    BIT(19)
75 #define SDC_CFG_BUSWIDTH_M              0x30000
76 #define SDC_CFG_BUSWIDTH_S              16
77
78 /* SDC_CMD */
79 #define SDC_CMD_BLK_LEN_M               0xfff0000
80 #define SDC_CMD_BLK_LEN_S               16
81 #define SDC_CMD_STOP                    BIT(14)
82 #define SDC_CMD_WR                      BIT(13)
83 #define SDC_CMD_DTYPE_M                 0x1800
84 #define SDC_CMD_DTYPE_S                 11
85 #define SDC_CMD_RSPTYP_M                0x380
86 #define SDC_CMD_RSPTYP_S                7
87 #define SDC_CMD_CMD_M                   0x3f
88 #define SDC_CMD_CMD_S                   0
89
90 /* SDC_STS */
91 #define SDC_STS_CMDBUSY                 BIT(1)
92 #define SDC_STS_SDCBUSY                 BIT(0)
93
94 /* SDC_ADV_CFG0 */
95 #define SDC_RX_ENHANCE_EN               BIT(20)
96
97 /* PATCH_BIT0 */
98 #define MSDC_INT_DAT_LATCH_CK_SEL_M     0x380
99 #define MSDC_INT_DAT_LATCH_CK_SEL_S     7
100
101 /* PATCH_BIT1 */
102 #define MSDC_PB1_STOP_DLY_M             0xf00
103 #define MSDC_PB1_STOP_DLY_S             8
104
105 /* PATCH_BIT2 */
106 #define MSDC_PB2_CRCSTSENSEL_M          0xe0000000
107 #define MSDC_PB2_CRCSTSENSEL_S          29
108 #define MSDC_PB2_CFGCRCSTS              BIT(28)
109 #define MSDC_PB2_RESPSTSENSEL_M         0x70000
110 #define MSDC_PB2_RESPSTSENSEL_S         16
111 #define MSDC_PB2_CFGRESP                BIT(15)
112 #define MSDC_PB2_RESPWAIT_M             0x0c
113 #define MSDC_PB2_RESPWAIT_S             2
114
115 /* PAD_TUNE */
116 #define MSDC_PAD_TUNE_CMDRRDLY_M        0x7c00000
117 #define MSDC_PAD_TUNE_CMDRRDLY_S        22
118 #define MSDC_PAD_TUNE_CMD_SEL           BIT(21)
119 #define MSDC_PAD_TUNE_CMDRDLY_M         0x1f0000
120 #define MSDC_PAD_TUNE_CMDRDLY_S         16
121 #define MSDC_PAD_TUNE_RXDLYSEL          BIT(15)
122 #define MSDC_PAD_TUNE_RD_SEL            BIT(13)
123 #define MSDC_PAD_TUNE_DATRRDLY_M        0x1f00
124 #define MSDC_PAD_TUNE_DATRRDLY_S        8
125 #define MSDC_PAD_TUNE_DATWRDLY_M        0x1f
126 #define MSDC_PAD_TUNE_DATWRDLY_S        0
127
128 #define PAD_CMD_TUNE_RX_DLY3            0x3E
129 #define PAD_CMD_TUNE_RX_DLY3_S          1
130
131 /* EMMC50_CFG0 */
132 #define EMMC50_CFG_CFCSTS_SEL           BIT(4)
133
134 /* SDC_FIFO_CFG */
135 #define SDC_FIFO_CFG_WRVALIDSEL         BIT(24)
136 #define SDC_FIFO_CFG_RDVALIDSEL         BIT(25)
137
138 /* EMMC_TOP_CONTROL mask */
139 #define PAD_RXDLY_SEL                   BIT(0)
140 #define DELAY_EN                        BIT(1)
141 #define PAD_DAT_RD_RXDLY2               (0x1f << 2)
142 #define PAD_DAT_RD_RXDLY                (0x1f << 7)
143 #define PAD_DAT_RD_RXDLY_S              7
144 #define PAD_DAT_RD_RXDLY2_SEL           BIT(12)
145 #define PAD_DAT_RD_RXDLY_SEL            BIT(13)
146 #define DATA_K_VALUE_SEL                BIT(14)
147 #define SDC_RX_ENH_EN                   BIT(15)
148
149 /* EMMC_TOP_CMD mask */
150 #define PAD_CMD_RXDLY2                  (0x1f << 0)
151 #define PAD_CMD_RXDLY                   (0x1f << 5)
152 #define PAD_CMD_RXDLY_S                 5
153 #define PAD_CMD_RD_RXDLY2_SEL           BIT(10)
154 #define PAD_CMD_RD_RXDLY_SEL            BIT(11)
155 #define PAD_CMD_TX_DLY                  (0x1f << 12)
156
157 /* SDC_CFG_BUSWIDTH */
158 #define MSDC_BUS_1BITS                  0x0
159 #define MSDC_BUS_4BITS                  0x1
160 #define MSDC_BUS_8BITS                  0x2
161
162 #define MSDC_FIFO_SIZE                  128
163
164 #define PAD_DELAY_MAX                   32
165
166 #define DEFAULT_CD_DEBOUNCE             8
167
168 #define CMD_INTS_MASK   \
169         (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
170
171 #define DATA_INTS_MASK  \
172         (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
173
174 /* Register offset */
175 struct mtk_sd_regs {
176         u32 msdc_cfg;
177         u32 msdc_iocon;
178         u32 msdc_ps;
179         u32 msdc_int;
180         u32 msdc_inten;
181         u32 msdc_fifocs;
182         u32 msdc_txdata;
183         u32 msdc_rxdata;
184         u32 reserved0[4];
185         u32 sdc_cfg;
186         u32 sdc_cmd;
187         u32 sdc_arg;
188         u32 sdc_sts;
189         u32 sdc_resp[4];
190         u32 sdc_blk_num;
191         u32 sdc_vol_chg;
192         u32 sdc_csts;
193         u32 sdc_csts_en;
194         u32 sdc_datcrc_sts;
195         u32 sdc_adv_cfg0;
196         u32 reserved1[2];
197         u32 emmc_cfg0;
198         u32 emmc_cfg1;
199         u32 emmc_sts;
200         u32 emmc_iocon;
201         u32 sd_acmd_resp;
202         u32 sd_acmd19_trg;
203         u32 sd_acmd19_sts;
204         u32 dma_sa_high4bit;
205         u32 dma_sa;
206         u32 dma_ca;
207         u32 dma_ctrl;
208         u32 dma_cfg;
209         u32 sw_dbg_sel;
210         u32 sw_dbg_out;
211         u32 dma_length;
212         u32 reserved2;
213         u32 patch_bit0;
214         u32 patch_bit1;
215         u32 patch_bit2;
216         u32 reserved3;
217         u32 dat0_tune_crc;
218         u32 dat1_tune_crc;
219         u32 dat2_tune_crc;
220         u32 dat3_tune_crc;
221         u32 cmd_tune_crc;
222         u32 sdio_tune_wind;
223         u32 reserved4[5];
224         u32 pad_tune;
225         u32 pad_tune0;
226         u32 pad_tune1;
227         u32 dat_rd_dly[4];
228         u32 reserved5[2];
229         u32 hw_dbg_sel;
230         u32 main_ver;
231         u32 eco_ver;
232         u32 reserved6[27];
233         u32 pad_ds_tune;
234         u32 pad_cmd_tune;
235         u32 reserved7[30];
236         u32 emmc50_cfg0;
237         u32 reserved8[7];
238         u32 sdc_fifo_cfg;
239 };
240
241 struct msdc_top_regs {
242         u32 emmc_top_control;
243         u32 emmc_top_cmd;
244         u32 emmc50_pad_ctl0;
245         u32 emmc50_pad_ds_tune;
246         u32 emmc50_pad_dat0_tune;
247         u32 emmc50_pad_dat1_tune;
248         u32 emmc50_pad_dat2_tune;
249         u32 emmc50_pad_dat3_tune;
250         u32 emmc50_pad_dat4_tune;
251         u32 emmc50_pad_dat5_tune;
252         u32 emmc50_pad_dat6_tune;
253         u32 emmc50_pad_dat7_tune;
254 };
255
256 struct msdc_compatible {
257         u8 clk_div_bits;
258         u8 sclk_cycle_shift;
259         bool pad_tune0;
260         bool async_fifo;
261         bool data_tune;
262         bool busy_check;
263         bool stop_clk_fix;
264         bool enhance_rx;
265 };
266
267 struct msdc_delay_phase {
268         u8 maxlen;
269         u8 start;
270         u8 final_phase;
271 };
272
273 struct msdc_plat {
274         struct mmc_config cfg;
275         struct mmc mmc;
276 };
277
278 struct msdc_tune_para {
279         u32 iocon;
280         u32 pad_tune;
281         u32 pad_cmd_tune;
282 };
283
284 struct msdc_host {
285         struct mtk_sd_regs *base;
286         struct msdc_top_regs *top_base;
287         struct mmc *mmc;
288
289         struct msdc_compatible *dev_comp;
290
291         struct clk src_clk;     /* for SD/MMC bus clock */
292         struct clk src_clk_cg;  /* optional, MSDC source clock control gate */
293         struct clk h_clk;       /* MSDC core clock */
294
295         u32 src_clk_freq;       /* source clock */
296         u32 mclk;               /* mmc framework required bus clock */
297         u32 sclk;               /* actual calculated bus clock */
298
299         /* operation timeout clocks */
300         u32 timeout_ns;
301         u32 timeout_clks;
302
303         /* tuning options */
304         u32 hs400_ds_delay;
305         u32 hs200_cmd_int_delay;
306         u32 hs200_write_int_delay;
307         u32 latch_ck;
308         u32 r_smpl;             /* sample edge */
309         bool hs400_mode;
310
311         /* whether to use gpio detection or built-in hw detection */
312         bool builtin_cd;
313         bool cd_active_high;
314
315         /* card detection / write protection GPIOs */
316 #if CONFIG_IS_ENABLED(DM_GPIO)
317         struct gpio_desc gpio_wp;
318         struct gpio_desc gpio_cd;
319 #endif
320
321         uint last_resp_type;
322         uint last_data_write;
323
324         enum bus_mode timing;
325
326         struct msdc_tune_para def_tune_para;
327         struct msdc_tune_para saved_tune_para;
328 };
329
330 static void msdc_reset_hw(struct msdc_host *host)
331 {
332         u32 reg;
333
334         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
335
336         readl_poll_timeout(&host->base->msdc_cfg, reg,
337                            !(reg & MSDC_CFG_RST), 1000000);
338 }
339
340 static void msdc_fifo_clr(struct msdc_host *host)
341 {
342         u32 reg;
343
344         setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
345
346         readl_poll_timeout(&host->base->msdc_fifocs, reg,
347                            !(reg & MSDC_FIFOCS_CLR), 1000000);
348 }
349
350 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
351 {
352         return (readl(&host->base->msdc_fifocs) &
353                 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
354 }
355
356 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
357 {
358         return (readl(&host->base->msdc_fifocs) &
359                 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
360 }
361
362 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
363 {
364         u32 resp;
365
366         switch (cmd->resp_type) {
367                 /* Actually, R1, R5, R6, R7 are the same */
368         case MMC_RSP_R1:
369                 resp = 0x1;
370                 break;
371         case MMC_RSP_R1b:
372                 resp = 0x7;
373                 break;
374         case MMC_RSP_R2:
375                 resp = 0x2;
376                 break;
377         case MMC_RSP_R3:
378                 resp = 0x3;
379                 break;
380         case MMC_RSP_NONE:
381         default:
382                 resp = 0x0;
383                 break;
384         }
385
386         return resp;
387 }
388
389 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
390                                     struct mmc_cmd *cmd,
391                                     struct mmc_data *data)
392 {
393         u32 opcode = cmd->cmdidx;
394         u32 resp_type = msdc_cmd_find_resp(host, cmd);
395         uint blocksize = 0;
396         u32 dtype = 0;
397         u32 rawcmd = 0;
398
399         switch (opcode) {
400         case MMC_CMD_WRITE_MULTIPLE_BLOCK:
401         case MMC_CMD_READ_MULTIPLE_BLOCK:
402                 dtype = 2;
403                 break;
404         case MMC_CMD_WRITE_SINGLE_BLOCK:
405         case MMC_CMD_READ_SINGLE_BLOCK:
406         case SD_CMD_APP_SEND_SCR:
407         case MMC_CMD_SEND_TUNING_BLOCK:
408         case MMC_CMD_SEND_TUNING_BLOCK_HS200:
409                 dtype = 1;
410                 break;
411         case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
412         case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
413         case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
414                 if (data)
415                         dtype = 1;
416         }
417
418         if (data) {
419                 if (data->flags == MMC_DATA_WRITE)
420                         rawcmd |= SDC_CMD_WR;
421
422                 if (data->blocks > 1)
423                         dtype = 2;
424
425                 blocksize = data->blocksize;
426         }
427
428         rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
429                 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
430                 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
431                 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
432
433         if (opcode == MMC_CMD_STOP_TRANSMISSION)
434                 rawcmd |= SDC_CMD_STOP;
435
436         return rawcmd;
437 }
438
439 static int msdc_cmd_done(struct msdc_host *host, int events,
440                          struct mmc_cmd *cmd)
441 {
442         u32 *rsp = cmd->response;
443         int ret = 0;
444
445         if (cmd->resp_type & MMC_RSP_PRESENT) {
446                 if (cmd->resp_type & MMC_RSP_136) {
447                         rsp[0] = readl(&host->base->sdc_resp[3]);
448                         rsp[1] = readl(&host->base->sdc_resp[2]);
449                         rsp[2] = readl(&host->base->sdc_resp[1]);
450                         rsp[3] = readl(&host->base->sdc_resp[0]);
451                 } else {
452                         rsp[0] = readl(&host->base->sdc_resp[0]);
453                 }
454         }
455
456         if (!(events & MSDC_INT_CMDRDY)) {
457                 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
458                     cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
459                         /*
460                          * should not clear fifo/interrupt as the tune data
461                          * may have alreay come.
462                          */
463                         msdc_reset_hw(host);
464
465                 if (events & MSDC_INT_CMDTMO)
466                         ret = -ETIMEDOUT;
467                 else
468                         ret = -EIO;
469         }
470
471         return ret;
472 }
473
474 static bool msdc_cmd_is_ready(struct msdc_host *host)
475 {
476         int ret;
477         u32 reg;
478
479         /* The max busy time we can endure is 20ms */
480         ret = readl_poll_timeout(&host->base->sdc_sts, reg,
481                                  !(reg & SDC_STS_CMDBUSY), 20000);
482
483         if (ret) {
484                 pr_err("CMD bus busy detected\n");
485                 msdc_reset_hw(host);
486                 return false;
487         }
488
489         if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
490                 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
491                                          reg & MSDC_PS_DAT0, 1000000);
492
493                 if (ret) {
494                         pr_err("Card stuck in programming state!\n");
495                         msdc_reset_hw(host);
496                         return false;
497                 }
498         }
499
500         return true;
501 }
502
503 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
504                               struct mmc_data *data)
505 {
506         u32 rawcmd;
507         u32 status;
508         u32 blocks = 0;
509         int ret;
510
511         if (!msdc_cmd_is_ready(host))
512                 return -EIO;
513
514         if ((readl(&host->base->msdc_fifocs) &
515             MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
516             (readl(&host->base->msdc_fifocs) &
517             MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
518                 pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
519                 msdc_reset_hw(host);
520         }
521
522         msdc_fifo_clr(host);
523
524         host->last_resp_type = cmd->resp_type;
525         host->last_data_write = 0;
526
527         rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
528
529         if (data)
530                 blocks = data->blocks;
531
532         writel(CMD_INTS_MASK, &host->base->msdc_int);
533         writel(DATA_INTS_MASK, &host->base->msdc_int);
534         writel(blocks, &host->base->sdc_blk_num);
535         writel(cmd->cmdarg, &host->base->sdc_arg);
536         writel(rawcmd, &host->base->sdc_cmd);
537
538         ret = readl_poll_timeout(&host->base->msdc_int, status,
539                                  status & CMD_INTS_MASK, 1000000);
540
541         if (ret)
542                 status = MSDC_INT_CMDTMO;
543
544         return msdc_cmd_done(host, status, cmd);
545 }
546
547 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
548 {
549         u32 *wbuf;
550
551         while ((size_t)buf % 4) {
552                 *buf++ = readb(&host->base->msdc_rxdata);
553                 size--;
554         }
555
556         wbuf = (u32 *)buf;
557         while (size >= 4) {
558                 *wbuf++ = readl(&host->base->msdc_rxdata);
559                 size -= 4;
560         }
561
562         buf = (u8 *)wbuf;
563         while (size) {
564                 *buf++ = readb(&host->base->msdc_rxdata);
565                 size--;
566         }
567 }
568
569 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
570 {
571         const u32 *wbuf;
572
573         while ((size_t)buf % 4) {
574                 writeb(*buf++, &host->base->msdc_txdata);
575                 size--;
576         }
577
578         wbuf = (const u32 *)buf;
579         while (size >= 4) {
580                 writel(*wbuf++, &host->base->msdc_txdata);
581                 size -= 4;
582         }
583
584         buf = (const u8 *)wbuf;
585         while (size) {
586                 writeb(*buf++, &host->base->msdc_txdata);
587                 size--;
588         }
589 }
590
591 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
592 {
593         u32 status;
594         u32 chksz;
595         int ret = 0;
596
597         while (1) {
598                 status = readl(&host->base->msdc_int);
599                 writel(status, &host->base->msdc_int);
600                 status &= DATA_INTS_MASK;
601
602                 if (status & MSDC_INT_DATCRCERR) {
603                         ret = -EIO;
604                         break;
605                 }
606
607                 if (status & MSDC_INT_DATTMO) {
608                         ret = -ETIMEDOUT;
609                         break;
610                 }
611
612                 chksz = min(size, (u32)MSDC_FIFO_SIZE);
613
614                 if (msdc_fifo_rx_bytes(host) >= chksz) {
615                         msdc_fifo_read(host, ptr, chksz);
616                         ptr += chksz;
617                         size -= chksz;
618                 }
619
620                 if (status & MSDC_INT_XFER_COMPL) {
621                         if (size) {
622                                 pr_err("data not fully read\n");
623                                 ret = -EIO;
624                         }
625
626                         break;
627                 }
628 }
629
630         return ret;
631 }
632
633 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
634 {
635         u32 status;
636         u32 chksz;
637         int ret = 0;
638
639         while (1) {
640                 status = readl(&host->base->msdc_int);
641                 writel(status, &host->base->msdc_int);
642                 status &= DATA_INTS_MASK;
643
644                 if (status & MSDC_INT_DATCRCERR) {
645                         ret = -EIO;
646                         break;
647                 }
648
649                 if (status & MSDC_INT_DATTMO) {
650                         ret = -ETIMEDOUT;
651                         break;
652                 }
653
654                 if (status & MSDC_INT_XFER_COMPL) {
655                         if (size) {
656                                 pr_err("data not fully written\n");
657                                 ret = -EIO;
658                         }
659
660                         break;
661                 }
662
663                 chksz = min(size, (u32)MSDC_FIFO_SIZE);
664
665                 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
666                         msdc_fifo_write(host, ptr, chksz);
667                         ptr += chksz;
668                         size -= chksz;
669                 }
670         }
671
672         return ret;
673 }
674
675 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
676 {
677         u32 size;
678         int ret;
679
680         if (data->flags == MMC_DATA_WRITE)
681                 host->last_data_write = 1;
682
683         size = data->blocks * data->blocksize;
684
685         if (data->flags == MMC_DATA_WRITE)
686                 ret = msdc_pio_write(host, (const u8 *)data->src, size);
687         else
688                 ret = msdc_pio_read(host, (u8 *)data->dest, size);
689
690         if (ret) {
691                 msdc_reset_hw(host);
692                 msdc_fifo_clr(host);
693         }
694
695         return ret;
696 }
697
698 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
699                              struct mmc_data *data)
700 {
701         struct msdc_host *host = dev_get_priv(dev);
702         int cmd_ret, data_ret;
703
704         cmd_ret = msdc_start_command(host, cmd, data);
705         if (cmd_ret &&
706             !(cmd_ret == -EIO &&
707             (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
708             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
709                 return cmd_ret;
710
711         if (data) {
712                 data_ret = msdc_start_data(host, data);
713                 if (cmd_ret)
714                         return cmd_ret;
715                 else
716                         return data_ret;
717         }
718
719         return 0;
720 }
721
722 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
723 {
724         u32 timeout, clk_ns, shift;
725         u32 mode = 0;
726
727         host->timeout_ns = ns;
728         host->timeout_clks = clks;
729
730         if (host->sclk == 0) {
731                 timeout = 0;
732         } else {
733                 shift = host->dev_comp->sclk_cycle_shift;
734                 clk_ns = 1000000000UL / host->sclk;
735                 timeout = (ns + clk_ns - 1) / clk_ns + clks;
736                 /* unit is 1048576 sclk cycles */
737                 timeout = (timeout + (0x1 << shift) - 1) >> shift;
738                 if (host->dev_comp->clk_div_bits == 8)
739                         mode = (readl(&host->base->msdc_cfg) &
740                                 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
741                 else
742                         mode = (readl(&host->base->msdc_cfg) &
743                                 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
744                 /* DDR mode will double the clk cycles for data timeout */
745                 timeout = mode >= 2 ? timeout * 2 : timeout;
746                 timeout = timeout > 1 ? timeout - 1 : 0;
747                 timeout = timeout > 255 ? 255 : timeout;
748         }
749
750         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
751                         timeout << SDC_CFG_DTOC_S);
752 }
753
754 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
755 {
756         u32 val = readl(&host->base->sdc_cfg);
757
758         val &= ~SDC_CFG_BUSWIDTH_M;
759
760         switch (width) {
761         default:
762         case 1:
763                 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
764                 break;
765         case 4:
766                 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
767                 break;
768         case 8:
769                 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
770                 break;
771         }
772
773         writel(val, &host->base->sdc_cfg);
774 }
775
776 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
777 {
778         u32 mode;
779         u32 div;
780         u32 sclk;
781         u32 reg;
782
783         if (!hz) {
784                 host->mclk = 0;
785                 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
786                 return;
787         }
788
789         if (host->dev_comp->clk_div_bits == 8)
790                 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
791         else
792                 clrbits_le32(&host->base->msdc_cfg,
793                              MSDC_CFG_HS400_CK_MODE_EXT);
794
795         if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
796             timing == MMC_HS_400) {
797                 if (timing == MMC_HS_400)
798                         mode = 0x3;
799                 else
800                         mode = 0x2; /* ddr mode and use divisor */
801
802                 if (hz >= (host->src_clk_freq >> 2)) {
803                         div = 0; /* mean div = 1/4 */
804                         sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
805                 } else {
806                         div = (host->src_clk_freq + ((hz << 2) - 1)) /
807                                (hz << 2);
808                         sclk = (host->src_clk_freq >> 2) / div;
809                         div = (div >> 1);
810                 }
811
812                 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
813                         if (host->dev_comp->clk_div_bits == 8)
814                                 setbits_le32(&host->base->msdc_cfg,
815                                              MSDC_CFG_HS400_CK_MODE);
816                         else
817                                 setbits_le32(&host->base->msdc_cfg,
818                                              MSDC_CFG_HS400_CK_MODE_EXT);
819
820                         sclk = host->src_clk_freq >> 1;
821                         div = 0; /* div is ignore when bit18 is set */
822                 }
823         } else if (hz >= host->src_clk_freq) {
824                 mode = 0x1; /* no divisor */
825                 div = 0;
826                 sclk = host->src_clk_freq;
827         } else {
828                 mode = 0x0; /* use divisor */
829                 if (hz >= (host->src_clk_freq >> 1)) {
830                         div = 0; /* mean div = 1/2 */
831                         sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
832                 } else {
833                         div = (host->src_clk_freq + ((hz << 2) - 1)) /
834                                (hz << 2);
835                         sclk = (host->src_clk_freq >> 2) / div;
836                 }
837         }
838
839         clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
840
841         if (host->dev_comp->clk_div_bits == 8) {
842                 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
843                 clrsetbits_le32(&host->base->msdc_cfg,
844                                 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
845                                 (mode << MSDC_CFG_CKMOD_S) |
846                                 (div << MSDC_CFG_CKDIV_S));
847         } else {
848                 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
849                                       MSDC_CFG_CKDIV_EXT_S));
850                 clrsetbits_le32(&host->base->msdc_cfg,
851                                 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
852                                 (mode << MSDC_CFG_CKMOD_EXT_S) |
853                                 (div << MSDC_CFG_CKDIV_EXT_S));
854         }
855
856         readl_poll_timeout(&host->base->msdc_cfg, reg,
857                            reg & MSDC_CFG_CKSTB, 1000000);
858
859         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
860         host->sclk = sclk;
861         host->mclk = hz;
862         host->timing = timing;
863
864         /* needed because clk changed. */
865         msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
866
867         /*
868          * mmc_select_hs400() will drop to 50Mhz and High speed mode,
869          * tune result of hs200/200Mhz is not suitable for 50Mhz
870          */
871         if (host->sclk <= 52000000) {
872                 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
873                 writel(host->def_tune_para.pad_tune,
874                        &host->base->pad_tune);
875         } else {
876                 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
877                 writel(host->saved_tune_para.pad_tune,
878                        &host->base->pad_tune);
879         }
880
881         dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
882 }
883
884 static int msdc_ops_set_ios(struct udevice *dev)
885 {
886         struct msdc_plat *plat = dev_get_platdata(dev);
887         struct msdc_host *host = dev_get_priv(dev);
888         struct mmc *mmc = &plat->mmc;
889         uint clock = mmc->clock;
890
891         msdc_set_buswidth(host, mmc->bus_width);
892
893         if (mmc->clk_disable)
894                 clock = 0;
895         else if (clock < mmc->cfg->f_min)
896                 clock = mmc->cfg->f_min;
897
898         if (host->mclk != clock || host->timing != mmc->selected_mode)
899                 msdc_set_mclk(host, mmc->selected_mode, clock);
900
901         return 0;
902 }
903
904 static int msdc_ops_get_cd(struct udevice *dev)
905 {
906         struct msdc_host *host = dev_get_priv(dev);
907         u32 val;
908
909         if (host->builtin_cd) {
910                 val = readl(&host->base->msdc_ps);
911                 val = !!(val & MSDC_PS_CDSTS);
912
913                 return !val ^ host->cd_active_high;
914         }
915
916 #if CONFIG_IS_ENABLED(DM_GPIO)
917         if (!host->gpio_cd.dev)
918                 return 1;
919
920         return dm_gpio_get_value(&host->gpio_cd);
921 #else
922         return 1;
923 #endif
924 }
925
926 static int msdc_ops_get_wp(struct udevice *dev)
927 {
928 #if CONFIG_IS_ENABLED(DM_GPIO)
929         struct msdc_host *host = dev_get_priv(dev);
930
931         if (!host->gpio_wp.dev)
932                 return 0;
933
934         return !dm_gpio_get_value(&host->gpio_wp);
935 #else
936         return 0;
937 #endif
938 }
939
940 #ifdef MMC_SUPPORTS_TUNING
941 static u32 test_delay_bit(u32 delay, u32 bit)
942 {
943         bit %= PAD_DELAY_MAX;
944         return delay & (1 << bit);
945 }
946
947 static int get_delay_len(u32 delay, u32 start_bit)
948 {
949         int i;
950
951         for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
952                 if (test_delay_bit(delay, start_bit + i) == 0)
953                         return i;
954         }
955
956         return PAD_DELAY_MAX - start_bit;
957 }
958
959 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
960 {
961         int start = 0, len = 0;
962         int start_final = 0, len_final = 0;
963         u8 final_phase = 0xff;
964         struct msdc_delay_phase delay_phase = { 0, };
965
966         if (delay == 0) {
967                 dev_err(dev, "phase error: [map:%x]\n", delay);
968                 delay_phase.final_phase = final_phase;
969                 return delay_phase;
970         }
971
972         while (start < PAD_DELAY_MAX) {
973                 len = get_delay_len(delay, start);
974                 if (len_final < len) {
975                         start_final = start;
976                         len_final = len;
977                 }
978
979                 start += len ? len : 1;
980                 if (len >= 12 && start_final < 4)
981                         break;
982         }
983
984         /* The rule is to find the smallest delay cell */
985         if (start_final == 0)
986                 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
987         else
988                 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
989
990         dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
991                  delay, len_final, final_phase);
992
993         delay_phase.maxlen = len_final;
994         delay_phase.start = start_final;
995         delay_phase.final_phase = final_phase;
996         return delay_phase;
997 }
998
999 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1000 {
1001         void __iomem *tune_reg = &host->base->pad_tune;
1002
1003         if (host->dev_comp->pad_tune0)
1004                 tune_reg = &host->base->pad_tune0;
1005
1006         if (host->top_base)
1007                 clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
1008                                 value << PAD_CMD_RXDLY_S);
1009         else
1010                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1011                                 value << MSDC_PAD_TUNE_CMDRDLY_S);
1012 }
1013
1014 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1015 {
1016         void __iomem *tune_reg = &host->base->pad_tune;
1017
1018         if (host->dev_comp->pad_tune0)
1019                 tune_reg = &host->base->pad_tune0;
1020
1021         if (host->top_base)
1022                 clrsetbits_le32(&host->top_base->emmc_top_control,
1023                                 PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
1024         else
1025                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1026                                 value << MSDC_PAD_TUNE_DATRRDLY_S);
1027 }
1028
1029 static int hs400_tune_response(struct udevice *dev, u32 opcode)
1030 {
1031         struct msdc_plat *plat = dev_get_platdata(dev);
1032         struct msdc_host *host = dev_get_priv(dev);
1033         struct mmc *mmc = &plat->mmc;
1034         u32 cmd_delay  = 0;
1035         struct msdc_delay_phase final_cmd_delay = { 0, };
1036         u8 final_delay;
1037         void __iomem *tune_reg = &host->base->pad_cmd_tune;
1038         int cmd_err;
1039         int i, j;
1040
1041         setbits_le32(&host->base->pad_cmd_tune, BIT(0));
1042
1043         if (mmc->selected_mode == MMC_HS_200 ||
1044             mmc->selected_mode == UHS_SDR104)
1045                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1046                                 host->hs200_cmd_int_delay <<
1047                                 MSDC_PAD_TUNE_CMDRRDLY_S);
1048
1049         if (host->r_smpl)
1050                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1051         else
1052                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1053
1054         for (i = 0; i < PAD_DELAY_MAX; i++) {
1055                 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1056                                 i << PAD_CMD_TUNE_RX_DLY3_S);
1057
1058                 for (j = 0; j < 3; j++) {
1059                         mmc_send_tuning(mmc, opcode, &cmd_err);
1060                         if (!cmd_err) {
1061                                 cmd_delay |= (1 << i);
1062                         } else {
1063                                 cmd_delay &= ~(1 << i);
1064                                 break;
1065                         }
1066                 }
1067         }
1068
1069         final_cmd_delay = get_best_delay(host, cmd_delay);
1070         clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1071                         final_cmd_delay.final_phase <<
1072                         PAD_CMD_TUNE_RX_DLY3_S);
1073         final_delay = final_cmd_delay.final_phase;
1074
1075         dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
1076         return final_delay == 0xff ? -EIO : 0;
1077 }
1078
1079 static int msdc_tune_response(struct udevice *dev, u32 opcode)
1080 {
1081         struct msdc_plat *plat = dev_get_platdata(dev);
1082         struct msdc_host *host = dev_get_priv(dev);
1083         struct mmc *mmc = &plat->mmc;
1084         u32 rise_delay = 0, fall_delay = 0;
1085         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1086         struct msdc_delay_phase internal_delay_phase;
1087         u8 final_delay, final_maxlen;
1088         u32 internal_delay = 0;
1089         void __iomem *tune_reg = &host->base->pad_tune;
1090         int cmd_err;
1091         int i, j;
1092
1093         if (host->dev_comp->pad_tune0)
1094                 tune_reg = &host->base->pad_tune0;
1095
1096         if (mmc->selected_mode == MMC_HS_200 ||
1097             mmc->selected_mode == UHS_SDR104)
1098                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1099                                 host->hs200_cmd_int_delay <<
1100                                 MSDC_PAD_TUNE_CMDRRDLY_S);
1101
1102         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1103
1104         for (i = 0; i < PAD_DELAY_MAX; i++) {
1105                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1106                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1107
1108                 for (j = 0; j < 3; j++) {
1109                         mmc_send_tuning(mmc, opcode, &cmd_err);
1110                         if (!cmd_err) {
1111                                 rise_delay |= (1 << i);
1112                         } else {
1113                                 rise_delay &= ~(1 << i);
1114                                 break;
1115                         }
1116                 }
1117         }
1118
1119         final_rise_delay = get_best_delay(host, rise_delay);
1120         /* if rising edge has enough margin, do not scan falling edge */
1121         if (final_rise_delay.maxlen >= 12 ||
1122             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1123                 goto skip_fall;
1124
1125         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1126         for (i = 0; i < PAD_DELAY_MAX; i++) {
1127                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1128                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1129
1130                 for (j = 0; j < 3; j++) {
1131                         mmc_send_tuning(mmc, opcode, &cmd_err);
1132                         if (!cmd_err) {
1133                                 fall_delay |= (1 << i);
1134                         } else {
1135                                 fall_delay &= ~(1 << i);
1136                                 break;
1137                         }
1138                 }
1139         }
1140
1141         final_fall_delay = get_best_delay(host, fall_delay);
1142
1143 skip_fall:
1144         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1145         if (final_maxlen == final_rise_delay.maxlen) {
1146                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1147                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1148                                 final_rise_delay.final_phase <<
1149                                 MSDC_PAD_TUNE_CMDRDLY_S);
1150                 final_delay = final_rise_delay.final_phase;
1151         } else {
1152                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1153                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1154                                 final_fall_delay.final_phase <<
1155                                 MSDC_PAD_TUNE_CMDRDLY_S);
1156                 final_delay = final_fall_delay.final_phase;
1157         }
1158
1159         if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1160                 goto skip_internal;
1161
1162         for (i = 0; i < PAD_DELAY_MAX; i++) {
1163                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1164                                 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1165
1166                 mmc_send_tuning(mmc, opcode, &cmd_err);
1167                 if (!cmd_err)
1168                         internal_delay |= (1 << i);
1169         }
1170
1171         dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
1172
1173         internal_delay_phase = get_best_delay(host, internal_delay);
1174         clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1175                         internal_delay_phase.final_phase <<
1176                         MSDC_PAD_TUNE_CMDRRDLY_S);
1177
1178 skip_internal:
1179         dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1180         return final_delay == 0xff ? -EIO : 0;
1181 }
1182
1183 static int msdc_tune_data(struct udevice *dev, u32 opcode)
1184 {
1185         struct msdc_plat *plat = dev_get_platdata(dev);
1186         struct msdc_host *host = dev_get_priv(dev);
1187         struct mmc *mmc = &plat->mmc;
1188         u32 rise_delay = 0, fall_delay = 0;
1189         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1190         u8 final_delay, final_maxlen;
1191         void __iomem *tune_reg = &host->base->pad_tune;
1192         int cmd_err;
1193         int i, ret;
1194
1195         if (host->dev_comp->pad_tune0)
1196                 tune_reg = &host->base->pad_tune0;
1197
1198         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1199         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1200
1201         for (i = 0; i < PAD_DELAY_MAX; i++) {
1202                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1203                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1204
1205                 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1206                 if (!ret) {
1207                         rise_delay |= (1 << i);
1208                 } else if (cmd_err) {
1209                         /* in this case, retune response is needed */
1210                         ret = msdc_tune_response(dev, opcode);
1211                         if (ret)
1212                                 break;
1213                 }
1214         }
1215
1216         final_rise_delay = get_best_delay(host, rise_delay);
1217         if (final_rise_delay.maxlen >= 12 ||
1218             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1219                 goto skip_fall;
1220
1221         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1222         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1223
1224         for (i = 0; i < PAD_DELAY_MAX; i++) {
1225                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1226                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1227
1228                 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1229                 if (!ret) {
1230                         fall_delay |= (1 << i);
1231                 } else if (cmd_err) {
1232                         /* in this case, retune response is needed */
1233                         ret = msdc_tune_response(dev, opcode);
1234                         if (ret)
1235                                 break;
1236                 }
1237         }
1238
1239         final_fall_delay = get_best_delay(host, fall_delay);
1240
1241 skip_fall:
1242         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1243         if (final_maxlen == final_rise_delay.maxlen) {
1244                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1245                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1246                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1247                                 final_rise_delay.final_phase <<
1248                                 MSDC_PAD_TUNE_DATRRDLY_S);
1249                 final_delay = final_rise_delay.final_phase;
1250         } else {
1251                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1252                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1253                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1254                                 final_fall_delay.final_phase <<
1255                                 MSDC_PAD_TUNE_DATRRDLY_S);
1256                 final_delay = final_fall_delay.final_phase;
1257         }
1258
1259         if (mmc->selected_mode == MMC_HS_200 ||
1260             mmc->selected_mode == UHS_SDR104)
1261                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1262                                 host->hs200_write_int_delay <<
1263                                 MSDC_PAD_TUNE_DATWRDLY_S);
1264
1265         dev_err(dev, "Final data pad delay: %x\n", final_delay);
1266
1267         return final_delay == 0xff ? -EIO : 0;
1268 }
1269
1270 /*
1271  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1272  * together, which can save the tuning time.
1273  */
1274 static int msdc_tune_together(struct udevice *dev, u32 opcode)
1275 {
1276         struct msdc_plat *plat = dev_get_platdata(dev);
1277         struct msdc_host *host = dev_get_priv(dev);
1278         struct mmc *mmc = &plat->mmc;
1279         u32 rise_delay = 0, fall_delay = 0;
1280         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1281         u8 final_delay, final_maxlen;
1282         int i, ret;
1283
1284         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1285         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1286
1287         for (i = 0; i < PAD_DELAY_MAX; i++) {
1288                 msdc_set_cmd_delay(host, i);
1289                 msdc_set_data_delay(host, i);
1290                 ret = mmc_send_tuning(mmc, opcode, NULL);
1291                 if (!ret)
1292                         rise_delay |= (1 << i);
1293         }
1294
1295         final_rise_delay = get_best_delay(host, rise_delay);
1296         if (final_rise_delay.maxlen >= 12 ||
1297             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1298                 goto skip_fall;
1299
1300         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1301         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1302
1303         for (i = 0; i < PAD_DELAY_MAX; i++) {
1304                 msdc_set_cmd_delay(host, i);
1305                 msdc_set_data_delay(host, i);
1306                 ret = mmc_send_tuning(mmc, opcode, NULL);
1307                 if (!ret)
1308                         fall_delay |= (1 << i);
1309         }
1310
1311         final_fall_delay = get_best_delay(host, fall_delay);
1312
1313 skip_fall:
1314         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1315         if (final_maxlen == final_rise_delay.maxlen) {
1316                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1317                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1318                 final_delay = final_rise_delay.final_phase;
1319         } else {
1320                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1321                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1322                 final_delay = final_fall_delay.final_phase;
1323         }
1324
1325         msdc_set_cmd_delay(host, final_delay);
1326         msdc_set_data_delay(host, final_delay);
1327
1328         dev_info(dev, "Final pad delay: %x\n", final_delay);
1329         return final_delay == 0xff ? -EIO : 0;
1330 }
1331
1332 static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1333 {
1334         struct msdc_plat *plat = dev_get_platdata(dev);
1335         struct msdc_host *host = dev_get_priv(dev);
1336         struct mmc *mmc = &plat->mmc;
1337         int ret = 0;
1338
1339         if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
1340                 ret = msdc_tune_together(dev, opcode);
1341                 if (ret == -EIO) {
1342                         dev_err(dev, "Tune fail!\n");
1343                         return ret;
1344                 }
1345
1346                 if (mmc->selected_mode == MMC_HS_400) {
1347                         clrbits_le32(&host->base->msdc_iocon,
1348                                      MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1349                         clrsetbits_le32(&host->base->pad_tune,
1350                                         MSDC_PAD_TUNE_DATRRDLY_M, 0);
1351
1352                         writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1353                         /* for hs400 mode it must be set to 0 */
1354                         clrbits_le32(&host->base->patch_bit2,
1355                                      MSDC_PB2_CFGCRCSTS);
1356                         host->hs400_mode = true;
1357                 }
1358                 goto tune_done;
1359         }
1360
1361         if (mmc->selected_mode == MMC_HS_400)
1362                 ret = hs400_tune_response(dev, opcode);
1363         else
1364                 ret = msdc_tune_response(dev, opcode);
1365         if (ret == -EIO) {
1366                 dev_err(dev, "Tune response fail!\n");
1367                 return ret;
1368         }
1369
1370         if (mmc->selected_mode != MMC_HS_400) {
1371                 ret = msdc_tune_data(dev, opcode);
1372                 if (ret == -EIO) {
1373                         dev_err(dev, "Tune data fail!\n");
1374                         return ret;
1375                 }
1376         }
1377
1378 tune_done:
1379         host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1380         host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1381         host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
1382
1383         return ret;
1384 }
1385 #endif
1386
1387 static void msdc_init_hw(struct msdc_host *host)
1388 {
1389         u32 val;
1390         void __iomem *tune_reg = &host->base->pad_tune;
1391
1392         if (host->dev_comp->pad_tune0)
1393                 tune_reg = &host->base->pad_tune0;
1394
1395         /* Configure to MMC/SD mode, clock free running */
1396         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1397
1398         /* Use PIO mode */
1399         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1400
1401         /* Reset */
1402         msdc_reset_hw(host);
1403
1404         /* Enable/disable hw card detection according to fdt option */
1405         if (host->builtin_cd)
1406                 clrsetbits_le32(&host->base->msdc_ps,
1407                         MSDC_PS_CDDBCE_M,
1408                         (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1409                         MSDC_PS_CDEN);
1410         else
1411                 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1412
1413         /* Clear all interrupts */
1414         val = readl(&host->base->msdc_int);
1415         writel(val, &host->base->msdc_int);
1416
1417         /* Enable data & cmd interrupts */
1418         writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1419
1420         writel(0, tune_reg);
1421         writel(0, &host->base->msdc_iocon);
1422
1423         if (host->r_smpl)
1424                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1425         else
1426                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1427
1428         writel(0x403c0046, &host->base->patch_bit0);
1429         writel(0xffff4089, &host->base->patch_bit1);
1430
1431         if (host->dev_comp->stop_clk_fix)
1432                 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1433                                 3 << MSDC_PB1_STOP_DLY_S);
1434
1435         if (host->dev_comp->busy_check)
1436                 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1437
1438         setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1439
1440         if (host->dev_comp->async_fifo) {
1441                 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1442                                 3 << MSDC_PB2_RESPWAIT_S);
1443
1444                 if (host->dev_comp->enhance_rx) {
1445                         if (host->top_base)
1446                                 setbits_le32(&host->top_base->emmc_top_control,
1447                                              SDC_RX_ENH_EN);
1448                         else
1449                                 setbits_le32(&host->base->sdc_adv_cfg0,
1450                                              SDC_RX_ENHANCE_EN);
1451                 } else {
1452                         clrsetbits_le32(&host->base->patch_bit2,
1453                                         MSDC_PB2_RESPSTSENSEL_M,
1454                                         2 << MSDC_PB2_RESPSTSENSEL_S);
1455                         clrsetbits_le32(&host->base->patch_bit2,
1456                                         MSDC_PB2_CRCSTSENSEL_M,
1457                                         2 << MSDC_PB2_CRCSTSENSEL_S);
1458                 }
1459
1460                 /* use async fifo to avoid tune internal delay */
1461                 clrbits_le32(&host->base->patch_bit2,
1462                              MSDC_PB2_CFGRESP);
1463                 clrbits_le32(&host->base->patch_bit2,
1464                              MSDC_PB2_CFGCRCSTS);
1465         }
1466
1467         if (host->dev_comp->data_tune) {
1468                 setbits_le32(tune_reg,
1469                              MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1470                 clrsetbits_le32(&host->base->patch_bit0,
1471                                 MSDC_INT_DAT_LATCH_CK_SEL_M,
1472                                 host->latch_ck <<
1473                                 MSDC_INT_DAT_LATCH_CK_SEL_S);
1474         } else {
1475                 /* choose clock tune */
1476                 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1477         }
1478
1479         /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1480         setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1481
1482         /* disable detecting SDIO device interrupt function */
1483         clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1484
1485         /* Configure to default data timeout */
1486         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1487                         3 << SDC_CFG_DTOC_S);
1488
1489         if (host->dev_comp->stop_clk_fix) {
1490                 clrbits_le32(&host->base->sdc_fifo_cfg,
1491                              SDC_FIFO_CFG_WRVALIDSEL);
1492                 clrbits_le32(&host->base->sdc_fifo_cfg,
1493                              SDC_FIFO_CFG_RDVALIDSEL);
1494         }
1495
1496         host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1497         host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1498 }
1499
1500 static void msdc_ungate_clock(struct msdc_host *host)
1501 {
1502         clk_enable(&host->src_clk);
1503         clk_enable(&host->h_clk);
1504         if (host->src_clk_cg.dev)
1505                 clk_enable(&host->src_clk_cg);
1506 }
1507
1508 static int msdc_drv_probe(struct udevice *dev)
1509 {
1510         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1511         struct msdc_plat *plat = dev_get_platdata(dev);
1512         struct msdc_host *host = dev_get_priv(dev);
1513         struct mmc_config *cfg = &plat->cfg;
1514
1515         cfg->name = dev->name;
1516
1517         host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1518
1519         host->src_clk_freq = clk_get_rate(&host->src_clk);
1520
1521         if (host->dev_comp->clk_div_bits == 8)
1522                 cfg->f_min = host->src_clk_freq / (4 * 255);
1523         else
1524                 cfg->f_min = host->src_clk_freq / (4 * 4095);
1525
1526         cfg->b_max = 1024;
1527         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1528
1529         host->mmc = &plat->mmc;
1530         host->timeout_ns = 100000000;
1531         host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
1532
1533 #ifdef CONFIG_PINCTRL
1534         pinctrl_select_state(dev, "default");
1535 #endif
1536
1537         msdc_ungate_clock(host);
1538         msdc_init_hw(host);
1539
1540         upriv->mmc = &plat->mmc;
1541
1542         return 0;
1543 }
1544
1545 static int msdc_ofdata_to_platdata(struct udevice *dev)
1546 {
1547         struct msdc_plat *plat = dev_get_platdata(dev);
1548         struct msdc_host *host = dev_get_priv(dev);
1549         struct mmc_config *cfg = &plat->cfg;
1550         fdt_addr_t base, top_base;
1551         int ret;
1552
1553         base = dev_read_addr(dev);
1554         if (base == FDT_ADDR_T_NONE)
1555                 return -EINVAL;
1556         host->base = map_sysmem(base, 0);
1557
1558         top_base = dev_read_addr_index(dev, 1);
1559         if (top_base == FDT_ADDR_T_NONE)
1560                 host->top_base = NULL;
1561         else
1562                 host->top_base = map_sysmem(top_base, 0);
1563
1564         ret = mmc_of_parse(dev, cfg);
1565         if (ret)
1566                 return ret;
1567
1568         ret = clk_get_by_name(dev, "source", &host->src_clk);
1569         if (ret < 0)
1570                 return ret;
1571
1572         ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1573         if (ret < 0)
1574                 return ret;
1575
1576         clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1577
1578 #if CONFIG_IS_ENABLED(DM_GPIO)
1579         gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1580         gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1581 #endif
1582
1583         host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1584         host->hs200_cmd_int_delay =
1585                         dev_read_u32_default(dev, "cmd_int_delay", 0);
1586         host->hs200_write_int_delay =
1587                         dev_read_u32_default(dev, "write_int_delay", 0);
1588         host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1589         host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1590         host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1591         host->cd_active_high = dev_read_bool(dev, "cd-active-high");
1592
1593         return 0;
1594 }
1595
1596 static int msdc_drv_bind(struct udevice *dev)
1597 {
1598         struct msdc_plat *plat = dev_get_platdata(dev);
1599
1600         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1601 }
1602
1603 static const struct dm_mmc_ops msdc_ops = {
1604         .send_cmd = msdc_ops_send_cmd,
1605         .set_ios = msdc_ops_set_ios,
1606         .get_cd = msdc_ops_get_cd,
1607         .get_wp = msdc_ops_get_wp,
1608 #ifdef MMC_SUPPORTS_TUNING
1609         .execute_tuning = msdc_execute_tuning,
1610 #endif
1611 };
1612
1613 static const struct msdc_compatible mt7620_compat = {
1614         .clk_div_bits = 8,
1615         .sclk_cycle_shift = 16,
1616         .pad_tune0 = false,
1617         .async_fifo = false,
1618         .data_tune = false,
1619         .busy_check = false,
1620         .stop_clk_fix = false,
1621         .enhance_rx = false
1622 };
1623
1624 static const struct msdc_compatible mt7623_compat = {
1625         .clk_div_bits = 12,
1626         .sclk_cycle_shift = 20,
1627         .pad_tune0 = true,
1628         .async_fifo = true,
1629         .data_tune = true,
1630         .busy_check = false,
1631         .stop_clk_fix = false,
1632         .enhance_rx = false
1633 };
1634
1635 static const struct msdc_compatible mt8512_compat = {
1636         .clk_div_bits = 12,
1637         .sclk_cycle_shift = 20,
1638         .pad_tune0 = true,
1639         .async_fifo = true,
1640         .data_tune = true,
1641         .busy_check = true,
1642         .stop_clk_fix = true,
1643 };
1644
1645 static const struct msdc_compatible mt8516_compat = {
1646         .clk_div_bits = 12,
1647         .sclk_cycle_shift = 20,
1648         .pad_tune0 = true,
1649         .async_fifo = true,
1650         .data_tune = true,
1651         .busy_check = true,
1652         .stop_clk_fix = true,
1653 };
1654
1655 static const struct msdc_compatible mt8183_compat = {
1656         .clk_div_bits = 12,
1657         .sclk_cycle_shift = 20,
1658         .pad_tune0 = true,
1659         .async_fifo = true,
1660         .data_tune = true,
1661         .busy_check = true,
1662         .stop_clk_fix = true,
1663 };
1664
1665 static const struct udevice_id msdc_ids[] = {
1666         { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
1667         { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
1668         { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
1669         { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
1670         { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
1671         {}
1672 };
1673
1674 U_BOOT_DRIVER(mtk_sd_drv) = {
1675         .name = "mtk_sd",
1676         .id = UCLASS_MMC,
1677         .of_match = msdc_ids,
1678         .ofdata_to_platdata = msdc_ofdata_to_platdata,
1679         .bind = msdc_drv_bind,
1680         .probe = msdc_drv_probe,
1681         .ops = &msdc_ops,
1682         .platdata_auto_alloc_size = sizeof(struct msdc_plat),
1683         .priv_auto_alloc_size = sizeof(struct msdc_host),
1684 };