1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek SD/MMC Card Interface driver
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
18 #include <dm/pinctrl.h>
19 #include <linux/bitops.h>
21 #include <linux/iopoll.h>
24 #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
25 #define MSDC_CFG_CKMOD_EXT_M 0x300000
26 #define MSDC_CFG_CKMOD_EXT_S 20
27 #define MSDC_CFG_CKDIV_EXT_M 0xfff00
28 #define MSDC_CFG_CKDIV_EXT_S 8
29 #define MSDC_CFG_HS400_CK_MODE BIT(18)
30 #define MSDC_CFG_CKMOD_M 0x30000
31 #define MSDC_CFG_CKMOD_S 16
32 #define MSDC_CFG_CKDIV_M 0xff00
33 #define MSDC_CFG_CKDIV_S 8
34 #define MSDC_CFG_CKSTB BIT(7)
35 #define MSDC_CFG_PIO BIT(3)
36 #define MSDC_CFG_RST BIT(2)
37 #define MSDC_CFG_CKPDN BIT(1)
38 #define MSDC_CFG_MODE BIT(0)
41 #define MSDC_IOCON_W_DSPL BIT(8)
42 #define MSDC_IOCON_DSPL BIT(2)
43 #define MSDC_IOCON_RSPL BIT(1)
46 #define MSDC_PS_DAT0 BIT(16)
47 #define MSDC_PS_CDDBCE_M 0xf000
48 #define MSDC_PS_CDDBCE_S 12
49 #define MSDC_PS_CDSTS BIT(1)
50 #define MSDC_PS_CDEN BIT(0)
52 /* #define MSDC_INT(EN) */
53 #define MSDC_INT_ACMDRDY BIT(3)
54 #define MSDC_INT_ACMDTMO BIT(4)
55 #define MSDC_INT_ACMDCRCERR BIT(5)
56 #define MSDC_INT_CMDRDY BIT(8)
57 #define MSDC_INT_CMDTMO BIT(9)
58 #define MSDC_INT_RSPCRCERR BIT(10)
59 #define MSDC_INT_XFER_COMPL BIT(12)
60 #define MSDC_INT_DATTMO BIT(14)
61 #define MSDC_INT_DATCRCERR BIT(15)
64 #define MSDC_FIFOCS_CLR BIT(31)
65 #define MSDC_FIFOCS_TXCNT_M 0xff0000
66 #define MSDC_FIFOCS_TXCNT_S 16
67 #define MSDC_FIFOCS_RXCNT_M 0xff
68 #define MSDC_FIFOCS_RXCNT_S 0
71 #define SDC_CFG_DTOC_M 0xff000000
72 #define SDC_CFG_DTOC_S 24
73 #define SDC_CFG_SDIOIDE BIT(20)
74 #define SDC_CFG_SDIO BIT(19)
75 #define SDC_CFG_BUSWIDTH_M 0x30000
76 #define SDC_CFG_BUSWIDTH_S 16
79 #define SDC_CMD_BLK_LEN_M 0xfff0000
80 #define SDC_CMD_BLK_LEN_S 16
81 #define SDC_CMD_STOP BIT(14)
82 #define SDC_CMD_WR BIT(13)
83 #define SDC_CMD_DTYPE_M 0x1800
84 #define SDC_CMD_DTYPE_S 11
85 #define SDC_CMD_RSPTYP_M 0x380
86 #define SDC_CMD_RSPTYP_S 7
87 #define SDC_CMD_CMD_M 0x3f
88 #define SDC_CMD_CMD_S 0
91 #define SDC_STS_CMDBUSY BIT(1)
92 #define SDC_STS_SDCBUSY BIT(0)
95 #define SDC_RX_ENHANCE_EN BIT(20)
98 #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
99 #define MSDC_INT_DAT_LATCH_CK_SEL_S 7
102 #define MSDC_PB1_STOP_DLY_M 0xf00
103 #define MSDC_PB1_STOP_DLY_S 8
106 #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
107 #define MSDC_PB2_CRCSTSENSEL_S 29
108 #define MSDC_PB2_CFGCRCSTS BIT(28)
109 #define MSDC_PB2_RESPSTSENSEL_M 0x70000
110 #define MSDC_PB2_RESPSTSENSEL_S 16
111 #define MSDC_PB2_CFGRESP BIT(15)
112 #define MSDC_PB2_RESPWAIT_M 0x0c
113 #define MSDC_PB2_RESPWAIT_S 2
116 #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
117 #define MSDC_PAD_TUNE_CMDRRDLY_S 22
118 #define MSDC_PAD_TUNE_CMD_SEL BIT(21)
119 #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
120 #define MSDC_PAD_TUNE_CMDRDLY_S 16
121 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
122 #define MSDC_PAD_TUNE_RD_SEL BIT(13)
123 #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
124 #define MSDC_PAD_TUNE_DATRRDLY_S 8
125 #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
126 #define MSDC_PAD_TUNE_DATWRDLY_S 0
129 #define EMMC50_CFG_CFCSTS_SEL BIT(4)
132 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
133 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
135 /* SDC_CFG_BUSWIDTH */
136 #define MSDC_BUS_1BITS 0x0
137 #define MSDC_BUS_4BITS 0x1
138 #define MSDC_BUS_8BITS 0x2
140 #define MSDC_FIFO_SIZE 128
142 #define PAD_DELAY_MAX 32
144 #define DEFAULT_CD_DEBOUNCE 8
146 #define CMD_INTS_MASK \
147 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
149 #define DATA_INTS_MASK \
150 (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
152 /* Register offset */
218 struct msdc_compatible {
229 struct msdc_delay_phase {
236 struct mmc_config cfg;
240 struct msdc_tune_para {
246 struct mtk_sd_regs *base;
249 struct msdc_compatible *dev_comp;
251 struct clk src_clk; /* for SD/MMC bus clock */
252 struct clk src_clk_cg; /* optional, MSDC source clock control gate */
253 struct clk h_clk; /* MSDC core clock */
255 u32 src_clk_freq; /* source clock */
256 u32 mclk; /* mmc framework required bus clock */
257 u32 sclk; /* actual calculated bus clock */
259 /* operation timeout clocks */
265 u32 hs200_cmd_int_delay;
266 u32 hs200_write_int_delay;
268 u32 r_smpl; /* sample edge */
271 /* whether to use gpio detection or built-in hw detection */
275 /* card detection / write protection GPIOs */
276 #if CONFIG_IS_ENABLED(DM_GPIO)
277 struct gpio_desc gpio_wp;
278 struct gpio_desc gpio_cd;
282 uint last_data_write;
284 enum bus_mode timing;
286 struct msdc_tune_para def_tune_para;
287 struct msdc_tune_para saved_tune_para;
290 static void msdc_reset_hw(struct msdc_host *host)
294 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
296 readl_poll_timeout(&host->base->msdc_cfg, reg,
297 !(reg & MSDC_CFG_RST), 1000000);
300 static void msdc_fifo_clr(struct msdc_host *host)
304 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
306 readl_poll_timeout(&host->base->msdc_fifocs, reg,
307 !(reg & MSDC_FIFOCS_CLR), 1000000);
310 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
312 return (readl(&host->base->msdc_fifocs) &
313 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
316 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
318 return (readl(&host->base->msdc_fifocs) &
319 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
322 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
326 switch (cmd->resp_type) {
327 /* Actually, R1, R5, R6, R7 are the same */
349 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
351 struct mmc_data *data)
353 u32 opcode = cmd->cmdidx;
354 u32 resp_type = msdc_cmd_find_resp(host, cmd);
360 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
361 case MMC_CMD_READ_MULTIPLE_BLOCK:
364 case MMC_CMD_WRITE_SINGLE_BLOCK:
365 case MMC_CMD_READ_SINGLE_BLOCK:
366 case SD_CMD_APP_SEND_SCR:
369 case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
370 case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
371 case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
377 if (data->flags == MMC_DATA_WRITE)
378 rawcmd |= SDC_CMD_WR;
380 if (data->blocks > 1)
383 blocksize = data->blocksize;
386 rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
387 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
388 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
389 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
391 if (opcode == MMC_CMD_STOP_TRANSMISSION)
392 rawcmd |= SDC_CMD_STOP;
397 static int msdc_cmd_done(struct msdc_host *host, int events,
400 u32 *rsp = cmd->response;
403 if (cmd->resp_type & MMC_RSP_PRESENT) {
404 if (cmd->resp_type & MMC_RSP_136) {
405 rsp[0] = readl(&host->base->sdc_resp[3]);
406 rsp[1] = readl(&host->base->sdc_resp[2]);
407 rsp[2] = readl(&host->base->sdc_resp[1]);
408 rsp[3] = readl(&host->base->sdc_resp[0]);
410 rsp[0] = readl(&host->base->sdc_resp[0]);
414 if (!(events & MSDC_INT_CMDRDY)) {
415 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
416 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
418 * should not clear fifo/interrupt as the tune data
419 * may have alreay come.
423 if (events & MSDC_INT_CMDTMO)
432 static bool msdc_cmd_is_ready(struct msdc_host *host)
437 /* The max busy time we can endure is 20ms */
438 ret = readl_poll_timeout(&host->base->sdc_sts, reg,
439 !(reg & SDC_STS_CMDBUSY), 20000);
442 pr_err("CMD bus busy detected\n");
447 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
448 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
449 reg & MSDC_PS_DAT0, 1000000);
452 pr_err("Card stuck in programming state!\n");
461 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
462 struct mmc_data *data)
469 if (!msdc_cmd_is_ready(host))
474 host->last_resp_type = cmd->resp_type;
475 host->last_data_write = 0;
477 rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
480 blocks = data->blocks;
482 writel(CMD_INTS_MASK, &host->base->msdc_int);
483 writel(blocks, &host->base->sdc_blk_num);
484 writel(cmd->cmdarg, &host->base->sdc_arg);
485 writel(rawcmd, &host->base->sdc_cmd);
487 ret = readl_poll_timeout(&host->base->msdc_int, status,
488 status & CMD_INTS_MASK, 1000000);
491 status = MSDC_INT_CMDTMO;
493 return msdc_cmd_done(host, status, cmd);
496 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
500 while ((size_t)buf % 4) {
501 *buf++ = readb(&host->base->msdc_rxdata);
507 *wbuf++ = readl(&host->base->msdc_rxdata);
513 *buf++ = readb(&host->base->msdc_rxdata);
518 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
522 while ((size_t)buf % 4) {
523 writeb(*buf++, &host->base->msdc_txdata);
527 wbuf = (const u32 *)buf;
529 writel(*wbuf++, &host->base->msdc_txdata);
533 buf = (const u8 *)wbuf;
535 writeb(*buf++, &host->base->msdc_txdata);
540 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
547 status = readl(&host->base->msdc_int);
548 writel(status, &host->base->msdc_int);
549 status &= DATA_INTS_MASK;
551 if (status & MSDC_INT_DATCRCERR) {
556 if (status & MSDC_INT_DATTMO) {
561 chksz = min(size, (u32)MSDC_FIFO_SIZE);
563 if (msdc_fifo_rx_bytes(host) >= chksz) {
564 msdc_fifo_read(host, ptr, chksz);
569 if (status & MSDC_INT_XFER_COMPL) {
571 pr_err("data not fully read\n");
582 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
589 status = readl(&host->base->msdc_int);
590 writel(status, &host->base->msdc_int);
591 status &= DATA_INTS_MASK;
593 if (status & MSDC_INT_DATCRCERR) {
598 if (status & MSDC_INT_DATTMO) {
603 if (status & MSDC_INT_XFER_COMPL) {
605 pr_err("data not fully written\n");
612 chksz = min(size, (u32)MSDC_FIFO_SIZE);
614 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
615 msdc_fifo_write(host, ptr, chksz);
624 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
631 if (data->flags == MMC_DATA_WRITE)
632 host->last_data_write = 1;
634 writel(DATA_INTS_MASK, &host->base->msdc_int);
636 size = data->blocks * data->blocksize;
638 if (data->flags == MMC_DATA_WRITE)
639 ret = msdc_pio_write(host, (const u8 *)data->src, size);
641 ret = msdc_pio_read(host, (u8 *)data->dest, size);
651 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
652 struct mmc_data *data)
654 struct msdc_host *host = dev_get_priv(dev);
657 ret = msdc_start_command(host, cmd, data);
662 return msdc_start_data(host, data);
667 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
669 u32 timeout, clk_ns, shift;
672 host->timeout_ns = ns;
673 host->timeout_clks = clks;
675 if (host->sclk == 0) {
678 shift = host->dev_comp->sclk_cycle_shift;
679 clk_ns = 1000000000UL / host->sclk;
680 timeout = (ns + clk_ns - 1) / clk_ns + clks;
681 /* unit is 1048576 sclk cycles */
682 timeout = (timeout + (0x1 << shift) - 1) >> shift;
683 if (host->dev_comp->clk_div_bits == 8)
684 mode = (readl(&host->base->msdc_cfg) &
685 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
687 mode = (readl(&host->base->msdc_cfg) &
688 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
689 /* DDR mode will double the clk cycles for data timeout */
690 timeout = mode >= 2 ? timeout * 2 : timeout;
691 timeout = timeout > 1 ? timeout - 1 : 0;
692 timeout = timeout > 255 ? 255 : timeout;
695 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
696 timeout << SDC_CFG_DTOC_S);
699 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
701 u32 val = readl(&host->base->sdc_cfg);
703 val &= ~SDC_CFG_BUSWIDTH_M;
708 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
711 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
714 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
718 writel(val, &host->base->sdc_cfg);
721 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
730 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
734 if (host->dev_comp->clk_div_bits == 8)
735 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
737 clrbits_le32(&host->base->msdc_cfg,
738 MSDC_CFG_HS400_CK_MODE_EXT);
740 if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
741 timing == MMC_HS_400) {
742 if (timing == MMC_HS_400)
745 mode = 0x2; /* ddr mode and use divisor */
747 if (hz >= (host->src_clk_freq >> 2)) {
748 div = 0; /* mean div = 1/4 */
749 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
751 div = (host->src_clk_freq + ((hz << 2) - 1)) /
753 sclk = (host->src_clk_freq >> 2) / div;
757 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
758 if (host->dev_comp->clk_div_bits == 8)
759 setbits_le32(&host->base->msdc_cfg,
760 MSDC_CFG_HS400_CK_MODE);
762 setbits_le32(&host->base->msdc_cfg,
763 MSDC_CFG_HS400_CK_MODE_EXT);
765 sclk = host->src_clk_freq >> 1;
766 div = 0; /* div is ignore when bit18 is set */
768 } else if (hz >= host->src_clk_freq) {
769 mode = 0x1; /* no divisor */
771 sclk = host->src_clk_freq;
773 mode = 0x0; /* use divisor */
774 if (hz >= (host->src_clk_freq >> 1)) {
775 div = 0; /* mean div = 1/2 */
776 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
778 div = (host->src_clk_freq + ((hz << 2) - 1)) /
780 sclk = (host->src_clk_freq >> 2) / div;
784 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
786 if (host->dev_comp->clk_div_bits == 8) {
787 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
788 clrsetbits_le32(&host->base->msdc_cfg,
789 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
790 (mode << MSDC_CFG_CKMOD_S) |
791 (div << MSDC_CFG_CKDIV_S));
793 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
794 MSDC_CFG_CKDIV_EXT_S));
795 clrsetbits_le32(&host->base->msdc_cfg,
796 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
797 (mode << MSDC_CFG_CKMOD_EXT_S) |
798 (div << MSDC_CFG_CKDIV_EXT_S));
801 readl_poll_timeout(&host->base->msdc_cfg, reg,
802 reg & MSDC_CFG_CKSTB, 1000000);
804 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
807 host->timing = timing;
809 /* needed because clk changed. */
810 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
813 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
814 * tune result of hs200/200Mhz is not suitable for 50Mhz
816 if (host->sclk <= 52000000) {
817 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
818 writel(host->def_tune_para.pad_tune,
819 &host->base->pad_tune);
821 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
822 writel(host->saved_tune_para.pad_tune,
823 &host->base->pad_tune);
826 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
829 static int msdc_ops_set_ios(struct udevice *dev)
831 struct msdc_plat *plat = dev_get_platdata(dev);
832 struct msdc_host *host = dev_get_priv(dev);
833 struct mmc *mmc = &plat->mmc;
834 uint clock = mmc->clock;
836 msdc_set_buswidth(host, mmc->bus_width);
838 if (mmc->clk_disable)
840 else if (clock < mmc->cfg->f_min)
841 clock = mmc->cfg->f_min;
843 if (host->mclk != clock || host->timing != mmc->selected_mode)
844 msdc_set_mclk(host, mmc->selected_mode, clock);
849 static int msdc_ops_get_cd(struct udevice *dev)
851 struct msdc_host *host = dev_get_priv(dev);
854 if (host->builtin_cd) {
855 val = readl(&host->base->msdc_ps);
856 val = !!(val & MSDC_PS_CDSTS);
858 return !val ^ host->cd_active_high;
861 #if CONFIG_IS_ENABLED(DM_GPIO)
862 if (!host->gpio_cd.dev)
865 return dm_gpio_get_value(&host->gpio_cd);
871 static int msdc_ops_get_wp(struct udevice *dev)
873 #if CONFIG_IS_ENABLED(DM_GPIO)
874 struct msdc_host *host = dev_get_priv(dev);
876 if (!host->gpio_wp.dev)
879 return !dm_gpio_get_value(&host->gpio_wp);
885 #ifdef MMC_SUPPORTS_TUNING
886 static u32 test_delay_bit(u32 delay, u32 bit)
888 bit %= PAD_DELAY_MAX;
889 return delay & (1 << bit);
892 static int get_delay_len(u32 delay, u32 start_bit)
896 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
897 if (test_delay_bit(delay, start_bit + i) == 0)
901 return PAD_DELAY_MAX - start_bit;
904 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
906 int start = 0, len = 0;
907 int start_final = 0, len_final = 0;
908 u8 final_phase = 0xff;
909 struct msdc_delay_phase delay_phase = { 0, };
912 dev_err(dev, "phase error: [map:%x]\n", delay);
913 delay_phase.final_phase = final_phase;
917 while (start < PAD_DELAY_MAX) {
918 len = get_delay_len(delay, start);
919 if (len_final < len) {
924 start += len ? len : 1;
925 if (len >= 12 && start_final < 4)
929 /* The rule is to find the smallest delay cell */
930 if (start_final == 0)
931 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
933 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
935 dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
936 delay, len_final, final_phase);
938 delay_phase.maxlen = len_final;
939 delay_phase.start = start_final;
940 delay_phase.final_phase = final_phase;
944 static int msdc_tune_response(struct udevice *dev, u32 opcode)
946 struct msdc_plat *plat = dev_get_platdata(dev);
947 struct msdc_host *host = dev_get_priv(dev);
948 struct mmc *mmc = &plat->mmc;
949 u32 rise_delay = 0, fall_delay = 0;
950 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
951 struct msdc_delay_phase internal_delay_phase;
952 u8 final_delay, final_maxlen;
953 u32 internal_delay = 0;
954 void __iomem *tune_reg = &host->base->pad_tune;
958 if (host->dev_comp->pad_tune0)
959 tune_reg = &host->base->pad_tune0;
961 if (mmc->selected_mode == MMC_HS_200 ||
962 mmc->selected_mode == UHS_SDR104)
963 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
964 host->hs200_cmd_int_delay <<
965 MSDC_PAD_TUNE_CMDRRDLY_S);
967 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
969 for (i = 0; i < PAD_DELAY_MAX; i++) {
970 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
971 i << MSDC_PAD_TUNE_CMDRDLY_S);
973 for (j = 0; j < 3; j++) {
974 mmc_send_tuning(mmc, opcode, &cmd_err);
976 rise_delay |= (1 << i);
978 rise_delay &= ~(1 << i);
984 final_rise_delay = get_best_delay(host, rise_delay);
985 /* if rising edge has enough margin, do not scan falling edge */
986 if (final_rise_delay.maxlen >= 12 ||
987 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
990 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
991 for (i = 0; i < PAD_DELAY_MAX; i++) {
992 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
993 i << MSDC_PAD_TUNE_CMDRDLY_S);
995 for (j = 0; j < 3; j++) {
996 mmc_send_tuning(mmc, opcode, &cmd_err);
998 fall_delay |= (1 << i);
1000 fall_delay &= ~(1 << i);
1006 final_fall_delay = get_best_delay(host, fall_delay);
1009 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1010 if (final_maxlen == final_rise_delay.maxlen) {
1011 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1012 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1013 final_rise_delay.final_phase <<
1014 MSDC_PAD_TUNE_CMDRDLY_S);
1015 final_delay = final_rise_delay.final_phase;
1017 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1018 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1019 final_fall_delay.final_phase <<
1020 MSDC_PAD_TUNE_CMDRDLY_S);
1021 final_delay = final_fall_delay.final_phase;
1024 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1027 for (i = 0; i < PAD_DELAY_MAX; i++) {
1028 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1029 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1031 mmc_send_tuning(mmc, opcode, &cmd_err);
1033 internal_delay |= (1 << i);
1036 dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
1038 internal_delay_phase = get_best_delay(host, internal_delay);
1039 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1040 internal_delay_phase.final_phase <<
1041 MSDC_PAD_TUNE_CMDRRDLY_S);
1044 dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1045 return final_delay == 0xff ? -EIO : 0;
1048 static int msdc_tune_data(struct udevice *dev, u32 opcode)
1050 struct msdc_plat *plat = dev_get_platdata(dev);
1051 struct msdc_host *host = dev_get_priv(dev);
1052 struct mmc *mmc = &plat->mmc;
1053 u32 rise_delay = 0, fall_delay = 0;
1054 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1055 u8 final_delay, final_maxlen;
1056 void __iomem *tune_reg = &host->base->pad_tune;
1060 if (host->dev_comp->pad_tune0)
1061 tune_reg = &host->base->pad_tune0;
1063 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1064 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1066 for (i = 0; i < PAD_DELAY_MAX; i++) {
1067 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1068 i << MSDC_PAD_TUNE_DATRRDLY_S);
1070 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1072 rise_delay |= (1 << i);
1073 } else if (cmd_err) {
1074 /* in this case, retune response is needed */
1075 ret = msdc_tune_response(dev, opcode);
1081 final_rise_delay = get_best_delay(host, rise_delay);
1082 if (final_rise_delay.maxlen >= 12 ||
1083 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1086 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1087 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1089 for (i = 0; i < PAD_DELAY_MAX; i++) {
1090 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1091 i << MSDC_PAD_TUNE_DATRRDLY_S);
1093 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1095 fall_delay |= (1 << i);
1096 } else if (cmd_err) {
1097 /* in this case, retune response is needed */
1098 ret = msdc_tune_response(dev, opcode);
1104 final_fall_delay = get_best_delay(host, fall_delay);
1107 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1108 if (final_maxlen == final_rise_delay.maxlen) {
1109 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1110 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1111 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1112 final_rise_delay.final_phase <<
1113 MSDC_PAD_TUNE_DATRRDLY_S);
1114 final_delay = final_rise_delay.final_phase;
1116 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1117 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1118 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1119 final_fall_delay.final_phase <<
1120 MSDC_PAD_TUNE_DATRRDLY_S);
1121 final_delay = final_fall_delay.final_phase;
1124 if (mmc->selected_mode == MMC_HS_200 ||
1125 mmc->selected_mode == UHS_SDR104)
1126 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1127 host->hs200_write_int_delay <<
1128 MSDC_PAD_TUNE_DATWRDLY_S);
1130 dev_err(dev, "Final data pad delay: %x\n", final_delay);
1132 return final_delay == 0xff ? -EIO : 0;
1135 static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1137 struct msdc_plat *plat = dev_get_platdata(dev);
1138 struct msdc_host *host = dev_get_priv(dev);
1139 struct mmc *mmc = &plat->mmc;
1142 if (mmc->selected_mode == MMC_HS_400) {
1143 writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1144 /* for hs400 mode it must be set to 0 */
1145 clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS);
1146 host->hs400_mode = true;
1149 ret = msdc_tune_response(dev, opcode);
1151 dev_err(dev, "Tune response fail!\n");
1155 if (!host->hs400_mode) {
1156 ret = msdc_tune_data(dev, opcode);
1158 dev_err(dev, "Tune data fail!\n");
1161 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1162 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1168 static void msdc_init_hw(struct msdc_host *host)
1171 void __iomem *tune_reg = &host->base->pad_tune;
1173 if (host->dev_comp->pad_tune0)
1174 tune_reg = &host->base->pad_tune0;
1176 /* Configure to MMC/SD mode, clock free running */
1177 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1180 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1183 msdc_reset_hw(host);
1185 /* Enable/disable hw card detection according to fdt option */
1186 if (host->builtin_cd)
1187 clrsetbits_le32(&host->base->msdc_ps,
1189 (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1192 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1194 /* Clear all interrupts */
1195 val = readl(&host->base->msdc_int);
1196 writel(val, &host->base->msdc_int);
1198 /* Enable data & cmd interrupts */
1199 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1201 writel(0, tune_reg);
1202 writel(0, &host->base->msdc_iocon);
1205 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1207 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1209 writel(0x403c0046, &host->base->patch_bit0);
1210 writel(0xffff4089, &host->base->patch_bit1);
1212 if (host->dev_comp->stop_clk_fix)
1213 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1214 3 << MSDC_PB1_STOP_DLY_S);
1216 if (host->dev_comp->busy_check)
1217 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1219 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1221 if (host->dev_comp->async_fifo) {
1222 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1223 3 << MSDC_PB2_RESPWAIT_S);
1225 if (host->dev_comp->enhance_rx) {
1226 setbits_le32(&host->base->sdc_adv_cfg0,
1229 clrsetbits_le32(&host->base->patch_bit2,
1230 MSDC_PB2_RESPSTSENSEL_M,
1231 2 << MSDC_PB2_RESPSTSENSEL_S);
1232 clrsetbits_le32(&host->base->patch_bit2,
1233 MSDC_PB2_CRCSTSENSEL_M,
1234 2 << MSDC_PB2_CRCSTSENSEL_S);
1237 /* use async fifo to avoid tune internal delay */
1238 clrbits_le32(&host->base->patch_bit2,
1240 clrbits_le32(&host->base->patch_bit2,
1241 MSDC_PB2_CFGCRCSTS);
1244 if (host->dev_comp->data_tune) {
1245 setbits_le32(tune_reg,
1246 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1247 clrsetbits_le32(&host->base->patch_bit0,
1248 MSDC_INT_DAT_LATCH_CK_SEL_M,
1250 MSDC_INT_DAT_LATCH_CK_SEL_S);
1252 /* choose clock tune */
1253 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1256 /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1257 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1259 /* disable detecting SDIO device interrupt function */
1260 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1262 /* Configure to default data timeout */
1263 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1264 3 << SDC_CFG_DTOC_S);
1266 if (host->dev_comp->stop_clk_fix) {
1267 clrbits_le32(&host->base->sdc_fifo_cfg,
1268 SDC_FIFO_CFG_WRVALIDSEL);
1269 clrbits_le32(&host->base->sdc_fifo_cfg,
1270 SDC_FIFO_CFG_RDVALIDSEL);
1273 host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1274 host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1277 static void msdc_ungate_clock(struct msdc_host *host)
1279 clk_enable(&host->src_clk);
1280 clk_enable(&host->h_clk);
1281 if (host->src_clk_cg.dev)
1282 clk_enable(&host->src_clk_cg);
1285 static int msdc_drv_probe(struct udevice *dev)
1287 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1288 struct msdc_plat *plat = dev_get_platdata(dev);
1289 struct msdc_host *host = dev_get_priv(dev);
1290 struct mmc_config *cfg = &plat->cfg;
1292 cfg->name = dev->name;
1294 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1296 host->src_clk_freq = clk_get_rate(&host->src_clk);
1298 if (host->dev_comp->clk_div_bits == 8)
1299 cfg->f_min = host->src_clk_freq / (4 * 255);
1301 cfg->f_min = host->src_clk_freq / (4 * 4095);
1302 cfg->f_max = host->src_clk_freq / 2;
1305 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1307 host->mmc = &plat->mmc;
1308 host->timeout_ns = 100000000;
1309 host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
1311 #ifdef CONFIG_PINCTRL
1312 pinctrl_select_state(dev, "default");
1315 msdc_ungate_clock(host);
1318 upriv->mmc = &plat->mmc;
1323 static int msdc_ofdata_to_platdata(struct udevice *dev)
1325 struct msdc_plat *plat = dev_get_platdata(dev);
1326 struct msdc_host *host = dev_get_priv(dev);
1327 struct mmc_config *cfg = &plat->cfg;
1330 host->base = (void *)dev_read_addr(dev);
1334 ret = mmc_of_parse(dev, cfg);
1338 ret = clk_get_by_name(dev, "source", &host->src_clk);
1342 ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1346 clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1348 #if CONFIG_IS_ENABLED(DM_GPIO)
1349 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1350 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1353 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1354 host->hs200_cmd_int_delay =
1355 dev_read_u32_default(dev, "cmd_int_delay", 0);
1356 host->hs200_write_int_delay =
1357 dev_read_u32_default(dev, "write_int_delay", 0);
1358 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1359 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1360 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1361 host->cd_active_high = dev_read_bool(dev, "cd-active-high");
1366 static int msdc_drv_bind(struct udevice *dev)
1368 struct msdc_plat *plat = dev_get_platdata(dev);
1370 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1373 static const struct dm_mmc_ops msdc_ops = {
1374 .send_cmd = msdc_ops_send_cmd,
1375 .set_ios = msdc_ops_set_ios,
1376 .get_cd = msdc_ops_get_cd,
1377 .get_wp = msdc_ops_get_wp,
1378 #ifdef MMC_SUPPORTS_TUNING
1379 .execute_tuning = msdc_execute_tuning,
1383 static const struct msdc_compatible mt7620_compat = {
1385 .sclk_cycle_shift = 16,
1387 .async_fifo = false,
1389 .busy_check = false,
1390 .stop_clk_fix = false,
1394 static const struct msdc_compatible mt7623_compat = {
1396 .sclk_cycle_shift = 20,
1400 .busy_check = false,
1401 .stop_clk_fix = false,
1405 static const struct msdc_compatible mt8516_compat = {
1407 .sclk_cycle_shift = 20,
1412 .stop_clk_fix = true,
1415 static const struct msdc_compatible mt8183_compat = {
1417 .sclk_cycle_shift = 20,
1422 .stop_clk_fix = true,
1425 static const struct udevice_id msdc_ids[] = {
1426 { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
1427 { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
1428 { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
1429 { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
1433 U_BOOT_DRIVER(mtk_sd_drv) = {
1436 .of_match = msdc_ids,
1437 .ofdata_to_platdata = msdc_ofdata_to_platdata,
1438 .bind = msdc_drv_bind,
1439 .probe = msdc_drv_probe,
1441 .platdata_auto_alloc_size = sizeof(struct msdc_plat),
1442 .priv_auto_alloc_size = sizeof(struct msdc_host),