drivers/mmc/mtk-sd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek SD/MMC Card Interface driver
   4  *
   5  * Copyright (C) 2018 MediaTek Inc.
   6  * Author: Weijie Gao <weijie.gao@mediatek.com>
   7  */
   8
   9 #include <clk.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <mmc.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <stdbool.h>
  16 #include <watchdog.h>
  17 #include <asm/gpio.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/bitops.h>
  20 #include <linux/io.h>
  21 #include <linux/iopoll.h>
  22
  23 /* MSDC_CFG */
  24 #define MSDC_CFG_HS400_CK_MODE_EXT      BIT(22)
  25 #define MSDC_CFG_CKMOD_EXT_M            0x300000
  26 #define MSDC_CFG_CKMOD_EXT_S            20
  27 #define MSDC_CFG_CKDIV_EXT_M            0xfff00
  28 #define MSDC_CFG_CKDIV_EXT_S            8
  29 #define MSDC_CFG_HS400_CK_MODE          BIT(18)
  30 #define MSDC_CFG_CKMOD_M                0x30000
  31 #define MSDC_CFG_CKMOD_S                16
  32 #define MSDC_CFG_CKDIV_M                0xff00
  33 #define MSDC_CFG_CKDIV_S                8
  34 #define MSDC_CFG_CKSTB                  BIT(7)
  35 #define MSDC_CFG_PIO                    BIT(3)
  36 #define MSDC_CFG_RST                    BIT(2)
  37 #define MSDC_CFG_CKPDN                  BIT(1)
  38 #define MSDC_CFG_MODE                   BIT(0)
  39
  40 /* MSDC_IOCON */
  41 #define MSDC_IOCON_W_DSPL               BIT(8)
  42 #define MSDC_IOCON_DSPL                 BIT(2)
  43 #define MSDC_IOCON_RSPL                 BIT(1)
  44
  45 /* MSDC_PS */
  46 #define MSDC_PS_DAT0                    BIT(16)
  47 #define MSDC_PS_CDDBCE_M                0xf000
  48 #define MSDC_PS_CDDBCE_S                12
  49 #define MSDC_PS_CDSTS                   BIT(1)
  50 #define MSDC_PS_CDEN                    BIT(0)
  51
  52 /* #define MSDC_INT(EN) */
  53 #define MSDC_INT_ACMDRDY                BIT(3)
  54 #define MSDC_INT_ACMDTMO                BIT(4)
  55 #define MSDC_INT_ACMDCRCERR             BIT(5)
  56 #define MSDC_INT_CMDRDY                 BIT(8)
  57 #define MSDC_INT_CMDTMO                 BIT(9)
  58 #define MSDC_INT_RSPCRCERR              BIT(10)
  59 #define MSDC_INT_XFER_COMPL             BIT(12)
  60 #define MSDC_INT_DATTMO                 BIT(14)
  61 #define MSDC_INT_DATCRCERR              BIT(15)
  62
  63 /* MSDC_FIFOCS */
  64 #define MSDC_FIFOCS_CLR                 BIT(31)
  65 #define MSDC_FIFOCS_TXCNT_M             0xff0000
  66 #define MSDC_FIFOCS_TXCNT_S             16
  67 #define MSDC_FIFOCS_RXCNT_M             0xff
  68 #define MSDC_FIFOCS_RXCNT_S             0
  69
  70 /* #define SDC_CFG */
  71 #define SDC_CFG_DTOC_M                  0xff000000
  72 #define SDC_CFG_DTOC_S                  24
  73 #define SDC_CFG_SDIOIDE                 BIT(20)
  74 #define SDC_CFG_SDIO                    BIT(19)
  75 #define SDC_CFG_BUSWIDTH_M              0x30000
  76 #define SDC_CFG_BUSWIDTH_S              16
  77
  78 /* SDC_CMD */
  79 #define SDC_CMD_BLK_LEN_M               0xfff0000
  80 #define SDC_CMD_BLK_LEN_S               16
  81 #define SDC_CMD_STOP                    BIT(14)
  82 #define SDC_CMD_WR                      BIT(13)
  83 #define SDC_CMD_DTYPE_M                 0x1800
  84 #define SDC_CMD_DTYPE_S                 11
  85 #define SDC_CMD_RSPTYP_M                0x380
  86 #define SDC_CMD_RSPTYP_S                7
  87 #define SDC_CMD_CMD_M                   0x3f
  88 #define SDC_CMD_CMD_S                   0
  89
  90 /* SDC_STS */
  91 #define SDC_STS_CMDBUSY                 BIT(1)
  92 #define SDC_STS_SDCBUSY                 BIT(0)
  93
  94 /* SDC_ADV_CFG0 */
  95 #define SDC_RX_ENHANCE_EN               BIT(20)
  96
  97 /* PATCH_BIT0 */
  98 #define MSDC_INT_DAT_LATCH_CK_SEL_M     0x380
  99 #define MSDC_INT_DAT_LATCH_CK_SEL_S     7
 100
 101 /* PATCH_BIT1 */
 102 #define MSDC_PB1_STOP_DLY_M             0xf00
 103 #define MSDC_PB1_STOP_DLY_S             8
 104
 105 /* PATCH_BIT2 */
 106 #define MSDC_PB2_CRCSTSENSEL_M          0xe0000000
 107 #define MSDC_PB2_CRCSTSENSEL_S          29
 108 #define MSDC_PB2_CFGCRCSTS              BIT(28)
 109 #define MSDC_PB2_RESPSTSENSEL_M         0x70000
 110 #define MSDC_PB2_RESPSTSENSEL_S         16
 111 #define MSDC_PB2_CFGRESP                BIT(15)
 112 #define MSDC_PB2_RESPWAIT_M             0x0c
 113 #define MSDC_PB2_RESPWAIT_S             2
 114
 115 /* PAD_TUNE */
 116 #define MSDC_PAD_TUNE_CMDRRDLY_M        0x7c00000
 117 #define MSDC_PAD_TUNE_CMDRRDLY_S        22
 118 #define MSDC_PAD_TUNE_CMD_SEL           BIT(21)
 119 #define MSDC_PAD_TUNE_CMDRDLY_M         0x1f0000
 120 #define MSDC_PAD_TUNE_CMDRDLY_S         16
 121 #define MSDC_PAD_TUNE_RXDLYSEL          BIT(15)
 122 #define MSDC_PAD_TUNE_RD_SEL            BIT(13)
 123 #define MSDC_PAD_TUNE_DATRRDLY_M        0x1f00
 124 #define MSDC_PAD_TUNE_DATRRDLY_S        8
 125 #define MSDC_PAD_TUNE_DATWRDLY_M        0x1f
 126 #define MSDC_PAD_TUNE_DATWRDLY_S        0
 127
 128 #define PAD_CMD_TUNE_RX_DLY3            0x3E
 129 #define PAD_CMD_TUNE_RX_DLY3_S          1
 130
 131 /* EMMC50_CFG0 */
 132 #define EMMC50_CFG_CFCSTS_SEL           BIT(4)
 133
 134 /* SDC_FIFO_CFG */
 135 #define SDC_FIFO_CFG_WRVALIDSEL         BIT(24)
 136 #define SDC_FIFO_CFG_RDVALIDSEL         BIT(25)
 137
 138 /* SDC_CFG_BUSWIDTH */
 139 #define MSDC_BUS_1BITS                  0x0
 140 #define MSDC_BUS_4BITS                  0x1
 141 #define MSDC_BUS_8BITS                  0x2
 142
 143 #define MSDC_FIFO_SIZE                  128
 144
 145 #define PAD_DELAY_MAX                   32
 146
 147 #define DEFAULT_CD_DEBOUNCE             8
 148
 149 #define CMD_INTS_MASK   \
 150         (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
 151
 152 #define DATA_INTS_MASK  \
 153         (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
 154
 155 /* Register offset */
 156 struct mtk_sd_regs {
 157         u32 msdc_cfg;
 158         u32 msdc_iocon;
 159         u32 msdc_ps;
 160         u32 msdc_int;
 161         u32 msdc_inten;
 162         u32 msdc_fifocs;
 163         u32 msdc_txdata;
 164         u32 msdc_rxdata;
 165         u32 reserved0[4];
 166         u32 sdc_cfg;
 167         u32 sdc_cmd;
 168         u32 sdc_arg;
 169         u32 sdc_sts;
 170         u32 sdc_resp[4];
 171         u32 sdc_blk_num;
 172         u32 sdc_vol_chg;
 173         u32 sdc_csts;
 174         u32 sdc_csts_en;
 175         u32 sdc_datcrc_sts;
 176         u32 sdc_adv_cfg0;
 177         u32 reserved1[2];
 178         u32 emmc_cfg0;
 179         u32 emmc_cfg1;
 180         u32 emmc_sts;
 181         u32 emmc_iocon;
 182         u32 sd_acmd_resp;
 183         u32 sd_acmd19_trg;
 184         u32 sd_acmd19_sts;
 185         u32 dma_sa_high4bit;
 186         u32 dma_sa;
 187         u32 dma_ca;
 188         u32 dma_ctrl;
 189         u32 dma_cfg;
 190         u32 sw_dbg_sel;
 191         u32 sw_dbg_out;
 192         u32 dma_length;
 193         u32 reserved2;
 194         u32 patch_bit0;
 195         u32 patch_bit1;
 196         u32 patch_bit2;
 197         u32 reserved3;
 198         u32 dat0_tune_crc;
 199         u32 dat1_tune_crc;
 200         u32 dat2_tune_crc;
 201         u32 dat3_tune_crc;
 202         u32 cmd_tune_crc;
 203         u32 sdio_tune_wind;
 204         u32 reserved4[5];
 205         u32 pad_tune;
 206         u32 pad_tune0;
 207         u32 pad_tune1;
 208         u32 dat_rd_dly[4];
 209         u32 reserved5[2];
 210         u32 hw_dbg_sel;
 211         u32 main_ver;
 212         u32 eco_ver;
 213         u32 reserved6[27];
 214         u32 pad_ds_tune;
 215         u32 pad_cmd_tune;
 216         u32 reserved7[30];
 217         u32 emmc50_cfg0;
 218         u32 reserved8[7];
 219         u32 sdc_fifo_cfg;
 220 };
 221
 222 struct msdc_compatible {
 223         u8 clk_div_bits;
 224         u8 sclk_cycle_shift;
 225         bool pad_tune0;
 226         bool async_fifo;
 227         bool data_tune;
 228         bool busy_check;
 229         bool stop_clk_fix;
 230         bool enhance_rx;
 231 };
 232
 233 struct msdc_delay_phase {
 234         u8 maxlen;
 235         u8 start;
 236         u8 final_phase;
 237 };
 238
 239 struct msdc_plat {
 240         struct mmc_config cfg;
 241         struct mmc mmc;
 242 };
 243
 244 struct msdc_tune_para {
 245         u32 iocon;
 246         u32 pad_tune;
 247         u32 pad_cmd_tune;
 248 };
 249
 250 struct msdc_host {
 251         struct mtk_sd_regs *base;
 252         struct mmc *mmc;
 253
 254         struct msdc_compatible *dev_comp;
 255
 256         struct clk src_clk;     /* for SD/MMC bus clock */
 257         struct clk src_clk_cg;  /* optional, MSDC source clock control gate */
 258         struct clk h_clk;       /* MSDC core clock */
 259
 260         u32 src_clk_freq;       /* source clock */
 261         u32 mclk;               /* mmc framework required bus clock */
 262         u32 sclk;               /* actual calculated bus clock */
 263
 264         /* operation timeout clocks */
 265         u32 timeout_ns;
 266         u32 timeout_clks;
 267
 268         /* tuning options */
 269         u32 hs400_ds_delay;
 270         u32 hs200_cmd_int_delay;
 271         u32 hs200_write_int_delay;
 272         u32 latch_ck;
 273         u32 r_smpl;             /* sample edge */
 274         bool hs400_mode;
 275
 276         /* whether to use gpio detection or built-in hw detection */
 277         bool builtin_cd;
 278         bool cd_active_high;
 279
 280         /* card detection / write protection GPIOs */
 281 #if CONFIG_IS_ENABLED(DM_GPIO)
 282         struct gpio_desc gpio_wp;
 283         struct gpio_desc gpio_cd;
 284 #endif
 285
 286         uint last_resp_type;
 287         uint last_data_write;
 288
 289         enum bus_mode timing;
 290
 291         struct msdc_tune_para def_tune_para;
 292         struct msdc_tune_para saved_tune_para;
 293 };
 294
 295 static void msdc_reset_hw(struct msdc_host *host)
 296 {
 297         u32 reg;
 298
 299         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
 300
 301         readl_poll_timeout(&host->base->msdc_cfg, reg,
 302                            !(reg & MSDC_CFG_RST), 1000000);
 303 }
 304
 305 static void msdc_fifo_clr(struct msdc_host *host)
 306 {
 307         u32 reg;
 308
 309         setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
 310
 311         readl_poll_timeout(&host->base->msdc_fifocs, reg,
 312                            !(reg & MSDC_FIFOCS_CLR), 1000000);
 313 }
 314
 315 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
 316 {
 317         return (readl(&host->base->msdc_fifocs) &
 318                 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
 319 }
 320
 321 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
 322 {
 323         return (readl(&host->base->msdc_fifocs) &
 324                 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
 325 }
 326
 327 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
 328 {
 329         u32 resp;
 330
 331         switch (cmd->resp_type) {
 332                 /* Actually, R1, R5, R6, R7 are the same */
 333         case MMC_RSP_R1:
 334                 resp = 0x1;
 335                 break;
 336         case MMC_RSP_R1b:
 337                 resp = 0x7;
 338                 break;
 339         case MMC_RSP_R2:
 340                 resp = 0x2;
 341                 break;
 342         case MMC_RSP_R3:
 343                 resp = 0x3;
 344                 break;
 345         case MMC_RSP_NONE:
 346         default:
 347                 resp = 0x0;
 348                 break;
 349         }
 350
 351         return resp;
 352 }
 353
 354 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
 355                                     struct mmc_cmd *cmd,
 356                                     struct mmc_data *data)
 357 {
 358         u32 opcode = cmd->cmdidx;
 359         u32 resp_type = msdc_cmd_find_resp(host, cmd);
 360         uint blocksize = 0;
 361         u32 dtype = 0;
 362         u32 rawcmd = 0;
 363
 364         switch (opcode) {
 365         case MMC_CMD_WRITE_MULTIPLE_BLOCK:
 366         case MMC_CMD_READ_MULTIPLE_BLOCK:
 367                 dtype = 2;
 368                 break;
 369         case MMC_CMD_WRITE_SINGLE_BLOCK:
 370         case MMC_CMD_READ_SINGLE_BLOCK:
 371         case SD_CMD_APP_SEND_SCR:
 372         case MMC_CMD_SEND_TUNING_BLOCK:
 373         case MMC_CMD_SEND_TUNING_BLOCK_HS200:
 374                 dtype = 1;
 375                 break;
 376         case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
 377         case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
 378         case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
 379                 if (data)
 380                         dtype = 1;
 381         }
 382
 383         if (data) {
 384                 if (data->flags == MMC_DATA_WRITE)
 385                         rawcmd |= SDC_CMD_WR;
 386
 387                 if (data->blocks > 1)
 388                         dtype = 2;
 389
 390                 blocksize = data->blocksize;
 391         }
 392
 393         rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
 394                 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
 395                 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
 396                 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
 397
 398         if (opcode == MMC_CMD_STOP_TRANSMISSION)
 399                 rawcmd |= SDC_CMD_STOP;
 400
 401         return rawcmd;
 402 }
 403
 404 static int msdc_cmd_done(struct msdc_host *host, int events,
 405                          struct mmc_cmd *cmd)
 406 {
 407         u32 *rsp = cmd->response;
 408         int ret = 0;
 409
 410         if (cmd->resp_type & MMC_RSP_PRESENT) {
 411                 if (cmd->resp_type & MMC_RSP_136) {
 412                         rsp[0] = readl(&host->base->sdc_resp[3]);
 413                         rsp[1] = readl(&host->base->sdc_resp[2]);
 414                         rsp[2] = readl(&host->base->sdc_resp[1]);
 415                         rsp[3] = readl(&host->base->sdc_resp[0]);
 416                 } else {
 417                         rsp[0] = readl(&host->base->sdc_resp[0]);
 418                 }
 419         }
 420
 421         if (!(events & MSDC_INT_CMDRDY)) {
 422                 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
 423                     cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
 424                         /*
 425                          * should not clear fifo/interrupt as the tune data
 426                          * may have alreay come.
 427                          */
 428                         msdc_reset_hw(host);
 429
 430                 if (events & MSDC_INT_CMDTMO)
 431                         ret = -ETIMEDOUT;
 432                 else
 433                         ret = -EIO;
 434         }
 435
 436         return ret;
 437 }
 438
 439 static bool msdc_cmd_is_ready(struct msdc_host *host)
 440 {
 441         int ret;
 442         u32 reg;
 443
 444         /* The max busy time we can endure is 20ms */
 445         ret = readl_poll_timeout(&host->base->sdc_sts, reg,
 446                                  !(reg & SDC_STS_CMDBUSY), 20000);
 447
 448         if (ret) {
 449                 pr_err("CMD bus busy detected\n");
 450                 msdc_reset_hw(host);
 451                 return false;
 452         }
 453
 454         if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
 455                 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
 456                                          reg & MSDC_PS_DAT0, 1000000);
 457
 458                 if (ret) {
 459                         pr_err("Card stuck in programming state!\n");
 460                         msdc_reset_hw(host);
 461                         return false;
 462                 }
 463         }
 464
 465         return true;
 466 }
 467
 468 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
 469                               struct mmc_data *data)
 470 {
 471         u32 rawcmd;
 472         u32 status;
 473         u32 blocks = 0;
 474         int ret;
 475
 476         if (!msdc_cmd_is_ready(host))
 477                 return -EIO;
 478
 479         if ((readl(&host->base->msdc_fifocs) &
 480             MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
 481             (readl(&host->base->msdc_fifocs) &
 482             MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
 483                 pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
 484                 msdc_reset_hw(host);
 485         }
 486
 487         msdc_fifo_clr(host);
 488
 489         host->last_resp_type = cmd->resp_type;
 490         host->last_data_write = 0;
 491
 492         rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
 493
 494         if (data)
 495                 blocks = data->blocks;
 496
 497         writel(CMD_INTS_MASK, &host->base->msdc_int);
 498         writel(blocks, &host->base->sdc_blk_num);
 499         writel(cmd->cmdarg, &host->base->sdc_arg);
 500         writel(rawcmd, &host->base->sdc_cmd);
 501
 502         ret = readl_poll_timeout(&host->base->msdc_int, status,
 503                                  status & CMD_INTS_MASK, 1000000);
 504
 505         if (ret)
 506                 status = MSDC_INT_CMDTMO;
 507
 508         return msdc_cmd_done(host, status, cmd);
 509 }
 510
 511 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
 512 {
 513         u32 *wbuf;
 514
 515         while ((size_t)buf % 4) {
 516                 *buf++ = readb(&host->base->msdc_rxdata);
 517                 size--;
 518         }
 519
 520         wbuf = (u32 *)buf;
 521         while (size >= 4) {
 522                 *wbuf++ = readl(&host->base->msdc_rxdata);
 523                 size -= 4;
 524         }
 525
 526         buf = (u8 *)wbuf;
 527         while (size) {
 528                 *buf++ = readb(&host->base->msdc_rxdata);
 529                 size--;
 530         }
 531 }
 532
 533 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
 534 {
 535         const u32 *wbuf;
 536
 537         while ((size_t)buf % 4) {
 538                 writeb(*buf++, &host->base->msdc_txdata);
 539                 size--;
 540         }
 541
 542         wbuf = (const u32 *)buf;
 543         while (size >= 4) {
 544                 writel(*wbuf++, &host->base->msdc_txdata);
 545                 size -= 4;
 546         }
 547
 548         buf = (const u8 *)wbuf;
 549         while (size) {
 550                 writeb(*buf++, &host->base->msdc_txdata);
 551                 size--;
 552         }
 553 }
 554
 555 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
 556 {
 557         u32 status;
 558         u32 chksz;
 559         int ret = 0;
 560
 561         while (1) {
 562                 status = readl(&host->base->msdc_int);
 563                 writel(status, &host->base->msdc_int);
 564                 status &= DATA_INTS_MASK;
 565
 566                 if (status & MSDC_INT_DATCRCERR) {
 567                         ret = -EIO;
 568                         break;
 569                 }
 570
 571                 if (status & MSDC_INT_DATTMO) {
 572                         ret = -ETIMEDOUT;
 573                         break;
 574                 }
 575
 576                 chksz = min(size, (u32)MSDC_FIFO_SIZE);
 577
 578                 if (msdc_fifo_rx_bytes(host) >= chksz) {
 579                         msdc_fifo_read(host, ptr, chksz);
 580                         ptr += chksz;
 581                         size -= chksz;
 582                 }
 583
 584                 if (status & MSDC_INT_XFER_COMPL) {
 585                         if (size) {
 586                                 pr_err("data not fully read\n");
 587                                 ret = -EIO;
 588                         }
 589
 590                         break;
 591                 }
 592 }
 593
 594         return ret;
 595 }
 596
 597 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
 598 {
 599         u32 status;
 600         u32 chksz;
 601         int ret = 0;
 602
 603         while (1) {
 604                 status = readl(&host->base->msdc_int);
 605                 writel(status, &host->base->msdc_int);
 606                 status &= DATA_INTS_MASK;
 607
 608                 if (status & MSDC_INT_DATCRCERR) {
 609                         ret = -EIO;
 610                         break;
 611                 }
 612
 613                 if (status & MSDC_INT_DATTMO) {
 614                         ret = -ETIMEDOUT;
 615                         break;
 616                 }
 617
 618                 if (status & MSDC_INT_XFER_COMPL) {
 619                         if (size) {
 620                                 pr_err("data not fully written\n");
 621                                 ret = -EIO;
 622                         }
 623
 624                         break;
 625                 }
 626
 627                 chksz = min(size, (u32)MSDC_FIFO_SIZE);
 628
 629                 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
 630                         msdc_fifo_write(host, ptr, chksz);
 631                         ptr += chksz;
 632                         size -= chksz;
 633                 }
 634         }
 635
 636         return ret;
 637 }
 638
 639 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
 640 {
 641         u32 size;
 642         int ret;
 643
 644         WATCHDOG_RESET();
 645
 646         if (data->flags == MMC_DATA_WRITE)
 647                 host->last_data_write = 1;
 648
 649         writel(DATA_INTS_MASK, &host->base->msdc_int);
 650
 651         size = data->blocks * data->blocksize;
 652
 653         if (data->flags == MMC_DATA_WRITE)
 654                 ret = msdc_pio_write(host, (const u8 *)data->src, size);
 655         else
 656                 ret = msdc_pio_read(host, (u8 *)data->dest, size);
 657
 658         if (ret) {
 659                 msdc_reset_hw(host);
 660                 msdc_fifo_clr(host);
 661         }
 662
 663         return ret;
 664 }
 665
 666 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 667                              struct mmc_data *data)
 668 {
 669         struct msdc_host *host = dev_get_priv(dev);
 670         int cmd_ret, data_ret;
 671
 672         cmd_ret = msdc_start_command(host, cmd, data);
 673         if (cmd_ret &&
 674             !(cmd_ret == -EIO &&
 675             (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 676             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
 677                 return cmd_ret;
 678
 679         if (data) {
 680                 data_ret = msdc_start_data(host, data);
 681                 if (cmd_ret)
 682                         return cmd_ret;
 683                 else
 684                         return data_ret;
 685         }
 686
 687         return 0;
 688 }
 689
 690 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
 691 {
 692         u32 timeout, clk_ns, shift;
 693         u32 mode = 0;
 694
 695         host->timeout_ns = ns;
 696         host->timeout_clks = clks;
 697
 698         if (host->sclk == 0) {
 699                 timeout = 0;
 700         } else {
 701                 shift = host->dev_comp->sclk_cycle_shift;
 702                 clk_ns = 1000000000UL / host->sclk;
 703                 timeout = (ns + clk_ns - 1) / clk_ns + clks;
 704                 /* unit is 1048576 sclk cycles */
 705                 timeout = (timeout + (0x1 << shift) - 1) >> shift;
 706                 if (host->dev_comp->clk_div_bits == 8)
 707                         mode = (readl(&host->base->msdc_cfg) &
 708                                 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
 709                 else
 710                         mode = (readl(&host->base->msdc_cfg) &
 711                                 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
 712                 /* DDR mode will double the clk cycles for data timeout */
 713                 timeout = mode >= 2 ? timeout * 2 : timeout;
 714                 timeout = timeout > 1 ? timeout - 1 : 0;
 715                 timeout = timeout > 255 ? 255 : timeout;
 716         }
 717
 718         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
 719                         timeout << SDC_CFG_DTOC_S);
 720 }
 721
 722 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
 723 {
 724         u32 val = readl(&host->base->sdc_cfg);
 725
 726         val &= ~SDC_CFG_BUSWIDTH_M;
 727
 728         switch (width) {
 729         default:
 730         case 1:
 731                 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
 732                 break;
 733         case 4:
 734                 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
 735                 break;
 736         case 8:
 737                 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
 738                 break;
 739         }
 740
 741         writel(val, &host->base->sdc_cfg);
 742 }
 743
 744 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
 745 {
 746         u32 mode;
 747         u32 div;
 748         u32 sclk;
 749         u32 reg;
 750
 751         if (!hz) {
 752                 host->mclk = 0;
 753                 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 754                 return;
 755         }
 756
 757         if (host->dev_comp->clk_div_bits == 8)
 758                 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
 759         else
 760                 clrbits_le32(&host->base->msdc_cfg,
 761                              MSDC_CFG_HS400_CK_MODE_EXT);
 762
 763         if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
 764             timing == MMC_HS_400) {
 765                 if (timing == MMC_HS_400)
 766                         mode = 0x3;
 767                 else
 768                         mode = 0x2; /* ddr mode and use divisor */
 769
 770                 if (hz >= (host->src_clk_freq >> 2)) {
 771                         div = 0; /* mean div = 1/4 */
 772                         sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
 773                 } else {
 774                         div = (host->src_clk_freq + ((hz << 2) - 1)) /
 775                                (hz << 2);
 776                         sclk = (host->src_clk_freq >> 2) / div;
 777                         div = (div >> 1);
 778                 }
 779
 780                 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
 781                         if (host->dev_comp->clk_div_bits == 8)
 782                                 setbits_le32(&host->base->msdc_cfg,
 783                                              MSDC_CFG_HS400_CK_MODE);
 784                         else
 785                                 setbits_le32(&host->base->msdc_cfg,
 786                                              MSDC_CFG_HS400_CK_MODE_EXT);
 787
 788                         sclk = host->src_clk_freq >> 1;
 789                         div = 0; /* div is ignore when bit18 is set */
 790                 }
 791         } else if (hz >= host->src_clk_freq) {
 792                 mode = 0x1; /* no divisor */
 793                 div = 0;
 794                 sclk = host->src_clk_freq;
 795         } else {
 796                 mode = 0x0; /* use divisor */
 797                 if (hz >= (host->src_clk_freq >> 1)) {
 798                         div = 0; /* mean div = 1/2 */
 799                         sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
 800                 } else {
 801                         div = (host->src_clk_freq + ((hz << 2) - 1)) /
 802                                (hz << 2);
 803                         sclk = (host->src_clk_freq >> 2) / div;
 804                 }
 805         }
 806
 807         clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 808
 809         if (host->dev_comp->clk_div_bits == 8) {
 810                 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
 811                 clrsetbits_le32(&host->base->msdc_cfg,
 812                                 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
 813                                 (mode << MSDC_CFG_CKMOD_S) |
 814                                 (div << MSDC_CFG_CKDIV_S));
 815         } else {
 816                 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
 817                                       MSDC_CFG_CKDIV_EXT_S));
 818                 clrsetbits_le32(&host->base->msdc_cfg,
 819                                 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
 820                                 (mode << MSDC_CFG_CKMOD_EXT_S) |
 821                                 (div << MSDC_CFG_CKDIV_EXT_S));
 822         }
 823
 824         readl_poll_timeout(&host->base->msdc_cfg, reg,
 825                            reg & MSDC_CFG_CKSTB, 1000000);
 826
 827         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 828         host->sclk = sclk;
 829         host->mclk = hz;
 830         host->timing = timing;
 831
 832         /* needed because clk changed. */
 833         msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
 834
 835         /*
 836          * mmc_select_hs400() will drop to 50Mhz and High speed mode,
 837          * tune result of hs200/200Mhz is not suitable for 50Mhz
 838          */
 839         if (host->sclk <= 52000000) {
 840                 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
 841                 writel(host->def_tune_para.pad_tune,
 842                        &host->base->pad_tune);
 843         } else {
 844                 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
 845                 writel(host->saved_tune_para.pad_tune,
 846                        &host->base->pad_tune);
 847         }
 848
 849         dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
 850 }
 851
 852 static int msdc_ops_set_ios(struct udevice *dev)
 853 {
 854         struct msdc_plat *plat = dev_get_platdata(dev);
 855         struct msdc_host *host = dev_get_priv(dev);
 856         struct mmc *mmc = &plat->mmc;
 857         uint clock = mmc->clock;
 858
 859         msdc_set_buswidth(host, mmc->bus_width);
 860
 861         if (mmc->clk_disable)
 862                 clock = 0;
 863         else if (clock < mmc->cfg->f_min)
 864                 clock = mmc->cfg->f_min;
 865
 866         if (host->mclk != clock || host->timing != mmc->selected_mode)
 867                 msdc_set_mclk(host, mmc->selected_mode, clock);
 868
 869         return 0;
 870 }
 871
 872 static int msdc_ops_get_cd(struct udevice *dev)
 873 {
 874         struct msdc_host *host = dev_get_priv(dev);
 875         u32 val;
 876
 877         if (host->builtin_cd) {
 878                 val = readl(&host->base->msdc_ps);
 879                 val = !!(val & MSDC_PS_CDSTS);
 880
 881                 return !val ^ host->cd_active_high;
 882         }
 883
 884 #if CONFIG_IS_ENABLED(DM_GPIO)
 885         if (!host->gpio_cd.dev)
 886                 return 1;
 887
 888         return dm_gpio_get_value(&host->gpio_cd);
 889 #else
 890         return 1;
 891 #endif
 892 }
 893
 894 static int msdc_ops_get_wp(struct udevice *dev)
 895 {
 896 #if CONFIG_IS_ENABLED(DM_GPIO)
 897         struct msdc_host *host = dev_get_priv(dev);
 898
 899         if (!host->gpio_wp.dev)
 900                 return 0;
 901
 902         return !dm_gpio_get_value(&host->gpio_wp);
 903 #else
 904         return 0;
 905 #endif
 906 }
 907
 908 #ifdef MMC_SUPPORTS_TUNING
 909 static u32 test_delay_bit(u32 delay, u32 bit)
 910 {
 911         bit %= PAD_DELAY_MAX;
 912         return delay & (1 << bit);
 913 }
 914
 915 static int get_delay_len(u32 delay, u32 start_bit)
 916 {
 917         int i;
 918
 919         for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
 920                 if (test_delay_bit(delay, start_bit + i) == 0)
 921                         return i;
 922         }
 923
 924         return PAD_DELAY_MAX - start_bit;
 925 }
 926
 927 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
 928 {
 929         int start = 0, len = 0;
 930         int start_final = 0, len_final = 0;
 931         u8 final_phase = 0xff;
 932         struct msdc_delay_phase delay_phase = { 0, };
 933
 934         if (delay == 0) {
 935                 dev_err(dev, "phase error: [map:%x]\n", delay);
 936                 delay_phase.final_phase = final_phase;
 937                 return delay_phase;
 938         }
 939
 940         while (start < PAD_DELAY_MAX) {
 941                 len = get_delay_len(delay, start);
 942                 if (len_final < len) {
 943                         start_final = start;
 944                         len_final = len;
 945                 }
 946
 947                 start += len ? len : 1;
 948                 if (len >= 12 && start_final < 4)
 949                         break;
 950         }
 951
 952         /* The rule is to find the smallest delay cell */
 953         if (start_final == 0)
 954                 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
 955         else
 956                 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
 957
 958         dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 959                  delay, len_final, final_phase);
 960
 961         delay_phase.maxlen = len_final;
 962         delay_phase.start = start_final;
 963         delay_phase.final_phase = final_phase;
 964         return delay_phase;
 965 }
 966
 967 static int hs400_tune_response(struct udevice *dev, u32 opcode)
 968 {
 969         struct msdc_plat *plat = dev_get_platdata(dev);
 970         struct msdc_host *host = dev_get_priv(dev);
 971         struct mmc *mmc = &plat->mmc;
 972         u32 cmd_delay  = 0;
 973         struct msdc_delay_phase final_cmd_delay = { 0, };
 974         u8 final_delay;
 975         void __iomem *tune_reg = &host->base->pad_cmd_tune;
 976         int cmd_err;
 977         int i, j;
 978
 979         setbits_le32(&host->base->pad_cmd_tune, BIT(0));
 980
 981         if (mmc->selected_mode == MMC_HS_200 ||
 982             mmc->selected_mode == UHS_SDR104)
 983                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
 984                                 host->hs200_cmd_int_delay <<
 985                                 MSDC_PAD_TUNE_CMDRRDLY_S);
 986
 987         if (host->r_smpl)
 988                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
 989         else
 990                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
 991
 992         for (i = 0; i < PAD_DELAY_MAX; i++) {
 993                 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
 994                                 i << PAD_CMD_TUNE_RX_DLY3_S);
 995
 996                 for (j = 0; j < 3; j++) {
 997                         mmc_send_tuning(mmc, opcode, &cmd_err);
 998                         if (!cmd_err) {
 999                                 cmd_delay |= (1 << i);
1000                         } else {
1001                                 cmd_delay &= ~(1 << i);
1002                                 break;
1003                         }
1004                 }
1005         }
1006
1007         final_cmd_delay = get_best_delay(host, cmd_delay);
1008         clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1009                         final_cmd_delay.final_phase <<
1010                         PAD_CMD_TUNE_RX_DLY3_S);
1011         final_delay = final_cmd_delay.final_phase;
1012
1013         dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1014         return final_delay == 0xff ? -EIO : 0;
1015 }
1016
1017 static int msdc_tune_response(struct udevice *dev, u32 opcode)
1018 {
1019         struct msdc_plat *plat = dev_get_platdata(dev);
1020         struct msdc_host *host = dev_get_priv(dev);
1021         struct mmc *mmc = &plat->mmc;
1022         u32 rise_delay = 0, fall_delay = 0;
1023         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1024         struct msdc_delay_phase internal_delay_phase;
1025         u8 final_delay, final_maxlen;
1026         u32 internal_delay = 0;
1027         void __iomem *tune_reg = &host->base->pad_tune;
1028         int cmd_err;
1029         int i, j;
1030
1031         if (host->dev_comp->pad_tune0)
1032                 tune_reg = &host->base->pad_tune0;
1033
1034         if (mmc->selected_mode == MMC_HS_200 ||
1035             mmc->selected_mode == UHS_SDR104)
1036                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1037                                 host->hs200_cmd_int_delay <<
1038                                 MSDC_PAD_TUNE_CMDRRDLY_S);
1039
1040         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1041
1042         for (i = 0; i < PAD_DELAY_MAX; i++) {
1043                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1044                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1045
1046                 for (j = 0; j < 3; j++) {
1047                         mmc_send_tuning(mmc, opcode, &cmd_err);
1048                         if (!cmd_err) {
1049                                 rise_delay |= (1 << i);
1050                         } else {
1051                                 rise_delay &= ~(1 << i);
1052                                 break;
1053                         }
1054                 }
1055         }
1056
1057         final_rise_delay = get_best_delay(host, rise_delay);
1058         /* if rising edge has enough margin, do not scan falling edge */
1059         if (final_rise_delay.maxlen >= 12 ||
1060             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1061                 goto skip_fall;
1062
1063         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1064         for (i = 0; i < PAD_DELAY_MAX; i++) {
1065                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1066                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1067
1068                 for (j = 0; j < 3; j++) {
1069                         mmc_send_tuning(mmc, opcode, &cmd_err);
1070                         if (!cmd_err) {
1071                                 fall_delay |= (1 << i);
1072                         } else {
1073                                 fall_delay &= ~(1 << i);
1074                                 break;
1075                         }
1076                 }
1077         }
1078
1079         final_fall_delay = get_best_delay(host, fall_delay);
1080
1081 skip_fall:
1082         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1083         if (final_maxlen == final_rise_delay.maxlen) {
1084                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1085                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1086                                 final_rise_delay.final_phase <<
1087                                 MSDC_PAD_TUNE_CMDRDLY_S);
1088                 final_delay = final_rise_delay.final_phase;
1089         } else {
1090                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1091                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1092                                 final_fall_delay.final_phase <<
1093                                 MSDC_PAD_TUNE_CMDRDLY_S);
1094                 final_delay = final_fall_delay.final_phase;
1095         }
1096
1097         if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1098                 goto skip_internal;
1099
1100         for (i = 0; i < PAD_DELAY_MAX; i++) {
1101                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1102                                 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1103
1104                 mmc_send_tuning(mmc, opcode, &cmd_err);
1105                 if (!cmd_err)
1106                         internal_delay |= (1 << i);
1107         }
1108
1109         dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
1110
1111         internal_delay_phase = get_best_delay(host, internal_delay);
1112         clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1113                         internal_delay_phase.final_phase <<
1114                         MSDC_PAD_TUNE_CMDRRDLY_S);
1115
1116 skip_internal:
1117         dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1118         return final_delay == 0xff ? -EIO : 0;
1119 }
1120
1121 static int msdc_tune_data(struct udevice *dev, u32 opcode)
1122 {
1123         struct msdc_plat *plat = dev_get_platdata(dev);
1124         struct msdc_host *host = dev_get_priv(dev);
1125         struct mmc *mmc = &plat->mmc;
1126         u32 rise_delay = 0, fall_delay = 0;
1127         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1128         u8 final_delay, final_maxlen;
1129         void __iomem *tune_reg = &host->base->pad_tune;
1130         int cmd_err;
1131         int i, ret;
1132
1133         if (host->dev_comp->pad_tune0)
1134                 tune_reg = &host->base->pad_tune0;
1135
1136         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1137         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1138
1139         for (i = 0; i < PAD_DELAY_MAX; i++) {
1140                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1141                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1142
1143                 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1144                 if (!ret) {
1145                         rise_delay |= (1 << i);
1146                 } else if (cmd_err) {
1147                         /* in this case, retune response is needed */
1148                         ret = msdc_tune_response(dev, opcode);
1149                         if (ret)
1150                                 break;
1151                 }
1152         }
1153
1154         final_rise_delay = get_best_delay(host, rise_delay);
1155         if (final_rise_delay.maxlen >= 12 ||
1156             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1157                 goto skip_fall;
1158
1159         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1160         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1161
1162         for (i = 0; i < PAD_DELAY_MAX; i++) {
1163                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1164                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1165
1166                 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1167                 if (!ret) {
1168                         fall_delay |= (1 << i);
1169                 } else if (cmd_err) {
1170                         /* in this case, retune response is needed */
1171                         ret = msdc_tune_response(dev, opcode);
1172                         if (ret)
1173                                 break;
1174                 }
1175         }
1176
1177         final_fall_delay = get_best_delay(host, fall_delay);
1178
1179 skip_fall:
1180         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1181         if (final_maxlen == final_rise_delay.maxlen) {
1182                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1183                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1184                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1185                                 final_rise_delay.final_phase <<
1186                                 MSDC_PAD_TUNE_DATRRDLY_S);
1187                 final_delay = final_rise_delay.final_phase;
1188         } else {
1189                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1190                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1191                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1192                                 final_fall_delay.final_phase <<
1193                                 MSDC_PAD_TUNE_DATRRDLY_S);
1194                 final_delay = final_fall_delay.final_phase;
1195         }
1196
1197         if (mmc->selected_mode == MMC_HS_200 ||
1198             mmc->selected_mode == UHS_SDR104)
1199                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1200                                 host->hs200_write_int_delay <<
1201                                 MSDC_PAD_TUNE_DATWRDLY_S);
1202
1203         dev_err(dev, "Final data pad delay: %x\n", final_delay);
1204
1205         return final_delay == 0xff ? -EIO : 0;
1206 }
1207
1208 /*
1209  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1210  * together, which can save the tuning time.
1211  */
1212 static int msdc_tune_together(struct udevice *dev, u32 opcode)
1213 {
1214         struct msdc_plat *plat = dev_get_platdata(dev);
1215         struct msdc_host *host = dev_get_priv(dev);
1216         struct mmc *mmc = &plat->mmc;
1217         u32 rise_delay = 0, fall_delay = 0;
1218         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1219         u8 final_delay, final_maxlen;
1220         void __iomem *tune_reg = &host->base->pad_tune;
1221         int i, ret;
1222
1223         if (host->dev_comp->pad_tune0)
1224                 tune_reg = &host->base->pad_tune0;
1225
1226         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1227         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1228
1229         for (i = 0; i < PAD_DELAY_MAX; i++) {
1230                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1231                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1232                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1233                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1234
1235                 ret = mmc_send_tuning(mmc, opcode, NULL);
1236                 if (!ret)
1237                         rise_delay |= (1 << i);
1238         }
1239
1240         final_rise_delay = get_best_delay(host, rise_delay);
1241         if (final_rise_delay.maxlen >= 12 ||
1242             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1243                 goto skip_fall;
1244
1245         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1246         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1247
1248         for (i = 0; i < PAD_DELAY_MAX; i++) {
1249                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1250                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1251                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1252                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1253
1254                 ret = mmc_send_tuning(mmc, opcode, NULL);
1255                 if (!ret)
1256                         fall_delay |= (1 << i);
1257         }
1258
1259         final_fall_delay = get_best_delay(host, fall_delay);
1260
1261 skip_fall:
1262         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1263         if (final_maxlen == final_rise_delay.maxlen) {
1264                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1265                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1266                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1267                                 final_rise_delay.final_phase <<
1268                                 MSDC_PAD_TUNE_CMDRDLY_S);
1269                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1270                                 final_rise_delay.final_phase <<
1271                                 MSDC_PAD_TUNE_DATRRDLY_S);
1272                 final_delay = final_rise_delay.final_phase;
1273         } else {
1274                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1275                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1276                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1277                                 final_fall_delay.final_phase <<
1278                                 MSDC_PAD_TUNE_CMDRDLY_S);
1279                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1280                                 final_fall_delay.final_phase <<
1281                                 MSDC_PAD_TUNE_DATRRDLY_S);
1282                 final_delay = final_fall_delay.final_phase;
1283         }
1284
1285         dev_err(dev, "Final pad delay: %x\n", final_delay);
1286
1287         return final_delay == 0xff ? -EIO : 0;
1288 }
1289
1290 static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1291 {
1292         struct msdc_plat *plat = dev_get_platdata(dev);
1293         struct msdc_host *host = dev_get_priv(dev);
1294         struct mmc *mmc = &plat->mmc;
1295         int ret = 0;
1296
1297         if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
1298                 ret = msdc_tune_together(dev, opcode);
1299                 if (ret == -EIO) {
1300                         dev_err(dev, "Tune fail!\n");
1301                         return ret;
1302                 }
1303
1304                 if (mmc->selected_mode == MMC_HS_400) {
1305                         clrbits_le32(&host->base->msdc_iocon,
1306                                      MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1307                         clrsetbits_le32(&host->base->pad_tune,
1308                                         MSDC_PAD_TUNE_DATRRDLY_M, 0);
1309
1310                         writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1311                         /* for hs400 mode it must be set to 0 */
1312                         clrbits_le32(&host->base->patch_bit2,
1313                                      MSDC_PB2_CFGCRCSTS);
1314                         host->hs400_mode = true;
1315                 }
1316                 goto tune_done;
1317         }
1318
1319         if (mmc->selected_mode == MMC_HS_400)
1320                 ret = hs400_tune_response(dev, opcode);
1321         else
1322                 ret = msdc_tune_response(dev, opcode);
1323         if (ret == -EIO) {
1324                 dev_err(dev, "Tune response fail!\n");
1325                 return ret;
1326         }
1327
1328         if (mmc->selected_mode != MMC_HS_400) {
1329                 ret = msdc_tune_data(dev, opcode);
1330                 if (ret == -EIO) {
1331                         dev_err(dev, "Tune data fail!\n");
1332                         return ret;
1333                 }
1334         }
1335
1336 tune_done:
1337         host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1338         host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1339         host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
1340
1341         return ret;
1342 }
1343 #endif
1344
1345 static void msdc_init_hw(struct msdc_host *host)
1346 {
1347         u32 val;
1348         void __iomem *tune_reg = &host->base->pad_tune;
1349
1350         if (host->dev_comp->pad_tune0)
1351                 tune_reg = &host->base->pad_tune0;
1352
1353         /* Configure to MMC/SD mode, clock free running */
1354         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1355
1356         /* Use PIO mode */
1357         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1358
1359         /* Reset */
1360         msdc_reset_hw(host);
1361
1362         /* Enable/disable hw card detection according to fdt option */
1363         if (host->builtin_cd)
1364                 clrsetbits_le32(&host->base->msdc_ps,
1365                         MSDC_PS_CDDBCE_M,
1366                         (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1367                         MSDC_PS_CDEN);
1368         else
1369                 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1370
1371         /* Clear all interrupts */
1372         val = readl(&host->base->msdc_int);
1373         writel(val, &host->base->msdc_int);
1374
1375         /* Enable data & cmd interrupts */
1376         writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1377
1378         writel(0, tune_reg);
1379         writel(0, &host->base->msdc_iocon);
1380
1381         if (host->r_smpl)
1382                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1383         else
1384                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1385
1386         writel(0x403c0046, &host->base->patch_bit0);
1387         writel(0xffff4089, &host->base->patch_bit1);
1388
1389         if (host->dev_comp->stop_clk_fix)
1390                 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1391                                 3 << MSDC_PB1_STOP_DLY_S);
1392
1393         if (host->dev_comp->busy_check)
1394                 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1395
1396         setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1397
1398         if (host->dev_comp->async_fifo) {
1399                 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1400                                 3 << MSDC_PB2_RESPWAIT_S);
1401
1402                 if (host->dev_comp->enhance_rx) {
1403                         setbits_le32(&host->base->sdc_adv_cfg0,
1404                                      SDC_RX_ENHANCE_EN);
1405                 } else {
1406                         clrsetbits_le32(&host->base->patch_bit2,
1407                                         MSDC_PB2_RESPSTSENSEL_M,
1408                                         2 << MSDC_PB2_RESPSTSENSEL_S);
1409                         clrsetbits_le32(&host->base->patch_bit2,
1410                                         MSDC_PB2_CRCSTSENSEL_M,
1411                                         2 << MSDC_PB2_CRCSTSENSEL_S);
1412                 }
1413
1414                 /* use async fifo to avoid tune internal delay */
1415                 clrbits_le32(&host->base->patch_bit2,
1416                              MSDC_PB2_CFGRESP);
1417                 clrbits_le32(&host->base->patch_bit2,
1418                              MSDC_PB2_CFGCRCSTS);
1419         }
1420
1421         if (host->dev_comp->data_tune) {
1422                 setbits_le32(tune_reg,
1423                              MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1424                 clrsetbits_le32(&host->base->patch_bit0,
1425                                 MSDC_INT_DAT_LATCH_CK_SEL_M,
1426                                 host->latch_ck <<
1427                                 MSDC_INT_DAT_LATCH_CK_SEL_S);
1428         } else {
1429                 /* choose clock tune */
1430                 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1431         }
1432
1433         /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1434         setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1435
1436         /* disable detecting SDIO device interrupt function */
1437         clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1438
1439         /* Configure to default data timeout */
1440         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1441                         3 << SDC_CFG_DTOC_S);
1442
1443         if (host->dev_comp->stop_clk_fix) {
1444                 clrbits_le32(&host->base->sdc_fifo_cfg,
1445                              SDC_FIFO_CFG_WRVALIDSEL);
1446                 clrbits_le32(&host->base->sdc_fifo_cfg,
1447                              SDC_FIFO_CFG_RDVALIDSEL);
1448         }
1449
1450         host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1451         host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1452 }
1453
1454 static void msdc_ungate_clock(struct msdc_host *host)
1455 {
1456         clk_enable(&host->src_clk);
1457         clk_enable(&host->h_clk);
1458         if (host->src_clk_cg.dev)
1459                 clk_enable(&host->src_clk_cg);
1460 }
1461
1462 static int msdc_drv_probe(struct udevice *dev)
1463 {
1464         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1465         struct msdc_plat *plat = dev_get_platdata(dev);
1466         struct msdc_host *host = dev_get_priv(dev);
1467         struct mmc_config *cfg = &plat->cfg;
1468
1469         cfg->name = dev->name;
1470
1471         host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1472
1473         host->src_clk_freq = clk_get_rate(&host->src_clk);
1474
1475         if (host->dev_comp->clk_div_bits == 8)
1476                 cfg->f_min = host->src_clk_freq / (4 * 255);
1477         else
1478                 cfg->f_min = host->src_clk_freq / (4 * 4095);
1479         cfg->f_max = host->src_clk_freq / 2;
1480
1481         cfg->b_max = 1024;
1482         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1483
1484         host->mmc = &plat->mmc;
1485         host->timeout_ns = 100000000;
1486         host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
1487
1488 #ifdef CONFIG_PINCTRL
1489         pinctrl_select_state(dev, "default");
1490 #endif
1491
1492         msdc_ungate_clock(host);
1493         msdc_init_hw(host);
1494
1495         upriv->mmc = &plat->mmc;
1496
1497         return 0;
1498 }
1499
1500 static int msdc_ofdata_to_platdata(struct udevice *dev)
1501 {
1502         struct msdc_plat *plat = dev_get_platdata(dev);
1503         struct msdc_host *host = dev_get_priv(dev);
1504         struct mmc_config *cfg = &plat->cfg;
1505         int ret;
1506
1507         host->base = (void *)dev_read_addr(dev);
1508         if (!host->base)
1509                 return -EINVAL;
1510
1511         ret = mmc_of_parse(dev, cfg);
1512         if (ret)
1513                 return ret;
1514
1515         ret = clk_get_by_name(dev, "source", &host->src_clk);
1516         if (ret < 0)
1517                 return ret;
1518
1519         ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1520         if (ret < 0)
1521                 return ret;
1522
1523         clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1524
1525 #if CONFIG_IS_ENABLED(DM_GPIO)
1526         gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1527         gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1528 #endif
1529
1530         host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1531         host->hs200_cmd_int_delay =
1532                         dev_read_u32_default(dev, "cmd_int_delay", 0);
1533         host->hs200_write_int_delay =
1534                         dev_read_u32_default(dev, "write_int_delay", 0);
1535         host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1536         host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1537         host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1538         host->cd_active_high = dev_read_bool(dev, "cd-active-high");
1539
1540         return 0;
1541 }
1542
1543 static int msdc_drv_bind(struct udevice *dev)
1544 {
1545         struct msdc_plat *plat = dev_get_platdata(dev);
1546
1547         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1548 }
1549
1550 static const struct dm_mmc_ops msdc_ops = {
1551         .send_cmd = msdc_ops_send_cmd,
1552         .set_ios = msdc_ops_set_ios,
1553         .get_cd = msdc_ops_get_cd,
1554         .get_wp = msdc_ops_get_wp,
1555 #ifdef MMC_SUPPORTS_TUNING
1556         .execute_tuning = msdc_execute_tuning,
1557 #endif
1558 };
1559
1560 static const struct msdc_compatible mt7620_compat = {
1561         .clk_div_bits = 8,
1562         .sclk_cycle_shift = 16,
1563         .pad_tune0 = false,
1564         .async_fifo = false,
1565         .data_tune = false,
1566         .busy_check = false,
1567         .stop_clk_fix = false,
1568         .enhance_rx = false
1569 };
1570
1571 static const struct msdc_compatible mt7623_compat = {
1572         .clk_div_bits = 12,
1573         .sclk_cycle_shift = 20,
1574         .pad_tune0 = true,
1575         .async_fifo = true,
1576         .data_tune = true,
1577         .busy_check = false,
1578         .stop_clk_fix = false,
1579         .enhance_rx = false
1580 };
1581
1582 static const struct msdc_compatible mt8516_compat = {
1583         .clk_div_bits = 12,
1584         .sclk_cycle_shift = 20,
1585         .pad_tune0 = true,
1586         .async_fifo = true,
1587         .data_tune = true,
1588         .busy_check = true,
1589         .stop_clk_fix = true,
1590 };
1591
1592 static const struct msdc_compatible mt8183_compat = {
1593         .clk_div_bits = 12,
1594         .sclk_cycle_shift = 20,
1595         .pad_tune0 = true,
1596         .async_fifo = true,
1597         .data_tune = true,
1598         .busy_check = true,
1599         .stop_clk_fix = true,
1600 };
1601
1602 static const struct udevice_id msdc_ids[] = {
1603         { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
1604         { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
1605         { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
1606         { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
1607         {}
1608 };
1609
1610 U_BOOT_DRIVER(mtk_sd_drv) = {
1611         .name = "mtk_sd",
1612         .id = UCLASS_MMC,
1613         .of_match = msdc_ids,
1614         .ofdata_to_platdata = msdc_ofdata_to_platdata,
1615         .bind = msdc_drv_bind,
1616         .probe = msdc_drv_probe,
1617         .ops = &msdc_ops,
1618         .platdata_auto_alloc_size = sizeof(struct msdc_plat),
1619         .priv_auto_alloc_size = sizeof(struct msdc_host),
1620 };