1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek SD/MMC Card Interface driver
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
18 #include <dm/device_compat.h>
19 #include <dm/pinctrl.h>
20 #include <linux/bitops.h>
22 #include <linux/iopoll.h>
25 #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
26 #define MSDC_CFG_CKMOD_EXT_M 0x300000
27 #define MSDC_CFG_CKMOD_EXT_S 20
28 #define MSDC_CFG_CKDIV_EXT_M 0xfff00
29 #define MSDC_CFG_CKDIV_EXT_S 8
30 #define MSDC_CFG_HS400_CK_MODE BIT(18)
31 #define MSDC_CFG_CKMOD_M 0x30000
32 #define MSDC_CFG_CKMOD_S 16
33 #define MSDC_CFG_CKDIV_M 0xff00
34 #define MSDC_CFG_CKDIV_S 8
35 #define MSDC_CFG_CKSTB BIT(7)
36 #define MSDC_CFG_PIO BIT(3)
37 #define MSDC_CFG_RST BIT(2)
38 #define MSDC_CFG_CKPDN BIT(1)
39 #define MSDC_CFG_MODE BIT(0)
42 #define MSDC_IOCON_W_DSPL BIT(8)
43 #define MSDC_IOCON_DSPL BIT(2)
44 #define MSDC_IOCON_RSPL BIT(1)
47 #define MSDC_PS_DAT0 BIT(16)
48 #define MSDC_PS_CDDBCE_M 0xf000
49 #define MSDC_PS_CDDBCE_S 12
50 #define MSDC_PS_CDSTS BIT(1)
51 #define MSDC_PS_CDEN BIT(0)
53 /* #define MSDC_INT(EN) */
54 #define MSDC_INT_ACMDRDY BIT(3)
55 #define MSDC_INT_ACMDTMO BIT(4)
56 #define MSDC_INT_ACMDCRCERR BIT(5)
57 #define MSDC_INT_CMDRDY BIT(8)
58 #define MSDC_INT_CMDTMO BIT(9)
59 #define MSDC_INT_RSPCRCERR BIT(10)
60 #define MSDC_INT_XFER_COMPL BIT(12)
61 #define MSDC_INT_DATTMO BIT(14)
62 #define MSDC_INT_DATCRCERR BIT(15)
65 #define MSDC_FIFOCS_CLR BIT(31)
66 #define MSDC_FIFOCS_TXCNT_M 0xff0000
67 #define MSDC_FIFOCS_TXCNT_S 16
68 #define MSDC_FIFOCS_RXCNT_M 0xff
69 #define MSDC_FIFOCS_RXCNT_S 0
72 #define SDC_CFG_DTOC_M 0xff000000
73 #define SDC_CFG_DTOC_S 24
74 #define SDC_CFG_SDIOIDE BIT(20)
75 #define SDC_CFG_SDIO BIT(19)
76 #define SDC_CFG_BUSWIDTH_M 0x30000
77 #define SDC_CFG_BUSWIDTH_S 16
80 #define SDC_CMD_BLK_LEN_M 0xfff0000
81 #define SDC_CMD_BLK_LEN_S 16
82 #define SDC_CMD_STOP BIT(14)
83 #define SDC_CMD_WR BIT(13)
84 #define SDC_CMD_DTYPE_M 0x1800
85 #define SDC_CMD_DTYPE_S 11
86 #define SDC_CMD_RSPTYP_M 0x380
87 #define SDC_CMD_RSPTYP_S 7
88 #define SDC_CMD_CMD_M 0x3f
89 #define SDC_CMD_CMD_S 0
92 #define SDC_STS_CMDBUSY BIT(1)
93 #define SDC_STS_SDCBUSY BIT(0)
96 #define SDC_RX_ENHANCE_EN BIT(20)
99 #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
100 #define MSDC_INT_DAT_LATCH_CK_SEL_S 7
103 #define MSDC_PB1_STOP_DLY_M 0xf00
104 #define MSDC_PB1_STOP_DLY_S 8
107 #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
108 #define MSDC_PB2_CRCSTSENSEL_S 29
109 #define MSDC_PB2_CFGCRCSTS BIT(28)
110 #define MSDC_PB2_RESPSTSENSEL_M 0x70000
111 #define MSDC_PB2_RESPSTSENSEL_S 16
112 #define MSDC_PB2_CFGRESP BIT(15)
113 #define MSDC_PB2_RESPWAIT_M 0x0c
114 #define MSDC_PB2_RESPWAIT_S 2
117 #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
118 #define MSDC_PAD_TUNE_CMDRRDLY_S 22
119 #define MSDC_PAD_TUNE_CMD_SEL BIT(21)
120 #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
121 #define MSDC_PAD_TUNE_CMDRDLY_S 16
122 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
123 #define MSDC_PAD_TUNE_RD_SEL BIT(13)
124 #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
125 #define MSDC_PAD_TUNE_DATRRDLY_S 8
126 #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
127 #define MSDC_PAD_TUNE_DATWRDLY_S 0
129 #define PAD_CMD_TUNE_RX_DLY3 0x3E
130 #define PAD_CMD_TUNE_RX_DLY3_S 1
133 #define EMMC50_CFG_CFCSTS_SEL BIT(4)
136 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
137 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
139 /* EMMC_TOP_CONTROL mask */
140 #define PAD_RXDLY_SEL BIT(0)
141 #define DELAY_EN BIT(1)
142 #define PAD_DAT_RD_RXDLY2 (0x1f << 2)
143 #define PAD_DAT_RD_RXDLY (0x1f << 7)
144 #define PAD_DAT_RD_RXDLY_S 7
145 #define PAD_DAT_RD_RXDLY2_SEL BIT(12)
146 #define PAD_DAT_RD_RXDLY_SEL BIT(13)
147 #define DATA_K_VALUE_SEL BIT(14)
148 #define SDC_RX_ENH_EN BIT(15)
150 /* EMMC_TOP_CMD mask */
151 #define PAD_CMD_RXDLY2 (0x1f << 0)
152 #define PAD_CMD_RXDLY (0x1f << 5)
153 #define PAD_CMD_RXDLY_S 5
154 #define PAD_CMD_RD_RXDLY2_SEL BIT(10)
155 #define PAD_CMD_RD_RXDLY_SEL BIT(11)
156 #define PAD_CMD_TX_DLY (0x1f << 12)
158 /* SDC_CFG_BUSWIDTH */
159 #define MSDC_BUS_1BITS 0x0
160 #define MSDC_BUS_4BITS 0x1
161 #define MSDC_BUS_8BITS 0x2
163 #define MSDC_FIFO_SIZE 128
165 #define PAD_DELAY_MAX 32
167 #define DEFAULT_CD_DEBOUNCE 8
169 #define CMD_INTS_MASK \
170 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
172 #define DATA_INTS_MASK \
173 (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
175 /* Register offset */
242 struct msdc_top_regs {
243 u32 emmc_top_control;
246 u32 emmc50_pad_ds_tune;
247 u32 emmc50_pad_dat0_tune;
248 u32 emmc50_pad_dat1_tune;
249 u32 emmc50_pad_dat2_tune;
250 u32 emmc50_pad_dat3_tune;
251 u32 emmc50_pad_dat4_tune;
252 u32 emmc50_pad_dat5_tune;
253 u32 emmc50_pad_dat6_tune;
254 u32 emmc50_pad_dat7_tune;
257 struct msdc_compatible {
268 struct msdc_delay_phase {
275 struct mmc_config cfg;
279 struct msdc_tune_para {
286 struct mtk_sd_regs *base;
287 struct msdc_top_regs *top_base;
290 struct msdc_compatible *dev_comp;
292 struct clk src_clk; /* for SD/MMC bus clock */
293 struct clk src_clk_cg; /* optional, MSDC source clock control gate */
294 struct clk h_clk; /* MSDC core clock */
296 u32 src_clk_freq; /* source clock */
297 u32 mclk; /* mmc framework required bus clock */
298 u32 sclk; /* actual calculated bus clock */
300 /* operation timeout clocks */
306 u32 hs200_cmd_int_delay;
307 u32 hs200_write_int_delay;
309 u32 r_smpl; /* sample edge */
312 /* whether to use gpio detection or built-in hw detection */
316 /* card detection / write protection GPIOs */
317 #if CONFIG_IS_ENABLED(DM_GPIO)
318 struct gpio_desc gpio_wp;
319 struct gpio_desc gpio_cd;
323 uint last_data_write;
325 enum bus_mode timing;
327 struct msdc_tune_para def_tune_para;
328 struct msdc_tune_para saved_tune_para;
331 static void msdc_reset_hw(struct msdc_host *host)
335 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
337 readl_poll_timeout(&host->base->msdc_cfg, reg,
338 !(reg & MSDC_CFG_RST), 1000000);
341 static void msdc_fifo_clr(struct msdc_host *host)
345 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
347 readl_poll_timeout(&host->base->msdc_fifocs, reg,
348 !(reg & MSDC_FIFOCS_CLR), 1000000);
351 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
353 return (readl(&host->base->msdc_fifocs) &
354 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
357 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
359 return (readl(&host->base->msdc_fifocs) &
360 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
363 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
367 switch (cmd->resp_type) {
368 /* Actually, R1, R5, R6, R7 are the same */
390 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
392 struct mmc_data *data)
394 u32 opcode = cmd->cmdidx;
395 u32 resp_type = msdc_cmd_find_resp(host, cmd);
401 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
402 case MMC_CMD_READ_MULTIPLE_BLOCK:
405 case MMC_CMD_WRITE_SINGLE_BLOCK:
406 case MMC_CMD_READ_SINGLE_BLOCK:
407 case SD_CMD_APP_SEND_SCR:
408 case MMC_CMD_SEND_TUNING_BLOCK:
409 case MMC_CMD_SEND_TUNING_BLOCK_HS200:
412 case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
413 case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
414 case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
420 if (data->flags == MMC_DATA_WRITE)
421 rawcmd |= SDC_CMD_WR;
423 if (data->blocks > 1)
426 blocksize = data->blocksize;
429 rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
430 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
431 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
432 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
434 if (opcode == MMC_CMD_STOP_TRANSMISSION)
435 rawcmd |= SDC_CMD_STOP;
440 static int msdc_cmd_done(struct msdc_host *host, int events,
443 u32 *rsp = cmd->response;
446 if (cmd->resp_type & MMC_RSP_PRESENT) {
447 if (cmd->resp_type & MMC_RSP_136) {
448 rsp[0] = readl(&host->base->sdc_resp[3]);
449 rsp[1] = readl(&host->base->sdc_resp[2]);
450 rsp[2] = readl(&host->base->sdc_resp[1]);
451 rsp[3] = readl(&host->base->sdc_resp[0]);
453 rsp[0] = readl(&host->base->sdc_resp[0]);
457 if (!(events & MSDC_INT_CMDRDY)) {
458 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
459 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
461 * should not clear fifo/interrupt as the tune data
462 * may have alreay come.
466 if (events & MSDC_INT_CMDTMO)
475 static bool msdc_cmd_is_ready(struct msdc_host *host)
480 /* The max busy time we can endure is 20ms */
481 ret = readl_poll_timeout(&host->base->sdc_sts, reg,
482 !(reg & SDC_STS_CMDBUSY), 20000);
485 pr_err("CMD bus busy detected\n");
490 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
491 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
492 reg & MSDC_PS_DAT0, 1000000);
495 pr_err("Card stuck in programming state!\n");
504 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
505 struct mmc_data *data)
512 if (!msdc_cmd_is_ready(host))
515 if ((readl(&host->base->msdc_fifocs) &
516 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
517 (readl(&host->base->msdc_fifocs) &
518 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
519 pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
525 host->last_resp_type = cmd->resp_type;
526 host->last_data_write = 0;
528 rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
531 blocks = data->blocks;
533 writel(CMD_INTS_MASK, &host->base->msdc_int);
534 writel(DATA_INTS_MASK, &host->base->msdc_int);
535 writel(blocks, &host->base->sdc_blk_num);
536 writel(cmd->cmdarg, &host->base->sdc_arg);
537 writel(rawcmd, &host->base->sdc_cmd);
539 ret = readl_poll_timeout(&host->base->msdc_int, status,
540 status & CMD_INTS_MASK, 1000000);
543 status = MSDC_INT_CMDTMO;
545 return msdc_cmd_done(host, status, cmd);
548 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
552 while ((size_t)buf % 4) {
553 *buf++ = readb(&host->base->msdc_rxdata);
559 *wbuf++ = readl(&host->base->msdc_rxdata);
565 *buf++ = readb(&host->base->msdc_rxdata);
570 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
574 while ((size_t)buf % 4) {
575 writeb(*buf++, &host->base->msdc_txdata);
579 wbuf = (const u32 *)buf;
581 writel(*wbuf++, &host->base->msdc_txdata);
585 buf = (const u8 *)wbuf;
587 writeb(*buf++, &host->base->msdc_txdata);
592 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
599 status = readl(&host->base->msdc_int);
600 writel(status, &host->base->msdc_int);
601 status &= DATA_INTS_MASK;
603 if (status & MSDC_INT_DATCRCERR) {
608 if (status & MSDC_INT_DATTMO) {
613 chksz = min(size, (u32)MSDC_FIFO_SIZE);
615 if (msdc_fifo_rx_bytes(host) >= chksz) {
616 msdc_fifo_read(host, ptr, chksz);
621 if (status & MSDC_INT_XFER_COMPL) {
623 pr_err("data not fully read\n");
634 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
641 status = readl(&host->base->msdc_int);
642 writel(status, &host->base->msdc_int);
643 status &= DATA_INTS_MASK;
645 if (status & MSDC_INT_DATCRCERR) {
650 if (status & MSDC_INT_DATTMO) {
655 if (status & MSDC_INT_XFER_COMPL) {
657 pr_err("data not fully written\n");
664 chksz = min(size, (u32)MSDC_FIFO_SIZE);
666 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
667 msdc_fifo_write(host, ptr, chksz);
676 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
681 if (data->flags == MMC_DATA_WRITE)
682 host->last_data_write = 1;
684 size = data->blocks * data->blocksize;
686 if (data->flags == MMC_DATA_WRITE)
687 ret = msdc_pio_write(host, (const u8 *)data->src, size);
689 ret = msdc_pio_read(host, (u8 *)data->dest, size);
699 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
700 struct mmc_data *data)
702 struct msdc_host *host = dev_get_priv(dev);
703 int cmd_ret, data_ret;
705 cmd_ret = msdc_start_command(host, cmd, data);
708 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
709 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
713 data_ret = msdc_start_data(host, data);
723 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
725 u32 timeout, clk_ns, shift;
728 host->timeout_ns = ns;
729 host->timeout_clks = clks;
731 if (host->sclk == 0) {
734 shift = host->dev_comp->sclk_cycle_shift;
735 clk_ns = 1000000000UL / host->sclk;
736 timeout = (ns + clk_ns - 1) / clk_ns + clks;
737 /* unit is 1048576 sclk cycles */
738 timeout = (timeout + (0x1 << shift) - 1) >> shift;
739 if (host->dev_comp->clk_div_bits == 8)
740 mode = (readl(&host->base->msdc_cfg) &
741 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
743 mode = (readl(&host->base->msdc_cfg) &
744 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
745 /* DDR mode will double the clk cycles for data timeout */
746 timeout = mode >= 2 ? timeout * 2 : timeout;
747 timeout = timeout > 1 ? timeout - 1 : 0;
748 timeout = timeout > 255 ? 255 : timeout;
751 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
752 timeout << SDC_CFG_DTOC_S);
755 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
757 u32 val = readl(&host->base->sdc_cfg);
759 val &= ~SDC_CFG_BUSWIDTH_M;
764 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
767 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
770 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
774 writel(val, &host->base->sdc_cfg);
777 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
786 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
790 if (host->dev_comp->clk_div_bits == 8)
791 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
793 clrbits_le32(&host->base->msdc_cfg,
794 MSDC_CFG_HS400_CK_MODE_EXT);
796 if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
797 timing == MMC_HS_400) {
798 if (timing == MMC_HS_400)
801 mode = 0x2; /* ddr mode and use divisor */
803 if (hz >= (host->src_clk_freq >> 2)) {
804 div = 0; /* mean div = 1/4 */
805 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
807 div = (host->src_clk_freq + ((hz << 2) - 1)) /
809 sclk = (host->src_clk_freq >> 2) / div;
813 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
814 if (host->dev_comp->clk_div_bits == 8)
815 setbits_le32(&host->base->msdc_cfg,
816 MSDC_CFG_HS400_CK_MODE);
818 setbits_le32(&host->base->msdc_cfg,
819 MSDC_CFG_HS400_CK_MODE_EXT);
821 sclk = host->src_clk_freq >> 1;
822 div = 0; /* div is ignore when bit18 is set */
824 } else if (hz >= host->src_clk_freq) {
825 mode = 0x1; /* no divisor */
827 sclk = host->src_clk_freq;
829 mode = 0x0; /* use divisor */
830 if (hz >= (host->src_clk_freq >> 1)) {
831 div = 0; /* mean div = 1/2 */
832 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
834 div = (host->src_clk_freq + ((hz << 2) - 1)) /
836 sclk = (host->src_clk_freq >> 2) / div;
840 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
842 if (host->dev_comp->clk_div_bits == 8) {
843 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
844 clrsetbits_le32(&host->base->msdc_cfg,
845 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
846 (mode << MSDC_CFG_CKMOD_S) |
847 (div << MSDC_CFG_CKDIV_S));
849 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
850 MSDC_CFG_CKDIV_EXT_S));
851 clrsetbits_le32(&host->base->msdc_cfg,
852 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
853 (mode << MSDC_CFG_CKMOD_EXT_S) |
854 (div << MSDC_CFG_CKDIV_EXT_S));
857 readl_poll_timeout(&host->base->msdc_cfg, reg,
858 reg & MSDC_CFG_CKSTB, 1000000);
860 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
863 host->timing = timing;
865 /* needed because clk changed. */
866 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
869 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
870 * tune result of hs200/200Mhz is not suitable for 50Mhz
872 if (host->sclk <= 52000000) {
873 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
874 writel(host->def_tune_para.pad_tune,
875 &host->base->pad_tune);
877 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
878 writel(host->saved_tune_para.pad_tune,
879 &host->base->pad_tune);
882 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
885 static int msdc_ops_set_ios(struct udevice *dev)
887 struct msdc_plat *plat = dev_get_platdata(dev);
888 struct msdc_host *host = dev_get_priv(dev);
889 struct mmc *mmc = &plat->mmc;
890 uint clock = mmc->clock;
892 msdc_set_buswidth(host, mmc->bus_width);
894 if (mmc->clk_disable)
896 else if (clock < mmc->cfg->f_min)
897 clock = mmc->cfg->f_min;
899 if (host->mclk != clock || host->timing != mmc->selected_mode)
900 msdc_set_mclk(host, mmc->selected_mode, clock);
905 static int msdc_ops_get_cd(struct udevice *dev)
907 struct msdc_host *host = dev_get_priv(dev);
910 if (host->builtin_cd) {
911 val = readl(&host->base->msdc_ps);
912 val = !!(val & MSDC_PS_CDSTS);
914 return !val ^ host->cd_active_high;
917 #if CONFIG_IS_ENABLED(DM_GPIO)
918 if (!host->gpio_cd.dev)
921 return dm_gpio_get_value(&host->gpio_cd);
927 static int msdc_ops_get_wp(struct udevice *dev)
929 #if CONFIG_IS_ENABLED(DM_GPIO)
930 struct msdc_host *host = dev_get_priv(dev);
932 if (!host->gpio_wp.dev)
935 return !dm_gpio_get_value(&host->gpio_wp);
941 #ifdef MMC_SUPPORTS_TUNING
942 static u32 test_delay_bit(u32 delay, u32 bit)
944 bit %= PAD_DELAY_MAX;
945 return delay & (1 << bit);
948 static int get_delay_len(u32 delay, u32 start_bit)
952 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
953 if (test_delay_bit(delay, start_bit + i) == 0)
957 return PAD_DELAY_MAX - start_bit;
960 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
962 int start = 0, len = 0;
963 int start_final = 0, len_final = 0;
964 u8 final_phase = 0xff;
965 struct msdc_delay_phase delay_phase = { 0, };
968 dev_err(dev, "phase error: [map:%x]\n", delay);
969 delay_phase.final_phase = final_phase;
973 while (start < PAD_DELAY_MAX) {
974 len = get_delay_len(delay, start);
975 if (len_final < len) {
980 start += len ? len : 1;
981 if (len >= 12 && start_final < 4)
985 /* The rule is to find the smallest delay cell */
986 if (start_final == 0)
987 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
989 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
991 dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
992 delay, len_final, final_phase);
994 delay_phase.maxlen = len_final;
995 delay_phase.start = start_final;
996 delay_phase.final_phase = final_phase;
1000 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1002 void __iomem *tune_reg = &host->base->pad_tune;
1004 if (host->dev_comp->pad_tune0)
1005 tune_reg = &host->base->pad_tune0;
1008 clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
1009 value << PAD_CMD_RXDLY_S);
1011 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1012 value << MSDC_PAD_TUNE_CMDRDLY_S);
1015 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1017 void __iomem *tune_reg = &host->base->pad_tune;
1019 if (host->dev_comp->pad_tune0)
1020 tune_reg = &host->base->pad_tune0;
1023 clrsetbits_le32(&host->top_base->emmc_top_control,
1024 PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
1026 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1027 value << MSDC_PAD_TUNE_DATRRDLY_S);
1030 static int hs400_tune_response(struct udevice *dev, u32 opcode)
1032 struct msdc_plat *plat = dev_get_platdata(dev);
1033 struct msdc_host *host = dev_get_priv(dev);
1034 struct mmc *mmc = &plat->mmc;
1036 struct msdc_delay_phase final_cmd_delay = { 0, };
1038 void __iomem *tune_reg = &host->base->pad_cmd_tune;
1042 setbits_le32(&host->base->pad_cmd_tune, BIT(0));
1044 if (mmc->selected_mode == MMC_HS_200 ||
1045 mmc->selected_mode == UHS_SDR104)
1046 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1047 host->hs200_cmd_int_delay <<
1048 MSDC_PAD_TUNE_CMDRRDLY_S);
1051 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1053 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1055 for (i = 0; i < PAD_DELAY_MAX; i++) {
1056 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1057 i << PAD_CMD_TUNE_RX_DLY3_S);
1059 for (j = 0; j < 3; j++) {
1060 mmc_send_tuning(mmc, opcode, &cmd_err);
1062 cmd_delay |= (1 << i);
1064 cmd_delay &= ~(1 << i);
1070 final_cmd_delay = get_best_delay(host, cmd_delay);
1071 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1072 final_cmd_delay.final_phase <<
1073 PAD_CMD_TUNE_RX_DLY3_S);
1074 final_delay = final_cmd_delay.final_phase;
1076 dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
1077 return final_delay == 0xff ? -EIO : 0;
1080 static int msdc_tune_response(struct udevice *dev, u32 opcode)
1082 struct msdc_plat *plat = dev_get_platdata(dev);
1083 struct msdc_host *host = dev_get_priv(dev);
1084 struct mmc *mmc = &plat->mmc;
1085 u32 rise_delay = 0, fall_delay = 0;
1086 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1087 struct msdc_delay_phase internal_delay_phase;
1088 u8 final_delay, final_maxlen;
1089 u32 internal_delay = 0;
1090 void __iomem *tune_reg = &host->base->pad_tune;
1094 if (host->dev_comp->pad_tune0)
1095 tune_reg = &host->base->pad_tune0;
1097 if (mmc->selected_mode == MMC_HS_200 ||
1098 mmc->selected_mode == UHS_SDR104)
1099 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1100 host->hs200_cmd_int_delay <<
1101 MSDC_PAD_TUNE_CMDRRDLY_S);
1103 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1105 for (i = 0; i < PAD_DELAY_MAX; i++) {
1106 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1107 i << MSDC_PAD_TUNE_CMDRDLY_S);
1109 for (j = 0; j < 3; j++) {
1110 mmc_send_tuning(mmc, opcode, &cmd_err);
1112 rise_delay |= (1 << i);
1114 rise_delay &= ~(1 << i);
1120 final_rise_delay = get_best_delay(host, rise_delay);
1121 /* if rising edge has enough margin, do not scan falling edge */
1122 if (final_rise_delay.maxlen >= 12 ||
1123 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1126 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1127 for (i = 0; i < PAD_DELAY_MAX; i++) {
1128 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1129 i << MSDC_PAD_TUNE_CMDRDLY_S);
1131 for (j = 0; j < 3; j++) {
1132 mmc_send_tuning(mmc, opcode, &cmd_err);
1134 fall_delay |= (1 << i);
1136 fall_delay &= ~(1 << i);
1142 final_fall_delay = get_best_delay(host, fall_delay);
1145 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1146 if (final_maxlen == final_rise_delay.maxlen) {
1147 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1148 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1149 final_rise_delay.final_phase <<
1150 MSDC_PAD_TUNE_CMDRDLY_S);
1151 final_delay = final_rise_delay.final_phase;
1153 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1154 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1155 final_fall_delay.final_phase <<
1156 MSDC_PAD_TUNE_CMDRDLY_S);
1157 final_delay = final_fall_delay.final_phase;
1160 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1163 for (i = 0; i < PAD_DELAY_MAX; i++) {
1164 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1165 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1167 mmc_send_tuning(mmc, opcode, &cmd_err);
1169 internal_delay |= (1 << i);
1172 dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
1174 internal_delay_phase = get_best_delay(host, internal_delay);
1175 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1176 internal_delay_phase.final_phase <<
1177 MSDC_PAD_TUNE_CMDRRDLY_S);
1180 dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1181 return final_delay == 0xff ? -EIO : 0;
1184 static int msdc_tune_data(struct udevice *dev, u32 opcode)
1186 struct msdc_plat *plat = dev_get_platdata(dev);
1187 struct msdc_host *host = dev_get_priv(dev);
1188 struct mmc *mmc = &plat->mmc;
1189 u32 rise_delay = 0, fall_delay = 0;
1190 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1191 u8 final_delay, final_maxlen;
1192 void __iomem *tune_reg = &host->base->pad_tune;
1196 if (host->dev_comp->pad_tune0)
1197 tune_reg = &host->base->pad_tune0;
1199 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1200 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1202 for (i = 0; i < PAD_DELAY_MAX; i++) {
1203 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1204 i << MSDC_PAD_TUNE_DATRRDLY_S);
1206 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1208 rise_delay |= (1 << i);
1209 } else if (cmd_err) {
1210 /* in this case, retune response is needed */
1211 ret = msdc_tune_response(dev, opcode);
1217 final_rise_delay = get_best_delay(host, rise_delay);
1218 if (final_rise_delay.maxlen >= 12 ||
1219 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1222 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1223 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1225 for (i = 0; i < PAD_DELAY_MAX; i++) {
1226 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1227 i << MSDC_PAD_TUNE_DATRRDLY_S);
1229 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1231 fall_delay |= (1 << i);
1232 } else if (cmd_err) {
1233 /* in this case, retune response is needed */
1234 ret = msdc_tune_response(dev, opcode);
1240 final_fall_delay = get_best_delay(host, fall_delay);
1243 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1244 if (final_maxlen == final_rise_delay.maxlen) {
1245 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1246 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1247 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1248 final_rise_delay.final_phase <<
1249 MSDC_PAD_TUNE_DATRRDLY_S);
1250 final_delay = final_rise_delay.final_phase;
1252 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1253 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1254 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1255 final_fall_delay.final_phase <<
1256 MSDC_PAD_TUNE_DATRRDLY_S);
1257 final_delay = final_fall_delay.final_phase;
1260 if (mmc->selected_mode == MMC_HS_200 ||
1261 mmc->selected_mode == UHS_SDR104)
1262 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1263 host->hs200_write_int_delay <<
1264 MSDC_PAD_TUNE_DATWRDLY_S);
1266 dev_err(dev, "Final data pad delay: %x\n", final_delay);
1268 return final_delay == 0xff ? -EIO : 0;
1272 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1273 * together, which can save the tuning time.
1275 static int msdc_tune_together(struct udevice *dev, u32 opcode)
1277 struct msdc_plat *plat = dev_get_platdata(dev);
1278 struct msdc_host *host = dev_get_priv(dev);
1279 struct mmc *mmc = &plat->mmc;
1280 u32 rise_delay = 0, fall_delay = 0;
1281 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1282 u8 final_delay, final_maxlen;
1285 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1286 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1288 for (i = 0; i < PAD_DELAY_MAX; i++) {
1289 msdc_set_cmd_delay(host, i);
1290 msdc_set_data_delay(host, i);
1291 ret = mmc_send_tuning(mmc, opcode, NULL);
1293 rise_delay |= (1 << i);
1296 final_rise_delay = get_best_delay(host, rise_delay);
1297 if (final_rise_delay.maxlen >= 12 ||
1298 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1301 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1302 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1304 for (i = 0; i < PAD_DELAY_MAX; i++) {
1305 msdc_set_cmd_delay(host, i);
1306 msdc_set_data_delay(host, i);
1307 ret = mmc_send_tuning(mmc, opcode, NULL);
1309 fall_delay |= (1 << i);
1312 final_fall_delay = get_best_delay(host, fall_delay);
1315 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1316 if (final_maxlen == final_rise_delay.maxlen) {
1317 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1318 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1319 final_delay = final_rise_delay.final_phase;
1321 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1322 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1323 final_delay = final_fall_delay.final_phase;
1326 msdc_set_cmd_delay(host, final_delay);
1327 msdc_set_data_delay(host, final_delay);
1329 dev_info(dev, "Final pad delay: %x\n", final_delay);
1330 return final_delay == 0xff ? -EIO : 0;
1333 static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1335 struct msdc_plat *plat = dev_get_platdata(dev);
1336 struct msdc_host *host = dev_get_priv(dev);
1337 struct mmc *mmc = &plat->mmc;
1340 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
1341 ret = msdc_tune_together(dev, opcode);
1343 dev_err(dev, "Tune fail!\n");
1347 if (mmc->selected_mode == MMC_HS_400) {
1348 clrbits_le32(&host->base->msdc_iocon,
1349 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1350 clrsetbits_le32(&host->base->pad_tune,
1351 MSDC_PAD_TUNE_DATRRDLY_M, 0);
1353 writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1354 /* for hs400 mode it must be set to 0 */
1355 clrbits_le32(&host->base->patch_bit2,
1356 MSDC_PB2_CFGCRCSTS);
1357 host->hs400_mode = true;
1362 if (mmc->selected_mode == MMC_HS_400)
1363 ret = hs400_tune_response(dev, opcode);
1365 ret = msdc_tune_response(dev, opcode);
1367 dev_err(dev, "Tune response fail!\n");
1371 if (mmc->selected_mode != MMC_HS_400) {
1372 ret = msdc_tune_data(dev, opcode);
1374 dev_err(dev, "Tune data fail!\n");
1380 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1381 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1382 host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
1388 static void msdc_init_hw(struct msdc_host *host)
1391 void __iomem *tune_reg = &host->base->pad_tune;
1393 if (host->dev_comp->pad_tune0)
1394 tune_reg = &host->base->pad_tune0;
1396 /* Configure to MMC/SD mode, clock free running */
1397 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1400 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1403 msdc_reset_hw(host);
1405 /* Enable/disable hw card detection according to fdt option */
1406 if (host->builtin_cd)
1407 clrsetbits_le32(&host->base->msdc_ps,
1409 (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1412 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1414 /* Clear all interrupts */
1415 val = readl(&host->base->msdc_int);
1416 writel(val, &host->base->msdc_int);
1418 /* Enable data & cmd interrupts */
1419 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1421 writel(0, tune_reg);
1422 writel(0, &host->base->msdc_iocon);
1425 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1427 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1429 writel(0x403c0046, &host->base->patch_bit0);
1430 writel(0xffff4089, &host->base->patch_bit1);
1432 if (host->dev_comp->stop_clk_fix)
1433 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1434 3 << MSDC_PB1_STOP_DLY_S);
1436 if (host->dev_comp->busy_check)
1437 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1439 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1441 if (host->dev_comp->async_fifo) {
1442 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1443 3 << MSDC_PB2_RESPWAIT_S);
1445 if (host->dev_comp->enhance_rx) {
1447 setbits_le32(&host->top_base->emmc_top_control,
1450 setbits_le32(&host->base->sdc_adv_cfg0,
1453 clrsetbits_le32(&host->base->patch_bit2,
1454 MSDC_PB2_RESPSTSENSEL_M,
1455 2 << MSDC_PB2_RESPSTSENSEL_S);
1456 clrsetbits_le32(&host->base->patch_bit2,
1457 MSDC_PB2_CRCSTSENSEL_M,
1458 2 << MSDC_PB2_CRCSTSENSEL_S);
1461 /* use async fifo to avoid tune internal delay */
1462 clrbits_le32(&host->base->patch_bit2,
1464 clrbits_le32(&host->base->patch_bit2,
1465 MSDC_PB2_CFGCRCSTS);
1468 if (host->dev_comp->data_tune) {
1469 setbits_le32(tune_reg,
1470 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1471 clrsetbits_le32(&host->base->patch_bit0,
1472 MSDC_INT_DAT_LATCH_CK_SEL_M,
1474 MSDC_INT_DAT_LATCH_CK_SEL_S);
1476 /* choose clock tune */
1477 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1480 /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1481 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1483 /* disable detecting SDIO device interrupt function */
1484 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1486 /* Configure to default data timeout */
1487 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1488 3 << SDC_CFG_DTOC_S);
1490 if (host->dev_comp->stop_clk_fix) {
1491 clrbits_le32(&host->base->sdc_fifo_cfg,
1492 SDC_FIFO_CFG_WRVALIDSEL);
1493 clrbits_le32(&host->base->sdc_fifo_cfg,
1494 SDC_FIFO_CFG_RDVALIDSEL);
1497 host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1498 host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1501 static void msdc_ungate_clock(struct msdc_host *host)
1503 clk_enable(&host->src_clk);
1504 clk_enable(&host->h_clk);
1505 if (host->src_clk_cg.dev)
1506 clk_enable(&host->src_clk_cg);
1509 static int msdc_drv_probe(struct udevice *dev)
1511 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1512 struct msdc_plat *plat = dev_get_platdata(dev);
1513 struct msdc_host *host = dev_get_priv(dev);
1514 struct mmc_config *cfg = &plat->cfg;
1516 cfg->name = dev->name;
1518 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1520 host->src_clk_freq = clk_get_rate(&host->src_clk);
1522 if (host->dev_comp->clk_div_bits == 8)
1523 cfg->f_min = host->src_clk_freq / (4 * 255);
1525 cfg->f_min = host->src_clk_freq / (4 * 4095);
1528 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1530 host->mmc = &plat->mmc;
1531 host->timeout_ns = 100000000;
1532 host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
1534 #ifdef CONFIG_PINCTRL
1535 pinctrl_select_state(dev, "default");
1538 msdc_ungate_clock(host);
1541 upriv->mmc = &plat->mmc;
1546 static int msdc_ofdata_to_platdata(struct udevice *dev)
1548 struct msdc_plat *plat = dev_get_platdata(dev);
1549 struct msdc_host *host = dev_get_priv(dev);
1550 struct mmc_config *cfg = &plat->cfg;
1551 fdt_addr_t base, top_base;
1554 base = dev_read_addr(dev);
1555 if (base == FDT_ADDR_T_NONE)
1557 host->base = map_sysmem(base, 0);
1559 top_base = dev_read_addr_index(dev, 1);
1560 if (top_base == FDT_ADDR_T_NONE)
1561 host->top_base = NULL;
1563 host->top_base = map_sysmem(top_base, 0);
1565 ret = mmc_of_parse(dev, cfg);
1569 ret = clk_get_by_name(dev, "source", &host->src_clk);
1573 ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1577 clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1579 #if CONFIG_IS_ENABLED(DM_GPIO)
1580 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1581 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1584 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1585 host->hs200_cmd_int_delay =
1586 dev_read_u32_default(dev, "cmd_int_delay", 0);
1587 host->hs200_write_int_delay =
1588 dev_read_u32_default(dev, "write_int_delay", 0);
1589 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1590 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1591 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1592 host->cd_active_high = dev_read_bool(dev, "cd-active-high");
1597 static int msdc_drv_bind(struct udevice *dev)
1599 struct msdc_plat *plat = dev_get_platdata(dev);
1601 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1604 static const struct dm_mmc_ops msdc_ops = {
1605 .send_cmd = msdc_ops_send_cmd,
1606 .set_ios = msdc_ops_set_ios,
1607 .get_cd = msdc_ops_get_cd,
1608 .get_wp = msdc_ops_get_wp,
1609 #ifdef MMC_SUPPORTS_TUNING
1610 .execute_tuning = msdc_execute_tuning,
1614 static const struct msdc_compatible mt7620_compat = {
1616 .sclk_cycle_shift = 16,
1618 .async_fifo = false,
1620 .busy_check = false,
1621 .stop_clk_fix = false,
1625 static const struct msdc_compatible mt7622_compat = {
1631 .stop_clk_fix = true,
1634 static const struct msdc_compatible mt7623_compat = {
1636 .sclk_cycle_shift = 20,
1640 .busy_check = false,
1641 .stop_clk_fix = false,
1645 static const struct msdc_compatible mt8512_compat = {
1647 .sclk_cycle_shift = 20,
1652 .stop_clk_fix = true,
1655 static const struct msdc_compatible mt8516_compat = {
1657 .sclk_cycle_shift = 20,
1662 .stop_clk_fix = true,
1665 static const struct msdc_compatible mt8183_compat = {
1667 .sclk_cycle_shift = 20,
1672 .stop_clk_fix = true,
1675 static const struct udevice_id msdc_ids[] = {
1676 { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
1677 { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
1678 { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
1679 { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
1680 { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
1681 { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
1685 U_BOOT_DRIVER(mtk_sd_drv) = {
1688 .of_match = msdc_ids,
1689 .ofdata_to_platdata = msdc_ofdata_to_platdata,
1690 .bind = msdc_drv_bind,
1691 .probe = msdc_drv_probe,
1693 .platdata_auto_alloc_size = sizeof(struct msdc_plat),
1694 .priv_auto_alloc_size = sizeof(struct msdc_host),