drivers/mmc/mtk-sd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek SD/MMC Card Interface driver
   4  *
   5  * Copyright (C) 2018 MediaTek Inc.
   6  * Author: Weijie Gao <weijie.gao@mediatek.com>
   7  */
   8
   9 #include <clk.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <mmc.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <mapmem.h>
  16 #include <stdbool.h>
  17 #include <watchdog.h>
  18 #include <asm/gpio.h>
  19 #include <dm/pinctrl.h>
  20 #include <linux/bitops.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23
  24 /* MSDC_CFG */
  25 #define MSDC_CFG_HS400_CK_MODE_EXT      BIT(22)
  26 #define MSDC_CFG_CKMOD_EXT_M            0x300000
  27 #define MSDC_CFG_CKMOD_EXT_S            20
  28 #define MSDC_CFG_CKDIV_EXT_M            0xfff00
  29 #define MSDC_CFG_CKDIV_EXT_S            8
  30 #define MSDC_CFG_HS400_CK_MODE          BIT(18)
  31 #define MSDC_CFG_CKMOD_M                0x30000
  32 #define MSDC_CFG_CKMOD_S                16
  33 #define MSDC_CFG_CKDIV_M                0xff00
  34 #define MSDC_CFG_CKDIV_S                8
  35 #define MSDC_CFG_CKSTB                  BIT(7)
  36 #define MSDC_CFG_PIO                    BIT(3)
  37 #define MSDC_CFG_RST                    BIT(2)
  38 #define MSDC_CFG_CKPDN                  BIT(1)
  39 #define MSDC_CFG_MODE                   BIT(0)
  40
  41 /* MSDC_IOCON */
  42 #define MSDC_IOCON_W_DSPL               BIT(8)
  43 #define MSDC_IOCON_DSPL                 BIT(2)
  44 #define MSDC_IOCON_RSPL                 BIT(1)
  45
  46 /* MSDC_PS */
  47 #define MSDC_PS_DAT0                    BIT(16)
  48 #define MSDC_PS_CDDBCE_M                0xf000
  49 #define MSDC_PS_CDDBCE_S                12
  50 #define MSDC_PS_CDSTS                   BIT(1)
  51 #define MSDC_PS_CDEN                    BIT(0)
  52
  53 /* #define MSDC_INT(EN) */
  54 #define MSDC_INT_ACMDRDY                BIT(3)
  55 #define MSDC_INT_ACMDTMO                BIT(4)
  56 #define MSDC_INT_ACMDCRCERR             BIT(5)
  57 #define MSDC_INT_CMDRDY                 BIT(8)
  58 #define MSDC_INT_CMDTMO                 BIT(9)
  59 #define MSDC_INT_RSPCRCERR              BIT(10)
  60 #define MSDC_INT_XFER_COMPL             BIT(12)
  61 #define MSDC_INT_DATTMO                 BIT(14)
  62 #define MSDC_INT_DATCRCERR              BIT(15)
  63
  64 /* MSDC_FIFOCS */
  65 #define MSDC_FIFOCS_CLR                 BIT(31)
  66 #define MSDC_FIFOCS_TXCNT_M             0xff0000
  67 #define MSDC_FIFOCS_TXCNT_S             16
  68 #define MSDC_FIFOCS_RXCNT_M             0xff
  69 #define MSDC_FIFOCS_RXCNT_S             0
  70
  71 /* #define SDC_CFG */
  72 #define SDC_CFG_DTOC_M                  0xff000000
  73 #define SDC_CFG_DTOC_S                  24
  74 #define SDC_CFG_SDIOIDE                 BIT(20)
  75 #define SDC_CFG_SDIO                    BIT(19)
  76 #define SDC_CFG_BUSWIDTH_M              0x30000
  77 #define SDC_CFG_BUSWIDTH_S              16
  78
  79 /* SDC_CMD */
  80 #define SDC_CMD_BLK_LEN_M               0xfff0000
  81 #define SDC_CMD_BLK_LEN_S               16
  82 #define SDC_CMD_STOP                    BIT(14)
  83 #define SDC_CMD_WR                      BIT(13)
  84 #define SDC_CMD_DTYPE_M                 0x1800
  85 #define SDC_CMD_DTYPE_S                 11
  86 #define SDC_CMD_RSPTYP_M                0x380
  87 #define SDC_CMD_RSPTYP_S                7
  88 #define SDC_CMD_CMD_M                   0x3f
  89 #define SDC_CMD_CMD_S                   0
  90
  91 /* SDC_STS */
  92 #define SDC_STS_CMDBUSY                 BIT(1)
  93 #define SDC_STS_SDCBUSY                 BIT(0)
  94
  95 /* SDC_ADV_CFG0 */
  96 #define SDC_RX_ENHANCE_EN               BIT(20)
  97
  98 /* PATCH_BIT0 */
  99 #define MSDC_INT_DAT_LATCH_CK_SEL_M     0x380
 100 #define MSDC_INT_DAT_LATCH_CK_SEL_S     7
 101
 102 /* PATCH_BIT1 */
 103 #define MSDC_PB1_STOP_DLY_M             0xf00
 104 #define MSDC_PB1_STOP_DLY_S             8
 105
 106 /* PATCH_BIT2 */
 107 #define MSDC_PB2_CRCSTSENSEL_M          0xe0000000
 108 #define MSDC_PB2_CRCSTSENSEL_S          29
 109 #define MSDC_PB2_CFGCRCSTS              BIT(28)
 110 #define MSDC_PB2_RESPSTSENSEL_M         0x70000
 111 #define MSDC_PB2_RESPSTSENSEL_S         16
 112 #define MSDC_PB2_CFGRESP                BIT(15)
 113 #define MSDC_PB2_RESPWAIT_M             0x0c
 114 #define MSDC_PB2_RESPWAIT_S             2
 115
 116 /* PAD_TUNE */
 117 #define MSDC_PAD_TUNE_CMDRRDLY_M        0x7c00000
 118 #define MSDC_PAD_TUNE_CMDRRDLY_S        22
 119 #define MSDC_PAD_TUNE_CMD_SEL           BIT(21)
 120 #define MSDC_PAD_TUNE_CMDRDLY_M         0x1f0000
 121 #define MSDC_PAD_TUNE_CMDRDLY_S         16
 122 #define MSDC_PAD_TUNE_RXDLYSEL          BIT(15)
 123 #define MSDC_PAD_TUNE_RD_SEL            BIT(13)
 124 #define MSDC_PAD_TUNE_DATRRDLY_M        0x1f00
 125 #define MSDC_PAD_TUNE_DATRRDLY_S        8
 126 #define MSDC_PAD_TUNE_DATWRDLY_M        0x1f
 127 #define MSDC_PAD_TUNE_DATWRDLY_S        0
 128
 129 #define PAD_CMD_TUNE_RX_DLY3            0x3E
 130 #define PAD_CMD_TUNE_RX_DLY3_S          1
 131
 132 /* EMMC50_CFG0 */
 133 #define EMMC50_CFG_CFCSTS_SEL           BIT(4)
 134
 135 /* SDC_FIFO_CFG */
 136 #define SDC_FIFO_CFG_WRVALIDSEL         BIT(24)
 137 #define SDC_FIFO_CFG_RDVALIDSEL         BIT(25)
 138
 139 /* EMMC_TOP_CONTROL mask */
 140 #define PAD_RXDLY_SEL                   BIT(0)
 141 #define DELAY_EN                        BIT(1)
 142 #define PAD_DAT_RD_RXDLY2               (0x1f << 2)
 143 #define PAD_DAT_RD_RXDLY                (0x1f << 7)
 144 #define PAD_DAT_RD_RXDLY_S              7
 145 #define PAD_DAT_RD_RXDLY2_SEL           BIT(12)
 146 #define PAD_DAT_RD_RXDLY_SEL            BIT(13)
 147 #define DATA_K_VALUE_SEL                BIT(14)
 148 #define SDC_RX_ENH_EN                   BIT(15)
 149
 150 /* EMMC_TOP_CMD mask */
 151 #define PAD_CMD_RXDLY2                  (0x1f << 0)
 152 #define PAD_CMD_RXDLY                   (0x1f << 5)
 153 #define PAD_CMD_RXDLY_S                 5
 154 #define PAD_CMD_RD_RXDLY2_SEL           BIT(10)
 155 #define PAD_CMD_RD_RXDLY_SEL            BIT(11)
 156 #define PAD_CMD_TX_DLY                  (0x1f << 12)
 157
 158 /* SDC_CFG_BUSWIDTH */
 159 #define MSDC_BUS_1BITS                  0x0
 160 #define MSDC_BUS_4BITS                  0x1
 161 #define MSDC_BUS_8BITS                  0x2
 162
 163 #define MSDC_FIFO_SIZE                  128
 164
 165 #define PAD_DELAY_MAX                   32
 166
 167 #define DEFAULT_CD_DEBOUNCE             8
 168
 169 #define CMD_INTS_MASK   \
 170         (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
 171
 172 #define DATA_INTS_MASK  \
 173         (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
 174
 175 /* Register offset */
 176 struct mtk_sd_regs {
 177         u32 msdc_cfg;
 178         u32 msdc_iocon;
 179         u32 msdc_ps;
 180         u32 msdc_int;
 181         u32 msdc_inten;
 182         u32 msdc_fifocs;
 183         u32 msdc_txdata;
 184         u32 msdc_rxdata;
 185         u32 reserved0[4];
 186         u32 sdc_cfg;
 187         u32 sdc_cmd;
 188         u32 sdc_arg;
 189         u32 sdc_sts;
 190         u32 sdc_resp[4];
 191         u32 sdc_blk_num;
 192         u32 sdc_vol_chg;
 193         u32 sdc_csts;
 194         u32 sdc_csts_en;
 195         u32 sdc_datcrc_sts;
 196         u32 sdc_adv_cfg0;
 197         u32 reserved1[2];
 198         u32 emmc_cfg0;
 199         u32 emmc_cfg1;
 200         u32 emmc_sts;
 201         u32 emmc_iocon;
 202         u32 sd_acmd_resp;
 203         u32 sd_acmd19_trg;
 204         u32 sd_acmd19_sts;
 205         u32 dma_sa_high4bit;
 206         u32 dma_sa;
 207         u32 dma_ca;
 208         u32 dma_ctrl;
 209         u32 dma_cfg;
 210         u32 sw_dbg_sel;
 211         u32 sw_dbg_out;
 212         u32 dma_length;
 213         u32 reserved2;
 214         u32 patch_bit0;
 215         u32 patch_bit1;
 216         u32 patch_bit2;
 217         u32 reserved3;
 218         u32 dat0_tune_crc;
 219         u32 dat1_tune_crc;
 220         u32 dat2_tune_crc;
 221         u32 dat3_tune_crc;
 222         u32 cmd_tune_crc;
 223         u32 sdio_tune_wind;
 224         u32 reserved4[5];
 225         u32 pad_tune;
 226         u32 pad_tune0;
 227         u32 pad_tune1;
 228         u32 dat_rd_dly[4];
 229         u32 reserved5[2];
 230         u32 hw_dbg_sel;
 231         u32 main_ver;
 232         u32 eco_ver;
 233         u32 reserved6[27];
 234         u32 pad_ds_tune;
 235         u32 pad_cmd_tune;
 236         u32 reserved7[30];
 237         u32 emmc50_cfg0;
 238         u32 reserved8[7];
 239         u32 sdc_fifo_cfg;
 240 };
 241
 242 struct msdc_top_regs {
 243         u32 emmc_top_control;
 244         u32 emmc_top_cmd;
 245         u32 emmc50_pad_ctl0;
 246         u32 emmc50_pad_ds_tune;
 247         u32 emmc50_pad_dat0_tune;
 248         u32 emmc50_pad_dat1_tune;
 249         u32 emmc50_pad_dat2_tune;
 250         u32 emmc50_pad_dat3_tune;
 251         u32 emmc50_pad_dat4_tune;
 252         u32 emmc50_pad_dat5_tune;
 253         u32 emmc50_pad_dat6_tune;
 254         u32 emmc50_pad_dat7_tune;
 255 };
 256
 257 struct msdc_compatible {
 258         u8 clk_div_bits;
 259         u8 sclk_cycle_shift;
 260         bool pad_tune0;
 261         bool async_fifo;
 262         bool data_tune;
 263         bool busy_check;
 264         bool stop_clk_fix;
 265         bool enhance_rx;
 266 };
 267
 268 struct msdc_delay_phase {
 269         u8 maxlen;
 270         u8 start;
 271         u8 final_phase;
 272 };
 273
 274 struct msdc_plat {
 275         struct mmc_config cfg;
 276         struct mmc mmc;
 277 };
 278
 279 struct msdc_tune_para {
 280         u32 iocon;
 281         u32 pad_tune;
 282         u32 pad_cmd_tune;
 283 };
 284
 285 struct msdc_host {
 286         struct mtk_sd_regs *base;
 287         struct msdc_top_regs *top_base;
 288         struct mmc *mmc;
 289
 290         struct msdc_compatible *dev_comp;
 291
 292         struct clk src_clk;     /* for SD/MMC bus clock */
 293         struct clk src_clk_cg;  /* optional, MSDC source clock control gate */
 294         struct clk h_clk;       /* MSDC core clock */
 295
 296         u32 src_clk_freq;       /* source clock */
 297         u32 mclk;               /* mmc framework required bus clock */
 298         u32 sclk;               /* actual calculated bus clock */
 299
 300         /* operation timeout clocks */
 301         u32 timeout_ns;
 302         u32 timeout_clks;
 303
 304         /* tuning options */
 305         u32 hs400_ds_delay;
 306         u32 hs200_cmd_int_delay;
 307         u32 hs200_write_int_delay;
 308         u32 latch_ck;
 309         u32 r_smpl;             /* sample edge */
 310         bool hs400_mode;
 311
 312         /* whether to use gpio detection or built-in hw detection */
 313         bool builtin_cd;
 314         bool cd_active_high;
 315
 316         /* card detection / write protection GPIOs */
 317 #if CONFIG_IS_ENABLED(DM_GPIO)
 318         struct gpio_desc gpio_wp;
 319         struct gpio_desc gpio_cd;
 320 #endif
 321
 322         uint last_resp_type;
 323         uint last_data_write;
 324
 325         enum bus_mode timing;
 326
 327         struct msdc_tune_para def_tune_para;
 328         struct msdc_tune_para saved_tune_para;
 329 };
 330
 331 static void msdc_reset_hw(struct msdc_host *host)
 332 {
 333         u32 reg;
 334
 335         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
 336
 337         readl_poll_timeout(&host->base->msdc_cfg, reg,
 338                            !(reg & MSDC_CFG_RST), 1000000);
 339 }
 340
 341 static void msdc_fifo_clr(struct msdc_host *host)
 342 {
 343         u32 reg;
 344
 345         setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
 346
 347         readl_poll_timeout(&host->base->msdc_fifocs, reg,
 348                            !(reg & MSDC_FIFOCS_CLR), 1000000);
 349 }
 350
 351 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
 352 {
 353         return (readl(&host->base->msdc_fifocs) &
 354                 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
 355 }
 356
 357 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
 358 {
 359         return (readl(&host->base->msdc_fifocs) &
 360                 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
 361 }
 362
 363 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
 364 {
 365         u32 resp;
 366
 367         switch (cmd->resp_type) {
 368                 /* Actually, R1, R5, R6, R7 are the same */
 369         case MMC_RSP_R1:
 370                 resp = 0x1;
 371                 break;
 372         case MMC_RSP_R1b:
 373                 resp = 0x7;
 374                 break;
 375         case MMC_RSP_R2:
 376                 resp = 0x2;
 377                 break;
 378         case MMC_RSP_R3:
 379                 resp = 0x3;
 380                 break;
 381         case MMC_RSP_NONE:
 382         default:
 383                 resp = 0x0;
 384                 break;
 385         }
 386
 387         return resp;
 388 }
 389
 390 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
 391                                     struct mmc_cmd *cmd,
 392                                     struct mmc_data *data)
 393 {
 394         u32 opcode = cmd->cmdidx;
 395         u32 resp_type = msdc_cmd_find_resp(host, cmd);
 396         uint blocksize = 0;
 397         u32 dtype = 0;
 398         u32 rawcmd = 0;
 399
 400         switch (opcode) {
 401         case MMC_CMD_WRITE_MULTIPLE_BLOCK:
 402         case MMC_CMD_READ_MULTIPLE_BLOCK:
 403                 dtype = 2;
 404                 break;
 405         case MMC_CMD_WRITE_SINGLE_BLOCK:
 406         case MMC_CMD_READ_SINGLE_BLOCK:
 407         case SD_CMD_APP_SEND_SCR:
 408         case MMC_CMD_SEND_TUNING_BLOCK:
 409         case MMC_CMD_SEND_TUNING_BLOCK_HS200:
 410                 dtype = 1;
 411                 break;
 412         case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
 413         case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
 414         case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
 415                 if (data)
 416                         dtype = 1;
 417         }
 418
 419         if (data) {
 420                 if (data->flags == MMC_DATA_WRITE)
 421                         rawcmd |= SDC_CMD_WR;
 422
 423                 if (data->blocks > 1)
 424                         dtype = 2;
 425
 426                 blocksize = data->blocksize;
 427         }
 428
 429         rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
 430                 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
 431                 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
 432                 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
 433
 434         if (opcode == MMC_CMD_STOP_TRANSMISSION)
 435                 rawcmd |= SDC_CMD_STOP;
 436
 437         return rawcmd;
 438 }
 439
 440 static int msdc_cmd_done(struct msdc_host *host, int events,
 441                          struct mmc_cmd *cmd)
 442 {
 443         u32 *rsp = cmd->response;
 444         int ret = 0;
 445
 446         if (cmd->resp_type & MMC_RSP_PRESENT) {
 447                 if (cmd->resp_type & MMC_RSP_136) {
 448                         rsp[0] = readl(&host->base->sdc_resp[3]);
 449                         rsp[1] = readl(&host->base->sdc_resp[2]);
 450                         rsp[2] = readl(&host->base->sdc_resp[1]);
 451                         rsp[3] = readl(&host->base->sdc_resp[0]);
 452                 } else {
 453                         rsp[0] = readl(&host->base->sdc_resp[0]);
 454                 }
 455         }
 456
 457         if (!(events & MSDC_INT_CMDRDY)) {
 458                 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
 459                     cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
 460                         /*
 461                          * should not clear fifo/interrupt as the tune data
 462                          * may have alreay come.
 463                          */
 464                         msdc_reset_hw(host);
 465
 466                 if (events & MSDC_INT_CMDTMO)
 467                         ret = -ETIMEDOUT;
 468                 else
 469                         ret = -EIO;
 470         }
 471
 472         return ret;
 473 }
 474
 475 static bool msdc_cmd_is_ready(struct msdc_host *host)
 476 {
 477         int ret;
 478         u32 reg;
 479
 480         /* The max busy time we can endure is 20ms */
 481         ret = readl_poll_timeout(&host->base->sdc_sts, reg,
 482                                  !(reg & SDC_STS_CMDBUSY), 20000);
 483
 484         if (ret) {
 485                 pr_err("CMD bus busy detected\n");
 486                 msdc_reset_hw(host);
 487                 return false;
 488         }
 489
 490         if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
 491                 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
 492                                          reg & MSDC_PS_DAT0, 1000000);
 493
 494                 if (ret) {
 495                         pr_err("Card stuck in programming state!\n");
 496                         msdc_reset_hw(host);
 497                         return false;
 498                 }
 499         }
 500
 501         return true;
 502 }
 503
 504 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
 505                               struct mmc_data *data)
 506 {
 507         u32 rawcmd;
 508         u32 status;
 509         u32 blocks = 0;
 510         int ret;
 511
 512         if (!msdc_cmd_is_ready(host))
 513                 return -EIO;
 514
 515         if ((readl(&host->base->msdc_fifocs) &
 516             MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
 517             (readl(&host->base->msdc_fifocs) &
 518             MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
 519                 pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
 520                 msdc_reset_hw(host);
 521         }
 522
 523         msdc_fifo_clr(host);
 524
 525         host->last_resp_type = cmd->resp_type;
 526         host->last_data_write = 0;
 527
 528         rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
 529
 530         if (data)
 531                 blocks = data->blocks;
 532
 533         writel(CMD_INTS_MASK, &host->base->msdc_int);
 534         writel(blocks, &host->base->sdc_blk_num);
 535         writel(cmd->cmdarg, &host->base->sdc_arg);
 536         writel(rawcmd, &host->base->sdc_cmd);
 537
 538         ret = readl_poll_timeout(&host->base->msdc_int, status,
 539                                  status & CMD_INTS_MASK, 1000000);
 540
 541         if (ret)
 542                 status = MSDC_INT_CMDTMO;
 543
 544         return msdc_cmd_done(host, status, cmd);
 545 }
 546
 547 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
 548 {
 549         u32 *wbuf;
 550
 551         while ((size_t)buf % 4) {
 552                 *buf++ = readb(&host->base->msdc_rxdata);
 553                 size--;
 554         }
 555
 556         wbuf = (u32 *)buf;
 557         while (size >= 4) {
 558                 *wbuf++ = readl(&host->base->msdc_rxdata);
 559                 size -= 4;
 560         }
 561
 562         buf = (u8 *)wbuf;
 563         while (size) {
 564                 *buf++ = readb(&host->base->msdc_rxdata);
 565                 size--;
 566         }
 567 }
 568
 569 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
 570 {
 571         const u32 *wbuf;
 572
 573         while ((size_t)buf % 4) {
 574                 writeb(*buf++, &host->base->msdc_txdata);
 575                 size--;
 576         }
 577
 578         wbuf = (const u32 *)buf;
 579         while (size >= 4) {
 580                 writel(*wbuf++, &host->base->msdc_txdata);
 581                 size -= 4;
 582         }
 583
 584         buf = (const u8 *)wbuf;
 585         while (size) {
 586                 writeb(*buf++, &host->base->msdc_txdata);
 587                 size--;
 588         }
 589 }
 590
 591 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
 592 {
 593         u32 status;
 594         u32 chksz;
 595         int ret = 0;
 596
 597         while (1) {
 598                 status = readl(&host->base->msdc_int);
 599                 writel(status, &host->base->msdc_int);
 600                 status &= DATA_INTS_MASK;
 601
 602                 if (status & MSDC_INT_DATCRCERR) {
 603                         ret = -EIO;
 604                         break;
 605                 }
 606
 607                 if (status & MSDC_INT_DATTMO) {
 608                         ret = -ETIMEDOUT;
 609                         break;
 610                 }
 611
 612                 chksz = min(size, (u32)MSDC_FIFO_SIZE);
 613
 614                 if (msdc_fifo_rx_bytes(host) >= chksz) {
 615                         msdc_fifo_read(host, ptr, chksz);
 616                         ptr += chksz;
 617                         size -= chksz;
 618                 }
 619
 620                 if (status & MSDC_INT_XFER_COMPL) {
 621                         if (size) {
 622                                 pr_err("data not fully read\n");
 623                                 ret = -EIO;
 624                         }
 625
 626                         break;
 627                 }
 628 }
 629
 630         return ret;
 631 }
 632
 633 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
 634 {
 635         u32 status;
 636         u32 chksz;
 637         int ret = 0;
 638
 639         while (1) {
 640                 status = readl(&host->base->msdc_int);
 641                 writel(status, &host->base->msdc_int);
 642                 status &= DATA_INTS_MASK;
 643
 644                 if (status & MSDC_INT_DATCRCERR) {
 645                         ret = -EIO;
 646                         break;
 647                 }
 648
 649                 if (status & MSDC_INT_DATTMO) {
 650                         ret = -ETIMEDOUT;
 651                         break;
 652                 }
 653
 654                 if (status & MSDC_INT_XFER_COMPL) {
 655                         if (size) {
 656                                 pr_err("data not fully written\n");
 657                                 ret = -EIO;
 658                         }
 659
 660                         break;
 661                 }
 662
 663                 chksz = min(size, (u32)MSDC_FIFO_SIZE);
 664
 665                 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
 666                         msdc_fifo_write(host, ptr, chksz);
 667                         ptr += chksz;
 668                         size -= chksz;
 669                 }
 670         }
 671
 672         return ret;
 673 }
 674
 675 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
 676 {
 677         u32 size;
 678         int ret;
 679
 680         WATCHDOG_RESET();
 681
 682         if (data->flags == MMC_DATA_WRITE)
 683                 host->last_data_write = 1;
 684
 685         writel(DATA_INTS_MASK, &host->base->msdc_int);
 686
 687         size = data->blocks * data->blocksize;
 688
 689         if (data->flags == MMC_DATA_WRITE)
 690                 ret = msdc_pio_write(host, (const u8 *)data->src, size);
 691         else
 692                 ret = msdc_pio_read(host, (u8 *)data->dest, size);
 693
 694         if (ret) {
 695                 msdc_reset_hw(host);
 696                 msdc_fifo_clr(host);
 697         }
 698
 699         return ret;
 700 }
 701
 702 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 703                              struct mmc_data *data)
 704 {
 705         struct msdc_host *host = dev_get_priv(dev);
 706         int cmd_ret, data_ret;
 707
 708         cmd_ret = msdc_start_command(host, cmd, data);
 709         if (cmd_ret &&
 710             !(cmd_ret == -EIO &&
 711             (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 712             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
 713                 return cmd_ret;
 714
 715         if (data) {
 716                 data_ret = msdc_start_data(host, data);
 717                 if (cmd_ret)
 718                         return cmd_ret;
 719                 else
 720                         return data_ret;
 721         }
 722
 723         return 0;
 724 }
 725
 726 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
 727 {
 728         u32 timeout, clk_ns, shift;
 729         u32 mode = 0;
 730
 731         host->timeout_ns = ns;
 732         host->timeout_clks = clks;
 733
 734         if (host->sclk == 0) {
 735                 timeout = 0;
 736         } else {
 737                 shift = host->dev_comp->sclk_cycle_shift;
 738                 clk_ns = 1000000000UL / host->sclk;
 739                 timeout = (ns + clk_ns - 1) / clk_ns + clks;
 740                 /* unit is 1048576 sclk cycles */
 741                 timeout = (timeout + (0x1 << shift) - 1) >> shift;
 742                 if (host->dev_comp->clk_div_bits == 8)
 743                         mode = (readl(&host->base->msdc_cfg) &
 744                                 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
 745                 else
 746                         mode = (readl(&host->base->msdc_cfg) &
 747                                 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
 748                 /* DDR mode will double the clk cycles for data timeout */
 749                 timeout = mode >= 2 ? timeout * 2 : timeout;
 750                 timeout = timeout > 1 ? timeout - 1 : 0;
 751                 timeout = timeout > 255 ? 255 : timeout;
 752         }
 753
 754         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
 755                         timeout << SDC_CFG_DTOC_S);
 756 }
 757
 758 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
 759 {
 760         u32 val = readl(&host->base->sdc_cfg);
 761
 762         val &= ~SDC_CFG_BUSWIDTH_M;
 763
 764         switch (width) {
 765         default:
 766         case 1:
 767                 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
 768                 break;
 769         case 4:
 770                 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
 771                 break;
 772         case 8:
 773                 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
 774                 break;
 775         }
 776
 777         writel(val, &host->base->sdc_cfg);
 778 }
 779
 780 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
 781 {
 782         u32 mode;
 783         u32 div;
 784         u32 sclk;
 785         u32 reg;
 786
 787         if (!hz) {
 788                 host->mclk = 0;
 789                 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 790                 return;
 791         }
 792
 793         if (host->dev_comp->clk_div_bits == 8)
 794                 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
 795         else
 796                 clrbits_le32(&host->base->msdc_cfg,
 797                              MSDC_CFG_HS400_CK_MODE_EXT);
 798
 799         if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
 800             timing == MMC_HS_400) {
 801                 if (timing == MMC_HS_400)
 802                         mode = 0x3;
 803                 else
 804                         mode = 0x2; /* ddr mode and use divisor */
 805
 806                 if (hz >= (host->src_clk_freq >> 2)) {
 807                         div = 0; /* mean div = 1/4 */
 808                         sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
 809                 } else {
 810                         div = (host->src_clk_freq + ((hz << 2) - 1)) /
 811                                (hz << 2);
 812                         sclk = (host->src_clk_freq >> 2) / div;
 813                         div = (div >> 1);
 814                 }
 815
 816                 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
 817                         if (host->dev_comp->clk_div_bits == 8)
 818                                 setbits_le32(&host->base->msdc_cfg,
 819                                              MSDC_CFG_HS400_CK_MODE);
 820                         else
 821                                 setbits_le32(&host->base->msdc_cfg,
 822                                              MSDC_CFG_HS400_CK_MODE_EXT);
 823
 824                         sclk = host->src_clk_freq >> 1;
 825                         div = 0; /* div is ignore when bit18 is set */
 826                 }
 827         } else if (hz >= host->src_clk_freq) {
 828                 mode = 0x1; /* no divisor */
 829                 div = 0;
 830                 sclk = host->src_clk_freq;
 831         } else {
 832                 mode = 0x0; /* use divisor */
 833                 if (hz >= (host->src_clk_freq >> 1)) {
 834                         div = 0; /* mean div = 1/2 */
 835                         sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
 836                 } else {
 837                         div = (host->src_clk_freq + ((hz << 2) - 1)) /
 838                                (hz << 2);
 839                         sclk = (host->src_clk_freq >> 2) / div;
 840                 }
 841         }
 842
 843         clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 844
 845         if (host->dev_comp->clk_div_bits == 8) {
 846                 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
 847                 clrsetbits_le32(&host->base->msdc_cfg,
 848                                 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
 849                                 (mode << MSDC_CFG_CKMOD_S) |
 850                                 (div << MSDC_CFG_CKDIV_S));
 851         } else {
 852                 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
 853                                       MSDC_CFG_CKDIV_EXT_S));
 854                 clrsetbits_le32(&host->base->msdc_cfg,
 855                                 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
 856                                 (mode << MSDC_CFG_CKMOD_EXT_S) |
 857                                 (div << MSDC_CFG_CKDIV_EXT_S));
 858         }
 859
 860         readl_poll_timeout(&host->base->msdc_cfg, reg,
 861                            reg & MSDC_CFG_CKSTB, 1000000);
 862
 863         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
 864         host->sclk = sclk;
 865         host->mclk = hz;
 866         host->timing = timing;
 867
 868         /* needed because clk changed. */
 869         msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
 870
 871         /*
 872          * mmc_select_hs400() will drop to 50Mhz and High speed mode,
 873          * tune result of hs200/200Mhz is not suitable for 50Mhz
 874          */
 875         if (host->sclk <= 52000000) {
 876                 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
 877                 writel(host->def_tune_para.pad_tune,
 878                        &host->base->pad_tune);
 879         } else {
 880                 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
 881                 writel(host->saved_tune_para.pad_tune,
 882                        &host->base->pad_tune);
 883         }
 884
 885         dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
 886 }
 887
 888 static int msdc_ops_set_ios(struct udevice *dev)
 889 {
 890         struct msdc_plat *plat = dev_get_platdata(dev);
 891         struct msdc_host *host = dev_get_priv(dev);
 892         struct mmc *mmc = &plat->mmc;
 893         uint clock = mmc->clock;
 894
 895         msdc_set_buswidth(host, mmc->bus_width);
 896
 897         if (mmc->clk_disable)
 898                 clock = 0;
 899         else if (clock < mmc->cfg->f_min)
 900                 clock = mmc->cfg->f_min;
 901
 902         if (host->mclk != clock || host->timing != mmc->selected_mode)
 903                 msdc_set_mclk(host, mmc->selected_mode, clock);
 904
 905         return 0;
 906 }
 907
 908 static int msdc_ops_get_cd(struct udevice *dev)
 909 {
 910         struct msdc_host *host = dev_get_priv(dev);
 911         u32 val;
 912
 913         if (host->builtin_cd) {
 914                 val = readl(&host->base->msdc_ps);
 915                 val = !!(val & MSDC_PS_CDSTS);
 916
 917                 return !val ^ host->cd_active_high;
 918         }
 919
 920 #if CONFIG_IS_ENABLED(DM_GPIO)
 921         if (!host->gpio_cd.dev)
 922                 return 1;
 923
 924         return dm_gpio_get_value(&host->gpio_cd);
 925 #else
 926         return 1;
 927 #endif
 928 }
 929
 930 static int msdc_ops_get_wp(struct udevice *dev)
 931 {
 932 #if CONFIG_IS_ENABLED(DM_GPIO)
 933         struct msdc_host *host = dev_get_priv(dev);
 934
 935         if (!host->gpio_wp.dev)
 936                 return 0;
 937
 938         return !dm_gpio_get_value(&host->gpio_wp);
 939 #else
 940         return 0;
 941 #endif
 942 }
 943
 944 #ifdef MMC_SUPPORTS_TUNING
 945 static u32 test_delay_bit(u32 delay, u32 bit)
 946 {
 947         bit %= PAD_DELAY_MAX;
 948         return delay & (1 << bit);
 949 }
 950
 951 static int get_delay_len(u32 delay, u32 start_bit)
 952 {
 953         int i;
 954
 955         for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
 956                 if (test_delay_bit(delay, start_bit + i) == 0)
 957                         return i;
 958         }
 959
 960         return PAD_DELAY_MAX - start_bit;
 961 }
 962
 963 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
 964 {
 965         int start = 0, len = 0;
 966         int start_final = 0, len_final = 0;
 967         u8 final_phase = 0xff;
 968         struct msdc_delay_phase delay_phase = { 0, };
 969
 970         if (delay == 0) {
 971                 dev_err(dev, "phase error: [map:%x]\n", delay);
 972                 delay_phase.final_phase = final_phase;
 973                 return delay_phase;
 974         }
 975
 976         while (start < PAD_DELAY_MAX) {
 977                 len = get_delay_len(delay, start);
 978                 if (len_final < len) {
 979                         start_final = start;
 980                         len_final = len;
 981                 }
 982
 983                 start += len ? len : 1;
 984                 if (len >= 12 && start_final < 4)
 985                         break;
 986         }
 987
 988         /* The rule is to find the smallest delay cell */
 989         if (start_final == 0)
 990                 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
 991         else
 992                 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
 993
 994         dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 995                  delay, len_final, final_phase);
 996
 997         delay_phase.maxlen = len_final;
 998         delay_phase.start = start_final;
 999         delay_phase.final_phase = final_phase;
1000         return delay_phase;
1001 }
1002
1003 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1004 {
1005         void __iomem *tune_reg = &host->base->pad_tune;
1006
1007         if (host->dev_comp->pad_tune0)
1008                 tune_reg = &host->base->pad_tune0;
1009
1010         if (host->top_base)
1011                 clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
1012                                 value << PAD_CMD_RXDLY_S);
1013         else
1014                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1015                                 value << MSDC_PAD_TUNE_CMDRDLY_S);
1016 }
1017
1018 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1019 {
1020         void __iomem *tune_reg = &host->base->pad_tune;
1021
1022         if (host->dev_comp->pad_tune0)
1023                 tune_reg = &host->base->pad_tune0;
1024
1025         if (host->top_base)
1026                 clrsetbits_le32(&host->top_base->emmc_top_control,
1027                                 PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
1028         else
1029                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1030                                 value << MSDC_PAD_TUNE_DATRRDLY_S);
1031 }
1032
1033 static int hs400_tune_response(struct udevice *dev, u32 opcode)
1034 {
1035         struct msdc_plat *plat = dev_get_platdata(dev);
1036         struct msdc_host *host = dev_get_priv(dev);
1037         struct mmc *mmc = &plat->mmc;
1038         u32 cmd_delay  = 0;
1039         struct msdc_delay_phase final_cmd_delay = { 0, };
1040         u8 final_delay;
1041         void __iomem *tune_reg = &host->base->pad_cmd_tune;
1042         int cmd_err;
1043         int i, j;
1044
1045         setbits_le32(&host->base->pad_cmd_tune, BIT(0));
1046
1047         if (mmc->selected_mode == MMC_HS_200 ||
1048             mmc->selected_mode == UHS_SDR104)
1049                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1050                                 host->hs200_cmd_int_delay <<
1051                                 MSDC_PAD_TUNE_CMDRRDLY_S);
1052
1053         if (host->r_smpl)
1054                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1055         else
1056                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1057
1058         for (i = 0; i < PAD_DELAY_MAX; i++) {
1059                 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1060                                 i << PAD_CMD_TUNE_RX_DLY3_S);
1061
1062                 for (j = 0; j < 3; j++) {
1063                         mmc_send_tuning(mmc, opcode, &cmd_err);
1064                         if (!cmd_err) {
1065                                 cmd_delay |= (1 << i);
1066                         } else {
1067                                 cmd_delay &= ~(1 << i);
1068                                 break;
1069                         }
1070                 }
1071         }
1072
1073         final_cmd_delay = get_best_delay(host, cmd_delay);
1074         clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1075                         final_cmd_delay.final_phase <<
1076                         PAD_CMD_TUNE_RX_DLY3_S);
1077         final_delay = final_cmd_delay.final_phase;
1078
1079         dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
1080         return final_delay == 0xff ? -EIO : 0;
1081 }
1082
1083 static int msdc_tune_response(struct udevice *dev, u32 opcode)
1084 {
1085         struct msdc_plat *plat = dev_get_platdata(dev);
1086         struct msdc_host *host = dev_get_priv(dev);
1087         struct mmc *mmc = &plat->mmc;
1088         u32 rise_delay = 0, fall_delay = 0;
1089         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1090         struct msdc_delay_phase internal_delay_phase;
1091         u8 final_delay, final_maxlen;
1092         u32 internal_delay = 0;
1093         void __iomem *tune_reg = &host->base->pad_tune;
1094         int cmd_err;
1095         int i, j;
1096
1097         if (host->dev_comp->pad_tune0)
1098                 tune_reg = &host->base->pad_tune0;
1099
1100         if (mmc->selected_mode == MMC_HS_200 ||
1101             mmc->selected_mode == UHS_SDR104)
1102                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1103                                 host->hs200_cmd_int_delay <<
1104                                 MSDC_PAD_TUNE_CMDRRDLY_S);
1105
1106         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1107
1108         for (i = 0; i < PAD_DELAY_MAX; i++) {
1109                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1110                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1111
1112                 for (j = 0; j < 3; j++) {
1113                         mmc_send_tuning(mmc, opcode, &cmd_err);
1114                         if (!cmd_err) {
1115                                 rise_delay |= (1 << i);
1116                         } else {
1117                                 rise_delay &= ~(1 << i);
1118                                 break;
1119                         }
1120                 }
1121         }
1122
1123         final_rise_delay = get_best_delay(host, rise_delay);
1124         /* if rising edge has enough margin, do not scan falling edge */
1125         if (final_rise_delay.maxlen >= 12 ||
1126             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1127                 goto skip_fall;
1128
1129         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1130         for (i = 0; i < PAD_DELAY_MAX; i++) {
1131                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1132                                 i << MSDC_PAD_TUNE_CMDRDLY_S);
1133
1134                 for (j = 0; j < 3; j++) {
1135                         mmc_send_tuning(mmc, opcode, &cmd_err);
1136                         if (!cmd_err) {
1137                                 fall_delay |= (1 << i);
1138                         } else {
1139                                 fall_delay &= ~(1 << i);
1140                                 break;
1141                         }
1142                 }
1143         }
1144
1145         final_fall_delay = get_best_delay(host, fall_delay);
1146
1147 skip_fall:
1148         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1149         if (final_maxlen == final_rise_delay.maxlen) {
1150                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1151                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1152                                 final_rise_delay.final_phase <<
1153                                 MSDC_PAD_TUNE_CMDRDLY_S);
1154                 final_delay = final_rise_delay.final_phase;
1155         } else {
1156                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1157                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1158                                 final_fall_delay.final_phase <<
1159                                 MSDC_PAD_TUNE_CMDRDLY_S);
1160                 final_delay = final_fall_delay.final_phase;
1161         }
1162
1163         if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1164                 goto skip_internal;
1165
1166         for (i = 0; i < PAD_DELAY_MAX; i++) {
1167                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1168                                 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1169
1170                 mmc_send_tuning(mmc, opcode, &cmd_err);
1171                 if (!cmd_err)
1172                         internal_delay |= (1 << i);
1173         }
1174
1175         dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
1176
1177         internal_delay_phase = get_best_delay(host, internal_delay);
1178         clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1179                         internal_delay_phase.final_phase <<
1180                         MSDC_PAD_TUNE_CMDRRDLY_S);
1181
1182 skip_internal:
1183         dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1184         return final_delay == 0xff ? -EIO : 0;
1185 }
1186
1187 static int msdc_tune_data(struct udevice *dev, u32 opcode)
1188 {
1189         struct msdc_plat *plat = dev_get_platdata(dev);
1190         struct msdc_host *host = dev_get_priv(dev);
1191         struct mmc *mmc = &plat->mmc;
1192         u32 rise_delay = 0, fall_delay = 0;
1193         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1194         u8 final_delay, final_maxlen;
1195         void __iomem *tune_reg = &host->base->pad_tune;
1196         int cmd_err;
1197         int i, ret;
1198
1199         if (host->dev_comp->pad_tune0)
1200                 tune_reg = &host->base->pad_tune0;
1201
1202         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1203         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1204
1205         for (i = 0; i < PAD_DELAY_MAX; i++) {
1206                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1207                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1208
1209                 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1210                 if (!ret) {
1211                         rise_delay |= (1 << i);
1212                 } else if (cmd_err) {
1213                         /* in this case, retune response is needed */
1214                         ret = msdc_tune_response(dev, opcode);
1215                         if (ret)
1216                                 break;
1217                 }
1218         }
1219
1220         final_rise_delay = get_best_delay(host, rise_delay);
1221         if (final_rise_delay.maxlen >= 12 ||
1222             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1223                 goto skip_fall;
1224
1225         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1226         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1227
1228         for (i = 0; i < PAD_DELAY_MAX; i++) {
1229                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1230                                 i << MSDC_PAD_TUNE_DATRRDLY_S);
1231
1232                 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1233                 if (!ret) {
1234                         fall_delay |= (1 << i);
1235                 } else if (cmd_err) {
1236                         /* in this case, retune response is needed */
1237                         ret = msdc_tune_response(dev, opcode);
1238                         if (ret)
1239                                 break;
1240                 }
1241         }
1242
1243         final_fall_delay = get_best_delay(host, fall_delay);
1244
1245 skip_fall:
1246         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1247         if (final_maxlen == final_rise_delay.maxlen) {
1248                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1249                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1250                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1251                                 final_rise_delay.final_phase <<
1252                                 MSDC_PAD_TUNE_DATRRDLY_S);
1253                 final_delay = final_rise_delay.final_phase;
1254         } else {
1255                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1256                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1257                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1258                                 final_fall_delay.final_phase <<
1259                                 MSDC_PAD_TUNE_DATRRDLY_S);
1260                 final_delay = final_fall_delay.final_phase;
1261         }
1262
1263         if (mmc->selected_mode == MMC_HS_200 ||
1264             mmc->selected_mode == UHS_SDR104)
1265                 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1266                                 host->hs200_write_int_delay <<
1267                                 MSDC_PAD_TUNE_DATWRDLY_S);
1268
1269         dev_err(dev, "Final data pad delay: %x\n", final_delay);
1270
1271         return final_delay == 0xff ? -EIO : 0;
1272 }
1273
1274 /*
1275  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1276  * together, which can save the tuning time.
1277  */
1278 static int msdc_tune_together(struct udevice *dev, u32 opcode)
1279 {
1280         struct msdc_plat *plat = dev_get_platdata(dev);
1281         struct msdc_host *host = dev_get_priv(dev);
1282         struct mmc *mmc = &plat->mmc;
1283         u32 rise_delay = 0, fall_delay = 0;
1284         struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1285         u8 final_delay, final_maxlen;
1286         int i, ret;
1287
1288         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1289         clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1290
1291         for (i = 0; i < PAD_DELAY_MAX; i++) {
1292                 msdc_set_cmd_delay(host, i);
1293                 msdc_set_data_delay(host, i);
1294                 ret = mmc_send_tuning(mmc, opcode, NULL);
1295                 if (!ret)
1296                         rise_delay |= (1 << i);
1297         }
1298
1299         final_rise_delay = get_best_delay(host, rise_delay);
1300         if (final_rise_delay.maxlen >= 12 ||
1301             (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1302                 goto skip_fall;
1303
1304         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1305         setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1306
1307         for (i = 0; i < PAD_DELAY_MAX; i++) {
1308                 msdc_set_cmd_delay(host, i);
1309                 msdc_set_data_delay(host, i);
1310                 ret = mmc_send_tuning(mmc, opcode, NULL);
1311                 if (!ret)
1312                         fall_delay |= (1 << i);
1313         }
1314
1315         final_fall_delay = get_best_delay(host, fall_delay);
1316
1317 skip_fall:
1318         final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1319         if (final_maxlen == final_rise_delay.maxlen) {
1320                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1321                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1322                 final_delay = final_rise_delay.final_phase;
1323         } else {
1324                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1325                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1326                 final_delay = final_fall_delay.final_phase;
1327         }
1328
1329         msdc_set_cmd_delay(host, final_delay);
1330         msdc_set_data_delay(host, final_delay);
1331
1332         dev_info(dev, "Final pad delay: %x\n", final_delay);
1333         return final_delay == 0xff ? -EIO : 0;
1334 }
1335
1336 static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1337 {
1338         struct msdc_plat *plat = dev_get_platdata(dev);
1339         struct msdc_host *host = dev_get_priv(dev);
1340         struct mmc *mmc = &plat->mmc;
1341         int ret = 0;
1342
1343         if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
1344                 ret = msdc_tune_together(dev, opcode);
1345                 if (ret == -EIO) {
1346                         dev_err(dev, "Tune fail!\n");
1347                         return ret;
1348                 }
1349
1350                 if (mmc->selected_mode == MMC_HS_400) {
1351                         clrbits_le32(&host->base->msdc_iocon,
1352                                      MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1353                         clrsetbits_le32(&host->base->pad_tune,
1354                                         MSDC_PAD_TUNE_DATRRDLY_M, 0);
1355
1356                         writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1357                         /* for hs400 mode it must be set to 0 */
1358                         clrbits_le32(&host->base->patch_bit2,
1359                                      MSDC_PB2_CFGCRCSTS);
1360                         host->hs400_mode = true;
1361                 }
1362                 goto tune_done;
1363         }
1364
1365         if (mmc->selected_mode == MMC_HS_400)
1366                 ret = hs400_tune_response(dev, opcode);
1367         else
1368                 ret = msdc_tune_response(dev, opcode);
1369         if (ret == -EIO) {
1370                 dev_err(dev, "Tune response fail!\n");
1371                 return ret;
1372         }
1373
1374         if (mmc->selected_mode != MMC_HS_400) {
1375                 ret = msdc_tune_data(dev, opcode);
1376                 if (ret == -EIO) {
1377                         dev_err(dev, "Tune data fail!\n");
1378                         return ret;
1379                 }
1380         }
1381
1382 tune_done:
1383         host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1384         host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1385         host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
1386
1387         return ret;
1388 }
1389 #endif
1390
1391 static void msdc_init_hw(struct msdc_host *host)
1392 {
1393         u32 val;
1394         void __iomem *tune_reg = &host->base->pad_tune;
1395
1396         if (host->dev_comp->pad_tune0)
1397                 tune_reg = &host->base->pad_tune0;
1398
1399         /* Configure to MMC/SD mode, clock free running */
1400         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1401
1402         /* Use PIO mode */
1403         setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1404
1405         /* Reset */
1406         msdc_reset_hw(host);
1407
1408         /* Enable/disable hw card detection according to fdt option */
1409         if (host->builtin_cd)
1410                 clrsetbits_le32(&host->base->msdc_ps,
1411                         MSDC_PS_CDDBCE_M,
1412                         (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1413                         MSDC_PS_CDEN);
1414         else
1415                 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1416
1417         /* Clear all interrupts */
1418         val = readl(&host->base->msdc_int);
1419         writel(val, &host->base->msdc_int);
1420
1421         /* Enable data & cmd interrupts */
1422         writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1423
1424         writel(0, tune_reg);
1425         writel(0, &host->base->msdc_iocon);
1426
1427         if (host->r_smpl)
1428                 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1429         else
1430                 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1431
1432         writel(0x403c0046, &host->base->patch_bit0);
1433         writel(0xffff4089, &host->base->patch_bit1);
1434
1435         if (host->dev_comp->stop_clk_fix)
1436                 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1437                                 3 << MSDC_PB1_STOP_DLY_S);
1438
1439         if (host->dev_comp->busy_check)
1440                 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1441
1442         setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1443
1444         if (host->dev_comp->async_fifo) {
1445                 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1446                                 3 << MSDC_PB2_RESPWAIT_S);
1447
1448                 if (host->dev_comp->enhance_rx) {
1449                         if (host->top_base)
1450                                 setbits_le32(&host->top_base->emmc_top_control,
1451                                              SDC_RX_ENH_EN);
1452                         else
1453                                 setbits_le32(&host->base->sdc_adv_cfg0,
1454                                              SDC_RX_ENHANCE_EN);
1455                 } else {
1456                         clrsetbits_le32(&host->base->patch_bit2,
1457                                         MSDC_PB2_RESPSTSENSEL_M,
1458                                         2 << MSDC_PB2_RESPSTSENSEL_S);
1459                         clrsetbits_le32(&host->base->patch_bit2,
1460                                         MSDC_PB2_CRCSTSENSEL_M,
1461                                         2 << MSDC_PB2_CRCSTSENSEL_S);
1462                 }
1463
1464                 /* use async fifo to avoid tune internal delay */
1465                 clrbits_le32(&host->base->patch_bit2,
1466                              MSDC_PB2_CFGRESP);
1467                 clrbits_le32(&host->base->patch_bit2,
1468                              MSDC_PB2_CFGCRCSTS);
1469         }
1470
1471         if (host->dev_comp->data_tune) {
1472                 setbits_le32(tune_reg,
1473                              MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1474                 clrsetbits_le32(&host->base->patch_bit0,
1475                                 MSDC_INT_DAT_LATCH_CK_SEL_M,
1476                                 host->latch_ck <<
1477                                 MSDC_INT_DAT_LATCH_CK_SEL_S);
1478         } else {
1479                 /* choose clock tune */
1480                 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1481         }
1482
1483         /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1484         setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1485
1486         /* disable detecting SDIO device interrupt function */
1487         clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1488
1489         /* Configure to default data timeout */
1490         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1491                         3 << SDC_CFG_DTOC_S);
1492
1493         if (host->dev_comp->stop_clk_fix) {
1494                 clrbits_le32(&host->base->sdc_fifo_cfg,
1495                              SDC_FIFO_CFG_WRVALIDSEL);
1496                 clrbits_le32(&host->base->sdc_fifo_cfg,
1497                              SDC_FIFO_CFG_RDVALIDSEL);
1498         }
1499
1500         host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1501         host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1502 }
1503
1504 static void msdc_ungate_clock(struct msdc_host *host)
1505 {
1506         clk_enable(&host->src_clk);
1507         clk_enable(&host->h_clk);
1508         if (host->src_clk_cg.dev)
1509                 clk_enable(&host->src_clk_cg);
1510 }
1511
1512 static int msdc_drv_probe(struct udevice *dev)
1513 {
1514         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1515         struct msdc_plat *plat = dev_get_platdata(dev);
1516         struct msdc_host *host = dev_get_priv(dev);
1517         struct mmc_config *cfg = &plat->cfg;
1518
1519         cfg->name = dev->name;
1520
1521         host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1522
1523         host->src_clk_freq = clk_get_rate(&host->src_clk);
1524
1525         if (host->dev_comp->clk_div_bits == 8)
1526                 cfg->f_min = host->src_clk_freq / (4 * 255);
1527         else
1528                 cfg->f_min = host->src_clk_freq / (4 * 4095);
1529
1530         cfg->b_max = 1024;
1531         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1532
1533         host->mmc = &plat->mmc;
1534         host->timeout_ns = 100000000;
1535         host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
1536
1537 #ifdef CONFIG_PINCTRL
1538         pinctrl_select_state(dev, "default");
1539 #endif
1540
1541         msdc_ungate_clock(host);
1542         msdc_init_hw(host);
1543
1544         upriv->mmc = &plat->mmc;
1545
1546         return 0;
1547 }
1548
1549 static int msdc_ofdata_to_platdata(struct udevice *dev)
1550 {
1551         struct msdc_plat *plat = dev_get_platdata(dev);
1552         struct msdc_host *host = dev_get_priv(dev);
1553         struct mmc_config *cfg = &plat->cfg;
1554         fdt_addr_t base, top_base;
1555         int ret;
1556
1557         base = dev_read_addr(dev);
1558         if (base == FDT_ADDR_T_NONE)
1559                 return -EINVAL;
1560         host->base = map_sysmem(base, 0);
1561
1562         top_base = dev_read_addr_index(dev, 1);
1563         if (top_base == FDT_ADDR_T_NONE)
1564                 host->top_base = NULL;
1565         else
1566                 host->top_base = map_sysmem(top_base, 0);
1567
1568         ret = mmc_of_parse(dev, cfg);
1569         if (ret)
1570                 return ret;
1571
1572         ret = clk_get_by_name(dev, "source", &host->src_clk);
1573         if (ret < 0)
1574                 return ret;
1575
1576         ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1577         if (ret < 0)
1578                 return ret;
1579
1580         clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1581
1582 #if CONFIG_IS_ENABLED(DM_GPIO)
1583         gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1584         gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1585 #endif
1586
1587         host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1588         host->hs200_cmd_int_delay =
1589                         dev_read_u32_default(dev, "cmd_int_delay", 0);
1590         host->hs200_write_int_delay =
1591                         dev_read_u32_default(dev, "write_int_delay", 0);
1592         host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1593         host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1594         host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1595         host->cd_active_high = dev_read_bool(dev, "cd-active-high");
1596
1597         return 0;
1598 }
1599
1600 static int msdc_drv_bind(struct udevice *dev)
1601 {
1602         struct msdc_plat *plat = dev_get_platdata(dev);
1603
1604         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1605 }
1606
1607 static const struct dm_mmc_ops msdc_ops = {
1608         .send_cmd = msdc_ops_send_cmd,
1609         .set_ios = msdc_ops_set_ios,
1610         .get_cd = msdc_ops_get_cd,
1611         .get_wp = msdc_ops_get_wp,
1612 #ifdef MMC_SUPPORTS_TUNING
1613         .execute_tuning = msdc_execute_tuning,
1614 #endif
1615 };
1616
1617 static const struct msdc_compatible mt7620_compat = {
1618         .clk_div_bits = 8,
1619         .sclk_cycle_shift = 16,
1620         .pad_tune0 = false,
1621         .async_fifo = false,
1622         .data_tune = false,
1623         .busy_check = false,
1624         .stop_clk_fix = false,
1625         .enhance_rx = false
1626 };
1627
1628 static const struct msdc_compatible mt7623_compat = {
1629         .clk_div_bits = 12,
1630         .sclk_cycle_shift = 20,
1631         .pad_tune0 = true,
1632         .async_fifo = true,
1633         .data_tune = true,
1634         .busy_check = false,
1635         .stop_clk_fix = false,
1636         .enhance_rx = false
1637 };
1638
1639 static const struct msdc_compatible mt8512_compat = {
1640         .clk_div_bits = 12,
1641         .sclk_cycle_shift = 20,
1642         .pad_tune0 = true,
1643         .async_fifo = true,
1644         .data_tune = true,
1645         .busy_check = true,
1646         .stop_clk_fix = true,
1647 };
1648
1649 static const struct msdc_compatible mt8516_compat = {
1650         .clk_div_bits = 12,
1651         .sclk_cycle_shift = 20,
1652         .pad_tune0 = true,
1653         .async_fifo = true,
1654         .data_tune = true,
1655         .busy_check = true,
1656         .stop_clk_fix = true,
1657 };
1658
1659 static const struct msdc_compatible mt8183_compat = {
1660         .clk_div_bits = 12,
1661         .sclk_cycle_shift = 20,
1662         .pad_tune0 = true,
1663         .async_fifo = true,
1664         .data_tune = true,
1665         .busy_check = true,
1666         .stop_clk_fix = true,
1667 };
1668
1669 static const struct udevice_id msdc_ids[] = {
1670         { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
1671         { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
1672         { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
1673         { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
1674         { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
1675         {}
1676 };
1677
1678 U_BOOT_DRIVER(mtk_sd_drv) = {
1679         .name = "mtk_sd",
1680         .id = UCLASS_MMC,
1681         .of_match = msdc_ids,
1682         .ofdata_to_platdata = msdc_ofdata_to_platdata,
1683         .bind = msdc_drv_bind,
1684         .probe = msdc_drv_probe,
1685         .ops = &msdc_ops,
1686         .platdata_auto_alloc_size = sizeof(struct msdc_plat),
1687         .priv_auto_alloc_size = sizeof(struct msdc_host),
1688 };