drivers/mmc/mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008, Freescale Semiconductor, Inc
   4  * Andy Fleming
   5  *
   6  * Based vaguely on the Linux code
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <blk.h>
  12 #include <command.h>
  13 #include <dm.h>
  14 #include <dm/device-internal.h>
  15 #include <errno.h>
  16 #include <mmc.h>
  17 #include <part.h>
  18 #include <power/regulator.h>
  19 #include <malloc.h>
  20 #include <memalign.h>
  21 #include <linux/list.h>
  22 #include <div64.h>
  23 #include "mmc_private.h"
  24
  25 #define DEFAULT_CMD6_TIMEOUT_MS  500
  26
  27 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  28
  29 #if !CONFIG_IS_ENABLED(DM_MMC)
  30
  31 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
  32 {
  33         return -ENOSYS;
  34 }
  35
  36 __weak int board_mmc_getwp(struct mmc *mmc)
  37 {
  38         return -1;
  39 }
  40
  41 int mmc_getwp(struct mmc *mmc)
  42 {
  43         int wp;
  44
  45         wp = board_mmc_getwp(mmc);
  46
  47         if (wp < 0) {
  48                 if (mmc->cfg->ops->getwp)
  49                         wp = mmc->cfg->ops->getwp(mmc);
  50                 else
  51                         wp = 0;
  52         }
  53
  54         return wp;
  55 }
  56
  57 __weak int board_mmc_getcd(struct mmc *mmc)
  58 {
  59         return -1;
  60 }
  61 #endif
  62
  63 #ifdef CONFIG_MMC_TRACE
  64 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  65 {
  66         printf("CMD_SEND:%d\n", cmd->cmdidx);
  67         printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  68 }
  69
  70 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  71 {
  72         int i;
  73         u8 *ptr;
  74
  75         if (ret) {
  76                 printf("\t\tRET\t\t\t %d\n", ret);
  77         } else {
  78                 switch (cmd->resp_type) {
  79                 case MMC_RSP_NONE:
  80                         printf("\t\tMMC_RSP_NONE\n");
  81                         break;
  82                 case MMC_RSP_R1:
  83                         printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  84                                 cmd->response[0]);
  85                         break;
  86                 case MMC_RSP_R1b:
  87                         printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  88                                 cmd->response[0]);
  89                         break;
  90                 case MMC_RSP_R2:
  91                         printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  92                                 cmd->response[0]);
  93                         printf("\t\t          \t\t 0x%08x \n",
  94                                 cmd->response[1]);
  95                         printf("\t\t          \t\t 0x%08x \n",
  96                                 cmd->response[2]);
  97                         printf("\t\t          \t\t 0x%08x \n",
  98                                 cmd->response[3]);
  99                         printf("\n");
 100                         printf("\t\t\t\t\tDUMPING DATA\n");
 101                         for (i = 0; i < 4; i++) {
 102                                 int j;
 103                                 printf("\t\t\t\t\t%03d - ", i*4);
 104                                 ptr = (u8 *)&cmd->response[i];
 105                                 ptr += 3;
 106                                 for (j = 0; j < 4; j++)
 107                                         printf("%02x ", *ptr--);
 108                                 printf("\n");
 109                         }
 110                         break;
 111                 case MMC_RSP_R3:
 112                         printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
 113                                 cmd->response[0]);
 114                         break;
 115                 default:
 116                         printf("\t\tERROR MMC rsp not supported\n");
 117                         break;
 118                 }
 119         }
 120 }
 121
 122 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
 123 {
 124         int status;
 125
 126         status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
 127         printf("CURR STATE:%d\n", status);
 128 }
 129 #endif
 130
 131 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
 132 const char *mmc_mode_name(enum bus_mode mode)
 133 {
 134         static const char *const names[] = {
 135               [MMC_LEGACY]      = "MMC legacy",
 136               [MMC_HS]          = "MMC High Speed (26MHz)",
 137               [SD_HS]           = "SD High Speed (50MHz)",
 138               [UHS_SDR12]       = "UHS SDR12 (25MHz)",
 139               [UHS_SDR25]       = "UHS SDR25 (50MHz)",
 140               [UHS_SDR50]       = "UHS SDR50 (100MHz)",
 141               [UHS_SDR104]      = "UHS SDR104 (208MHz)",
 142               [UHS_DDR50]       = "UHS DDR50 (50MHz)",
 143               [MMC_HS_52]       = "MMC High Speed (52MHz)",
 144               [MMC_DDR_52]      = "MMC DDR52 (52MHz)",
 145               [MMC_HS_200]      = "HS200 (200MHz)",
 146               [MMC_HS_400]      = "HS400 (200MHz)",
 147               [MMC_HS_400_ES]   = "HS400ES (200MHz)",
 148         };
 149
 150         if (mode >= MMC_MODES_END)
 151                 return "Unknown mode";
 152         else
 153                 return names[mode];
 154 }
 155 #endif
 156
 157 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
 158 {
 159         static const int freqs[] = {
 160               [MMC_LEGACY]      = 25000000,
 161               [MMC_HS]          = 26000000,
 162               [SD_HS]           = 50000000,
 163               [MMC_HS_52]       = 52000000,
 164               [MMC_DDR_52]      = 52000000,
 165               [UHS_SDR12]       = 25000000,
 166               [UHS_SDR25]       = 50000000,
 167               [UHS_SDR50]       = 100000000,
 168               [UHS_DDR50]       = 50000000,
 169               [UHS_SDR104]      = 208000000,
 170               [MMC_HS_200]      = 200000000,
 171               [MMC_HS_400]      = 200000000,
 172               [MMC_HS_400_ES]   = 200000000,
 173         };
 174
 175         if (mode == MMC_LEGACY)
 176                 return mmc->legacy_speed;
 177         else if (mode >= MMC_MODES_END)
 178                 return 0;
 179         else
 180                 return freqs[mode];
 181 }
 182
 183 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
 184 {
 185         mmc->selected_mode = mode;
 186         mmc->tran_speed = mmc_mode2freq(mmc, mode);
 187         mmc->ddr_mode = mmc_is_mode_ddr(mode);
 188         pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
 189                  mmc->tran_speed / 1000000);
 190         return 0;
 191 }
 192
 193 #if !CONFIG_IS_ENABLED(DM_MMC)
 194 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 195 {
 196         int ret;
 197
 198         mmmc_trace_before_send(mmc, cmd);
 199         ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 200         mmmc_trace_after_send(mmc, cmd, ret);
 201
 202         return ret;
 203 }
 204 #endif
 205
 206 int mmc_send_status(struct mmc *mmc, unsigned int *status)
 207 {
 208         struct mmc_cmd cmd;
 209         int err, retries = 5;
 210
 211         cmd.cmdidx = MMC_CMD_SEND_STATUS;
 212         cmd.resp_type = MMC_RSP_R1;
 213         if (!mmc_host_is_spi(mmc))
 214                 cmd.cmdarg = mmc->rca << 16;
 215
 216         while (retries--) {
 217                 err = mmc_send_cmd(mmc, &cmd, NULL);
 218                 if (!err) {
 219                         mmc_trace_state(mmc, &cmd);
 220                         *status = cmd.response[0];
 221                         return 0;
 222                 }
 223         }
 224         mmc_trace_state(mmc, &cmd);
 225         return -ECOMM;
 226 }
 227
 228 int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
 229 {
 230         unsigned int status;
 231         int err;
 232
 233         err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 234         if (err != -ENOSYS)
 235                 return err;
 236
 237         while (1) {
 238                 err = mmc_send_status(mmc, &status);
 239                 if (err)
 240                         return err;
 241
 242                 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
 243                     (status & MMC_STATUS_CURR_STATE) !=
 244                      MMC_STATE_PRG)
 245                         break;
 246
 247                 if (status & MMC_STATUS_MASK) {
 248 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 249                         pr_err("Status Error: 0x%08x\n", status);
 250 #endif
 251                         return -ECOMM;
 252                 }
 253
 254                 if (timeout_ms-- <= 0)
 255                         break;
 256
 257                 udelay(1000);
 258         }
 259
 260         if (timeout_ms <= 0) {
 261 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 262                 pr_err("Timeout waiting card ready\n");
 263 #endif
 264                 return -ETIMEDOUT;
 265         }
 266
 267         return 0;
 268 }
 269
 270 int mmc_set_blocklen(struct mmc *mmc, int len)
 271 {
 272         struct mmc_cmd cmd;
 273         int err;
 274
 275         if (mmc->ddr_mode)
 276                 return 0;
 277
 278         cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
 279         cmd.resp_type = MMC_RSP_R1;
 280         cmd.cmdarg = len;
 281
 282         err = mmc_send_cmd(mmc, &cmd, NULL);
 283
 284 #ifdef CONFIG_MMC_QUIRKS
 285         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
 286                 int retries = 4;
 287                 /*
 288                  * It has been seen that SET_BLOCKLEN may fail on the first
 289                  * attempt, let's try a few more time
 290                  */
 291                 do {
 292                         err = mmc_send_cmd(mmc, &cmd, NULL);
 293                         if (!err)
 294                                 break;
 295                 } while (retries--);
 296         }
 297 #endif
 298
 299         return err;
 300 }
 301
 302 #ifdef MMC_SUPPORTS_TUNING
 303 static const u8 tuning_blk_pattern_4bit[] = {
 304         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 305         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 306         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 307         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 308         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 309         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 310         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 311         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 312 };
 313
 314 static const u8 tuning_blk_pattern_8bit[] = {
 315         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 316         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 317         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 318         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 319         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 320         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 321         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 322         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 323         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 324         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 325         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 326         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 327         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 328         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 329         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 330         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 331 };
 332
 333 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
 334 {
 335         struct mmc_cmd cmd;
 336         struct mmc_data data;
 337         const u8 *tuning_block_pattern;
 338         int size, err;
 339
 340         if (mmc->bus_width == 8) {
 341                 tuning_block_pattern = tuning_blk_pattern_8bit;
 342                 size = sizeof(tuning_blk_pattern_8bit);
 343         } else if (mmc->bus_width == 4) {
 344                 tuning_block_pattern = tuning_blk_pattern_4bit;
 345                 size = sizeof(tuning_blk_pattern_4bit);
 346         } else {
 347                 return -EINVAL;
 348         }
 349
 350         ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
 351
 352         cmd.cmdidx = opcode;
 353         cmd.cmdarg = 0;
 354         cmd.resp_type = MMC_RSP_R1;
 355
 356         data.dest = (void *)data_buf;
 357         data.blocks = 1;
 358         data.blocksize = size;
 359         data.flags = MMC_DATA_READ;
 360
 361         err = mmc_send_cmd(mmc, &cmd, &data);
 362         if (err)
 363                 return err;
 364
 365         if (memcmp(data_buf, tuning_block_pattern, size))
 366                 return -EIO;
 367
 368         return 0;
 369 }
 370 #endif
 371
 372 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 373                            lbaint_t blkcnt)
 374 {
 375         struct mmc_cmd cmd;
 376         struct mmc_data data;
 377
 378         if (blkcnt > 1)
 379                 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
 380         else
 381                 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
 382
 383         if (mmc->high_capacity)
 384                 cmd.cmdarg = start;
 385         else
 386                 cmd.cmdarg = start * mmc->read_bl_len;
 387
 388         cmd.resp_type = MMC_RSP_R1;
 389
 390         data.dest = dst;
 391         data.blocks = blkcnt;
 392         data.blocksize = mmc->read_bl_len;
 393         data.flags = MMC_DATA_READ;
 394
 395         if (mmc_send_cmd(mmc, &cmd, &data))
 396                 return 0;
 397
 398         if (blkcnt > 1) {
 399                 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 400                 cmd.cmdarg = 0;
 401                 cmd.resp_type = MMC_RSP_R1b;
 402                 if (mmc_send_cmd(mmc, &cmd, NULL)) {
 403 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 404                         pr_err("mmc fail to send stop cmd\n");
 405 #endif
 406                         return 0;
 407                 }
 408         }
 409
 410         return blkcnt;
 411 }
 412
 413 #if !CONFIG_IS_ENABLED(DM_MMC)
 414 static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
 415 {
 416         if (mmc->cfg->ops->get_b_max)
 417                 return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
 418         else
 419                 return mmc->cfg->b_max;
 420 }
 421 #endif
 422
 423 #if CONFIG_IS_ENABLED(BLK)
 424 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
 425 #else
 426 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 427                 void *dst)
 428 #endif
 429 {
 430 #if CONFIG_IS_ENABLED(BLK)
 431         struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 432 #endif
 433         int dev_num = block_dev->devnum;
 434         int err;
 435         lbaint_t cur, blocks_todo = blkcnt;
 436         uint b_max;
 437
 438         if (blkcnt == 0)
 439                 return 0;
 440
 441         struct mmc *mmc = find_mmc_device(dev_num);
 442         if (!mmc)
 443                 return 0;
 444
 445         if (CONFIG_IS_ENABLED(MMC_TINY))
 446                 err = mmc_switch_part(mmc, block_dev->hwpart);
 447         else
 448                 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
 449
 450         if (err < 0)
 451                 return 0;
 452
 453         if ((start + blkcnt) > block_dev->lba) {
 454 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 455                 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
 456                        start + blkcnt, block_dev->lba);
 457 #endif
 458                 return 0;
 459         }
 460
 461         if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
 462                 pr_debug("%s: Failed to set blocklen\n", __func__);
 463                 return 0;
 464         }
 465
 466         b_max = mmc_get_b_max(mmc, dst, blkcnt);
 467
 468         do {
 469                 cur = (blocks_todo > b_max) ? b_max : blocks_todo;
 470                 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
 471                         pr_debug("%s: Failed to read blocks\n", __func__);
 472                         return 0;
 473                 }
 474                 blocks_todo -= cur;
 475                 start += cur;
 476                 dst += cur * mmc->read_bl_len;
 477         } while (blocks_todo > 0);
 478
 479         return blkcnt;
 480 }
 481
 482 static int mmc_go_idle(struct mmc *mmc)
 483 {
 484         struct mmc_cmd cmd;
 485         int err;
 486
 487         udelay(1000);
 488
 489         cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
 490         cmd.cmdarg = 0;
 491         cmd.resp_type = MMC_RSP_NONE;
 492
 493         err = mmc_send_cmd(mmc, &cmd, NULL);
 494
 495         if (err)
 496                 return err;
 497
 498         udelay(2000);
 499
 500         return 0;
 501 }
 502
 503 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 504 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
 505 {
 506         struct mmc_cmd cmd;
 507         int err = 0;
 508
 509         /*
 510          * Send CMD11 only if the request is to switch the card to
 511          * 1.8V signalling.
 512          */
 513         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 514                 return mmc_set_signal_voltage(mmc, signal_voltage);
 515
 516         cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
 517         cmd.cmdarg = 0;
 518         cmd.resp_type = MMC_RSP_R1;
 519
 520         err = mmc_send_cmd(mmc, &cmd, NULL);
 521         if (err)
 522                 return err;
 523
 524         if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
 525                 return -EIO;
 526
 527         /*
 528          * The card should drive cmd and dat[0:3] low immediately
 529          * after the response of cmd11, but wait 100 us to be sure
 530          */
 531         err = mmc_wait_dat0(mmc, 0, 100);
 532         if (err == -ENOSYS)
 533                 udelay(100);
 534         else if (err)
 535                 return -ETIMEDOUT;
 536
 537         /*
 538          * During a signal voltage level switch, the clock must be gated
 539          * for 5 ms according to the SD spec
 540          */
 541         mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
 542
 543         err = mmc_set_signal_voltage(mmc, signal_voltage);
 544         if (err)
 545                 return err;
 546
 547         /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
 548         mdelay(10);
 549         mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
 550
 551         /*
 552          * Failure to switch is indicated by the card holding
 553          * dat[0:3] low. Wait for at least 1 ms according to spec
 554          */
 555         err = mmc_wait_dat0(mmc, 1, 1000);
 556         if (err == -ENOSYS)
 557                 udelay(1000);
 558         else if (err)
 559                 return -ETIMEDOUT;
 560
 561         return 0;
 562 }
 563 #endif
 564
 565 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
 566 {
 567         int timeout = 1000;
 568         int err;
 569         struct mmc_cmd cmd;
 570
 571         while (1) {
 572                 cmd.cmdidx = MMC_CMD_APP_CMD;
 573                 cmd.resp_type = MMC_RSP_R1;
 574                 cmd.cmdarg = 0;
 575
 576                 err = mmc_send_cmd(mmc, &cmd, NULL);
 577
 578                 if (err)
 579                         return err;
 580
 581                 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
 582                 cmd.resp_type = MMC_RSP_R3;
 583
 584                 /*
 585                  * Most cards do not answer if some reserved bits
 586                  * in the ocr are set. However, Some controller
 587                  * can set bit 7 (reserved for low voltages), but
 588                  * how to manage low voltages SD card is not yet
 589                  * specified.
 590                  */
 591                 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
 592                         (mmc->cfg->voltages & 0xff8000);
 593
 594                 if (mmc->version == SD_VERSION_2)
 595                         cmd.cmdarg |= OCR_HCS;
 596
 597                 if (uhs_en)
 598                         cmd.cmdarg |= OCR_S18R;
 599
 600                 err = mmc_send_cmd(mmc, &cmd, NULL);
 601
 602                 if (err)
 603                         return err;
 604
 605                 if (cmd.response[0] & OCR_BUSY)
 606                         break;
 607
 608                 if (timeout-- <= 0)
 609                         return -EOPNOTSUPP;
 610
 611                 udelay(1000);
 612         }
 613
 614         if (mmc->version != SD_VERSION_2)
 615                 mmc->version = SD_VERSION_1_0;
 616
 617         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 618                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 619                 cmd.resp_type = MMC_RSP_R3;
 620                 cmd.cmdarg = 0;
 621
 622                 err = mmc_send_cmd(mmc, &cmd, NULL);
 623
 624                 if (err)
 625                         return err;
 626         }
 627
 628         mmc->ocr = cmd.response[0];
 629
 630 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 631         if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
 632             == 0x41000000) {
 633                 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
 634                 if (err)
 635                         return err;
 636         }
 637 #endif
 638
 639         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 640         mmc->rca = 0;
 641
 642         return 0;
 643 }
 644
 645 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
 646 {
 647         struct mmc_cmd cmd;
 648         int err;
 649
 650         cmd.cmdidx = MMC_CMD_SEND_OP_COND;
 651         cmd.resp_type = MMC_RSP_R3;
 652         cmd.cmdarg = 0;
 653         if (use_arg && !mmc_host_is_spi(mmc))
 654                 cmd.cmdarg = OCR_HCS |
 655                         (mmc->cfg->voltages &
 656                         (mmc->ocr & OCR_VOLTAGE_MASK)) |
 657                         (mmc->ocr & OCR_ACCESS_MODE);
 658
 659         err = mmc_send_cmd(mmc, &cmd, NULL);
 660         if (err)
 661                 return err;
 662         mmc->ocr = cmd.response[0];
 663         return 0;
 664 }
 665
 666 static int mmc_send_op_cond(struct mmc *mmc)
 667 {
 668         int err, i;
 669
 670         /* Some cards seem to need this */
 671         mmc_go_idle(mmc);
 672
 673         /* Asking to the card its capabilities */
 674         for (i = 0; i < 2; i++) {
 675                 err = mmc_send_op_cond_iter(mmc, i != 0);
 676                 if (err)
 677                         return err;
 678
 679                 /* exit if not busy (flag seems to be inverted) */
 680                 if (mmc->ocr & OCR_BUSY)
 681                         break;
 682         }
 683         mmc->op_cond_pending = 1;
 684         return 0;
 685 }
 686
 687 static int mmc_complete_op_cond(struct mmc *mmc)
 688 {
 689         struct mmc_cmd cmd;
 690         int timeout = 1000;
 691         ulong start;
 692         int err;
 693
 694         mmc->op_cond_pending = 0;
 695         if (!(mmc->ocr & OCR_BUSY)) {
 696                 /* Some cards seem to need this */
 697                 mmc_go_idle(mmc);
 698
 699                 start = get_timer(0);
 700                 while (1) {
 701                         err = mmc_send_op_cond_iter(mmc, 1);
 702                         if (err)
 703                                 return err;
 704                         if (mmc->ocr & OCR_BUSY)
 705                                 break;
 706                         if (get_timer(start) > timeout)
 707                                 return -EOPNOTSUPP;
 708                         udelay(100);
 709                 }
 710         }
 711
 712         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 713                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 714                 cmd.resp_type = MMC_RSP_R3;
 715                 cmd.cmdarg = 0;
 716
 717                 err = mmc_send_cmd(mmc, &cmd, NULL);
 718
 719                 if (err)
 720                         return err;
 721
 722                 mmc->ocr = cmd.response[0];
 723         }
 724
 725         mmc->version = MMC_VERSION_UNKNOWN;
 726
 727         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 728         mmc->rca = 1;
 729
 730         return 0;
 731 }
 732
 733
 734 int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 735 {
 736         struct mmc_cmd cmd;
 737         struct mmc_data data;
 738         int err;
 739
 740         /* Get the Card Status Register */
 741         cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
 742         cmd.resp_type = MMC_RSP_R1;
 743         cmd.cmdarg = 0;
 744
 745         data.dest = (char *)ext_csd;
 746         data.blocks = 1;
 747         data.blocksize = MMC_MAX_BLOCK_LEN;
 748         data.flags = MMC_DATA_READ;
 749
 750         err = mmc_send_cmd(mmc, &cmd, &data);
 751
 752         return err;
 753 }
 754
 755 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 756                         bool send_status)
 757 {
 758         unsigned int status, start;
 759         struct mmc_cmd cmd;
 760         int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
 761         bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
 762                               (index == EXT_CSD_PART_CONF);
 763         int retries = 3;
 764         int ret;
 765
 766         if (mmc->gen_cmd6_time)
 767                 timeout_ms = mmc->gen_cmd6_time * 10;
 768
 769         if (is_part_switch  && mmc->part_switch_time)
 770                 timeout_ms = mmc->part_switch_time * 10;
 771
 772         cmd.cmdidx = MMC_CMD_SWITCH;
 773         cmd.resp_type = MMC_RSP_R1b;
 774         cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
 775                                  (index << 16) |
 776                                  (value << 8);
 777
 778         do {
 779                 ret = mmc_send_cmd(mmc, &cmd, NULL);
 780         } while (ret && retries-- > 0);
 781
 782         if (ret)
 783                 return ret;
 784
 785         start = get_timer(0);
 786
 787         /* poll dat0 for rdy/buys status */
 788         ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 789         if (ret && ret != -ENOSYS)
 790                 return ret;
 791
 792         /*
 793          * In cases when not allowed to poll by using CMD13 or because we aren't
 794          * capable of polling by using mmc_wait_dat0, then rely on waiting the
 795          * stated timeout to be sufficient.
 796          */
 797         if (ret == -ENOSYS && !send_status)
 798                 mdelay(timeout_ms);
 799
 800         /* Finally wait until the card is ready or indicates a failure
 801          * to switch. It doesn't hurt to use CMD13 here even if send_status
 802          * is false, because by now (after 'timeout_ms' ms) the bus should be
 803          * reliable.
 804          */
 805         do {
 806                 ret = mmc_send_status(mmc, &status);
 807
 808                 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
 809                         pr_debug("switch failed %d/%d/0x%x !\n", set, index,
 810                                  value);
 811                         return -EIO;
 812                 }
 813                 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
 814                         return 0;
 815                 udelay(100);
 816         } while (get_timer(start) < timeout_ms);
 817
 818         return -ETIMEDOUT;
 819 }
 820
 821 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 822 {
 823         return __mmc_switch(mmc, set, index, value, true);
 824 }
 825
 826 int mmc_boot_wp(struct mmc *mmc)
 827 {
 828         return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
 829 }
 830
 831 #if !CONFIG_IS_ENABLED(MMC_TINY)
 832 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
 833                               bool hsdowngrade)
 834 {
 835         int err;
 836         int speed_bits;
 837
 838         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 839
 840         switch (mode) {
 841         case MMC_HS:
 842         case MMC_HS_52:
 843         case MMC_DDR_52:
 844                 speed_bits = EXT_CSD_TIMING_HS;
 845                 break;
 846 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 847         case MMC_HS_200:
 848                 speed_bits = EXT_CSD_TIMING_HS200;
 849                 break;
 850 #endif
 851 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 852         case MMC_HS_400:
 853                 speed_bits = EXT_CSD_TIMING_HS400;
 854                 break;
 855 #endif
 856 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 857         case MMC_HS_400_ES:
 858                 speed_bits = EXT_CSD_TIMING_HS400;
 859                 break;
 860 #endif
 861         case MMC_LEGACY:
 862                 speed_bits = EXT_CSD_TIMING_LEGACY;
 863                 break;
 864         default:
 865                 return -EINVAL;
 866         }
 867
 868         err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
 869                            speed_bits, !hsdowngrade);
 870         if (err)
 871                 return err;
 872
 873 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 874     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 875         /*
 876          * In case the eMMC is in HS200/HS400 mode and we are downgrading
 877          * to HS mode, the card clock are still running much faster than
 878          * the supported HS mode clock, so we can not reliably read out
 879          * Extended CSD. Reconfigure the controller to run at HS mode.
 880          */
 881         if (hsdowngrade) {
 882                 mmc_select_mode(mmc, MMC_HS);
 883                 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
 884         }
 885 #endif
 886
 887         if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
 888                 /* Now check to see that it worked */
 889                 err = mmc_send_ext_csd(mmc, test_csd);
 890                 if (err)
 891                         return err;
 892
 893                 /* No high-speed support */
 894                 if (!test_csd[EXT_CSD_HS_TIMING])
 895                         return -ENOTSUPP;
 896         }
 897
 898         return 0;
 899 }
 900
 901 static int mmc_get_capabilities(struct mmc *mmc)
 902 {
 903         u8 *ext_csd = mmc->ext_csd;
 904         char cardtype;
 905
 906         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
 907
 908         if (mmc_host_is_spi(mmc))
 909                 return 0;
 910
 911         /* Only version 4 supports high-speed */
 912         if (mmc->version < MMC_VERSION_4)
 913                 return 0;
 914
 915         if (!ext_csd) {
 916                 pr_err("No ext_csd found!\n"); /* this should enver happen */
 917                 return -ENOTSUPP;
 918         }
 919
 920         mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
 921
 922         cardtype = ext_csd[EXT_CSD_CARD_TYPE];
 923         mmc->cardtype = cardtype;
 924
 925 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 926         if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
 927                         EXT_CSD_CARD_TYPE_HS200_1_8V)) {
 928                 mmc->card_caps |= MMC_MODE_HS200;
 929         }
 930 #endif
 931 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
 932         CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 933         if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
 934                         EXT_CSD_CARD_TYPE_HS400_1_8V)) {
 935                 mmc->card_caps |= MMC_MODE_HS400;
 936         }
 937 #endif
 938         if (cardtype & EXT_CSD_CARD_TYPE_52) {
 939                 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
 940                         mmc->card_caps |= MMC_MODE_DDR_52MHz;
 941                 mmc->card_caps |= MMC_MODE_HS_52MHz;
 942         }
 943         if (cardtype & EXT_CSD_CARD_TYPE_26)
 944                 mmc->card_caps |= MMC_MODE_HS;
 945
 946 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 947         if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
 948             (mmc->card_caps & MMC_MODE_HS400)) {
 949                 mmc->card_caps |= MMC_MODE_HS400_ES;
 950         }
 951 #endif
 952
 953         return 0;
 954 }
 955 #endif
 956
 957 static int mmc_set_capacity(struct mmc *mmc, int part_num)
 958 {
 959         switch (part_num) {
 960         case 0:
 961                 mmc->capacity = mmc->capacity_user;
 962                 break;
 963         case 1:
 964         case 2:
 965                 mmc->capacity = mmc->capacity_boot;
 966                 break;
 967         case 3:
 968                 mmc->capacity = mmc->capacity_rpmb;
 969                 break;
 970         case 4:
 971         case 5:
 972         case 6:
 973         case 7:
 974                 mmc->capacity = mmc->capacity_gp[part_num - 4];
 975                 break;
 976         default:
 977                 return -1;
 978         }
 979
 980         mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 981
 982         return 0;
 983 }
 984
 985 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 986 {
 987         int ret;
 988         int retry = 3;
 989
 990         do {
 991                 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 992                                  EXT_CSD_PART_CONF,
 993                                  (mmc->part_config & ~PART_ACCESS_MASK)
 994                                  | (part_num & PART_ACCESS_MASK));
 995         } while (ret && retry--);
 996
 997         /*
 998          * Set the capacity if the switch succeeded or was intended
 999          * to return to representing the raw device.
1000          */
1001         if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
1002                 ret = mmc_set_capacity(mmc, part_num);
1003                 mmc_get_blk_desc(mmc)->hwpart = part_num;
1004         }
1005
1006         return ret;
1007 }
1008
1009 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
1010 int mmc_hwpart_config(struct mmc *mmc,
1011                       const struct mmc_hwpart_conf *conf,
1012                       enum mmc_hwpart_conf_mode mode)
1013 {
1014         u8 part_attrs = 0;
1015         u32 enh_size_mult;
1016         u32 enh_start_addr;
1017         u32 gp_size_mult[4];
1018         u32 max_enh_size_mult;
1019         u32 tot_enh_size_mult = 0;
1020         u8 wr_rel_set;
1021         int i, pidx, err;
1022         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1023
1024         if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1025                 return -EINVAL;
1026
1027         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
1028                 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
1029                 return -EMEDIUMTYPE;
1030         }
1031
1032         if (!(mmc->part_support & PART_SUPPORT)) {
1033                 pr_err("Card does not support partitioning\n");
1034                 return -EMEDIUMTYPE;
1035         }
1036
1037         if (!mmc->hc_wp_grp_size) {
1038                 pr_err("Card does not define HC WP group size\n");
1039                 return -EMEDIUMTYPE;
1040         }
1041
1042         /* check partition alignment and total enhanced size */
1043         if (conf->user.enh_size) {
1044                 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1045                     conf->user.enh_start % mmc->hc_wp_grp_size) {
1046                         pr_err("User data enhanced area not HC WP group "
1047                                "size aligned\n");
1048                         return -EINVAL;
1049                 }
1050                 part_attrs |= EXT_CSD_ENH_USR;
1051                 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1052                 if (mmc->high_capacity) {
1053                         enh_start_addr = conf->user.enh_start;
1054                 } else {
1055                         enh_start_addr = (conf->user.enh_start << 9);
1056                 }
1057         } else {
1058                 enh_size_mult = 0;
1059                 enh_start_addr = 0;
1060         }
1061         tot_enh_size_mult += enh_size_mult;
1062
1063         for (pidx = 0; pidx < 4; pidx++) {
1064                 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1065                         pr_err("GP%i partition not HC WP group size "
1066                                "aligned\n", pidx+1);
1067                         return -EINVAL;
1068                 }
1069                 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1070                 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1071                         part_attrs |= EXT_CSD_ENH_GP(pidx);
1072                         tot_enh_size_mult += gp_size_mult[pidx];
1073                 }
1074         }
1075
1076         if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1077                 pr_err("Card does not support enhanced attribute\n");
1078                 return -EMEDIUMTYPE;
1079         }
1080
1081         err = mmc_send_ext_csd(mmc, ext_csd);
1082         if (err)
1083                 return err;
1084
1085         max_enh_size_mult =
1086                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1087                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1088                 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1089         if (tot_enh_size_mult > max_enh_size_mult) {
1090                 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1091                        tot_enh_size_mult, max_enh_size_mult);
1092                 return -EMEDIUMTYPE;
1093         }
1094
1095         /* The default value of EXT_CSD_WR_REL_SET is device
1096          * dependent, the values can only be changed if the
1097          * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1098          * changed only once and before partitioning is completed. */
1099         wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1100         if (conf->user.wr_rel_change) {
1101                 if (conf->user.wr_rel_set)
1102                         wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1103                 else
1104                         wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1105         }
1106         for (pidx = 0; pidx < 4; pidx++) {
1107                 if (conf->gp_part[pidx].wr_rel_change) {
1108                         if (conf->gp_part[pidx].wr_rel_set)
1109                                 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1110                         else
1111                                 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1112                 }
1113         }
1114
1115         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1116             !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1117                 puts("Card does not support host controlled partition write "
1118                      "reliability settings\n");
1119                 return -EMEDIUMTYPE;
1120         }
1121
1122         if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1123             EXT_CSD_PARTITION_SETTING_COMPLETED) {
1124                 pr_err("Card already partitioned\n");
1125                 return -EPERM;
1126         }
1127
1128         if (mode == MMC_HWPART_CONF_CHECK)
1129                 return 0;
1130
1131         /* Partitioning requires high-capacity size definitions */
1132         if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1133                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1134                                  EXT_CSD_ERASE_GROUP_DEF, 1);
1135
1136                 if (err)
1137                         return err;
1138
1139                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1140
1141 #if CONFIG_IS_ENABLED(MMC_WRITE)
1142                 /* update erase group size to be high-capacity */
1143                 mmc->erase_grp_size =
1144                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1145 #endif
1146
1147         }
1148
1149         /* all OK, write the configuration */
1150         for (i = 0; i < 4; i++) {
1151                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1152                                  EXT_CSD_ENH_START_ADDR+i,
1153                                  (enh_start_addr >> (i*8)) & 0xFF);
1154                 if (err)
1155                         return err;
1156         }
1157         for (i = 0; i < 3; i++) {
1158                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1159                                  EXT_CSD_ENH_SIZE_MULT+i,
1160                                  (enh_size_mult >> (i*8)) & 0xFF);
1161                 if (err)
1162                         return err;
1163         }
1164         for (pidx = 0; pidx < 4; pidx++) {
1165                 for (i = 0; i < 3; i++) {
1166                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1167                                          EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1168                                          (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1169                         if (err)
1170                                 return err;
1171                 }
1172         }
1173         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1174                          EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1175         if (err)
1176                 return err;
1177
1178         if (mode == MMC_HWPART_CONF_SET)
1179                 return 0;
1180
1181         /* The WR_REL_SET is a write-once register but shall be
1182          * written before setting PART_SETTING_COMPLETED. As it is
1183          * write-once we can only write it when completing the
1184          * partitioning. */
1185         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1186                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1187                                  EXT_CSD_WR_REL_SET, wr_rel_set);
1188                 if (err)
1189                         return err;
1190         }
1191
1192         /* Setting PART_SETTING_COMPLETED confirms the partition
1193          * configuration but it only becomes effective after power
1194          * cycle, so we do not adjust the partition related settings
1195          * in the mmc struct. */
1196
1197         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1198                          EXT_CSD_PARTITION_SETTING,
1199                          EXT_CSD_PARTITION_SETTING_COMPLETED);
1200         if (err)
1201                 return err;
1202
1203         return 0;
1204 }
1205 #endif
1206
1207 #if !CONFIG_IS_ENABLED(DM_MMC)
1208 int mmc_getcd(struct mmc *mmc)
1209 {
1210         int cd;
1211
1212         cd = board_mmc_getcd(mmc);
1213
1214         if (cd < 0) {
1215                 if (mmc->cfg->ops->getcd)
1216                         cd = mmc->cfg->ops->getcd(mmc);
1217                 else
1218                         cd = 1;
1219         }
1220
1221         return cd;
1222 }
1223 #endif
1224
1225 #if !CONFIG_IS_ENABLED(MMC_TINY)
1226 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1227 {
1228         struct mmc_cmd cmd;
1229         struct mmc_data data;
1230
1231         /* Switch the frequency */
1232         cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1233         cmd.resp_type = MMC_RSP_R1;
1234         cmd.cmdarg = (mode << 31) | 0xffffff;
1235         cmd.cmdarg &= ~(0xf << (group * 4));
1236         cmd.cmdarg |= value << (group * 4);
1237
1238         data.dest = (char *)resp;
1239         data.blocksize = 64;
1240         data.blocks = 1;
1241         data.flags = MMC_DATA_READ;
1242
1243         return mmc_send_cmd(mmc, &cmd, &data);
1244 }
1245
1246 static int sd_get_capabilities(struct mmc *mmc)
1247 {
1248         int err;
1249         struct mmc_cmd cmd;
1250         ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1251         ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1252         struct mmc_data data;
1253         int timeout;
1254 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1255         u32 sd3_bus_mode;
1256 #endif
1257
1258         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
1259
1260         if (mmc_host_is_spi(mmc))
1261                 return 0;
1262
1263         /* Read the SCR to find out if this card supports higher speeds */
1264         cmd.cmdidx = MMC_CMD_APP_CMD;
1265         cmd.resp_type = MMC_RSP_R1;
1266         cmd.cmdarg = mmc->rca << 16;
1267
1268         err = mmc_send_cmd(mmc, &cmd, NULL);
1269
1270         if (err)
1271                 return err;
1272
1273         cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1274         cmd.resp_type = MMC_RSP_R1;
1275         cmd.cmdarg = 0;
1276
1277         timeout = 3;
1278
1279 retry_scr:
1280         data.dest = (char *)scr;
1281         data.blocksize = 8;
1282         data.blocks = 1;
1283         data.flags = MMC_DATA_READ;
1284
1285         err = mmc_send_cmd(mmc, &cmd, &data);
1286
1287         if (err) {
1288                 if (timeout--)
1289                         goto retry_scr;
1290
1291                 return err;
1292         }
1293
1294         mmc->scr[0] = __be32_to_cpu(scr[0]);
1295         mmc->scr[1] = __be32_to_cpu(scr[1]);
1296
1297         switch ((mmc->scr[0] >> 24) & 0xf) {
1298         case 0:
1299                 mmc->version = SD_VERSION_1_0;
1300                 break;
1301         case 1:
1302                 mmc->version = SD_VERSION_1_10;
1303                 break;
1304         case 2:
1305                 mmc->version = SD_VERSION_2;
1306                 if ((mmc->scr[0] >> 15) & 0x1)
1307                         mmc->version = SD_VERSION_3;
1308                 break;
1309         default:
1310                 mmc->version = SD_VERSION_1_0;
1311                 break;
1312         }
1313
1314         if (mmc->scr[0] & SD_DATA_4BIT)
1315                 mmc->card_caps |= MMC_MODE_4BIT;
1316
1317         /* Version 1.0 doesn't support switching */
1318         if (mmc->version == SD_VERSION_1_0)
1319                 return 0;
1320
1321         timeout = 4;
1322         while (timeout--) {
1323                 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1324                                 (u8 *)switch_status);
1325
1326                 if (err)
1327                         return err;
1328
1329                 /* The high-speed function is busy.  Try again */
1330                 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1331                         break;
1332         }
1333
1334         /* If high-speed isn't supported, we return */
1335         if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1336                 mmc->card_caps |= MMC_CAP(SD_HS);
1337
1338 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1339         /* Version before 3.0 don't support UHS modes */
1340         if (mmc->version < SD_VERSION_3)
1341                 return 0;
1342
1343         sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1344         if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1345                 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1346         if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1347                 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1348         if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1349                 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1350         if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1351                 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1352         if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1353                 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1354 #endif
1355
1356         return 0;
1357 }
1358
1359 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1360 {
1361         int err;
1362
1363         ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1364         int speed;
1365
1366         /* SD version 1.00 and 1.01 does not support CMD 6 */
1367         if (mmc->version == SD_VERSION_1_0)
1368                 return 0;
1369
1370         switch (mode) {
1371         case MMC_LEGACY:
1372                 speed = UHS_SDR12_BUS_SPEED;
1373                 break;
1374         case SD_HS:
1375                 speed = HIGH_SPEED_BUS_SPEED;
1376                 break;
1377 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1378         case UHS_SDR12:
1379                 speed = UHS_SDR12_BUS_SPEED;
1380                 break;
1381         case UHS_SDR25:
1382                 speed = UHS_SDR25_BUS_SPEED;
1383                 break;
1384         case UHS_SDR50:
1385                 speed = UHS_SDR50_BUS_SPEED;
1386                 break;
1387         case UHS_DDR50:
1388                 speed = UHS_DDR50_BUS_SPEED;
1389                 break;
1390         case UHS_SDR104:
1391                 speed = UHS_SDR104_BUS_SPEED;
1392                 break;
1393 #endif
1394         default:
1395                 return -EINVAL;
1396         }
1397
1398         err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1399         if (err)
1400                 return err;
1401
1402         if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1403                 return -ENOTSUPP;
1404
1405         return 0;
1406 }
1407
1408 static int sd_select_bus_width(struct mmc *mmc, int w)
1409 {
1410         int err;
1411         struct mmc_cmd cmd;
1412
1413         if ((w != 4) && (w != 1))
1414                 return -EINVAL;
1415
1416         cmd.cmdidx = MMC_CMD_APP_CMD;
1417         cmd.resp_type = MMC_RSP_R1;
1418         cmd.cmdarg = mmc->rca << 16;
1419
1420         err = mmc_send_cmd(mmc, &cmd, NULL);
1421         if (err)
1422                 return err;
1423
1424         cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1425         cmd.resp_type = MMC_RSP_R1;
1426         if (w == 4)
1427                 cmd.cmdarg = 2;
1428         else if (w == 1)
1429                 cmd.cmdarg = 0;
1430         err = mmc_send_cmd(mmc, &cmd, NULL);
1431         if (err)
1432                 return err;
1433
1434         return 0;
1435 }
1436 #endif
1437
1438 #if CONFIG_IS_ENABLED(MMC_WRITE)
1439 static int sd_read_ssr(struct mmc *mmc)
1440 {
1441         static const unsigned int sd_au_size[] = {
1442                 0,              SZ_16K / 512,           SZ_32K / 512,
1443                 SZ_64K / 512,   SZ_128K / 512,          SZ_256K / 512,
1444                 SZ_512K / 512,  SZ_1M / 512,            SZ_2M / 512,
1445                 SZ_4M / 512,    SZ_8M / 512,            (SZ_8M + SZ_4M) / 512,
1446                 SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1447                 SZ_64M / 512,
1448         };
1449         int err, i;
1450         struct mmc_cmd cmd;
1451         ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1452         struct mmc_data data;
1453         int timeout = 3;
1454         unsigned int au, eo, et, es;
1455
1456         cmd.cmdidx = MMC_CMD_APP_CMD;
1457         cmd.resp_type = MMC_RSP_R1;
1458         cmd.cmdarg = mmc->rca << 16;
1459
1460         err = mmc_send_cmd(mmc, &cmd, NULL);
1461 #ifdef CONFIG_MMC_QUIRKS
1462         if (err && (mmc->quirks & MMC_QUIRK_RETRY_APP_CMD)) {
1463                 int retries = 4;
1464                 /*
1465                  * It has been seen that APP_CMD may fail on the first
1466                  * attempt, let's try a few more times
1467                  */
1468                 do {
1469                         err = mmc_send_cmd(mmc, &cmd, NULL);
1470                         if (!err)
1471                                 break;
1472                 } while (retries--);
1473         }
1474 #endif
1475         if (err)
1476                 return err;
1477
1478         cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1479         cmd.resp_type = MMC_RSP_R1;
1480         cmd.cmdarg = 0;
1481
1482 retry_ssr:
1483         data.dest = (char *)ssr;
1484         data.blocksize = 64;
1485         data.blocks = 1;
1486         data.flags = MMC_DATA_READ;
1487
1488         err = mmc_send_cmd(mmc, &cmd, &data);
1489         if (err) {
1490                 if (timeout--)
1491                         goto retry_ssr;
1492
1493                 return err;
1494         }
1495
1496         for (i = 0; i < 16; i++)
1497                 ssr[i] = be32_to_cpu(ssr[i]);
1498
1499         au = (ssr[2] >> 12) & 0xF;
1500         if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1501                 mmc->ssr.au = sd_au_size[au];
1502                 es = (ssr[3] >> 24) & 0xFF;
1503                 es |= (ssr[2] & 0xFF) << 8;
1504                 et = (ssr[3] >> 18) & 0x3F;
1505                 if (es && et) {
1506                         eo = (ssr[3] >> 16) & 0x3;
1507                         mmc->ssr.erase_timeout = (et * 1000) / es;
1508                         mmc->ssr.erase_offset = eo * 1000;
1509                 }
1510         } else {
1511                 pr_debug("Invalid Allocation Unit Size.\n");
1512         }
1513
1514         return 0;
1515 }
1516 #endif
1517 /* frequency bases */
1518 /* divided by 10 to be nice to platforms without floating point */
1519 static const int fbase[] = {
1520         10000,
1521         100000,
1522         1000000,
1523         10000000,
1524 };
1525
1526 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
1527  * to platforms without floating point.
1528  */
1529 static const u8 multipliers[] = {
1530         0,      /* reserved */
1531         10,
1532         12,
1533         13,
1534         15,
1535         20,
1536         25,
1537         30,
1538         35,
1539         40,
1540         45,
1541         50,
1542         55,
1543         60,
1544         70,
1545         80,
1546 };
1547
1548 static inline int bus_width(uint cap)
1549 {
1550         if (cap == MMC_MODE_8BIT)
1551                 return 8;
1552         if (cap == MMC_MODE_4BIT)
1553                 return 4;
1554         if (cap == MMC_MODE_1BIT)
1555                 return 1;
1556         pr_warn("invalid bus witdh capability 0x%x\n", cap);
1557         return 0;
1558 }
1559
1560 #if !CONFIG_IS_ENABLED(DM_MMC)
1561 #ifdef MMC_SUPPORTS_TUNING
1562 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1563 {
1564         return -ENOTSUPP;
1565 }
1566 #endif
1567
1568 static int mmc_set_ios(struct mmc *mmc)
1569 {
1570         int ret = 0;
1571
1572         if (mmc->cfg->ops->set_ios)
1573                 ret = mmc->cfg->ops->set_ios(mmc);
1574
1575         return ret;
1576 }
1577
1578 static int mmc_host_power_cycle(struct mmc *mmc)
1579 {
1580         int ret = 0;
1581
1582         if (mmc->cfg->ops->host_power_cycle)
1583                 ret = mmc->cfg->ops->host_power_cycle(mmc);
1584
1585         return ret;
1586 }
1587 #endif
1588
1589 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1590 {
1591         if (!disable) {
1592                 if (clock > mmc->cfg->f_max)
1593                         clock = mmc->cfg->f_max;
1594
1595                 if (clock < mmc->cfg->f_min)
1596                         clock = mmc->cfg->f_min;
1597         }
1598
1599         mmc->clock = clock;
1600         mmc->clk_disable = disable;
1601
1602         debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1603
1604         return mmc_set_ios(mmc);
1605 }
1606
1607 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1608 {
1609         mmc->bus_width = width;
1610
1611         return mmc_set_ios(mmc);
1612 }
1613
1614 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1615 /*
1616  * helper function to display the capabilities in a human
1617  * friendly manner. The capabilities include bus width and
1618  * supported modes.
1619  */
1620 void mmc_dump_capabilities(const char *text, uint caps)
1621 {
1622         enum bus_mode mode;
1623
1624         pr_debug("%s: widths [", text);
1625         if (caps & MMC_MODE_8BIT)
1626                 pr_debug("8, ");
1627         if (caps & MMC_MODE_4BIT)
1628                 pr_debug("4, ");
1629         if (caps & MMC_MODE_1BIT)
1630                 pr_debug("1, ");
1631         pr_debug("\b\b] modes [");
1632         for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1633                 if (MMC_CAP(mode) & caps)
1634                         pr_debug("%s, ", mmc_mode_name(mode));
1635         pr_debug("\b\b]\n");
1636 }
1637 #endif
1638
1639 struct mode_width_tuning {
1640         enum bus_mode mode;
1641         uint widths;
1642 #ifdef MMC_SUPPORTS_TUNING
1643         uint tuning;
1644 #endif
1645 };
1646
1647 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1648 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1649 {
1650         switch (voltage) {
1651         case MMC_SIGNAL_VOLTAGE_000: return 0;
1652         case MMC_SIGNAL_VOLTAGE_330: return 3300;
1653         case MMC_SIGNAL_VOLTAGE_180: return 1800;
1654         case MMC_SIGNAL_VOLTAGE_120: return 1200;
1655         }
1656         return -EINVAL;
1657 }
1658
1659 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1660 {
1661         int err;
1662
1663         if (mmc->signal_voltage == signal_voltage)
1664                 return 0;
1665
1666         mmc->signal_voltage = signal_voltage;
1667         err = mmc_set_ios(mmc);
1668         if (err)
1669                 pr_debug("unable to set voltage (err %d)\n", err);
1670
1671         return err;
1672 }
1673 #else
1674 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1675 {
1676         return 0;
1677 }
1678 #endif
1679
1680 #if !CONFIG_IS_ENABLED(MMC_TINY)
1681 static const struct mode_width_tuning sd_modes_by_pref[] = {
1682 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1683 #ifdef MMC_SUPPORTS_TUNING
1684         {
1685                 .mode = UHS_SDR104,
1686                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1687                 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1688         },
1689 #endif
1690         {
1691                 .mode = UHS_SDR50,
1692                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1693         },
1694         {
1695                 .mode = UHS_DDR50,
1696                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1697         },
1698         {
1699                 .mode = UHS_SDR25,
1700                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1701         },
1702 #endif
1703         {
1704                 .mode = SD_HS,
1705                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1706         },
1707 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1708         {
1709                 .mode = UHS_SDR12,
1710                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1711         },
1712 #endif
1713         {
1714                 .mode = MMC_LEGACY,
1715                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1716         }
1717 };
1718
1719 #define for_each_sd_mode_by_pref(caps, mwt) \
1720         for (mwt = sd_modes_by_pref;\
1721              mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1722              mwt++) \
1723                 if (caps & MMC_CAP(mwt->mode))
1724
1725 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1726 {
1727         int err;
1728         uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1729         const struct mode_width_tuning *mwt;
1730 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1731         bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1732 #else
1733         bool uhs_en = false;
1734 #endif
1735         uint caps;
1736
1737 #ifdef DEBUG
1738         mmc_dump_capabilities("sd card", card_caps);
1739         mmc_dump_capabilities("host", mmc->host_caps);
1740 #endif
1741
1742         if (mmc_host_is_spi(mmc)) {
1743                 mmc_set_bus_width(mmc, 1);
1744                 mmc_select_mode(mmc, MMC_LEGACY);
1745                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1746                 return 0;
1747         }
1748
1749         /* Restrict card's capabilities by what the host can do */
1750         caps = card_caps & mmc->host_caps;
1751
1752         if (!uhs_en)
1753                 caps &= ~UHS_CAPS;
1754
1755         for_each_sd_mode_by_pref(caps, mwt) {
1756                 uint *w;
1757
1758                 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1759                         if (*w & caps & mwt->widths) {
1760                                 pr_debug("trying mode %s width %d (at %d MHz)\n",
1761                                          mmc_mode_name(mwt->mode),
1762                                          bus_width(*w),
1763                                          mmc_mode2freq(mmc, mwt->mode) / 1000000);
1764
1765                                 /* configure the bus width (card + host) */
1766                                 err = sd_select_bus_width(mmc, bus_width(*w));
1767                                 if (err)
1768                                         goto error;
1769                                 mmc_set_bus_width(mmc, bus_width(*w));
1770
1771                                 /* configure the bus mode (card) */
1772                                 err = sd_set_card_speed(mmc, mwt->mode);
1773                                 if (err)
1774                                         goto error;
1775
1776                                 /* configure the bus mode (host) */
1777                                 mmc_select_mode(mmc, mwt->mode);
1778                                 mmc_set_clock(mmc, mmc->tran_speed,
1779                                                 MMC_CLK_ENABLE);
1780
1781 #ifdef MMC_SUPPORTS_TUNING
1782                                 /* execute tuning if needed */
1783                                 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1784                                         err = mmc_execute_tuning(mmc,
1785                                                                  mwt->tuning);
1786                                         if (err) {
1787                                                 pr_debug("tuning failed\n");
1788                                                 goto error;
1789                                         }
1790                                 }
1791 #endif
1792
1793 #if CONFIG_IS_ENABLED(MMC_WRITE)
1794                                 err = sd_read_ssr(mmc);
1795                                 if (err)
1796                                         pr_warn("unable to read ssr\n");
1797 #endif
1798                                 if (!err)
1799                                         return 0;
1800
1801 error:
1802                                 /* revert to a safer bus speed */
1803                                 mmc_select_mode(mmc, MMC_LEGACY);
1804                                 mmc_set_clock(mmc, mmc->tran_speed,
1805                                                 MMC_CLK_ENABLE);
1806                         }
1807                 }
1808         }
1809
1810         pr_err("unable to select a mode\n");
1811         return -ENOTSUPP;
1812 }
1813
1814 /*
1815  * read the compare the part of ext csd that is constant.
1816  * This can be used to check that the transfer is working
1817  * as expected.
1818  */
1819 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1820 {
1821         int err;
1822         const u8 *ext_csd = mmc->ext_csd;
1823         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1824
1825         if (mmc->version < MMC_VERSION_4)
1826                 return 0;
1827
1828         err = mmc_send_ext_csd(mmc, test_csd);
1829         if (err)
1830                 return err;
1831
1832         /* Only compare read only fields */
1833         if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1834                 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1835             ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1836                 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1837             ext_csd[EXT_CSD_REV]
1838                 == test_csd[EXT_CSD_REV] &&
1839             ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1840                 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1841             memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1842                    &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1843                 return 0;
1844
1845         return -EBADMSG;
1846 }
1847
1848 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1849 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1850                                   uint32_t allowed_mask)
1851 {
1852         u32 card_mask = 0;
1853
1854         switch (mode) {
1855         case MMC_HS_400_ES:
1856         case MMC_HS_400:
1857         case MMC_HS_200:
1858                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1859                     EXT_CSD_CARD_TYPE_HS400_1_8V))
1860                         card_mask |= MMC_SIGNAL_VOLTAGE_180;
1861                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1862                     EXT_CSD_CARD_TYPE_HS400_1_2V))
1863                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1864                 break;
1865         case MMC_DDR_52:
1866                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1867                         card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1868                                      MMC_SIGNAL_VOLTAGE_180;
1869                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1870                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1871                 break;
1872         default:
1873                 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1874                 break;
1875         }
1876
1877         while (card_mask & allowed_mask) {
1878                 enum mmc_voltage best_match;
1879
1880                 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1881                 if (!mmc_set_signal_voltage(mmc,  best_match))
1882                         return 0;
1883
1884                 allowed_mask &= ~best_match;
1885         }
1886
1887         return -ENOTSUPP;
1888 }
1889 #else
1890 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1891                                          uint32_t allowed_mask)
1892 {
1893         return 0;
1894 }
1895 #endif
1896
1897 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1898 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1899         {
1900                 .mode = MMC_HS_400_ES,
1901                 .widths = MMC_MODE_8BIT,
1902         },
1903 #endif
1904 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1905         {
1906                 .mode = MMC_HS_400,
1907                 .widths = MMC_MODE_8BIT,
1908                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1909         },
1910 #endif
1911 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1912         {
1913                 .mode = MMC_HS_200,
1914                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1915                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1916         },
1917 #endif
1918         {
1919                 .mode = MMC_DDR_52,
1920                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1921         },
1922         {
1923                 .mode = MMC_HS_52,
1924                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1925         },
1926         {
1927                 .mode = MMC_HS,
1928                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1929         },
1930         {
1931                 .mode = MMC_LEGACY,
1932                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1933         }
1934 };
1935
1936 #define for_each_mmc_mode_by_pref(caps, mwt) \
1937         for (mwt = mmc_modes_by_pref;\
1938             mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1939             mwt++) \
1940                 if (caps & MMC_CAP(mwt->mode))
1941
1942 static const struct ext_csd_bus_width {
1943         uint cap;
1944         bool is_ddr;
1945         uint ext_csd_bits;
1946 } ext_csd_bus_width[] = {
1947         {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1948         {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1949         {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1950         {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1951         {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1952 };
1953
1954 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1955 static int mmc_select_hs400(struct mmc *mmc)
1956 {
1957         int err;
1958
1959         /* Set timing to HS200 for tuning */
1960         err = mmc_set_card_speed(mmc, MMC_HS_200, false);
1961         if (err)
1962                 return err;
1963
1964         /* configure the bus mode (host) */
1965         mmc_select_mode(mmc, MMC_HS_200);
1966         mmc_set_clock(mmc, mmc->tran_speed, false);
1967
1968         /* execute tuning if needed */
1969         err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1970         if (err) {
1971                 debug("tuning failed\n");
1972                 return err;
1973         }
1974
1975         /* Set back to HS */
1976         mmc_set_card_speed(mmc, MMC_HS, true);
1977
1978         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1979                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1980         if (err)
1981                 return err;
1982
1983         err = mmc_set_card_speed(mmc, MMC_HS_400, false);
1984         if (err)
1985                 return err;
1986
1987         mmc_select_mode(mmc, MMC_HS_400);
1988         err = mmc_set_clock(mmc, mmc->tran_speed, false);
1989         if (err)
1990                 return err;
1991
1992         return 0;
1993 }
1994 #else
1995 static int mmc_select_hs400(struct mmc *mmc)
1996 {
1997         return -ENOTSUPP;
1998 }
1999 #endif
2000
2001 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
2002 #if !CONFIG_IS_ENABLED(DM_MMC)
2003 static int mmc_set_enhanced_strobe(struct mmc *mmc)
2004 {
2005         return -ENOTSUPP;
2006 }
2007 #endif
2008 static int mmc_select_hs400es(struct mmc *mmc)
2009 {
2010         int err;
2011
2012         err = mmc_set_card_speed(mmc, MMC_HS, true);
2013         if (err)
2014                 return err;
2015
2016         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2017                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2018                          EXT_CSD_BUS_WIDTH_STROBE);
2019         if (err) {
2020                 printf("switch to bus width for hs400 failed\n");
2021                 return err;
2022         }
2023         /* TODO: driver strength */
2024         err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2025         if (err)
2026                 return err;
2027
2028         mmc_select_mode(mmc, MMC_HS_400_ES);
2029         err = mmc_set_clock(mmc, mmc->tran_speed, false);
2030         if (err)
2031                 return err;
2032
2033         return mmc_set_enhanced_strobe(mmc);
2034 }
2035 #else
2036 static int mmc_select_hs400es(struct mmc *mmc)
2037 {
2038         return -ENOTSUPP;
2039 }
2040 #endif
2041
2042 #define for_each_supported_width(caps, ddr, ecbv) \
2043         for (ecbv = ext_csd_bus_width;\
2044             ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2045             ecbv++) \
2046                 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2047
2048 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
2049 {
2050         int err;
2051         const struct mode_width_tuning *mwt;
2052         const struct ext_csd_bus_width *ecbw;
2053
2054 #ifdef DEBUG
2055         mmc_dump_capabilities("mmc", card_caps);
2056         mmc_dump_capabilities("host", mmc->host_caps);
2057 #endif
2058
2059         if (mmc_host_is_spi(mmc)) {
2060                 mmc_set_bus_width(mmc, 1);
2061                 mmc_select_mode(mmc, MMC_LEGACY);
2062                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2063                 return 0;
2064         }
2065
2066         /* Restrict card's capabilities by what the host can do */
2067         card_caps &= mmc->host_caps;
2068
2069         /* Only version 4 of MMC supports wider bus widths */
2070         if (mmc->version < MMC_VERSION_4)
2071                 return 0;
2072
2073         if (!mmc->ext_csd) {
2074                 pr_debug("No ext_csd found!\n"); /* this should enver happen */
2075                 return -ENOTSUPP;
2076         }
2077
2078 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2079     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2080         /*
2081          * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2082          * before doing anything else, since a transition from either of
2083          * the HS200/HS400 mode directly to legacy mode is not supported.
2084          */
2085         if (mmc->selected_mode == MMC_HS_200 ||
2086             mmc->selected_mode == MMC_HS_400)
2087                 mmc_set_card_speed(mmc, MMC_HS, true);
2088         else
2089 #endif
2090                 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
2091
2092         for_each_mmc_mode_by_pref(card_caps, mwt) {
2093                 for_each_supported_width(card_caps & mwt->widths,
2094                                          mmc_is_mode_ddr(mwt->mode), ecbw) {
2095                         enum mmc_voltage old_voltage;
2096                         pr_debug("trying mode %s width %d (at %d MHz)\n",
2097                                  mmc_mode_name(mwt->mode),
2098                                  bus_width(ecbw->cap),
2099                                  mmc_mode2freq(mmc, mwt->mode) / 1000000);
2100                         old_voltage = mmc->signal_voltage;
2101                         err = mmc_set_lowest_voltage(mmc, mwt->mode,
2102                                                      MMC_ALL_SIGNAL_VOLTAGE);
2103                         if (err)
2104                                 continue;
2105
2106                         /* configure the bus width (card + host) */
2107                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2108                                     EXT_CSD_BUS_WIDTH,
2109                                     ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2110                         if (err)
2111                                 goto error;
2112                         mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2113
2114                         if (mwt->mode == MMC_HS_400) {
2115                                 err = mmc_select_hs400(mmc);
2116                                 if (err) {
2117                                         printf("Select HS400 failed %d\n", err);
2118                                         goto error;
2119                                 }
2120                         } else if (mwt->mode == MMC_HS_400_ES) {
2121                                 err = mmc_select_hs400es(mmc);
2122                                 if (err) {
2123                                         printf("Select HS400ES failed %d\n",
2124                                                err);
2125                                         goto error;
2126                                 }
2127                         } else {
2128                                 /* configure the bus speed (card) */
2129                                 err = mmc_set_card_speed(mmc, mwt->mode, false);
2130                                 if (err)
2131                                         goto error;
2132
2133                                 /*
2134                                  * configure the bus width AND the ddr mode
2135                                  * (card). The host side will be taken care
2136                                  * of in the next step
2137                                  */
2138                                 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2139                                         err = mmc_switch(mmc,
2140                                                          EXT_CSD_CMD_SET_NORMAL,
2141                                                          EXT_CSD_BUS_WIDTH,
2142                                                          ecbw->ext_csd_bits);
2143                                         if (err)
2144                                                 goto error;
2145                                 }
2146
2147                                 /* configure the bus mode (host) */
2148                                 mmc_select_mode(mmc, mwt->mode);
2149                                 mmc_set_clock(mmc, mmc->tran_speed,
2150                                               MMC_CLK_ENABLE);
2151 #ifdef MMC_SUPPORTS_TUNING
2152
2153                                 /* execute tuning if needed */
2154                                 if (mwt->tuning) {
2155                                         err = mmc_execute_tuning(mmc,
2156                                                                  mwt->tuning);
2157                                         if (err) {
2158                                                 pr_debug("tuning failed\n");
2159                                                 goto error;
2160                                         }
2161                                 }
2162 #endif
2163                         }
2164
2165                         /* do a transfer to check the configuration */
2166                         err = mmc_read_and_compare_ext_csd(mmc);
2167                         if (!err)
2168                                 return 0;
2169 error:
2170                         mmc_set_signal_voltage(mmc, old_voltage);
2171                         /* if an error occured, revert to a safer bus mode */
2172                         mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2173                                    EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2174                         mmc_select_mode(mmc, MMC_LEGACY);
2175                         mmc_set_bus_width(mmc, 1);
2176                 }
2177         }
2178
2179         pr_err("unable to select a mode\n");
2180
2181         return -ENOTSUPP;
2182 }
2183 #endif
2184
2185 #if CONFIG_IS_ENABLED(MMC_TINY)
2186 DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2187 #endif
2188
2189 static int mmc_startup_v4(struct mmc *mmc)
2190 {
2191         int err, i;
2192         u64 capacity;
2193         bool has_parts = false;
2194         bool part_completed;
2195         static const u32 mmc_versions[] = {
2196                 MMC_VERSION_4,
2197                 MMC_VERSION_4_1,
2198                 MMC_VERSION_4_2,
2199                 MMC_VERSION_4_3,
2200                 MMC_VERSION_4_4,
2201                 MMC_VERSION_4_41,
2202                 MMC_VERSION_4_5,
2203                 MMC_VERSION_5_0,
2204                 MMC_VERSION_5_1
2205         };
2206
2207 #if CONFIG_IS_ENABLED(MMC_TINY)
2208         u8 *ext_csd = ext_csd_bkup;
2209
2210         if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2211                 return 0;
2212
2213         if (!mmc->ext_csd)
2214                 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2215
2216         err = mmc_send_ext_csd(mmc, ext_csd);
2217         if (err)
2218                 goto error;
2219
2220         /* store the ext csd for future reference */
2221         if (!mmc->ext_csd)
2222                 mmc->ext_csd = ext_csd;
2223 #else
2224         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2225
2226         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2227                 return 0;
2228
2229         /* check  ext_csd version and capacity */
2230         err = mmc_send_ext_csd(mmc, ext_csd);
2231         if (err)
2232                 goto error;
2233
2234         /* store the ext csd for future reference */
2235         if (!mmc->ext_csd)
2236                 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2237         if (!mmc->ext_csd)
2238                 return -ENOMEM;
2239         memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2240 #endif
2241         if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2242                 return -EINVAL;
2243
2244         mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2245
2246         if (mmc->version >= MMC_VERSION_4_2) {
2247                 /*
2248                  * According to the JEDEC Standard, the value of
2249                  * ext_csd's capacity is valid if the value is more
2250                  * than 2GB
2251                  */
2252                 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2253                                 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2254                                 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2255                                 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2256                 capacity *= MMC_MAX_BLOCK_LEN;
2257                 if ((capacity >> 20) > 2 * 1024)
2258                         mmc->capacity_user = capacity;
2259         }
2260
2261         if (mmc->version >= MMC_VERSION_4_5)
2262                 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2263
2264         /* The partition data may be non-zero but it is only
2265          * effective if PARTITION_SETTING_COMPLETED is set in
2266          * EXT_CSD, so ignore any data if this bit is not set,
2267          * except for enabling the high-capacity group size
2268          * definition (see below).
2269          */
2270         part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2271                             EXT_CSD_PARTITION_SETTING_COMPLETED);
2272
2273         mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2274         /* Some eMMC set the value too low so set a minimum */
2275         if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2276                 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2277
2278         /* store the partition info of emmc */
2279         mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2280         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2281             ext_csd[EXT_CSD_BOOT_MULT])
2282                 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2283         if (part_completed &&
2284             (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2285                 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2286
2287         mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2288
2289         mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2290
2291         for (i = 0; i < 4; i++) {
2292                 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2293                 uint mult = (ext_csd[idx + 2] << 16) +
2294                         (ext_csd[idx + 1] << 8) + ext_csd[idx];
2295                 if (mult)
2296                         has_parts = true;
2297                 if (!part_completed)
2298                         continue;
2299                 mmc->capacity_gp[i] = mult;
2300                 mmc->capacity_gp[i] *=
2301                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2302                 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2303                 mmc->capacity_gp[i] <<= 19;
2304         }
2305
2306 #ifndef CONFIG_SPL_BUILD
2307         if (part_completed) {
2308                 mmc->enh_user_size =
2309                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2310                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2311                         ext_csd[EXT_CSD_ENH_SIZE_MULT];
2312                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2313                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2314                 mmc->enh_user_size <<= 19;
2315                 mmc->enh_user_start =
2316                         (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2317                         (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2318                         (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2319                         ext_csd[EXT_CSD_ENH_START_ADDR];
2320                 if (mmc->high_capacity)
2321                         mmc->enh_user_start <<= 9;
2322         }
2323 #endif
2324
2325         /*
2326          * Host needs to enable ERASE_GRP_DEF bit if device is
2327          * partitioned. This bit will be lost every time after a reset
2328          * or power off. This will affect erase size.
2329          */
2330         if (part_completed)
2331                 has_parts = true;
2332         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2333             (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2334                 has_parts = true;
2335         if (has_parts) {
2336                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2337                                  EXT_CSD_ERASE_GROUP_DEF, 1);
2338
2339                 if (err)
2340                         goto error;
2341
2342                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2343         }
2344
2345         if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2346 #if CONFIG_IS_ENABLED(MMC_WRITE)
2347                 /* Read out group size from ext_csd */
2348                 mmc->erase_grp_size =
2349                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2350 #endif
2351                 /*
2352                  * if high capacity and partition setting completed
2353                  * SEC_COUNT is valid even if it is smaller than 2 GiB
2354                  * JEDEC Standard JESD84-B45, 6.2.4
2355                  */
2356                 if (mmc->high_capacity && part_completed) {
2357                         capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2358                                 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2359                                 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2360                                 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2361                         capacity *= MMC_MAX_BLOCK_LEN;
2362                         mmc->capacity_user = capacity;
2363                 }
2364         }
2365 #if CONFIG_IS_ENABLED(MMC_WRITE)
2366         else {
2367                 /* Calculate the group size from the csd value. */
2368                 int erase_gsz, erase_gmul;
2369
2370                 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2371                 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2372                 mmc->erase_grp_size = (erase_gsz + 1)
2373                         * (erase_gmul + 1);
2374         }
2375 #endif
2376 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2377         mmc->hc_wp_grp_size = 1024
2378                 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2379                 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2380 #endif
2381
2382         mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2383
2384         return 0;
2385 error:
2386         if (mmc->ext_csd) {
2387 #if !CONFIG_IS_ENABLED(MMC_TINY)
2388                 free(mmc->ext_csd);
2389 #endif
2390                 mmc->ext_csd = NULL;
2391         }
2392         return err;
2393 }
2394
2395 static int mmc_startup(struct mmc *mmc)
2396 {
2397         int err, i;
2398         uint mult, freq;
2399         u64 cmult, csize;
2400         struct mmc_cmd cmd;
2401         struct blk_desc *bdesc;
2402
2403 #ifdef CONFIG_MMC_SPI_CRC_ON
2404         if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2405                 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2406                 cmd.resp_type = MMC_RSP_R1;
2407                 cmd.cmdarg = 1;
2408                 err = mmc_send_cmd(mmc, &cmd, NULL);
2409                 if (err)
2410                         return err;
2411         }
2412 #endif
2413
2414         /* Put the Card in Identify Mode */
2415         cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2416                 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2417         cmd.resp_type = MMC_RSP_R2;
2418         cmd.cmdarg = 0;
2419
2420         err = mmc_send_cmd(mmc, &cmd, NULL);
2421
2422 #ifdef CONFIG_MMC_QUIRKS
2423         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2424                 int retries = 4;
2425                 /*
2426                  * It has been seen that SEND_CID may fail on the first
2427                  * attempt, let's try a few more time
2428                  */
2429                 do {
2430                         err = mmc_send_cmd(mmc, &cmd, NULL);
2431                         if (!err)
2432                                 break;
2433                 } while (retries--);
2434         }
2435 #endif
2436
2437         if (err)
2438                 return err;
2439
2440         memcpy(mmc->cid, cmd.response, 16);
2441
2442         /*
2443          * For MMC cards, set the Relative Address.
2444          * For SD cards, get the Relatvie Address.
2445          * This also puts the cards into Standby State
2446          */
2447         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2448                 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2449                 cmd.cmdarg = mmc->rca << 16;
2450                 cmd.resp_type = MMC_RSP_R6;
2451
2452                 err = mmc_send_cmd(mmc, &cmd, NULL);
2453
2454                 if (err)
2455                         return err;
2456
2457                 if (IS_SD(mmc))
2458                         mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2459         }
2460
2461         /* Get the Card-Specific Data */
2462         cmd.cmdidx = MMC_CMD_SEND_CSD;
2463         cmd.resp_type = MMC_RSP_R2;
2464         cmd.cmdarg = mmc->rca << 16;
2465
2466         err = mmc_send_cmd(mmc, &cmd, NULL);
2467
2468         if (err)
2469                 return err;
2470
2471         mmc->csd[0] = cmd.response[0];
2472         mmc->csd[1] = cmd.response[1];
2473         mmc->csd[2] = cmd.response[2];
2474         mmc->csd[3] = cmd.response[3];
2475
2476         if (mmc->version == MMC_VERSION_UNKNOWN) {
2477                 int version = (cmd.response[0] >> 26) & 0xf;
2478
2479                 switch (version) {
2480                 case 0:
2481                         mmc->version = MMC_VERSION_1_2;
2482                         break;
2483                 case 1:
2484                         mmc->version = MMC_VERSION_1_4;
2485                         break;
2486                 case 2:
2487                         mmc->version = MMC_VERSION_2_2;
2488                         break;
2489                 case 3:
2490                         mmc->version = MMC_VERSION_3;
2491                         break;
2492                 case 4:
2493                         mmc->version = MMC_VERSION_4;
2494                         break;
2495                 default:
2496                         mmc->version = MMC_VERSION_1_2;
2497                         break;
2498                 }
2499         }
2500
2501         /* divide frequency by 10, since the mults are 10x bigger */
2502         freq = fbase[(cmd.response[0] & 0x7)];
2503         mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2504
2505         mmc->legacy_speed = freq * mult;
2506         mmc_select_mode(mmc, MMC_LEGACY);
2507
2508         mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2509         mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2510 #if CONFIG_IS_ENABLED(MMC_WRITE)
2511
2512         if (IS_SD(mmc))
2513                 mmc->write_bl_len = mmc->read_bl_len;
2514         else
2515                 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2516 #endif
2517
2518         if (mmc->high_capacity) {
2519                 csize = (mmc->csd[1] & 0x3f) << 16
2520                         | (mmc->csd[2] & 0xffff0000) >> 16;
2521                 cmult = 8;
2522         } else {
2523                 csize = (mmc->csd[1] & 0x3ff) << 2
2524                         | (mmc->csd[2] & 0xc0000000) >> 30;
2525                 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2526         }
2527
2528         mmc->capacity_user = (csize + 1) << (cmult + 2);
2529         mmc->capacity_user *= mmc->read_bl_len;
2530         mmc->capacity_boot = 0;
2531         mmc->capacity_rpmb = 0;
2532         for (i = 0; i < 4; i++)
2533                 mmc->capacity_gp[i] = 0;
2534
2535         if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2536                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2537
2538 #if CONFIG_IS_ENABLED(MMC_WRITE)
2539         if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2540                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2541 #endif
2542
2543         if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2544                 cmd.cmdidx = MMC_CMD_SET_DSR;
2545                 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2546                 cmd.resp_type = MMC_RSP_NONE;
2547                 if (mmc_send_cmd(mmc, &cmd, NULL))
2548                         pr_warn("MMC: SET_DSR failed\n");
2549         }
2550
2551         /* Select the card, and put it into Transfer Mode */
2552         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2553                 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2554                 cmd.resp_type = MMC_RSP_R1;
2555                 cmd.cmdarg = mmc->rca << 16;
2556                 err = mmc_send_cmd(mmc, &cmd, NULL);
2557
2558                 if (err)
2559                         return err;
2560         }
2561
2562         /*
2563          * For SD, its erase group is always one sector
2564          */
2565 #if CONFIG_IS_ENABLED(MMC_WRITE)
2566         mmc->erase_grp_size = 1;
2567 #endif
2568         mmc->part_config = MMCPART_NOAVAILABLE;
2569
2570         err = mmc_startup_v4(mmc);
2571         if (err)
2572                 return err;
2573
2574         err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2575         if (err)
2576                 return err;
2577
2578 #if CONFIG_IS_ENABLED(MMC_TINY)
2579         mmc_set_clock(mmc, mmc->legacy_speed, false);
2580         mmc_select_mode(mmc, MMC_LEGACY);
2581         mmc_set_bus_width(mmc, 1);
2582 #else
2583         if (IS_SD(mmc)) {
2584                 err = sd_get_capabilities(mmc);
2585                 if (err)
2586                         return err;
2587                 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2588         } else {
2589                 err = mmc_get_capabilities(mmc);
2590                 if (err)
2591                         return err;
2592                 err = mmc_select_mode_and_width(mmc, mmc->card_caps);
2593         }
2594 #endif
2595         if (err)
2596                 return err;
2597
2598         mmc->best_mode = mmc->selected_mode;
2599
2600         /* Fix the block length for DDR mode */
2601         if (mmc->ddr_mode) {
2602                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2603 #if CONFIG_IS_ENABLED(MMC_WRITE)
2604                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2605 #endif
2606         }
2607
2608         /* fill in device description */
2609         bdesc = mmc_get_blk_desc(mmc);
2610         bdesc->lun = 0;
2611         bdesc->hwpart = 0;
2612         bdesc->type = 0;
2613         bdesc->blksz = mmc->read_bl_len;
2614         bdesc->log2blksz = LOG2(bdesc->blksz);
2615         bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2616 #if !defined(CONFIG_SPL_BUILD) || \
2617                 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2618                 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
2619         sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2620                 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2621                 (mmc->cid[3] >> 16) & 0xffff);
2622         sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2623                 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2624                 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2625                 (mmc->cid[2] >> 24) & 0xff);
2626         sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2627                 (mmc->cid[2] >> 16) & 0xf);
2628 #else
2629         bdesc->vendor[0] = 0;
2630         bdesc->product[0] = 0;
2631         bdesc->revision[0] = 0;
2632 #endif
2633
2634 #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2635         part_init(bdesc);
2636 #endif
2637
2638         return 0;
2639 }
2640
2641 static int mmc_send_if_cond(struct mmc *mmc)
2642 {
2643         struct mmc_cmd cmd;
2644         int err;
2645
2646         cmd.cmdidx = SD_CMD_SEND_IF_COND;
2647         /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2648         cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2649         cmd.resp_type = MMC_RSP_R7;
2650
2651         err = mmc_send_cmd(mmc, &cmd, NULL);
2652
2653         if (err)
2654                 return err;
2655
2656         if ((cmd.response[0] & 0xff) != 0xaa)
2657                 return -EOPNOTSUPP;
2658         else
2659                 mmc->version = SD_VERSION_2;
2660
2661         return 0;
2662 }
2663
2664 #if !CONFIG_IS_ENABLED(DM_MMC)
2665 /* board-specific MMC power initializations. */
2666 __weak void board_mmc_power_init(void)
2667 {
2668 }
2669 #endif
2670
2671 static int mmc_power_init(struct mmc *mmc)
2672 {
2673 #if CONFIG_IS_ENABLED(DM_MMC)
2674 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2675         int ret;
2676
2677         ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2678                                           &mmc->vmmc_supply);
2679         if (ret)
2680                 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2681
2682         ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2683                                           &mmc->vqmmc_supply);
2684         if (ret)
2685                 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2686 #endif
2687 #else /* !CONFIG_DM_MMC */
2688         /*
2689          * Driver model should use a regulator, as above, rather than calling
2690          * out to board code.
2691          */
2692         board_mmc_power_init();
2693 #endif
2694         return 0;
2695 }
2696
2697 /*
2698  * put the host in the initial state:
2699  * - turn on Vdd (card power supply)
2700  * - configure the bus width and clock to minimal values
2701  */
2702 static void mmc_set_initial_state(struct mmc *mmc)
2703 {
2704         int err;
2705
2706         /* First try to set 3.3V. If it fails set to 1.8V */
2707         err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2708         if (err != 0)
2709                 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2710         if (err != 0)
2711                 pr_warn("mmc: failed to set signal voltage\n");
2712
2713         mmc_select_mode(mmc, MMC_LEGACY);
2714         mmc_set_bus_width(mmc, 1);
2715         mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2716 }
2717
2718 static int mmc_power_on(struct mmc *mmc)
2719 {
2720 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2721         if (mmc->vmmc_supply) {
2722                 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2723
2724                 if (ret) {
2725                         puts("Error enabling VMMC supply\n");
2726                         return ret;
2727                 }
2728         }
2729 #endif
2730         return 0;
2731 }
2732
2733 static int mmc_power_off(struct mmc *mmc)
2734 {
2735         mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
2736 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2737         if (mmc->vmmc_supply) {
2738                 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2739
2740                 if (ret) {
2741                         pr_debug("Error disabling VMMC supply\n");
2742                         return ret;
2743                 }
2744         }
2745 #endif
2746         return 0;
2747 }
2748
2749 static int mmc_power_cycle(struct mmc *mmc)
2750 {
2751         int ret;
2752
2753         ret = mmc_power_off(mmc);
2754         if (ret)
2755                 return ret;
2756
2757         ret = mmc_host_power_cycle(mmc);
2758         if (ret)
2759                 return ret;
2760
2761         /*
2762          * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2763          * to be on the safer side.
2764          */
2765         udelay(2000);
2766         return mmc_power_on(mmc);
2767 }
2768
2769 int mmc_get_op_cond(struct mmc *mmc)
2770 {
2771         bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2772         int err;
2773
2774         if (mmc->has_init)
2775                 return 0;
2776
2777 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2778         mmc_adapter_card_type_ident();
2779 #endif
2780         err = mmc_power_init(mmc);
2781         if (err)
2782                 return err;
2783
2784 #ifdef CONFIG_MMC_QUIRKS
2785         mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2786                       MMC_QUIRK_RETRY_SEND_CID |
2787                       MMC_QUIRK_RETRY_APP_CMD;
2788 #endif
2789
2790         err = mmc_power_cycle(mmc);
2791         if (err) {
2792                 /*
2793                  * if power cycling is not supported, we should not try
2794                  * to use the UHS modes, because we wouldn't be able to
2795                  * recover from an error during the UHS initialization.
2796                  */
2797                 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2798                 uhs_en = false;
2799                 mmc->host_caps &= ~UHS_CAPS;
2800                 err = mmc_power_on(mmc);
2801         }
2802         if (err)
2803                 return err;
2804
2805 #if CONFIG_IS_ENABLED(DM_MMC)
2806         /* The device has already been probed ready for use */
2807 #else
2808         /* made sure it's not NULL earlier */
2809         err = mmc->cfg->ops->init(mmc);
2810         if (err)
2811                 return err;
2812 #endif
2813         mmc->ddr_mode = 0;
2814
2815 retry:
2816         mmc_set_initial_state(mmc);
2817
2818         /* Reset the Card */
2819         err = mmc_go_idle(mmc);
2820
2821         if (err)
2822                 return err;
2823
2824         /* The internal partition reset to user partition(0) at every CMD0*/
2825         mmc_get_blk_desc(mmc)->hwpart = 0;
2826
2827         /* Test for SD version 2 */
2828         err = mmc_send_if_cond(mmc);
2829
2830         /* Now try to get the SD card's operating condition */
2831         err = sd_send_op_cond(mmc, uhs_en);
2832         if (err && uhs_en) {
2833                 uhs_en = false;
2834                 mmc_power_cycle(mmc);
2835                 goto retry;
2836         }
2837
2838         /* If the command timed out, we check for an MMC card */
2839         if (err == -ETIMEDOUT) {
2840                 err = mmc_send_op_cond(mmc);
2841
2842                 if (err) {
2843 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2844                         pr_err("Card did not respond to voltage select!\n");
2845 #endif
2846                         return -EOPNOTSUPP;
2847                 }
2848         }
2849
2850         return err;
2851 }
2852
2853 int mmc_start_init(struct mmc *mmc)
2854 {
2855         bool no_card;
2856         int err = 0;
2857
2858         /*
2859          * all hosts are capable of 1 bit bus-width and able to use the legacy
2860          * timings.
2861          */
2862         mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
2863                          MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2864 #if CONFIG_IS_ENABLED(DM_MMC)
2865         mmc_deferred_probe(mmc);
2866 #endif
2867 #if !defined(CONFIG_MMC_BROKEN_CD)
2868         no_card = mmc_getcd(mmc) == 0;
2869 #else
2870         no_card = 0;
2871 #endif
2872 #if !CONFIG_IS_ENABLED(DM_MMC)
2873         /* we pretend there's no card when init is NULL */
2874         no_card = no_card || (mmc->cfg->ops->init == NULL);
2875 #endif
2876         if (no_card) {
2877                 mmc->has_init = 0;
2878 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2879                 pr_err("MMC: no card present\n");
2880 #endif
2881                 return -ENOMEDIUM;
2882         }
2883
2884         err = mmc_get_op_cond(mmc);
2885
2886         if (!err)
2887                 mmc->init_in_progress = 1;
2888
2889         return err;
2890 }
2891
2892 static int mmc_complete_init(struct mmc *mmc)
2893 {
2894         int err = 0;
2895
2896         mmc->init_in_progress = 0;
2897         if (mmc->op_cond_pending)
2898                 err = mmc_complete_op_cond(mmc);
2899
2900         if (!err)
2901                 err = mmc_startup(mmc);
2902         if (err)
2903                 mmc->has_init = 0;
2904         else
2905                 mmc->has_init = 1;
2906         return err;
2907 }
2908
2909 int mmc_init(struct mmc *mmc)
2910 {
2911         int err = 0;
2912         __maybe_unused ulong start;
2913 #if CONFIG_IS_ENABLED(DM_MMC)
2914         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2915
2916         upriv->mmc = mmc;
2917 #endif
2918         if (mmc->has_init)
2919                 return 0;
2920
2921         start = get_timer(0);
2922
2923         if (!mmc->init_in_progress)
2924                 err = mmc_start_init(mmc);
2925
2926         if (!err)
2927                 err = mmc_complete_init(mmc);
2928         if (err)
2929                 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2930
2931         return err;
2932 }
2933
2934 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2935     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2936     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2937 int mmc_deinit(struct mmc *mmc)
2938 {
2939         u32 caps_filtered;
2940
2941         if (!mmc->has_init)
2942                 return 0;
2943
2944         if (IS_SD(mmc)) {
2945                 caps_filtered = mmc->card_caps &
2946                         ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2947                           MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2948                           MMC_CAP(UHS_SDR104));
2949
2950                 return sd_select_mode_and_width(mmc, caps_filtered);
2951         } else {
2952                 caps_filtered = mmc->card_caps &
2953                         ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2954
2955                 return mmc_select_mode_and_width(mmc, caps_filtered);
2956         }
2957 }
2958 #endif
2959
2960 int mmc_set_dsr(struct mmc *mmc, u16 val)
2961 {
2962         mmc->dsr = val;
2963         return 0;
2964 }
2965
2966 /* CPU-specific MMC initializations */
2967 __weak int cpu_mmc_init(bd_t *bis)
2968 {
2969         return -1;
2970 }
2971
2972 /* board-specific MMC initializations. */
2973 __weak int board_mmc_init(bd_t *bis)
2974 {
2975         return -1;
2976 }
2977
2978 void mmc_set_preinit(struct mmc *mmc, int preinit)
2979 {
2980         mmc->preinit = preinit;
2981 }
2982
2983 #if CONFIG_IS_ENABLED(DM_MMC)
2984 static int mmc_probe(bd_t *bis)
2985 {
2986         int ret, i;
2987         struct uclass *uc;
2988         struct udevice *dev;
2989
2990         ret = uclass_get(UCLASS_MMC, &uc);
2991         if (ret)
2992                 return ret;
2993
2994         /*
2995          * Try to add them in sequence order. Really with driver model we
2996          * should allow holes, but the current MMC list does not allow that.
2997          * So if we request 0, 1, 3 we will get 0, 1, 2.
2998          */
2999         for (i = 0; ; i++) {
3000                 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
3001                 if (ret == -ENODEV)
3002                         break;
3003         }
3004         uclass_foreach_dev(dev, uc) {
3005                 ret = device_probe(dev);
3006                 if (ret)
3007                         pr_err("%s - probe failed: %d\n", dev->name, ret);
3008         }
3009
3010         return 0;
3011 }
3012 #else
3013 static int mmc_probe(bd_t *bis)
3014 {
3015         if (board_mmc_init(bis) < 0)
3016                 cpu_mmc_init(bis);
3017
3018         return 0;
3019 }
3020 #endif
3021
3022 int mmc_initialize(bd_t *bis)
3023 {
3024         static int initialized = 0;
3025         int ret;
3026         if (initialized)        /* Avoid initializing mmc multiple times */
3027                 return 0;
3028         initialized = 1;
3029
3030 #if !CONFIG_IS_ENABLED(BLK)
3031 #if !CONFIG_IS_ENABLED(MMC_TINY)
3032         mmc_list_init();
3033 #endif
3034 #endif
3035         ret = mmc_probe(bis);
3036         if (ret)
3037                 return ret;
3038
3039 #ifndef CONFIG_SPL_BUILD
3040         print_mmc_devices(',');
3041 #endif
3042
3043         mmc_do_preinit();
3044         return 0;
3045 }
3046
3047 #if CONFIG_IS_ENABLED(DM_MMC)
3048 int mmc_init_device(int num)
3049 {
3050         struct udevice *dev;
3051         struct mmc *m;
3052         int ret;
3053
3054         ret = uclass_get_device(UCLASS_MMC, num, &dev);
3055         if (ret)
3056                 return ret;
3057
3058         m = mmc_get_mmc_dev(dev);
3059         if (!m)
3060                 return 0;
3061 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
3062         mmc_set_preinit(m, 1);
3063 #endif
3064         if (m->preinit)
3065                 mmc_start_init(m);
3066
3067         return 0;
3068 }
3069 #endif
3070
3071 #ifdef CONFIG_CMD_BKOPS_ENABLE
3072 int mmc_set_bkops_enable(struct mmc *mmc)
3073 {
3074         int err;
3075         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3076
3077         err = mmc_send_ext_csd(mmc, ext_csd);
3078         if (err) {
3079                 puts("Could not get ext_csd register values\n");
3080                 return err;
3081         }
3082
3083         if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3084                 puts("Background operations not supported on device\n");
3085                 return -EMEDIUMTYPE;
3086         }
3087
3088         if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
3089                 puts("Background operations already enabled\n");
3090                 return 0;
3091         }
3092
3093         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
3094         if (err) {
3095                 puts("Failed to enable manual background operations\n");
3096                 return err;
3097         }
3098
3099         puts("Enabled manual background operations\n");
3100
3101         return 0;
3102 }
3103 #endif