drivers/mmc/mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008, Freescale Semiconductor, Inc
   4  * Andy Fleming
   5  *
   6  * Based vaguely on the Linux code
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <command.h>
  12 #include <dm.h>
  13 #include <dm/device-internal.h>
  14 #include <errno.h>
  15 #include <mmc.h>
  16 #include <part.h>
  17 #include <power/regulator.h>
  18 #include <malloc.h>
  19 #include <memalign.h>
  20 #include <linux/list.h>
  21 #include <div64.h>
  22 #include "mmc_private.h"
  23
  24 #define DEFAULT_CMD6_TIMEOUT_MS  500
  25
  26 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  27 static int mmc_power_cycle(struct mmc *mmc);
  28 #if !CONFIG_IS_ENABLED(MMC_TINY)
  29 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
  30 #endif
  31
  32 #if !CONFIG_IS_ENABLED(DM_MMC)
  33
  34 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
  35 {
  36         return -ENOSYS;
  37 }
  38
  39 __weak int board_mmc_getwp(struct mmc *mmc)
  40 {
  41         return -1;
  42 }
  43
  44 int mmc_getwp(struct mmc *mmc)
  45 {
  46         int wp;
  47
  48         wp = board_mmc_getwp(mmc);
  49
  50         if (wp < 0) {
  51                 if (mmc->cfg->ops->getwp)
  52                         wp = mmc->cfg->ops->getwp(mmc);
  53                 else
  54                         wp = 0;
  55         }
  56
  57         return wp;
  58 }
  59
  60 __weak int board_mmc_getcd(struct mmc *mmc)
  61 {
  62         return -1;
  63 }
  64 #endif
  65
  66 #ifdef CONFIG_MMC_TRACE
  67 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  68 {
  69         printf("CMD_SEND:%d\n", cmd->cmdidx);
  70         printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  71 }
  72
  73 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  74 {
  75         int i;
  76         u8 *ptr;
  77
  78         if (ret) {
  79                 printf("\t\tRET\t\t\t %d\n", ret);
  80         } else {
  81                 switch (cmd->resp_type) {
  82                 case MMC_RSP_NONE:
  83                         printf("\t\tMMC_RSP_NONE\n");
  84                         break;
  85                 case MMC_RSP_R1:
  86                         printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  87                                 cmd->response[0]);
  88                         break;
  89                 case MMC_RSP_R1b:
  90                         printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  91                                 cmd->response[0]);
  92                         break;
  93                 case MMC_RSP_R2:
  94                         printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  95                                 cmd->response[0]);
  96                         printf("\t\t          \t\t 0x%08x \n",
  97                                 cmd->response[1]);
  98                         printf("\t\t          \t\t 0x%08x \n",
  99                                 cmd->response[2]);
 100                         printf("\t\t          \t\t 0x%08x \n",
 101                                 cmd->response[3]);
 102                         printf("\n");
 103                         printf("\t\t\t\t\tDUMPING DATA\n");
 104                         for (i = 0; i < 4; i++) {
 105                                 int j;
 106                                 printf("\t\t\t\t\t%03d - ", i*4);
 107                                 ptr = (u8 *)&cmd->response[i];
 108                                 ptr += 3;
 109                                 for (j = 0; j < 4; j++)
 110                                         printf("%02x ", *ptr--);
 111                                 printf("\n");
 112                         }
 113                         break;
 114                 case MMC_RSP_R3:
 115                         printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
 116                                 cmd->response[0]);
 117                         break;
 118                 default:
 119                         printf("\t\tERROR MMC rsp not supported\n");
 120                         break;
 121                 }
 122         }
 123 }
 124
 125 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
 126 {
 127         int status;
 128
 129         status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
 130         printf("CURR STATE:%d\n", status);
 131 }
 132 #endif
 133
 134 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
 135 const char *mmc_mode_name(enum bus_mode mode)
 136 {
 137         static const char *const names[] = {
 138               [MMC_LEGACY]      = "MMC legacy",
 139               [SD_LEGACY]       = "SD Legacy",
 140               [MMC_HS]          = "MMC High Speed (26MHz)",
 141               [SD_HS]           = "SD High Speed (50MHz)",
 142               [UHS_SDR12]       = "UHS SDR12 (25MHz)",
 143               [UHS_SDR25]       = "UHS SDR25 (50MHz)",
 144               [UHS_SDR50]       = "UHS SDR50 (100MHz)",
 145               [UHS_SDR104]      = "UHS SDR104 (208MHz)",
 146               [UHS_DDR50]       = "UHS DDR50 (50MHz)",
 147               [MMC_HS_52]       = "MMC High Speed (52MHz)",
 148               [MMC_DDR_52]      = "MMC DDR52 (52MHz)",
 149               [MMC_HS_200]      = "HS200 (200MHz)",
 150               [MMC_HS_400]      = "HS400 (200MHz)",
 151               [MMC_HS_400_ES]   = "HS400ES (200MHz)",
 152         };
 153
 154         if (mode >= MMC_MODES_END)
 155                 return "Unknown mode";
 156         else
 157                 return names[mode];
 158 }
 159 #endif
 160
 161 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
 162 {
 163         static const int freqs[] = {
 164               [MMC_LEGACY]      = 25000000,
 165               [SD_LEGACY]       = 25000000,
 166               [MMC_HS]          = 26000000,
 167               [SD_HS]           = 50000000,
 168               [MMC_HS_52]       = 52000000,
 169               [MMC_DDR_52]      = 52000000,
 170               [UHS_SDR12]       = 25000000,
 171               [UHS_SDR25]       = 50000000,
 172               [UHS_SDR50]       = 100000000,
 173               [UHS_DDR50]       = 50000000,
 174               [UHS_SDR104]      = 208000000,
 175               [MMC_HS_200]      = 200000000,
 176               [MMC_HS_400]      = 200000000,
 177               [MMC_HS_400_ES]   = 200000000,
 178         };
 179
 180         if (mode == MMC_LEGACY)
 181                 return mmc->legacy_speed;
 182         else if (mode >= MMC_MODES_END)
 183                 return 0;
 184         else
 185                 return freqs[mode];
 186 }
 187
 188 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
 189 {
 190         mmc->selected_mode = mode;
 191         mmc->tran_speed = mmc_mode2freq(mmc, mode);
 192         mmc->ddr_mode = mmc_is_mode_ddr(mode);
 193         pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
 194                  mmc->tran_speed / 1000000);
 195         return 0;
 196 }
 197
 198 #if !CONFIG_IS_ENABLED(DM_MMC)
 199 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 200 {
 201         int ret;
 202
 203         mmmc_trace_before_send(mmc, cmd);
 204         ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 205         mmmc_trace_after_send(mmc, cmd, ret);
 206
 207         return ret;
 208 }
 209 #endif
 210
 211 int mmc_send_status(struct mmc *mmc, unsigned int *status)
 212 {
 213         struct mmc_cmd cmd;
 214         int err, retries = 5;
 215
 216         cmd.cmdidx = MMC_CMD_SEND_STATUS;
 217         cmd.resp_type = MMC_RSP_R1;
 218         if (!mmc_host_is_spi(mmc))
 219                 cmd.cmdarg = mmc->rca << 16;
 220
 221         while (retries--) {
 222                 err = mmc_send_cmd(mmc, &cmd, NULL);
 223                 if (!err) {
 224                         mmc_trace_state(mmc, &cmd);
 225                         *status = cmd.response[0];
 226                         return 0;
 227                 }
 228         }
 229         mmc_trace_state(mmc, &cmd);
 230         return -ECOMM;
 231 }
 232
 233 int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
 234 {
 235         unsigned int status;
 236         int err;
 237
 238         err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 239         if (err != -ENOSYS)
 240                 return err;
 241
 242         while (1) {
 243                 err = mmc_send_status(mmc, &status);
 244                 if (err)
 245                         return err;
 246
 247                 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
 248                     (status & MMC_STATUS_CURR_STATE) !=
 249                      MMC_STATE_PRG)
 250                         break;
 251
 252                 if (status & MMC_STATUS_MASK) {
 253 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 254                         pr_err("Status Error: 0x%08x\n", status);
 255 #endif
 256                         return -ECOMM;
 257                 }
 258
 259                 if (timeout_ms-- <= 0)
 260                         break;
 261
 262                 udelay(1000);
 263         }
 264
 265         if (timeout_ms <= 0) {
 266 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 267                 pr_err("Timeout waiting card ready\n");
 268 #endif
 269                 return -ETIMEDOUT;
 270         }
 271
 272         return 0;
 273 }
 274
 275 int mmc_set_blocklen(struct mmc *mmc, int len)
 276 {
 277         struct mmc_cmd cmd;
 278         int err;
 279
 280         if (mmc->ddr_mode)
 281                 return 0;
 282
 283         cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
 284         cmd.resp_type = MMC_RSP_R1;
 285         cmd.cmdarg = len;
 286
 287         err = mmc_send_cmd(mmc, &cmd, NULL);
 288
 289 #ifdef CONFIG_MMC_QUIRKS
 290         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
 291                 int retries = 4;
 292                 /*
 293                  * It has been seen that SET_BLOCKLEN may fail on the first
 294                  * attempt, let's try a few more time
 295                  */
 296                 do {
 297                         err = mmc_send_cmd(mmc, &cmd, NULL);
 298                         if (!err)
 299                                 break;
 300                 } while (retries--);
 301         }
 302 #endif
 303
 304         return err;
 305 }
 306
 307 #ifdef MMC_SUPPORTS_TUNING
 308 static const u8 tuning_blk_pattern_4bit[] = {
 309         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 310         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 311         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 312         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 313         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 314         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 315         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 316         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 317 };
 318
 319 static const u8 tuning_blk_pattern_8bit[] = {
 320         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 321         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 322         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 323         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 324         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 325         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 326         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 327         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 328         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 329         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 330         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 331         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 332         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 333         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 334         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 335         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 336 };
 337
 338 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
 339 {
 340         struct mmc_cmd cmd;
 341         struct mmc_data data;
 342         const u8 *tuning_block_pattern;
 343         int size, err;
 344
 345         if (mmc->bus_width == 8) {
 346                 tuning_block_pattern = tuning_blk_pattern_8bit;
 347                 size = sizeof(tuning_blk_pattern_8bit);
 348         } else if (mmc->bus_width == 4) {
 349                 tuning_block_pattern = tuning_blk_pattern_4bit;
 350                 size = sizeof(tuning_blk_pattern_4bit);
 351         } else {
 352                 return -EINVAL;
 353         }
 354
 355         ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
 356
 357         cmd.cmdidx = opcode;
 358         cmd.cmdarg = 0;
 359         cmd.resp_type = MMC_RSP_R1;
 360
 361         data.dest = (void *)data_buf;
 362         data.blocks = 1;
 363         data.blocksize = size;
 364         data.flags = MMC_DATA_READ;
 365
 366         err = mmc_send_cmd(mmc, &cmd, &data);
 367         if (err)
 368                 return err;
 369
 370         if (memcmp(data_buf, tuning_block_pattern, size))
 371                 return -EIO;
 372
 373         return 0;
 374 }
 375 #endif
 376
 377 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 378                            lbaint_t blkcnt)
 379 {
 380         struct mmc_cmd cmd;
 381         struct mmc_data data;
 382
 383         if (blkcnt > 1)
 384                 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
 385         else
 386                 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
 387
 388         if (mmc->high_capacity)
 389                 cmd.cmdarg = start;
 390         else
 391                 cmd.cmdarg = start * mmc->read_bl_len;
 392
 393         cmd.resp_type = MMC_RSP_R1;
 394
 395         data.dest = dst;
 396         data.blocks = blkcnt;
 397         data.blocksize = mmc->read_bl_len;
 398         data.flags = MMC_DATA_READ;
 399
 400         if (mmc_send_cmd(mmc, &cmd, &data))
 401                 return 0;
 402
 403         if (blkcnt > 1) {
 404                 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 405                 cmd.cmdarg = 0;
 406                 cmd.resp_type = MMC_RSP_R1b;
 407                 if (mmc_send_cmd(mmc, &cmd, NULL)) {
 408 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 409                         pr_err("mmc fail to send stop cmd\n");
 410 #endif
 411                         return 0;
 412                 }
 413         }
 414
 415         return blkcnt;
 416 }
 417
 418 #if CONFIG_IS_ENABLED(BLK)
 419 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
 420 #else
 421 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 422                 void *dst)
 423 #endif
 424 {
 425 #if CONFIG_IS_ENABLED(BLK)
 426         struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 427 #endif
 428         int dev_num = block_dev->devnum;
 429         int err;
 430         lbaint_t cur, blocks_todo = blkcnt;
 431
 432         if (blkcnt == 0)
 433                 return 0;
 434
 435         struct mmc *mmc = find_mmc_device(dev_num);
 436         if (!mmc)
 437                 return 0;
 438
 439         if (CONFIG_IS_ENABLED(MMC_TINY))
 440                 err = mmc_switch_part(mmc, block_dev->hwpart);
 441         else
 442                 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
 443
 444         if (err < 0)
 445                 return 0;
 446
 447         if ((start + blkcnt) > block_dev->lba) {
 448 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 449                 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
 450                        start + blkcnt, block_dev->lba);
 451 #endif
 452                 return 0;
 453         }
 454
 455         if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
 456                 pr_debug("%s: Failed to set blocklen\n", __func__);
 457                 return 0;
 458         }
 459
 460         do {
 461                 cur = (blocks_todo > mmc->cfg->b_max) ?
 462                         mmc->cfg->b_max : blocks_todo;
 463                 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
 464                         pr_debug("%s: Failed to read blocks\n", __func__);
 465                         return 0;
 466                 }
 467                 blocks_todo -= cur;
 468                 start += cur;
 469                 dst += cur * mmc->read_bl_len;
 470         } while (blocks_todo > 0);
 471
 472         return blkcnt;
 473 }
 474
 475 static int mmc_go_idle(struct mmc *mmc)
 476 {
 477         struct mmc_cmd cmd;
 478         int err;
 479
 480         udelay(1000);
 481
 482         cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
 483         cmd.cmdarg = 0;
 484         cmd.resp_type = MMC_RSP_NONE;
 485
 486         err = mmc_send_cmd(mmc, &cmd, NULL);
 487
 488         if (err)
 489                 return err;
 490
 491         udelay(2000);
 492
 493         return 0;
 494 }
 495
 496 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 497 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
 498 {
 499         struct mmc_cmd cmd;
 500         int err = 0;
 501
 502         /*
 503          * Send CMD11 only if the request is to switch the card to
 504          * 1.8V signalling.
 505          */
 506         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 507                 return mmc_set_signal_voltage(mmc, signal_voltage);
 508
 509         cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
 510         cmd.cmdarg = 0;
 511         cmd.resp_type = MMC_RSP_R1;
 512
 513         err = mmc_send_cmd(mmc, &cmd, NULL);
 514         if (err)
 515                 return err;
 516
 517         if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
 518                 return -EIO;
 519
 520         /*
 521          * The card should drive cmd and dat[0:3] low immediately
 522          * after the response of cmd11, but wait 100 us to be sure
 523          */
 524         err = mmc_wait_dat0(mmc, 0, 100);
 525         if (err == -ENOSYS)
 526                 udelay(100);
 527         else if (err)
 528                 return -ETIMEDOUT;
 529
 530         /*
 531          * During a signal voltage level switch, the clock must be gated
 532          * for 5 ms according to the SD spec
 533          */
 534         mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
 535
 536         err = mmc_set_signal_voltage(mmc, signal_voltage);
 537         if (err)
 538                 return err;
 539
 540         /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
 541         mdelay(10);
 542         mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
 543
 544         /*
 545          * Failure to switch is indicated by the card holding
 546          * dat[0:3] low. Wait for at least 1 ms according to spec
 547          */
 548         err = mmc_wait_dat0(mmc, 1, 1000);
 549         if (err == -ENOSYS)
 550                 udelay(1000);
 551         else if (err)
 552                 return -ETIMEDOUT;
 553
 554         return 0;
 555 }
 556 #endif
 557
 558 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
 559 {
 560         int timeout = 1000;
 561         int err;
 562         struct mmc_cmd cmd;
 563
 564         while (1) {
 565                 cmd.cmdidx = MMC_CMD_APP_CMD;
 566                 cmd.resp_type = MMC_RSP_R1;
 567                 cmd.cmdarg = 0;
 568
 569                 err = mmc_send_cmd(mmc, &cmd, NULL);
 570
 571                 if (err)
 572                         return err;
 573
 574                 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
 575                 cmd.resp_type = MMC_RSP_R3;
 576
 577                 /*
 578                  * Most cards do not answer if some reserved bits
 579                  * in the ocr are set. However, Some controller
 580                  * can set bit 7 (reserved for low voltages), but
 581                  * how to manage low voltages SD card is not yet
 582                  * specified.
 583                  */
 584                 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
 585                         (mmc->cfg->voltages & 0xff8000);
 586
 587                 if (mmc->version == SD_VERSION_2)
 588                         cmd.cmdarg |= OCR_HCS;
 589
 590                 if (uhs_en)
 591                         cmd.cmdarg |= OCR_S18R;
 592
 593                 err = mmc_send_cmd(mmc, &cmd, NULL);
 594
 595                 if (err)
 596                         return err;
 597
 598                 if (cmd.response[0] & OCR_BUSY)
 599                         break;
 600
 601                 if (timeout-- <= 0)
 602                         return -EOPNOTSUPP;
 603
 604                 udelay(1000);
 605         }
 606
 607         if (mmc->version != SD_VERSION_2)
 608                 mmc->version = SD_VERSION_1_0;
 609
 610         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 611                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 612                 cmd.resp_type = MMC_RSP_R3;
 613                 cmd.cmdarg = 0;
 614
 615                 err = mmc_send_cmd(mmc, &cmd, NULL);
 616
 617                 if (err)
 618                         return err;
 619         }
 620
 621         mmc->ocr = cmd.response[0];
 622
 623 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 624         if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
 625             == 0x41000000) {
 626                 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
 627                 if (err)
 628                         return err;
 629         }
 630 #endif
 631
 632         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 633         mmc->rca = 0;
 634
 635         return 0;
 636 }
 637
 638 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
 639 {
 640         struct mmc_cmd cmd;
 641         int err;
 642
 643         cmd.cmdidx = MMC_CMD_SEND_OP_COND;
 644         cmd.resp_type = MMC_RSP_R3;
 645         cmd.cmdarg = 0;
 646         if (use_arg && !mmc_host_is_spi(mmc))
 647                 cmd.cmdarg = OCR_HCS |
 648                         (mmc->cfg->voltages &
 649                         (mmc->ocr & OCR_VOLTAGE_MASK)) |
 650                         (mmc->ocr & OCR_ACCESS_MODE);
 651
 652         err = mmc_send_cmd(mmc, &cmd, NULL);
 653         if (err)
 654                 return err;
 655         mmc->ocr = cmd.response[0];
 656         return 0;
 657 }
 658
 659 static int mmc_send_op_cond(struct mmc *mmc)
 660 {
 661         int err, i;
 662
 663         /* Some cards seem to need this */
 664         mmc_go_idle(mmc);
 665
 666         /* Asking to the card its capabilities */
 667         for (i = 0; i < 2; i++) {
 668                 err = mmc_send_op_cond_iter(mmc, i != 0);
 669                 if (err)
 670                         return err;
 671
 672                 /* exit if not busy (flag seems to be inverted) */
 673                 if (mmc->ocr & OCR_BUSY)
 674                         break;
 675         }
 676         mmc->op_cond_pending = 1;
 677         return 0;
 678 }
 679
 680 static int mmc_complete_op_cond(struct mmc *mmc)
 681 {
 682         struct mmc_cmd cmd;
 683         int timeout = 1000;
 684         ulong start;
 685         int err;
 686
 687         mmc->op_cond_pending = 0;
 688         if (!(mmc->ocr & OCR_BUSY)) {
 689                 /* Some cards seem to need this */
 690                 mmc_go_idle(mmc);
 691
 692                 start = get_timer(0);
 693                 while (1) {
 694                         err = mmc_send_op_cond_iter(mmc, 1);
 695                         if (err)
 696                                 return err;
 697                         if (mmc->ocr & OCR_BUSY)
 698                                 break;
 699                         if (get_timer(start) > timeout)
 700                                 return -EOPNOTSUPP;
 701                         udelay(100);
 702                 }
 703         }
 704
 705         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 706                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 707                 cmd.resp_type = MMC_RSP_R3;
 708                 cmd.cmdarg = 0;
 709
 710                 err = mmc_send_cmd(mmc, &cmd, NULL);
 711
 712                 if (err)
 713                         return err;
 714
 715                 mmc->ocr = cmd.response[0];
 716         }
 717
 718         mmc->version = MMC_VERSION_UNKNOWN;
 719
 720         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 721         mmc->rca = 1;
 722
 723         return 0;
 724 }
 725
 726
 727 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 728 {
 729         struct mmc_cmd cmd;
 730         struct mmc_data data;
 731         int err;
 732
 733         /* Get the Card Status Register */
 734         cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
 735         cmd.resp_type = MMC_RSP_R1;
 736         cmd.cmdarg = 0;
 737
 738         data.dest = (char *)ext_csd;
 739         data.blocks = 1;
 740         data.blocksize = MMC_MAX_BLOCK_LEN;
 741         data.flags = MMC_DATA_READ;
 742
 743         err = mmc_send_cmd(mmc, &cmd, &data);
 744
 745         return err;
 746 }
 747
 748 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 749                         bool send_status)
 750 {
 751         unsigned int status, start;
 752         struct mmc_cmd cmd;
 753         int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
 754         bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
 755                               (index == EXT_CSD_PART_CONF);
 756         int retries = 3;
 757         int ret;
 758
 759         if (mmc->gen_cmd6_time)
 760                 timeout_ms = mmc->gen_cmd6_time * 10;
 761
 762         if (is_part_switch  && mmc->part_switch_time)
 763                 timeout_ms = mmc->part_switch_time * 10;
 764
 765         cmd.cmdidx = MMC_CMD_SWITCH;
 766         cmd.resp_type = MMC_RSP_R1b;
 767         cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
 768                                  (index << 16) |
 769                                  (value << 8);
 770
 771         do {
 772                 ret = mmc_send_cmd(mmc, &cmd, NULL);
 773         } while (ret && retries-- > 0);
 774
 775         if (ret)
 776                 return ret;
 777
 778         start = get_timer(0);
 779
 780         /* poll dat0 for rdy/buys status */
 781         ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 782         if (ret && ret != -ENOSYS)
 783                 return ret;
 784
 785         /*
 786          * In cases when not allowed to poll by using CMD13 or because we aren't
 787          * capable of polling by using mmc_wait_dat0, then rely on waiting the
 788          * stated timeout to be sufficient.
 789          */
 790         if (ret == -ENOSYS && !send_status)
 791                 mdelay(timeout_ms);
 792
 793         /* Finally wait until the card is ready or indicates a failure
 794          * to switch. It doesn't hurt to use CMD13 here even if send_status
 795          * is false, because by now (after 'timeout_ms' ms) the bus should be
 796          * reliable.
 797          */
 798         do {
 799                 ret = mmc_send_status(mmc, &status);
 800
 801                 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
 802                         pr_debug("switch failed %d/%d/0x%x !\n", set, index,
 803                                  value);
 804                         return -EIO;
 805                 }
 806                 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
 807                         return 0;
 808                 udelay(100);
 809         } while (get_timer(start) < timeout_ms);
 810
 811         return -ETIMEDOUT;
 812 }
 813
 814 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 815 {
 816         return __mmc_switch(mmc, set, index, value, true);
 817 }
 818
 819 #if !CONFIG_IS_ENABLED(MMC_TINY)
 820 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
 821                               bool hsdowngrade)
 822 {
 823         int err;
 824         int speed_bits;
 825
 826         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 827
 828         switch (mode) {
 829         case MMC_HS:
 830         case MMC_HS_52:
 831         case MMC_DDR_52:
 832                 speed_bits = EXT_CSD_TIMING_HS;
 833                 break;
 834 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 835         case MMC_HS_200:
 836                 speed_bits = EXT_CSD_TIMING_HS200;
 837                 break;
 838 #endif
 839 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 840         case MMC_HS_400:
 841                 speed_bits = EXT_CSD_TIMING_HS400;
 842                 break;
 843 #endif
 844 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 845         case MMC_HS_400_ES:
 846                 speed_bits = EXT_CSD_TIMING_HS400;
 847                 break;
 848 #endif
 849         case MMC_LEGACY:
 850                 speed_bits = EXT_CSD_TIMING_LEGACY;
 851                 break;
 852         default:
 853                 return -EINVAL;
 854         }
 855
 856         err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
 857                            speed_bits, !hsdowngrade);
 858         if (err)
 859                 return err;
 860
 861 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 862     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 863         /*
 864          * In case the eMMC is in HS200/HS400 mode and we are downgrading
 865          * to HS mode, the card clock are still running much faster than
 866          * the supported HS mode clock, so we can not reliably read out
 867          * Extended CSD. Reconfigure the controller to run at HS mode.
 868          */
 869         if (hsdowngrade) {
 870                 mmc_select_mode(mmc, MMC_HS);
 871                 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
 872         }
 873 #endif
 874
 875         if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
 876                 /* Now check to see that it worked */
 877                 err = mmc_send_ext_csd(mmc, test_csd);
 878                 if (err)
 879                         return err;
 880
 881                 /* No high-speed support */
 882                 if (!test_csd[EXT_CSD_HS_TIMING])
 883                         return -ENOTSUPP;
 884         }
 885
 886         return 0;
 887 }
 888
 889 static int mmc_get_capabilities(struct mmc *mmc)
 890 {
 891         u8 *ext_csd = mmc->ext_csd;
 892         char cardtype;
 893
 894         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
 895
 896         if (mmc_host_is_spi(mmc))
 897                 return 0;
 898
 899         /* Only version 4 supports high-speed */
 900         if (mmc->version < MMC_VERSION_4)
 901                 return 0;
 902
 903         if (!ext_csd) {
 904                 pr_err("No ext_csd found!\n"); /* this should enver happen */
 905                 return -ENOTSUPP;
 906         }
 907
 908         mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
 909
 910         cardtype = ext_csd[EXT_CSD_CARD_TYPE];
 911         mmc->cardtype = cardtype;
 912
 913 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 914         if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
 915                         EXT_CSD_CARD_TYPE_HS200_1_8V)) {
 916                 mmc->card_caps |= MMC_MODE_HS200;
 917         }
 918 #endif
 919 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
 920         CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 921         if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
 922                         EXT_CSD_CARD_TYPE_HS400_1_8V)) {
 923                 mmc->card_caps |= MMC_MODE_HS400;
 924         }
 925 #endif
 926         if (cardtype & EXT_CSD_CARD_TYPE_52) {
 927                 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
 928                         mmc->card_caps |= MMC_MODE_DDR_52MHz;
 929                 mmc->card_caps |= MMC_MODE_HS_52MHz;
 930         }
 931         if (cardtype & EXT_CSD_CARD_TYPE_26)
 932                 mmc->card_caps |= MMC_MODE_HS;
 933
 934 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 935         if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
 936             (mmc->card_caps & MMC_MODE_HS400)) {
 937                 mmc->card_caps |= MMC_MODE_HS400_ES;
 938         }
 939 #endif
 940
 941         return 0;
 942 }
 943 #endif
 944
 945 static int mmc_set_capacity(struct mmc *mmc, int part_num)
 946 {
 947         switch (part_num) {
 948         case 0:
 949                 mmc->capacity = mmc->capacity_user;
 950                 break;
 951         case 1:
 952         case 2:
 953                 mmc->capacity = mmc->capacity_boot;
 954                 break;
 955         case 3:
 956                 mmc->capacity = mmc->capacity_rpmb;
 957                 break;
 958         case 4:
 959         case 5:
 960         case 6:
 961         case 7:
 962                 mmc->capacity = mmc->capacity_gp[part_num - 4];
 963                 break;
 964         default:
 965                 return -1;
 966         }
 967
 968         mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 969
 970         return 0;
 971 }
 972
 973 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 974 {
 975         int ret;
 976         int retry = 3;
 977
 978         do {
 979                 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 980                                  EXT_CSD_PART_CONF,
 981                                  (mmc->part_config & ~PART_ACCESS_MASK)
 982                                  | (part_num & PART_ACCESS_MASK));
 983         } while (ret && retry--);
 984
 985         /*
 986          * Set the capacity if the switch succeeded or was intended
 987          * to return to representing the raw device.
 988          */
 989         if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
 990                 ret = mmc_set_capacity(mmc, part_num);
 991                 mmc_get_blk_desc(mmc)->hwpart = part_num;
 992         }
 993
 994         return ret;
 995 }
 996
 997 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
 998 int mmc_hwpart_config(struct mmc *mmc,
 999                       const struct mmc_hwpart_conf *conf,
1000                       enum mmc_hwpart_conf_mode mode)
1001 {
1002         u8 part_attrs = 0;
1003         u32 enh_size_mult;
1004         u32 enh_start_addr;
1005         u32 gp_size_mult[4];
1006         u32 max_enh_size_mult;
1007         u32 tot_enh_size_mult = 0;
1008         u8 wr_rel_set;
1009         int i, pidx, err;
1010         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1011
1012         if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1013                 return -EINVAL;
1014
1015         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
1016                 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
1017                 return -EMEDIUMTYPE;
1018         }
1019
1020         if (!(mmc->part_support & PART_SUPPORT)) {
1021                 pr_err("Card does not support partitioning\n");
1022                 return -EMEDIUMTYPE;
1023         }
1024
1025         if (!mmc->hc_wp_grp_size) {
1026                 pr_err("Card does not define HC WP group size\n");
1027                 return -EMEDIUMTYPE;
1028         }
1029
1030         /* check partition alignment and total enhanced size */
1031         if (conf->user.enh_size) {
1032                 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1033                     conf->user.enh_start % mmc->hc_wp_grp_size) {
1034                         pr_err("User data enhanced area not HC WP group "
1035                                "size aligned\n");
1036                         return -EINVAL;
1037                 }
1038                 part_attrs |= EXT_CSD_ENH_USR;
1039                 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1040                 if (mmc->high_capacity) {
1041                         enh_start_addr = conf->user.enh_start;
1042                 } else {
1043                         enh_start_addr = (conf->user.enh_start << 9);
1044                 }
1045         } else {
1046                 enh_size_mult = 0;
1047                 enh_start_addr = 0;
1048         }
1049         tot_enh_size_mult += enh_size_mult;
1050
1051         for (pidx = 0; pidx < 4; pidx++) {
1052                 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1053                         pr_err("GP%i partition not HC WP group size "
1054                                "aligned\n", pidx+1);
1055                         return -EINVAL;
1056                 }
1057                 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1058                 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1059                         part_attrs |= EXT_CSD_ENH_GP(pidx);
1060                         tot_enh_size_mult += gp_size_mult[pidx];
1061                 }
1062         }
1063
1064         if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1065                 pr_err("Card does not support enhanced attribute\n");
1066                 return -EMEDIUMTYPE;
1067         }
1068
1069         err = mmc_send_ext_csd(mmc, ext_csd);
1070         if (err)
1071                 return err;
1072
1073         max_enh_size_mult =
1074                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1075                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1076                 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1077         if (tot_enh_size_mult > max_enh_size_mult) {
1078                 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1079                        tot_enh_size_mult, max_enh_size_mult);
1080                 return -EMEDIUMTYPE;
1081         }
1082
1083         /* The default value of EXT_CSD_WR_REL_SET is device
1084          * dependent, the values can only be changed if the
1085          * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1086          * changed only once and before partitioning is completed. */
1087         wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1088         if (conf->user.wr_rel_change) {
1089                 if (conf->user.wr_rel_set)
1090                         wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1091                 else
1092                         wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1093         }
1094         for (pidx = 0; pidx < 4; pidx++) {
1095                 if (conf->gp_part[pidx].wr_rel_change) {
1096                         if (conf->gp_part[pidx].wr_rel_set)
1097                                 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1098                         else
1099                                 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1100                 }
1101         }
1102
1103         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1104             !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1105                 puts("Card does not support host controlled partition write "
1106                      "reliability settings\n");
1107                 return -EMEDIUMTYPE;
1108         }
1109
1110         if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1111             EXT_CSD_PARTITION_SETTING_COMPLETED) {
1112                 pr_err("Card already partitioned\n");
1113                 return -EPERM;
1114         }
1115
1116         if (mode == MMC_HWPART_CONF_CHECK)
1117                 return 0;
1118
1119         /* Partitioning requires high-capacity size definitions */
1120         if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1121                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1122                                  EXT_CSD_ERASE_GROUP_DEF, 1);
1123
1124                 if (err)
1125                         return err;
1126
1127                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1128
1129                 /* update erase group size to be high-capacity */
1130                 mmc->erase_grp_size =
1131                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1132
1133         }
1134
1135         /* all OK, write the configuration */
1136         for (i = 0; i < 4; i++) {
1137                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1138                                  EXT_CSD_ENH_START_ADDR+i,
1139                                  (enh_start_addr >> (i*8)) & 0xFF);
1140                 if (err)
1141                         return err;
1142         }
1143         for (i = 0; i < 3; i++) {
1144                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1145                                  EXT_CSD_ENH_SIZE_MULT+i,
1146                                  (enh_size_mult >> (i*8)) & 0xFF);
1147                 if (err)
1148                         return err;
1149         }
1150         for (pidx = 0; pidx < 4; pidx++) {
1151                 for (i = 0; i < 3; i++) {
1152                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1153                                          EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1154                                          (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1155                         if (err)
1156                                 return err;
1157                 }
1158         }
1159         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1160                          EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1161         if (err)
1162                 return err;
1163
1164         if (mode == MMC_HWPART_CONF_SET)
1165                 return 0;
1166
1167         /* The WR_REL_SET is a write-once register but shall be
1168          * written before setting PART_SETTING_COMPLETED. As it is
1169          * write-once we can only write it when completing the
1170          * partitioning. */
1171         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1172                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1173                                  EXT_CSD_WR_REL_SET, wr_rel_set);
1174                 if (err)
1175                         return err;
1176         }
1177
1178         /* Setting PART_SETTING_COMPLETED confirms the partition
1179          * configuration but it only becomes effective after power
1180          * cycle, so we do not adjust the partition related settings
1181          * in the mmc struct. */
1182
1183         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1184                          EXT_CSD_PARTITION_SETTING,
1185                          EXT_CSD_PARTITION_SETTING_COMPLETED);
1186         if (err)
1187                 return err;
1188
1189         return 0;
1190 }
1191 #endif
1192
1193 #if !CONFIG_IS_ENABLED(DM_MMC)
1194 int mmc_getcd(struct mmc *mmc)
1195 {
1196         int cd;
1197
1198         cd = board_mmc_getcd(mmc);
1199
1200         if (cd < 0) {
1201                 if (mmc->cfg->ops->getcd)
1202                         cd = mmc->cfg->ops->getcd(mmc);
1203                 else
1204                         cd = 1;
1205         }
1206
1207         return cd;
1208 }
1209 #endif
1210
1211 #if !CONFIG_IS_ENABLED(MMC_TINY)
1212 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1213 {
1214         struct mmc_cmd cmd;
1215         struct mmc_data data;
1216
1217         /* Switch the frequency */
1218         cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1219         cmd.resp_type = MMC_RSP_R1;
1220         cmd.cmdarg = (mode << 31) | 0xffffff;
1221         cmd.cmdarg &= ~(0xf << (group * 4));
1222         cmd.cmdarg |= value << (group * 4);
1223
1224         data.dest = (char *)resp;
1225         data.blocksize = 64;
1226         data.blocks = 1;
1227         data.flags = MMC_DATA_READ;
1228
1229         return mmc_send_cmd(mmc, &cmd, &data);
1230 }
1231
1232 static int sd_get_capabilities(struct mmc *mmc)
1233 {
1234         int err;
1235         struct mmc_cmd cmd;
1236         ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1237         ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1238         struct mmc_data data;
1239         int timeout;
1240 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1241         u32 sd3_bus_mode;
1242 #endif
1243
1244         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1245
1246         if (mmc_host_is_spi(mmc))
1247                 return 0;
1248
1249         /* Read the SCR to find out if this card supports higher speeds */
1250         cmd.cmdidx = MMC_CMD_APP_CMD;
1251         cmd.resp_type = MMC_RSP_R1;
1252         cmd.cmdarg = mmc->rca << 16;
1253
1254         err = mmc_send_cmd(mmc, &cmd, NULL);
1255
1256         if (err)
1257                 return err;
1258
1259         cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1260         cmd.resp_type = MMC_RSP_R1;
1261         cmd.cmdarg = 0;
1262
1263         timeout = 3;
1264
1265 retry_scr:
1266         data.dest = (char *)scr;
1267         data.blocksize = 8;
1268         data.blocks = 1;
1269         data.flags = MMC_DATA_READ;
1270
1271         err = mmc_send_cmd(mmc, &cmd, &data);
1272
1273         if (err) {
1274                 if (timeout--)
1275                         goto retry_scr;
1276
1277                 return err;
1278         }
1279
1280         mmc->scr[0] = __be32_to_cpu(scr[0]);
1281         mmc->scr[1] = __be32_to_cpu(scr[1]);
1282
1283         switch ((mmc->scr[0] >> 24) & 0xf) {
1284         case 0:
1285                 mmc->version = SD_VERSION_1_0;
1286                 break;
1287         case 1:
1288                 mmc->version = SD_VERSION_1_10;
1289                 break;
1290         case 2:
1291                 mmc->version = SD_VERSION_2;
1292                 if ((mmc->scr[0] >> 15) & 0x1)
1293                         mmc->version = SD_VERSION_3;
1294                 break;
1295         default:
1296                 mmc->version = SD_VERSION_1_0;
1297                 break;
1298         }
1299
1300         if (mmc->scr[0] & SD_DATA_4BIT)
1301                 mmc->card_caps |= MMC_MODE_4BIT;
1302
1303         /* Version 1.0 doesn't support switching */
1304         if (mmc->version == SD_VERSION_1_0)
1305                 return 0;
1306
1307         timeout = 4;
1308         while (timeout--) {
1309                 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1310                                 (u8 *)switch_status);
1311
1312                 if (err)
1313                         return err;
1314
1315                 /* The high-speed function is busy.  Try again */
1316                 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1317                         break;
1318         }
1319
1320         /* If high-speed isn't supported, we return */
1321         if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1322                 mmc->card_caps |= MMC_CAP(SD_HS);
1323
1324 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1325         /* Version before 3.0 don't support UHS modes */
1326         if (mmc->version < SD_VERSION_3)
1327                 return 0;
1328
1329         sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1330         if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1331                 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1332         if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1333                 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1334         if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1335                 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1336         if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1337                 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1338         if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1339                 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1340 #endif
1341
1342         return 0;
1343 }
1344
1345 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1346 {
1347         int err;
1348
1349         ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1350         int speed;
1351
1352         /* SD version 1.00 and 1.01 does not support CMD 6 */
1353         if (mmc->version == SD_VERSION_1_0)
1354                 return 0;
1355
1356         switch (mode) {
1357         case SD_LEGACY:
1358                 speed = UHS_SDR12_BUS_SPEED;
1359                 break;
1360         case SD_HS:
1361                 speed = HIGH_SPEED_BUS_SPEED;
1362                 break;
1363 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1364         case UHS_SDR12:
1365                 speed = UHS_SDR12_BUS_SPEED;
1366                 break;
1367         case UHS_SDR25:
1368                 speed = UHS_SDR25_BUS_SPEED;
1369                 break;
1370         case UHS_SDR50:
1371                 speed = UHS_SDR50_BUS_SPEED;
1372                 break;
1373         case UHS_DDR50:
1374                 speed = UHS_DDR50_BUS_SPEED;
1375                 break;
1376         case UHS_SDR104:
1377                 speed = UHS_SDR104_BUS_SPEED;
1378                 break;
1379 #endif
1380         default:
1381                 return -EINVAL;
1382         }
1383
1384         err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1385         if (err)
1386                 return err;
1387
1388         if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1389                 return -ENOTSUPP;
1390
1391         return 0;
1392 }
1393
1394 static int sd_select_bus_width(struct mmc *mmc, int w)
1395 {
1396         int err;
1397         struct mmc_cmd cmd;
1398
1399         if ((w != 4) && (w != 1))
1400                 return -EINVAL;
1401
1402         cmd.cmdidx = MMC_CMD_APP_CMD;
1403         cmd.resp_type = MMC_RSP_R1;
1404         cmd.cmdarg = mmc->rca << 16;
1405
1406         err = mmc_send_cmd(mmc, &cmd, NULL);
1407         if (err)
1408                 return err;
1409
1410         cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1411         cmd.resp_type = MMC_RSP_R1;
1412         if (w == 4)
1413                 cmd.cmdarg = 2;
1414         else if (w == 1)
1415                 cmd.cmdarg = 0;
1416         err = mmc_send_cmd(mmc, &cmd, NULL);
1417         if (err)
1418                 return err;
1419
1420         return 0;
1421 }
1422 #endif
1423
1424 #if CONFIG_IS_ENABLED(MMC_WRITE)
1425 static int sd_read_ssr(struct mmc *mmc)
1426 {
1427         static const unsigned int sd_au_size[] = {
1428                 0,              SZ_16K / 512,           SZ_32K / 512,
1429                 SZ_64K / 512,   SZ_128K / 512,          SZ_256K / 512,
1430                 SZ_512K / 512,  SZ_1M / 512,            SZ_2M / 512,
1431                 SZ_4M / 512,    SZ_8M / 512,            (SZ_8M + SZ_4M) / 512,
1432                 SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1433                 SZ_64M / 512,
1434         };
1435         int err, i;
1436         struct mmc_cmd cmd;
1437         ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1438         struct mmc_data data;
1439         int timeout = 3;
1440         unsigned int au, eo, et, es;
1441
1442         cmd.cmdidx = MMC_CMD_APP_CMD;
1443         cmd.resp_type = MMC_RSP_R1;
1444         cmd.cmdarg = mmc->rca << 16;
1445
1446         err = mmc_send_cmd(mmc, &cmd, NULL);
1447 #ifdef CONFIG_MMC_QUIRKS
1448         if (err && (mmc->quirks & MMC_QUIRK_RETRY_APP_CMD)) {
1449                 int retries = 4;
1450                 /*
1451                  * It has been seen that APP_CMD may fail on the first
1452                  * attempt, let's try a few more times
1453                  */
1454                 do {
1455                         err = mmc_send_cmd(mmc, &cmd, NULL);
1456                         if (!err)
1457                                 break;
1458                 } while (retries--);
1459         }
1460 #endif
1461         if (err)
1462                 return err;
1463
1464         cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1465         cmd.resp_type = MMC_RSP_R1;
1466         cmd.cmdarg = 0;
1467
1468 retry_ssr:
1469         data.dest = (char *)ssr;
1470         data.blocksize = 64;
1471         data.blocks = 1;
1472         data.flags = MMC_DATA_READ;
1473
1474         err = mmc_send_cmd(mmc, &cmd, &data);
1475         if (err) {
1476                 if (timeout--)
1477                         goto retry_ssr;
1478
1479                 return err;
1480         }
1481
1482         for (i = 0; i < 16; i++)
1483                 ssr[i] = be32_to_cpu(ssr[i]);
1484
1485         au = (ssr[2] >> 12) & 0xF;
1486         if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1487                 mmc->ssr.au = sd_au_size[au];
1488                 es = (ssr[3] >> 24) & 0xFF;
1489                 es |= (ssr[2] & 0xFF) << 8;
1490                 et = (ssr[3] >> 18) & 0x3F;
1491                 if (es && et) {
1492                         eo = (ssr[3] >> 16) & 0x3;
1493                         mmc->ssr.erase_timeout = (et * 1000) / es;
1494                         mmc->ssr.erase_offset = eo * 1000;
1495                 }
1496         } else {
1497                 pr_debug("Invalid Allocation Unit Size.\n");
1498         }
1499
1500         return 0;
1501 }
1502 #endif
1503 /* frequency bases */
1504 /* divided by 10 to be nice to platforms without floating point */
1505 static const int fbase[] = {
1506         10000,
1507         100000,
1508         1000000,
1509         10000000,
1510 };
1511
1512 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
1513  * to platforms without floating point.
1514  */
1515 static const u8 multipliers[] = {
1516         0,      /* reserved */
1517         10,
1518         12,
1519         13,
1520         15,
1521         20,
1522         25,
1523         30,
1524         35,
1525         40,
1526         45,
1527         50,
1528         55,
1529         60,
1530         70,
1531         80,
1532 };
1533
1534 static inline int bus_width(uint cap)
1535 {
1536         if (cap == MMC_MODE_8BIT)
1537                 return 8;
1538         if (cap == MMC_MODE_4BIT)
1539                 return 4;
1540         if (cap == MMC_MODE_1BIT)
1541                 return 1;
1542         pr_warn("invalid bus witdh capability 0x%x\n", cap);
1543         return 0;
1544 }
1545
1546 #if !CONFIG_IS_ENABLED(DM_MMC)
1547 #ifdef MMC_SUPPORTS_TUNING
1548 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1549 {
1550         return -ENOTSUPP;
1551 }
1552 #endif
1553
1554 static int mmc_set_ios(struct mmc *mmc)
1555 {
1556         int ret = 0;
1557
1558         if (mmc->cfg->ops->set_ios)
1559                 ret = mmc->cfg->ops->set_ios(mmc);
1560
1561         return ret;
1562 }
1563
1564 static int mmc_host_power_cycle(struct mmc *mmc)
1565 {
1566         int ret = 0;
1567
1568         if (mmc->cfg->ops->host_power_cycle)
1569                 ret = mmc->cfg->ops->host_power_cycle(mmc);
1570
1571         return ret;
1572 }
1573 #endif
1574
1575 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1576 {
1577         if (!disable) {
1578                 if (clock > mmc->cfg->f_max)
1579                         clock = mmc->cfg->f_max;
1580
1581                 if (clock < mmc->cfg->f_min)
1582                         clock = mmc->cfg->f_min;
1583         }
1584
1585         mmc->clock = clock;
1586         mmc->clk_disable = disable;
1587
1588         debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1589
1590         return mmc_set_ios(mmc);
1591 }
1592
1593 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1594 {
1595         mmc->bus_width = width;
1596
1597         return mmc_set_ios(mmc);
1598 }
1599
1600 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1601 /*
1602  * helper function to display the capabilities in a human
1603  * friendly manner. The capabilities include bus width and
1604  * supported modes.
1605  */
1606 void mmc_dump_capabilities(const char *text, uint caps)
1607 {
1608         enum bus_mode mode;
1609
1610         pr_debug("%s: widths [", text);
1611         if (caps & MMC_MODE_8BIT)
1612                 pr_debug("8, ");
1613         if (caps & MMC_MODE_4BIT)
1614                 pr_debug("4, ");
1615         if (caps & MMC_MODE_1BIT)
1616                 pr_debug("1, ");
1617         pr_debug("\b\b] modes [");
1618         for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1619                 if (MMC_CAP(mode) & caps)
1620                         pr_debug("%s, ", mmc_mode_name(mode));
1621         pr_debug("\b\b]\n");
1622 }
1623 #endif
1624
1625 struct mode_width_tuning {
1626         enum bus_mode mode;
1627         uint widths;
1628 #ifdef MMC_SUPPORTS_TUNING
1629         uint tuning;
1630 #endif
1631 };
1632
1633 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1634 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1635 {
1636         switch (voltage) {
1637         case MMC_SIGNAL_VOLTAGE_000: return 0;
1638         case MMC_SIGNAL_VOLTAGE_330: return 3300;
1639         case MMC_SIGNAL_VOLTAGE_180: return 1800;
1640         case MMC_SIGNAL_VOLTAGE_120: return 1200;
1641         }
1642         return -EINVAL;
1643 }
1644
1645 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1646 {
1647         int err;
1648
1649         if (mmc->signal_voltage == signal_voltage)
1650                 return 0;
1651
1652         mmc->signal_voltage = signal_voltage;
1653         err = mmc_set_ios(mmc);
1654         if (err)
1655                 pr_debug("unable to set voltage (err %d)\n", err);
1656
1657         return err;
1658 }
1659 #else
1660 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1661 {
1662         return 0;
1663 }
1664 #endif
1665
1666 #if !CONFIG_IS_ENABLED(MMC_TINY)
1667 static const struct mode_width_tuning sd_modes_by_pref[] = {
1668 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1669 #ifdef MMC_SUPPORTS_TUNING
1670         {
1671                 .mode = UHS_SDR104,
1672                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1673                 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1674         },
1675 #endif
1676         {
1677                 .mode = UHS_SDR50,
1678                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1679         },
1680         {
1681                 .mode = UHS_DDR50,
1682                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1683         },
1684         {
1685                 .mode = UHS_SDR25,
1686                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1687         },
1688 #endif
1689         {
1690                 .mode = SD_HS,
1691                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1692         },
1693 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1694         {
1695                 .mode = UHS_SDR12,
1696                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1697         },
1698 #endif
1699         {
1700                 .mode = SD_LEGACY,
1701                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1702         }
1703 };
1704
1705 #define for_each_sd_mode_by_pref(caps, mwt) \
1706         for (mwt = sd_modes_by_pref;\
1707              mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1708              mwt++) \
1709                 if (caps & MMC_CAP(mwt->mode))
1710
1711 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1712 {
1713         int err;
1714         uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1715         const struct mode_width_tuning *mwt;
1716 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1717         bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1718 #else
1719         bool uhs_en = false;
1720 #endif
1721         uint caps;
1722
1723 #ifdef DEBUG
1724         mmc_dump_capabilities("sd card", card_caps);
1725         mmc_dump_capabilities("host", mmc->host_caps);
1726 #endif
1727
1728         if (mmc_host_is_spi(mmc)) {
1729                 mmc_set_bus_width(mmc, 1);
1730                 mmc_select_mode(mmc, SD_LEGACY);
1731                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1732                 return 0;
1733         }
1734
1735         /* Restrict card's capabilities by what the host can do */
1736         caps = card_caps & mmc->host_caps;
1737
1738         if (!uhs_en)
1739                 caps &= ~UHS_CAPS;
1740
1741         for_each_sd_mode_by_pref(caps, mwt) {
1742                 uint *w;
1743
1744                 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1745                         if (*w & caps & mwt->widths) {
1746                                 pr_debug("trying mode %s width %d (at %d MHz)\n",
1747                                          mmc_mode_name(mwt->mode),
1748                                          bus_width(*w),
1749                                          mmc_mode2freq(mmc, mwt->mode) / 1000000);
1750
1751                                 /* configure the bus width (card + host) */
1752                                 err = sd_select_bus_width(mmc, bus_width(*w));
1753                                 if (err)
1754                                         goto error;
1755                                 mmc_set_bus_width(mmc, bus_width(*w));
1756
1757                                 /* configure the bus mode (card) */
1758                                 err = sd_set_card_speed(mmc, mwt->mode);
1759                                 if (err)
1760                                         goto error;
1761
1762                                 /* configure the bus mode (host) */
1763                                 mmc_select_mode(mmc, mwt->mode);
1764                                 mmc_set_clock(mmc, mmc->tran_speed,
1765                                                 MMC_CLK_ENABLE);
1766
1767 #ifdef MMC_SUPPORTS_TUNING
1768                                 /* execute tuning if needed */
1769                                 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1770                                         err = mmc_execute_tuning(mmc,
1771                                                                  mwt->tuning);
1772                                         if (err) {
1773                                                 pr_debug("tuning failed\n");
1774                                                 goto error;
1775                                         }
1776                                 }
1777 #endif
1778
1779 #if CONFIG_IS_ENABLED(MMC_WRITE)
1780                                 err = sd_read_ssr(mmc);
1781                                 if (err)
1782                                         pr_warn("unable to read ssr\n");
1783 #endif
1784                                 if (!err)
1785                                         return 0;
1786
1787 error:
1788                                 /* revert to a safer bus speed */
1789                                 mmc_select_mode(mmc, SD_LEGACY);
1790                                 mmc_set_clock(mmc, mmc->tran_speed,
1791                                                 MMC_CLK_ENABLE);
1792                         }
1793                 }
1794         }
1795
1796         pr_err("unable to select a mode\n");
1797         return -ENOTSUPP;
1798 }
1799
1800 /*
1801  * read the compare the part of ext csd that is constant.
1802  * This can be used to check that the transfer is working
1803  * as expected.
1804  */
1805 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1806 {
1807         int err;
1808         const u8 *ext_csd = mmc->ext_csd;
1809         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1810
1811         if (mmc->version < MMC_VERSION_4)
1812                 return 0;
1813
1814         err = mmc_send_ext_csd(mmc, test_csd);
1815         if (err)
1816                 return err;
1817
1818         /* Only compare read only fields */
1819         if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1820                 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1821             ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1822                 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1823             ext_csd[EXT_CSD_REV]
1824                 == test_csd[EXT_CSD_REV] &&
1825             ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1826                 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1827             memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1828                    &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1829                 return 0;
1830
1831         return -EBADMSG;
1832 }
1833
1834 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1835 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1836                                   uint32_t allowed_mask)
1837 {
1838         u32 card_mask = 0;
1839
1840         switch (mode) {
1841         case MMC_HS_400_ES:
1842         case MMC_HS_400:
1843         case MMC_HS_200:
1844                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1845                     EXT_CSD_CARD_TYPE_HS400_1_8V))
1846                         card_mask |= MMC_SIGNAL_VOLTAGE_180;
1847                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1848                     EXT_CSD_CARD_TYPE_HS400_1_2V))
1849                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1850                 break;
1851         case MMC_DDR_52:
1852                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1853                         card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1854                                      MMC_SIGNAL_VOLTAGE_180;
1855                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1856                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1857                 break;
1858         default:
1859                 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1860                 break;
1861         }
1862
1863         while (card_mask & allowed_mask) {
1864                 enum mmc_voltage best_match;
1865
1866                 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1867                 if (!mmc_set_signal_voltage(mmc,  best_match))
1868                         return 0;
1869
1870                 allowed_mask &= ~best_match;
1871         }
1872
1873         return -ENOTSUPP;
1874 }
1875 #else
1876 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1877                                          uint32_t allowed_mask)
1878 {
1879         return 0;
1880 }
1881 #endif
1882
1883 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1884 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1885         {
1886                 .mode = MMC_HS_400_ES,
1887                 .widths = MMC_MODE_8BIT,
1888         },
1889 #endif
1890 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1891         {
1892                 .mode = MMC_HS_400,
1893                 .widths = MMC_MODE_8BIT,
1894                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1895         },
1896 #endif
1897 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1898         {
1899                 .mode = MMC_HS_200,
1900                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1901                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1902         },
1903 #endif
1904         {
1905                 .mode = MMC_DDR_52,
1906                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1907         },
1908         {
1909                 .mode = MMC_HS_52,
1910                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1911         },
1912         {
1913                 .mode = MMC_HS,
1914                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1915         },
1916         {
1917                 .mode = MMC_LEGACY,
1918                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1919         }
1920 };
1921
1922 #define for_each_mmc_mode_by_pref(caps, mwt) \
1923         for (mwt = mmc_modes_by_pref;\
1924             mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1925             mwt++) \
1926                 if (caps & MMC_CAP(mwt->mode))
1927
1928 static const struct ext_csd_bus_width {
1929         uint cap;
1930         bool is_ddr;
1931         uint ext_csd_bits;
1932 } ext_csd_bus_width[] = {
1933         {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1934         {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1935         {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1936         {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1937         {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1938 };
1939
1940 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1941 static int mmc_select_hs400(struct mmc *mmc)
1942 {
1943         int err;
1944
1945         /* Set timing to HS200 for tuning */
1946         err = mmc_set_card_speed(mmc, MMC_HS_200, false);
1947         if (err)
1948                 return err;
1949
1950         /* configure the bus mode (host) */
1951         mmc_select_mode(mmc, MMC_HS_200);
1952         mmc_set_clock(mmc, mmc->tran_speed, false);
1953
1954         /* execute tuning if needed */
1955         err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1956         if (err) {
1957                 debug("tuning failed\n");
1958                 return err;
1959         }
1960
1961         /* Set back to HS */
1962         mmc_set_card_speed(mmc, MMC_HS, true);
1963
1964         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1965                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1966         if (err)
1967                 return err;
1968
1969         err = mmc_set_card_speed(mmc, MMC_HS_400, false);
1970         if (err)
1971                 return err;
1972
1973         mmc_select_mode(mmc, MMC_HS_400);
1974         err = mmc_set_clock(mmc, mmc->tran_speed, false);
1975         if (err)
1976                 return err;
1977
1978         return 0;
1979 }
1980 #else
1981 static int mmc_select_hs400(struct mmc *mmc)
1982 {
1983         return -ENOTSUPP;
1984 }
1985 #endif
1986
1987 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1988 #if !CONFIG_IS_ENABLED(DM_MMC)
1989 static int mmc_set_enhanced_strobe(struct mmc *mmc)
1990 {
1991         return -ENOTSUPP;
1992 }
1993 #endif
1994 static int mmc_select_hs400es(struct mmc *mmc)
1995 {
1996         int err;
1997
1998         err = mmc_set_card_speed(mmc, MMC_HS, true);
1999         if (err)
2000                 return err;
2001
2002         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2003                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2004                          EXT_CSD_BUS_WIDTH_STROBE);
2005         if (err) {
2006                 printf("switch to bus width for hs400 failed\n");
2007                 return err;
2008         }
2009         /* TODO: driver strength */
2010         err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2011         if (err)
2012                 return err;
2013
2014         mmc_select_mode(mmc, MMC_HS_400_ES);
2015         err = mmc_set_clock(mmc, mmc->tran_speed, false);
2016         if (err)
2017                 return err;
2018
2019         return mmc_set_enhanced_strobe(mmc);
2020 }
2021 #else
2022 static int mmc_select_hs400es(struct mmc *mmc)
2023 {
2024         return -ENOTSUPP;
2025 }
2026 #endif
2027
2028 #define for_each_supported_width(caps, ddr, ecbv) \
2029         for (ecbv = ext_csd_bus_width;\
2030             ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2031             ecbv++) \
2032                 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2033
2034 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
2035 {
2036         int err;
2037         const struct mode_width_tuning *mwt;
2038         const struct ext_csd_bus_width *ecbw;
2039
2040 #ifdef DEBUG
2041         mmc_dump_capabilities("mmc", card_caps);
2042         mmc_dump_capabilities("host", mmc->host_caps);
2043 #endif
2044
2045         if (mmc_host_is_spi(mmc)) {
2046                 mmc_set_bus_width(mmc, 1);
2047                 mmc_select_mode(mmc, MMC_LEGACY);
2048                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2049                 return 0;
2050         }
2051
2052         /* Restrict card's capabilities by what the host can do */
2053         card_caps &= mmc->host_caps;
2054
2055         /* Only version 4 of MMC supports wider bus widths */
2056         if (mmc->version < MMC_VERSION_4)
2057                 return 0;
2058
2059         if (!mmc->ext_csd) {
2060                 pr_debug("No ext_csd found!\n"); /* this should enver happen */
2061                 return -ENOTSUPP;
2062         }
2063
2064 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2065     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2066         /*
2067          * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2068          * before doing anything else, since a transition from either of
2069          * the HS200/HS400 mode directly to legacy mode is not supported.
2070          */
2071         if (mmc->selected_mode == MMC_HS_200 ||
2072             mmc->selected_mode == MMC_HS_400)
2073                 mmc_set_card_speed(mmc, MMC_HS, true);
2074         else
2075 #endif
2076                 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
2077
2078         for_each_mmc_mode_by_pref(card_caps, mwt) {
2079                 for_each_supported_width(card_caps & mwt->widths,
2080                                          mmc_is_mode_ddr(mwt->mode), ecbw) {
2081                         enum mmc_voltage old_voltage;
2082                         pr_debug("trying mode %s width %d (at %d MHz)\n",
2083                                  mmc_mode_name(mwt->mode),
2084                                  bus_width(ecbw->cap),
2085                                  mmc_mode2freq(mmc, mwt->mode) / 1000000);
2086                         old_voltage = mmc->signal_voltage;
2087                         err = mmc_set_lowest_voltage(mmc, mwt->mode,
2088                                                      MMC_ALL_SIGNAL_VOLTAGE);
2089                         if (err)
2090                                 continue;
2091
2092                         /* configure the bus width (card + host) */
2093                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2094                                     EXT_CSD_BUS_WIDTH,
2095                                     ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2096                         if (err)
2097                                 goto error;
2098                         mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2099
2100                         if (mwt->mode == MMC_HS_400) {
2101                                 err = mmc_select_hs400(mmc);
2102                                 if (err) {
2103                                         printf("Select HS400 failed %d\n", err);
2104                                         goto error;
2105                                 }
2106                         } else if (mwt->mode == MMC_HS_400_ES) {
2107                                 err = mmc_select_hs400es(mmc);
2108                                 if (err) {
2109                                         printf("Select HS400ES failed %d\n",
2110                                                err);
2111                                         goto error;
2112                                 }
2113                         } else {
2114                                 /* configure the bus speed (card) */
2115                                 err = mmc_set_card_speed(mmc, mwt->mode, false);
2116                                 if (err)
2117                                         goto error;
2118
2119                                 /*
2120                                  * configure the bus width AND the ddr mode
2121                                  * (card). The host side will be taken care
2122                                  * of in the next step
2123                                  */
2124                                 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2125                                         err = mmc_switch(mmc,
2126                                                          EXT_CSD_CMD_SET_NORMAL,
2127                                                          EXT_CSD_BUS_WIDTH,
2128                                                          ecbw->ext_csd_bits);
2129                                         if (err)
2130                                                 goto error;
2131                                 }
2132
2133                                 /* configure the bus mode (host) */
2134                                 mmc_select_mode(mmc, mwt->mode);
2135                                 mmc_set_clock(mmc, mmc->tran_speed,
2136                                               MMC_CLK_ENABLE);
2137 #ifdef MMC_SUPPORTS_TUNING
2138
2139                                 /* execute tuning if needed */
2140                                 if (mwt->tuning) {
2141                                         err = mmc_execute_tuning(mmc,
2142                                                                  mwt->tuning);
2143                                         if (err) {
2144                                                 pr_debug("tuning failed\n");
2145                                                 goto error;
2146                                         }
2147                                 }
2148 #endif
2149                         }
2150
2151                         /* do a transfer to check the configuration */
2152                         err = mmc_read_and_compare_ext_csd(mmc);
2153                         if (!err)
2154                                 return 0;
2155 error:
2156                         mmc_set_signal_voltage(mmc, old_voltage);
2157                         /* if an error occured, revert to a safer bus mode */
2158                         mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2159                                    EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2160                         mmc_select_mode(mmc, MMC_LEGACY);
2161                         mmc_set_bus_width(mmc, 1);
2162                 }
2163         }
2164
2165         pr_err("unable to select a mode\n");
2166
2167         return -ENOTSUPP;
2168 }
2169 #endif
2170
2171 #if CONFIG_IS_ENABLED(MMC_TINY)
2172 DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2173 #endif
2174
2175 static int mmc_startup_v4(struct mmc *mmc)
2176 {
2177         int err, i;
2178         u64 capacity;
2179         bool has_parts = false;
2180         bool part_completed;
2181         static const u32 mmc_versions[] = {
2182                 MMC_VERSION_4,
2183                 MMC_VERSION_4_1,
2184                 MMC_VERSION_4_2,
2185                 MMC_VERSION_4_3,
2186                 MMC_VERSION_4_4,
2187                 MMC_VERSION_4_41,
2188                 MMC_VERSION_4_5,
2189                 MMC_VERSION_5_0,
2190                 MMC_VERSION_5_1
2191         };
2192
2193 #if CONFIG_IS_ENABLED(MMC_TINY)
2194         u8 *ext_csd = ext_csd_bkup;
2195
2196         if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2197                 return 0;
2198
2199         if (!mmc->ext_csd)
2200                 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2201
2202         err = mmc_send_ext_csd(mmc, ext_csd);
2203         if (err)
2204                 goto error;
2205
2206         /* store the ext csd for future reference */
2207         if (!mmc->ext_csd)
2208                 mmc->ext_csd = ext_csd;
2209 #else
2210         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2211
2212         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2213                 return 0;
2214
2215         /* check  ext_csd version and capacity */
2216         err = mmc_send_ext_csd(mmc, ext_csd);
2217         if (err)
2218                 goto error;
2219
2220         /* store the ext csd for future reference */
2221         if (!mmc->ext_csd)
2222                 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2223         if (!mmc->ext_csd)
2224                 return -ENOMEM;
2225         memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2226 #endif
2227         if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2228                 return -EINVAL;
2229
2230         mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2231
2232         if (mmc->version >= MMC_VERSION_4_2) {
2233                 /*
2234                  * According to the JEDEC Standard, the value of
2235                  * ext_csd's capacity is valid if the value is more
2236                  * than 2GB
2237                  */
2238                 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2239                                 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2240                                 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2241                                 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2242                 capacity *= MMC_MAX_BLOCK_LEN;
2243                 if ((capacity >> 20) > 2 * 1024)
2244                         mmc->capacity_user = capacity;
2245         }
2246
2247         if (mmc->version >= MMC_VERSION_4_5)
2248                 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2249
2250         /* The partition data may be non-zero but it is only
2251          * effective if PARTITION_SETTING_COMPLETED is set in
2252          * EXT_CSD, so ignore any data if this bit is not set,
2253          * except for enabling the high-capacity group size
2254          * definition (see below).
2255          */
2256         part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2257                             EXT_CSD_PARTITION_SETTING_COMPLETED);
2258
2259         mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2260         /* Some eMMC set the value too low so set a minimum */
2261         if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2262                 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2263
2264         /* store the partition info of emmc */
2265         mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2266         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2267             ext_csd[EXT_CSD_BOOT_MULT])
2268                 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2269         if (part_completed &&
2270             (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2271                 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2272
2273         mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2274
2275         mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2276
2277         for (i = 0; i < 4; i++) {
2278                 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2279                 uint mult = (ext_csd[idx + 2] << 16) +
2280                         (ext_csd[idx + 1] << 8) + ext_csd[idx];
2281                 if (mult)
2282                         has_parts = true;
2283                 if (!part_completed)
2284                         continue;
2285                 mmc->capacity_gp[i] = mult;
2286                 mmc->capacity_gp[i] *=
2287                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2288                 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2289                 mmc->capacity_gp[i] <<= 19;
2290         }
2291
2292 #ifndef CONFIG_SPL_BUILD
2293         if (part_completed) {
2294                 mmc->enh_user_size =
2295                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2296                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2297                         ext_csd[EXT_CSD_ENH_SIZE_MULT];
2298                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2299                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2300                 mmc->enh_user_size <<= 19;
2301                 mmc->enh_user_start =
2302                         (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2303                         (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2304                         (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2305                         ext_csd[EXT_CSD_ENH_START_ADDR];
2306                 if (mmc->high_capacity)
2307                         mmc->enh_user_start <<= 9;
2308         }
2309 #endif
2310
2311         /*
2312          * Host needs to enable ERASE_GRP_DEF bit if device is
2313          * partitioned. This bit will be lost every time after a reset
2314          * or power off. This will affect erase size.
2315          */
2316         if (part_completed)
2317                 has_parts = true;
2318         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2319             (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2320                 has_parts = true;
2321         if (has_parts) {
2322                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2323                                  EXT_CSD_ERASE_GROUP_DEF, 1);
2324
2325                 if (err)
2326                         goto error;
2327
2328                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2329         }
2330
2331         if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2332 #if CONFIG_IS_ENABLED(MMC_WRITE)
2333                 /* Read out group size from ext_csd */
2334                 mmc->erase_grp_size =
2335                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2336 #endif
2337                 /*
2338                  * if high capacity and partition setting completed
2339                  * SEC_COUNT is valid even if it is smaller than 2 GiB
2340                  * JEDEC Standard JESD84-B45, 6.2.4
2341                  */
2342                 if (mmc->high_capacity && part_completed) {
2343                         capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2344                                 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2345                                 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2346                                 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2347                         capacity *= MMC_MAX_BLOCK_LEN;
2348                         mmc->capacity_user = capacity;
2349                 }
2350         }
2351 #if CONFIG_IS_ENABLED(MMC_WRITE)
2352         else {
2353                 /* Calculate the group size from the csd value. */
2354                 int erase_gsz, erase_gmul;
2355
2356                 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2357                 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2358                 mmc->erase_grp_size = (erase_gsz + 1)
2359                         * (erase_gmul + 1);
2360         }
2361 #endif
2362 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2363         mmc->hc_wp_grp_size = 1024
2364                 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2365                 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2366 #endif
2367
2368         mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2369
2370         return 0;
2371 error:
2372         if (mmc->ext_csd) {
2373 #if !CONFIG_IS_ENABLED(MMC_TINY)
2374                 free(mmc->ext_csd);
2375 #endif
2376                 mmc->ext_csd = NULL;
2377         }
2378         return err;
2379 }
2380
2381 static int mmc_startup(struct mmc *mmc)
2382 {
2383         int err, i;
2384         uint mult, freq;
2385         u64 cmult, csize;
2386         struct mmc_cmd cmd;
2387         struct blk_desc *bdesc;
2388
2389 #ifdef CONFIG_MMC_SPI_CRC_ON
2390         if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2391                 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2392                 cmd.resp_type = MMC_RSP_R1;
2393                 cmd.cmdarg = 1;
2394                 err = mmc_send_cmd(mmc, &cmd, NULL);
2395                 if (err)
2396                         return err;
2397         }
2398 #endif
2399
2400         /* Put the Card in Identify Mode */
2401         cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2402                 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2403         cmd.resp_type = MMC_RSP_R2;
2404         cmd.cmdarg = 0;
2405
2406         err = mmc_send_cmd(mmc, &cmd, NULL);
2407
2408 #ifdef CONFIG_MMC_QUIRKS
2409         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2410                 int retries = 4;
2411                 /*
2412                  * It has been seen that SEND_CID may fail on the first
2413                  * attempt, let's try a few more time
2414                  */
2415                 do {
2416                         err = mmc_send_cmd(mmc, &cmd, NULL);
2417                         if (!err)
2418                                 break;
2419                 } while (retries--);
2420         }
2421 #endif
2422
2423         if (err)
2424                 return err;
2425
2426         memcpy(mmc->cid, cmd.response, 16);
2427
2428         /*
2429          * For MMC cards, set the Relative Address.
2430          * For SD cards, get the Relatvie Address.
2431          * This also puts the cards into Standby State
2432          */
2433         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2434                 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2435                 cmd.cmdarg = mmc->rca << 16;
2436                 cmd.resp_type = MMC_RSP_R6;
2437
2438                 err = mmc_send_cmd(mmc, &cmd, NULL);
2439
2440                 if (err)
2441                         return err;
2442
2443                 if (IS_SD(mmc))
2444                         mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2445         }
2446
2447         /* Get the Card-Specific Data */
2448         cmd.cmdidx = MMC_CMD_SEND_CSD;
2449         cmd.resp_type = MMC_RSP_R2;
2450         cmd.cmdarg = mmc->rca << 16;
2451
2452         err = mmc_send_cmd(mmc, &cmd, NULL);
2453
2454         if (err)
2455                 return err;
2456
2457         mmc->csd[0] = cmd.response[0];
2458         mmc->csd[1] = cmd.response[1];
2459         mmc->csd[2] = cmd.response[2];
2460         mmc->csd[3] = cmd.response[3];
2461
2462         if (mmc->version == MMC_VERSION_UNKNOWN) {
2463                 int version = (cmd.response[0] >> 26) & 0xf;
2464
2465                 switch (version) {
2466                 case 0:
2467                         mmc->version = MMC_VERSION_1_2;
2468                         break;
2469                 case 1:
2470                         mmc->version = MMC_VERSION_1_4;
2471                         break;
2472                 case 2:
2473                         mmc->version = MMC_VERSION_2_2;
2474                         break;
2475                 case 3:
2476                         mmc->version = MMC_VERSION_3;
2477                         break;
2478                 case 4:
2479                         mmc->version = MMC_VERSION_4;
2480                         break;
2481                 default:
2482                         mmc->version = MMC_VERSION_1_2;
2483                         break;
2484                 }
2485         }
2486
2487         /* divide frequency by 10, since the mults are 10x bigger */
2488         freq = fbase[(cmd.response[0] & 0x7)];
2489         mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2490
2491         mmc->legacy_speed = freq * mult;
2492         mmc_select_mode(mmc, MMC_LEGACY);
2493
2494         mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2495         mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2496 #if CONFIG_IS_ENABLED(MMC_WRITE)
2497
2498         if (IS_SD(mmc))
2499                 mmc->write_bl_len = mmc->read_bl_len;
2500         else
2501                 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2502 #endif
2503
2504         if (mmc->high_capacity) {
2505                 csize = (mmc->csd[1] & 0x3f) << 16
2506                         | (mmc->csd[2] & 0xffff0000) >> 16;
2507                 cmult = 8;
2508         } else {
2509                 csize = (mmc->csd[1] & 0x3ff) << 2
2510                         | (mmc->csd[2] & 0xc0000000) >> 30;
2511                 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2512         }
2513
2514         mmc->capacity_user = (csize + 1) << (cmult + 2);
2515         mmc->capacity_user *= mmc->read_bl_len;
2516         mmc->capacity_boot = 0;
2517         mmc->capacity_rpmb = 0;
2518         for (i = 0; i < 4; i++)
2519                 mmc->capacity_gp[i] = 0;
2520
2521         if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2522                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2523
2524 #if CONFIG_IS_ENABLED(MMC_WRITE)
2525         if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2526                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2527 #endif
2528
2529         if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2530                 cmd.cmdidx = MMC_CMD_SET_DSR;
2531                 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2532                 cmd.resp_type = MMC_RSP_NONE;
2533                 if (mmc_send_cmd(mmc, &cmd, NULL))
2534                         pr_warn("MMC: SET_DSR failed\n");
2535         }
2536
2537         /* Select the card, and put it into Transfer Mode */
2538         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2539                 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2540                 cmd.resp_type = MMC_RSP_R1;
2541                 cmd.cmdarg = mmc->rca << 16;
2542                 err = mmc_send_cmd(mmc, &cmd, NULL);
2543
2544                 if (err)
2545                         return err;
2546         }
2547
2548         /*
2549          * For SD, its erase group is always one sector
2550          */
2551 #if CONFIG_IS_ENABLED(MMC_WRITE)
2552         mmc->erase_grp_size = 1;
2553 #endif
2554         mmc->part_config = MMCPART_NOAVAILABLE;
2555
2556         err = mmc_startup_v4(mmc);
2557         if (err)
2558                 return err;
2559
2560         err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2561         if (err)
2562                 return err;
2563
2564 #if CONFIG_IS_ENABLED(MMC_TINY)
2565         mmc_set_clock(mmc, mmc->legacy_speed, false);
2566         mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2567         mmc_set_bus_width(mmc, 1);
2568 #else
2569         if (IS_SD(mmc)) {
2570                 err = sd_get_capabilities(mmc);
2571                 if (err)
2572                         return err;
2573                 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2574         } else {
2575                 err = mmc_get_capabilities(mmc);
2576                 if (err)
2577                         return err;
2578                 mmc_select_mode_and_width(mmc, mmc->card_caps);
2579         }
2580 #endif
2581         if (err)
2582                 return err;
2583
2584         mmc->best_mode = mmc->selected_mode;
2585
2586         /* Fix the block length for DDR mode */
2587         if (mmc->ddr_mode) {
2588                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2589 #if CONFIG_IS_ENABLED(MMC_WRITE)
2590                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2591 #endif
2592         }
2593
2594         /* fill in device description */
2595         bdesc = mmc_get_blk_desc(mmc);
2596         bdesc->lun = 0;
2597         bdesc->hwpart = 0;
2598         bdesc->type = 0;
2599         bdesc->blksz = mmc->read_bl_len;
2600         bdesc->log2blksz = LOG2(bdesc->blksz);
2601         bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2602 #if !defined(CONFIG_SPL_BUILD) || \
2603                 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2604                 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
2605         sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2606                 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2607                 (mmc->cid[3] >> 16) & 0xffff);
2608         sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2609                 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2610                 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2611                 (mmc->cid[2] >> 24) & 0xff);
2612         sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2613                 (mmc->cid[2] >> 16) & 0xf);
2614 #else
2615         bdesc->vendor[0] = 0;
2616         bdesc->product[0] = 0;
2617         bdesc->revision[0] = 0;
2618 #endif
2619
2620 #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2621         part_init(bdesc);
2622 #endif
2623
2624         return 0;
2625 }
2626
2627 static int mmc_send_if_cond(struct mmc *mmc)
2628 {
2629         struct mmc_cmd cmd;
2630         int err;
2631
2632         cmd.cmdidx = SD_CMD_SEND_IF_COND;
2633         /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2634         cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2635         cmd.resp_type = MMC_RSP_R7;
2636
2637         err = mmc_send_cmd(mmc, &cmd, NULL);
2638
2639         if (err)
2640                 return err;
2641
2642         if ((cmd.response[0] & 0xff) != 0xaa)
2643                 return -EOPNOTSUPP;
2644         else
2645                 mmc->version = SD_VERSION_2;
2646
2647         return 0;
2648 }
2649
2650 #if !CONFIG_IS_ENABLED(DM_MMC)
2651 /* board-specific MMC power initializations. */
2652 __weak void board_mmc_power_init(void)
2653 {
2654 }
2655 #endif
2656
2657 static int mmc_power_init(struct mmc *mmc)
2658 {
2659 #if CONFIG_IS_ENABLED(DM_MMC)
2660 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2661         int ret;
2662
2663         ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2664                                           &mmc->vmmc_supply);
2665         if (ret)
2666                 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2667
2668         ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2669                                           &mmc->vqmmc_supply);
2670         if (ret)
2671                 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2672 #endif
2673 #else /* !CONFIG_DM_MMC */
2674         /*
2675          * Driver model should use a regulator, as above, rather than calling
2676          * out to board code.
2677          */
2678         board_mmc_power_init();
2679 #endif
2680         return 0;
2681 }
2682
2683 /*
2684  * put the host in the initial state:
2685  * - turn on Vdd (card power supply)
2686  * - configure the bus width and clock to minimal values
2687  */
2688 static void mmc_set_initial_state(struct mmc *mmc)
2689 {
2690         int err;
2691
2692         /* First try to set 3.3V. If it fails set to 1.8V */
2693         err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2694         if (err != 0)
2695                 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2696         if (err != 0)
2697                 pr_warn("mmc: failed to set signal voltage\n");
2698
2699         mmc_select_mode(mmc, MMC_LEGACY);
2700         mmc_set_bus_width(mmc, 1);
2701         mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2702 }
2703
2704 static int mmc_power_on(struct mmc *mmc)
2705 {
2706 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2707         if (mmc->vmmc_supply) {
2708                 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2709
2710                 if (ret) {
2711                         puts("Error enabling VMMC supply\n");
2712                         return ret;
2713                 }
2714         }
2715 #endif
2716         return 0;
2717 }
2718
2719 static int mmc_power_off(struct mmc *mmc)
2720 {
2721         mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
2722 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2723         if (mmc->vmmc_supply) {
2724                 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2725
2726                 if (ret) {
2727                         pr_debug("Error disabling VMMC supply\n");
2728                         return ret;
2729                 }
2730         }
2731 #endif
2732         return 0;
2733 }
2734
2735 static int mmc_power_cycle(struct mmc *mmc)
2736 {
2737         int ret;
2738
2739         ret = mmc_power_off(mmc);
2740         if (ret)
2741                 return ret;
2742
2743         ret = mmc_host_power_cycle(mmc);
2744         if (ret)
2745                 return ret;
2746
2747         /*
2748          * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2749          * to be on the safer side.
2750          */
2751         udelay(2000);
2752         return mmc_power_on(mmc);
2753 }
2754
2755 int mmc_get_op_cond(struct mmc *mmc)
2756 {
2757         bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2758         int err;
2759
2760         if (mmc->has_init)
2761                 return 0;
2762
2763 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2764         mmc_adapter_card_type_ident();
2765 #endif
2766         err = mmc_power_init(mmc);
2767         if (err)
2768                 return err;
2769
2770 #ifdef CONFIG_MMC_QUIRKS
2771         mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2772                       MMC_QUIRK_RETRY_SEND_CID |
2773                       MMC_QUIRK_RETRY_APP_CMD;
2774 #endif
2775
2776         err = mmc_power_cycle(mmc);
2777         if (err) {
2778                 /*
2779                  * if power cycling is not supported, we should not try
2780                  * to use the UHS modes, because we wouldn't be able to
2781                  * recover from an error during the UHS initialization.
2782                  */
2783                 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2784                 uhs_en = false;
2785                 mmc->host_caps &= ~UHS_CAPS;
2786                 err = mmc_power_on(mmc);
2787         }
2788         if (err)
2789                 return err;
2790
2791 #if CONFIG_IS_ENABLED(DM_MMC)
2792         /* The device has already been probed ready for use */
2793 #else
2794         /* made sure it's not NULL earlier */
2795         err = mmc->cfg->ops->init(mmc);
2796         if (err)
2797                 return err;
2798 #endif
2799         mmc->ddr_mode = 0;
2800
2801 retry:
2802         mmc_set_initial_state(mmc);
2803
2804         /* Reset the Card */
2805         err = mmc_go_idle(mmc);
2806
2807         if (err)
2808                 return err;
2809
2810         /* The internal partition reset to user partition(0) at every CMD0*/
2811         mmc_get_blk_desc(mmc)->hwpart = 0;
2812
2813         /* Test for SD version 2 */
2814         err = mmc_send_if_cond(mmc);
2815
2816         /* Now try to get the SD card's operating condition */
2817         err = sd_send_op_cond(mmc, uhs_en);
2818         if (err && uhs_en) {
2819                 uhs_en = false;
2820                 mmc_power_cycle(mmc);
2821                 goto retry;
2822         }
2823
2824         /* If the command timed out, we check for an MMC card */
2825         if (err == -ETIMEDOUT) {
2826                 err = mmc_send_op_cond(mmc);
2827
2828                 if (err) {
2829 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2830                         pr_err("Card did not respond to voltage select!\n");
2831 #endif
2832                         return -EOPNOTSUPP;
2833                 }
2834         }
2835
2836         return err;
2837 }
2838
2839 int mmc_start_init(struct mmc *mmc)
2840 {
2841         bool no_card;
2842         int err = 0;
2843
2844         /*
2845          * all hosts are capable of 1 bit bus-width and able to use the legacy
2846          * timings.
2847          */
2848         mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2849                          MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2850
2851 #if !defined(CONFIG_MMC_BROKEN_CD)
2852         no_card = mmc_getcd(mmc) == 0;
2853 #else
2854         no_card = 0;
2855 #endif
2856 #if !CONFIG_IS_ENABLED(DM_MMC)
2857         /* we pretend there's no card when init is NULL */
2858         no_card = no_card || (mmc->cfg->ops->init == NULL);
2859 #endif
2860         if (no_card) {
2861                 mmc->has_init = 0;
2862 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2863                 pr_err("MMC: no card present\n");
2864 #endif
2865                 return -ENOMEDIUM;
2866         }
2867
2868         err = mmc_get_op_cond(mmc);
2869
2870         if (!err)
2871                 mmc->init_in_progress = 1;
2872
2873         return err;
2874 }
2875
2876 static int mmc_complete_init(struct mmc *mmc)
2877 {
2878         int err = 0;
2879
2880         mmc->init_in_progress = 0;
2881         if (mmc->op_cond_pending)
2882                 err = mmc_complete_op_cond(mmc);
2883
2884         if (!err)
2885                 err = mmc_startup(mmc);
2886         if (err)
2887                 mmc->has_init = 0;
2888         else
2889                 mmc->has_init = 1;
2890         return err;
2891 }
2892
2893 int mmc_init(struct mmc *mmc)
2894 {
2895         int err = 0;
2896         __maybe_unused ulong start;
2897 #if CONFIG_IS_ENABLED(DM_MMC)
2898         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2899
2900         upriv->mmc = mmc;
2901 #endif
2902         if (mmc->has_init)
2903                 return 0;
2904
2905         start = get_timer(0);
2906
2907         if (!mmc->init_in_progress)
2908                 err = mmc_start_init(mmc);
2909
2910         if (!err)
2911                 err = mmc_complete_init(mmc);
2912         if (err)
2913                 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2914
2915         return err;
2916 }
2917
2918 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2919     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2920     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2921 int mmc_deinit(struct mmc *mmc)
2922 {
2923         u32 caps_filtered;
2924
2925         if (!mmc->has_init)
2926                 return 0;
2927
2928         if (IS_SD(mmc)) {
2929                 caps_filtered = mmc->card_caps &
2930                         ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2931                           MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2932                           MMC_CAP(UHS_SDR104));
2933
2934                 return sd_select_mode_and_width(mmc, caps_filtered);
2935         } else {
2936                 caps_filtered = mmc->card_caps &
2937                         ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2938
2939                 return mmc_select_mode_and_width(mmc, caps_filtered);
2940         }
2941 }
2942 #endif
2943
2944 int mmc_set_dsr(struct mmc *mmc, u16 val)
2945 {
2946         mmc->dsr = val;
2947         return 0;
2948 }
2949
2950 /* CPU-specific MMC initializations */
2951 __weak int cpu_mmc_init(bd_t *bis)
2952 {
2953         return -1;
2954 }
2955
2956 /* board-specific MMC initializations. */
2957 __weak int board_mmc_init(bd_t *bis)
2958 {
2959         return -1;
2960 }
2961
2962 void mmc_set_preinit(struct mmc *mmc, int preinit)
2963 {
2964         mmc->preinit = preinit;
2965 }
2966
2967 #if CONFIG_IS_ENABLED(DM_MMC)
2968 static int mmc_probe(bd_t *bis)
2969 {
2970         int ret, i;
2971         struct uclass *uc;
2972         struct udevice *dev;
2973
2974         ret = uclass_get(UCLASS_MMC, &uc);
2975         if (ret)
2976                 return ret;
2977
2978         /*
2979          * Try to add them in sequence order. Really with driver model we
2980          * should allow holes, but the current MMC list does not allow that.
2981          * So if we request 0, 1, 3 we will get 0, 1, 2.
2982          */
2983         for (i = 0; ; i++) {
2984                 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2985                 if (ret == -ENODEV)
2986                         break;
2987         }
2988         uclass_foreach_dev(dev, uc) {
2989                 ret = device_probe(dev);
2990                 if (ret)
2991                         pr_err("%s - probe failed: %d\n", dev->name, ret);
2992         }
2993
2994         return 0;
2995 }
2996 #else
2997 static int mmc_probe(bd_t *bis)
2998 {
2999         if (board_mmc_init(bis) < 0)
3000                 cpu_mmc_init(bis);
3001
3002         return 0;
3003 }
3004 #endif
3005
3006 int mmc_initialize(bd_t *bis)
3007 {
3008         static int initialized = 0;
3009         int ret;
3010         if (initialized)        /* Avoid initializing mmc multiple times */
3011                 return 0;
3012         initialized = 1;
3013
3014 #if !CONFIG_IS_ENABLED(BLK)
3015 #if !CONFIG_IS_ENABLED(MMC_TINY)
3016         mmc_list_init();
3017 #endif
3018 #endif
3019         ret = mmc_probe(bis);
3020         if (ret)
3021                 return ret;
3022
3023 #ifndef CONFIG_SPL_BUILD
3024         print_mmc_devices(',');
3025 #endif
3026
3027         mmc_do_preinit();
3028         return 0;
3029 }
3030
3031 #if CONFIG_IS_ENABLED(DM_MMC)
3032 int mmc_init_device(int num)
3033 {
3034         struct udevice *dev;
3035         struct mmc *m;
3036         int ret;
3037
3038         ret = uclass_get_device(UCLASS_MMC, num, &dev);
3039         if (ret)
3040                 return ret;
3041
3042         m = mmc_get_mmc_dev(dev);
3043         if (!m)
3044                 return 0;
3045 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
3046         mmc_set_preinit(m, 1);
3047 #endif
3048         if (m->preinit)
3049                 mmc_start_init(m);
3050
3051         return 0;
3052 }
3053 #endif
3054
3055 #ifdef CONFIG_CMD_BKOPS_ENABLE
3056 int mmc_set_bkops_enable(struct mmc *mmc)
3057 {
3058         int err;
3059         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3060
3061         err = mmc_send_ext_csd(mmc, ext_csd);
3062         if (err) {
3063                 puts("Could not get ext_csd register values\n");
3064                 return err;
3065         }
3066
3067         if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3068                 puts("Background operations not supported on device\n");
3069                 return -EMEDIUMTYPE;
3070         }
3071
3072         if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
3073                 puts("Background operations already enabled\n");
3074                 return 0;
3075         }
3076
3077         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
3078         if (err) {
3079                 puts("Failed to enable manual background operations\n");
3080                 return err;
3081         }
3082
3083         puts("Enabled manual background operations\n");
3084
3085         return 0;
3086 }
3087 #endif