2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
33 #if CONFIG_IS_ENABLED(MMC_TINY)
34 static struct mmc mmc_static;
35 struct mmc *find_mmc_device(int dev_num)
40 void mmc_do_preinit(void)
42 struct mmc *m = &mmc_static;
43 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m, 1);
50 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
52 return &mmc->block_dev;
56 #if !CONFIG_IS_ENABLED(DM_MMC)
57 __weak int board_mmc_getwp(struct mmc *mmc)
62 int mmc_getwp(struct mmc *mmc)
66 wp = board_mmc_getwp(mmc);
69 if (mmc->cfg->ops->getwp)
70 wp = mmc->cfg->ops->getwp(mmc);
78 __weak int board_mmc_getcd(struct mmc *mmc)
84 #ifdef CONFIG_MMC_TRACE
85 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
87 printf("CMD_SEND:%d\n", cmd->cmdidx);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
91 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
97 printf("\t\tRET\t\t\t %d\n", ret);
99 switch (cmd->resp_type) {
101 printf("\t\tMMC_RSP_NONE\n");
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
114 printf("\t\t \t\t 0x%08X \n",
116 printf("\t\t \t\t 0x%08X \n",
118 printf("\t\t \t\t 0x%08X \n",
121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i = 0; i < 4; i++) {
124 printf("\t\t\t\t\t%03d - ", i*4);
125 ptr = (u8 *)&cmd->response[i];
127 for (j = 0; j < 4; j++)
128 printf("%02X ", *ptr--);
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
137 printf("\t\tERROR MMC rsp not supported\n");
143 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
147 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
148 printf("CURR STATE:%d\n", status);
152 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
153 const char *mmc_mode_name(enum bus_mode mode)
155 static const char *const names[] = {
156 [MMC_LEGACY] = "MMC legacy",
157 [SD_LEGACY] = "SD Legacy",
158 [MMC_HS] = "MMC High Speed (26MHz)",
159 [SD_HS] = "SD High Speed (50MHz)",
160 [UHS_SDR12] = "UHS SDR12 (25MHz)",
161 [UHS_SDR25] = "UHS SDR25 (50MHz)",
162 [UHS_SDR50] = "UHS SDR50 (100MHz)",
163 [UHS_SDR104] = "UHS SDR104 (208MHz)",
164 [UHS_DDR50] = "UHS DDR50 (50MHz)",
165 [MMC_HS_52] = "MMC High Speed (52MHz)",
166 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
167 [MMC_HS_200] = "HS200 (200MHz)",
170 if (mode >= MMC_MODES_END)
171 return "Unknown mode";
177 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
179 static const int freqs[] = {
180 [SD_LEGACY] = 25000000,
183 [UHS_SDR12] = 25000000,
184 [UHS_SDR25] = 50000000,
185 [UHS_SDR50] = 100000000,
186 [UHS_SDR104] = 208000000,
187 [UHS_DDR50] = 50000000,
188 [MMC_HS_52] = 52000000,
189 [MMC_DDR_52] = 52000000,
190 [MMC_HS_200] = 200000000,
193 if (mode == MMC_LEGACY)
194 return mmc->legacy_speed;
195 else if (mode >= MMC_MODES_END)
201 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
203 mmc->selected_mode = mode;
204 mmc->tran_speed = mmc_mode2freq(mmc, mode);
205 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
206 mmc->tran_speed / 1000000);
210 #if !CONFIG_IS_ENABLED(DM_MMC)
211 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
215 mmmc_trace_before_send(mmc, cmd);
216 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
217 mmmc_trace_after_send(mmc, cmd, ret);
223 int mmc_send_status(struct mmc *mmc, int timeout)
226 int err, retries = 5;
228 cmd.cmdidx = MMC_CMD_SEND_STATUS;
229 cmd.resp_type = MMC_RSP_R1;
230 if (!mmc_host_is_spi(mmc))
231 cmd.cmdarg = mmc->rca << 16;
234 err = mmc_send_cmd(mmc, &cmd, NULL);
236 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
237 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
241 if (cmd.response[0] & MMC_STATUS_MASK) {
242 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
243 printf("Status Error: 0x%08X\n",
248 } else if (--retries < 0)
257 mmc_trace_state(mmc, &cmd);
259 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
260 printf("Timeout waiting card ready\n");
268 int mmc_set_blocklen(struct mmc *mmc, int len)
275 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
276 cmd.resp_type = MMC_RSP_R1;
279 return mmc_send_cmd(mmc, &cmd, NULL);
282 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
286 struct mmc_data data;
289 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
291 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
293 if (mmc->high_capacity)
296 cmd.cmdarg = start * mmc->read_bl_len;
298 cmd.resp_type = MMC_RSP_R1;
301 data.blocks = blkcnt;
302 data.blocksize = mmc->read_bl_len;
303 data.flags = MMC_DATA_READ;
305 if (mmc_send_cmd(mmc, &cmd, &data))
309 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
311 cmd.resp_type = MMC_RSP_R1b;
312 if (mmc_send_cmd(mmc, &cmd, NULL)) {
313 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
314 printf("mmc fail to send stop cmd\n");
323 #if CONFIG_IS_ENABLED(BLK)
324 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
326 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
330 #if CONFIG_IS_ENABLED(BLK)
331 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
333 int dev_num = block_dev->devnum;
335 lbaint_t cur, blocks_todo = blkcnt;
340 struct mmc *mmc = find_mmc_device(dev_num);
344 if (CONFIG_IS_ENABLED(MMC_TINY))
345 err = mmc_switch_part(mmc, block_dev->hwpart);
347 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
352 if ((start + blkcnt) > block_dev->lba) {
353 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
354 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
355 start + blkcnt, block_dev->lba);
360 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
361 debug("%s: Failed to set blocklen\n", __func__);
366 cur = (blocks_todo > mmc->cfg->b_max) ?
367 mmc->cfg->b_max : blocks_todo;
368 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
369 debug("%s: Failed to read blocks\n", __func__);
374 dst += cur * mmc->read_bl_len;
375 } while (blocks_todo > 0);
380 static int mmc_go_idle(struct mmc *mmc)
387 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
389 cmd.resp_type = MMC_RSP_NONE;
391 err = mmc_send_cmd(mmc, &cmd, NULL);
401 static int sd_send_op_cond(struct mmc *mmc)
408 cmd.cmdidx = MMC_CMD_APP_CMD;
409 cmd.resp_type = MMC_RSP_R1;
412 err = mmc_send_cmd(mmc, &cmd, NULL);
417 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
418 cmd.resp_type = MMC_RSP_R3;
421 * Most cards do not answer if some reserved bits
422 * in the ocr are set. However, Some controller
423 * can set bit 7 (reserved for low voltages), but
424 * how to manage low voltages SD card is not yet
427 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
428 (mmc->cfg->voltages & 0xff8000);
430 if (mmc->version == SD_VERSION_2)
431 cmd.cmdarg |= OCR_HCS;
433 err = mmc_send_cmd(mmc, &cmd, NULL);
438 if (cmd.response[0] & OCR_BUSY)
447 if (mmc->version != SD_VERSION_2)
448 mmc->version = SD_VERSION_1_0;
450 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
451 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
452 cmd.resp_type = MMC_RSP_R3;
455 err = mmc_send_cmd(mmc, &cmd, NULL);
461 mmc->ocr = cmd.response[0];
463 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
469 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
474 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
475 cmd.resp_type = MMC_RSP_R3;
477 if (use_arg && !mmc_host_is_spi(mmc))
478 cmd.cmdarg = OCR_HCS |
479 (mmc->cfg->voltages &
480 (mmc->ocr & OCR_VOLTAGE_MASK)) |
481 (mmc->ocr & OCR_ACCESS_MODE);
483 err = mmc_send_cmd(mmc, &cmd, NULL);
486 mmc->ocr = cmd.response[0];
490 static int mmc_send_op_cond(struct mmc *mmc)
494 /* Some cards seem to need this */
497 /* Asking to the card its capabilities */
498 for (i = 0; i < 2; i++) {
499 err = mmc_send_op_cond_iter(mmc, i != 0);
503 /* exit if not busy (flag seems to be inverted) */
504 if (mmc->ocr & OCR_BUSY)
507 mmc->op_cond_pending = 1;
511 static int mmc_complete_op_cond(struct mmc *mmc)
518 mmc->op_cond_pending = 0;
519 if (!(mmc->ocr & OCR_BUSY)) {
520 /* Some cards seem to need this */
523 start = get_timer(0);
525 err = mmc_send_op_cond_iter(mmc, 1);
528 if (mmc->ocr & OCR_BUSY)
530 if (get_timer(start) > timeout)
536 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
537 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
538 cmd.resp_type = MMC_RSP_R3;
541 err = mmc_send_cmd(mmc, &cmd, NULL);
546 mmc->ocr = cmd.response[0];
549 mmc->version = MMC_VERSION_UNKNOWN;
551 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
558 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
561 struct mmc_data data;
564 /* Get the Card Status Register */
565 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
566 cmd.resp_type = MMC_RSP_R1;
569 data.dest = (char *)ext_csd;
571 data.blocksize = MMC_MAX_BLOCK_LEN;
572 data.flags = MMC_DATA_READ;
574 err = mmc_send_cmd(mmc, &cmd, &data);
579 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
586 cmd.cmdidx = MMC_CMD_SWITCH;
587 cmd.resp_type = MMC_RSP_R1b;
588 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
592 while (retries > 0) {
593 ret = mmc_send_cmd(mmc, &cmd, NULL);
595 /* Waiting for the ready status */
597 ret = mmc_send_status(mmc, timeout);
608 static int mmc_change_freq(struct mmc *mmc)
610 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
614 mmc->card_caps = MMC_MODE_1BIT;
616 if (mmc_host_is_spi(mmc))
619 /* Only version 4 supports high-speed */
620 if (mmc->version < MMC_VERSION_4)
623 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
625 err = mmc_send_ext_csd(mmc, ext_csd);
630 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
632 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
637 /* Now check to see that it worked */
638 err = mmc_send_ext_csd(mmc, ext_csd);
643 /* No high-speed support */
644 if (!ext_csd[EXT_CSD_HS_TIMING])
647 /* High Speed is set, there are two types: 52MHz and 26MHz */
648 if (cardtype & EXT_CSD_CARD_TYPE_52) {
649 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
650 mmc->card_caps |= MMC_MODE_DDR_52MHz;
651 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
653 mmc->card_caps |= MMC_MODE_HS;
659 static int mmc_set_capacity(struct mmc *mmc, int part_num)
663 mmc->capacity = mmc->capacity_user;
667 mmc->capacity = mmc->capacity_boot;
670 mmc->capacity = mmc->capacity_rpmb;
676 mmc->capacity = mmc->capacity_gp[part_num - 4];
682 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
687 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
691 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
692 (mmc->part_config & ~PART_ACCESS_MASK)
693 | (part_num & PART_ACCESS_MASK));
696 * Set the capacity if the switch succeeded or was intended
697 * to return to representing the raw device.
699 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
700 ret = mmc_set_capacity(mmc, part_num);
701 mmc_get_blk_desc(mmc)->hwpart = part_num;
707 int mmc_hwpart_config(struct mmc *mmc,
708 const struct mmc_hwpart_conf *conf,
709 enum mmc_hwpart_conf_mode mode)
715 u32 max_enh_size_mult;
716 u32 tot_enh_size_mult = 0;
719 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
721 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
724 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
725 printf("eMMC >= 4.4 required for enhanced user data area\n");
729 if (!(mmc->part_support & PART_SUPPORT)) {
730 printf("Card does not support partitioning\n");
734 if (!mmc->hc_wp_grp_size) {
735 printf("Card does not define HC WP group size\n");
739 /* check partition alignment and total enhanced size */
740 if (conf->user.enh_size) {
741 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
742 conf->user.enh_start % mmc->hc_wp_grp_size) {
743 printf("User data enhanced area not HC WP group "
747 part_attrs |= EXT_CSD_ENH_USR;
748 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
749 if (mmc->high_capacity) {
750 enh_start_addr = conf->user.enh_start;
752 enh_start_addr = (conf->user.enh_start << 9);
758 tot_enh_size_mult += enh_size_mult;
760 for (pidx = 0; pidx < 4; pidx++) {
761 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
762 printf("GP%i partition not HC WP group size "
763 "aligned\n", pidx+1);
766 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
767 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
768 part_attrs |= EXT_CSD_ENH_GP(pidx);
769 tot_enh_size_mult += gp_size_mult[pidx];
773 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
774 printf("Card does not support enhanced attribute\n");
778 err = mmc_send_ext_csd(mmc, ext_csd);
783 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
784 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
785 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
786 if (tot_enh_size_mult > max_enh_size_mult) {
787 printf("Total enhanced size exceeds maximum (%u > %u)\n",
788 tot_enh_size_mult, max_enh_size_mult);
792 /* The default value of EXT_CSD_WR_REL_SET is device
793 * dependent, the values can only be changed if the
794 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
795 * changed only once and before partitioning is completed. */
796 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
797 if (conf->user.wr_rel_change) {
798 if (conf->user.wr_rel_set)
799 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
801 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
803 for (pidx = 0; pidx < 4; pidx++) {
804 if (conf->gp_part[pidx].wr_rel_change) {
805 if (conf->gp_part[pidx].wr_rel_set)
806 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
808 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
812 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
813 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
814 puts("Card does not support host controlled partition write "
815 "reliability settings\n");
819 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
820 EXT_CSD_PARTITION_SETTING_COMPLETED) {
821 printf("Card already partitioned\n");
825 if (mode == MMC_HWPART_CONF_CHECK)
828 /* Partitioning requires high-capacity size definitions */
829 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
830 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
831 EXT_CSD_ERASE_GROUP_DEF, 1);
836 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
838 /* update erase group size to be high-capacity */
839 mmc->erase_grp_size =
840 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
844 /* all OK, write the configuration */
845 for (i = 0; i < 4; i++) {
846 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
847 EXT_CSD_ENH_START_ADDR+i,
848 (enh_start_addr >> (i*8)) & 0xFF);
852 for (i = 0; i < 3; i++) {
853 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
854 EXT_CSD_ENH_SIZE_MULT+i,
855 (enh_size_mult >> (i*8)) & 0xFF);
859 for (pidx = 0; pidx < 4; pidx++) {
860 for (i = 0; i < 3; i++) {
861 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
862 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
863 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
868 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
869 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
873 if (mode == MMC_HWPART_CONF_SET)
876 /* The WR_REL_SET is a write-once register but shall be
877 * written before setting PART_SETTING_COMPLETED. As it is
878 * write-once we can only write it when completing the
880 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
881 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
882 EXT_CSD_WR_REL_SET, wr_rel_set);
887 /* Setting PART_SETTING_COMPLETED confirms the partition
888 * configuration but it only becomes effective after power
889 * cycle, so we do not adjust the partition related settings
890 * in the mmc struct. */
892 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
893 EXT_CSD_PARTITION_SETTING,
894 EXT_CSD_PARTITION_SETTING_COMPLETED);
901 #if !CONFIG_IS_ENABLED(DM_MMC)
902 int mmc_getcd(struct mmc *mmc)
906 cd = board_mmc_getcd(mmc);
909 if (mmc->cfg->ops->getcd)
910 cd = mmc->cfg->ops->getcd(mmc);
919 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
922 struct mmc_data data;
924 /* Switch the frequency */
925 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
926 cmd.resp_type = MMC_RSP_R1;
927 cmd.cmdarg = (mode << 31) | 0xffffff;
928 cmd.cmdarg &= ~(0xf << (group * 4));
929 cmd.cmdarg |= value << (group * 4);
931 data.dest = (char *)resp;
934 data.flags = MMC_DATA_READ;
936 return mmc_send_cmd(mmc, &cmd, &data);
940 static int sd_get_capabilities(struct mmc *mmc)
944 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
945 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
946 struct mmc_data data;
949 mmc->card_caps = MMC_MODE_1BIT;
951 if (mmc_host_is_spi(mmc))
954 /* Read the SCR to find out if this card supports higher speeds */
955 cmd.cmdidx = MMC_CMD_APP_CMD;
956 cmd.resp_type = MMC_RSP_R1;
957 cmd.cmdarg = mmc->rca << 16;
959 err = mmc_send_cmd(mmc, &cmd, NULL);
964 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
965 cmd.resp_type = MMC_RSP_R1;
971 data.dest = (char *)scr;
974 data.flags = MMC_DATA_READ;
976 err = mmc_send_cmd(mmc, &cmd, &data);
985 mmc->scr[0] = __be32_to_cpu(scr[0]);
986 mmc->scr[1] = __be32_to_cpu(scr[1]);
988 switch ((mmc->scr[0] >> 24) & 0xf) {
990 mmc->version = SD_VERSION_1_0;
993 mmc->version = SD_VERSION_1_10;
996 mmc->version = SD_VERSION_2;
997 if ((mmc->scr[0] >> 15) & 0x1)
998 mmc->version = SD_VERSION_3;
1001 mmc->version = SD_VERSION_1_0;
1005 if (mmc->scr[0] & SD_DATA_4BIT)
1006 mmc->card_caps |= MMC_MODE_4BIT;
1008 /* Version 1.0 doesn't support switching */
1009 if (mmc->version == SD_VERSION_1_0)
1014 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1015 (u8 *)switch_status);
1020 /* The high-speed function is busy. Try again */
1021 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1025 /* If high-speed isn't supported, we return */
1026 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1027 mmc->card_caps |= MMC_CAP(SD_HS);
1032 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1036 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1038 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
1042 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) != 0x01000000)
1048 int sd_select_bus_width(struct mmc *mmc, int w)
1053 if ((w != 4) && (w != 1))
1056 cmd.cmdidx = MMC_CMD_APP_CMD;
1057 cmd.resp_type = MMC_RSP_R1;
1058 cmd.cmdarg = mmc->rca << 16;
1060 err = mmc_send_cmd(mmc, &cmd, NULL);
1064 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1065 cmd.resp_type = MMC_RSP_R1;
1070 err = mmc_send_cmd(mmc, &cmd, NULL);
1077 static int sd_read_ssr(struct mmc *mmc)
1081 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1082 struct mmc_data data;
1084 unsigned int au, eo, et, es;
1086 cmd.cmdidx = MMC_CMD_APP_CMD;
1087 cmd.resp_type = MMC_RSP_R1;
1088 cmd.cmdarg = mmc->rca << 16;
1090 err = mmc_send_cmd(mmc, &cmd, NULL);
1094 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1095 cmd.resp_type = MMC_RSP_R1;
1099 data.dest = (char *)ssr;
1100 data.blocksize = 64;
1102 data.flags = MMC_DATA_READ;
1104 err = mmc_send_cmd(mmc, &cmd, &data);
1112 for (i = 0; i < 16; i++)
1113 ssr[i] = be32_to_cpu(ssr[i]);
1115 au = (ssr[2] >> 12) & 0xF;
1116 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1117 mmc->ssr.au = sd_au_size[au];
1118 es = (ssr[3] >> 24) & 0xFF;
1119 es |= (ssr[2] & 0xFF) << 8;
1120 et = (ssr[3] >> 18) & 0x3F;
1122 eo = (ssr[3] >> 16) & 0x3;
1123 mmc->ssr.erase_timeout = (et * 1000) / es;
1124 mmc->ssr.erase_offset = eo * 1000;
1127 debug("Invalid Allocation Unit Size.\n");
1133 /* frequency bases */
1134 /* divided by 10 to be nice to platforms without floating point */
1135 static const int fbase[] = {
1142 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1143 * to platforms without floating point.
1145 static const u8 multipliers[] = {
1164 static inline int bus_width(uint cap)
1166 if (cap == MMC_MODE_8BIT)
1168 if (cap == MMC_MODE_4BIT)
1170 if (cap == MMC_MODE_1BIT)
1172 printf("invalid bus witdh capability 0x%x\n", cap);
1176 #if !CONFIG_IS_ENABLED(DM_MMC)
1177 static void mmc_set_ios(struct mmc *mmc)
1179 if (mmc->cfg->ops->set_ios)
1180 mmc->cfg->ops->set_ios(mmc);
1184 void mmc_set_clock(struct mmc *mmc, uint clock)
1186 if (clock > mmc->cfg->f_max)
1187 clock = mmc->cfg->f_max;
1189 if (clock < mmc->cfg->f_min)
1190 clock = mmc->cfg->f_min;
1197 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1199 mmc->bus_width = width;
1204 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1206 * helper function to display the capabilities in a human
1207 * friendly manner. The capabilities include bus width and
1210 void mmc_dump_capabilities(const char *text, uint caps)
1214 printf("%s: widths [", text);
1215 if (caps & MMC_MODE_8BIT)
1217 if (caps & MMC_MODE_4BIT)
1219 if (caps & MMC_MODE_1BIT)
1221 printf("\b\b] modes [");
1222 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1223 if (MMC_CAP(mode) & caps)
1224 printf("%s, ", mmc_mode_name(mode));
1229 struct mode_width_tuning {
1234 static const struct mode_width_tuning sd_modes_by_pref[] = {
1237 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1241 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1245 #define for_each_sd_mode_by_pref(caps, mwt) \
1246 for (mwt = sd_modes_by_pref;\
1247 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1249 if (caps & MMC_CAP(mwt->mode))
1251 static int sd_select_mode_and_width(struct mmc *mmc)
1254 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1255 const struct mode_width_tuning *mwt;
1257 err = sd_get_capabilities(mmc);
1260 /* Restrict card's capabilities by what the host can do */
1261 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1263 for_each_sd_mode_by_pref(mmc->card_caps, mwt) {
1266 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1267 if (*w & mmc->card_caps & mwt->widths) {
1268 debug("trying mode %s width %d (at %d MHz)\n",
1269 mmc_mode_name(mwt->mode),
1271 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1273 /* configure the bus width (card + host) */
1274 err = sd_select_bus_width(mmc, bus_width(*w));
1277 mmc_set_bus_width(mmc, bus_width(*w));
1279 /* configure the bus mode (card) */
1280 err = sd_set_card_speed(mmc, mwt->mode);
1284 /* configure the bus mode (host) */
1285 mmc_select_mode(mmc, mwt->mode);
1286 mmc_set_clock(mmc, mmc->tran_speed);
1288 err = sd_read_ssr(mmc);
1292 printf("bad ssr\n");
1295 /* revert to a safer bus speed */
1296 mmc_select_mode(mmc, SD_LEGACY);
1297 mmc_set_clock(mmc, mmc->tran_speed);
1302 printf("unable to select a mode\n");
1307 * read the compare the part of ext csd that is constant.
1308 * This can be used to check that the transfer is working
1311 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1314 const u8 *ext_csd = mmc->ext_csd;
1315 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1317 err = mmc_send_ext_csd(mmc, test_csd);
1321 /* Only compare read only fields */
1322 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1323 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1324 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1325 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1326 ext_csd[EXT_CSD_REV]
1327 == test_csd[EXT_CSD_REV] &&
1328 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1329 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1330 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1331 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1337 static int mmc_select_bus_freq_width(struct mmc *mmc)
1339 /* An array of possible bus widths in order of preference */
1340 static const unsigned int ext_csd_bits[] = {
1341 EXT_CSD_DDR_BUS_WIDTH_8,
1342 EXT_CSD_DDR_BUS_WIDTH_4,
1343 EXT_CSD_BUS_WIDTH_8,
1344 EXT_CSD_BUS_WIDTH_4,
1345 EXT_CSD_BUS_WIDTH_1,
1347 /* An array to map CSD bus widths to host cap bits */
1348 static const unsigned int ext_to_hostcaps[] = {
1349 [EXT_CSD_DDR_BUS_WIDTH_4] =
1350 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1351 [EXT_CSD_DDR_BUS_WIDTH_8] =
1352 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1353 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1354 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1356 /* An array to map chosen bus width to an integer */
1357 static const unsigned int widths[] = {
1363 err = mmc_change_freq(mmc);
1367 /* Restrict card's capabilities by what the host can do */
1368 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1370 /* Only version 4 of MMC supports wider bus widths */
1371 if (mmc->version < MMC_VERSION_4)
1374 if (!mmc->ext_csd) {
1375 debug("No ext_csd found!\n"); /* this should enver happen */
1379 for (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1380 unsigned int extw = ext_csd_bits[idx];
1381 unsigned int caps = ext_to_hostcaps[extw];
1383 * If the bus width is still not changed,
1384 * don't try to set the default again.
1385 * Otherwise, recover from switch attempts
1386 * by switching to 1-bit bus width.
1388 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1389 mmc->bus_width == 1) {
1395 * Check to make sure the card and controller support
1396 * these capabilities
1398 if ((mmc->card_caps & caps) != caps)
1401 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1402 EXT_CSD_BUS_WIDTH, extw);
1407 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1408 mmc_set_bus_width(mmc, widths[idx]);
1410 err = mmc_read_and_compare_ext_csd(mmc);
1418 if (mmc->card_caps & MMC_MODE_HS_52MHz) {
1420 mmc_select_mode(mmc, MMC_DDR_52);
1422 mmc_select_mode(mmc, MMC_HS_52);
1423 } else if (mmc->card_caps & MMC_MODE_HS)
1424 mmc_select_mode(mmc, MMC_HS);
1429 static int mmc_startup_v4(struct mmc *mmc)
1433 bool has_parts = false;
1434 bool part_completed;
1437 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1440 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1444 mmc->ext_csd = ext_csd;
1446 /* check ext_csd version and capacity */
1447 err = mmc_send_ext_csd(mmc, ext_csd);
1450 if (ext_csd[EXT_CSD_REV] >= 2) {
1452 * According to the JEDEC Standard, the value of
1453 * ext_csd's capacity is valid if the value is more
1456 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1457 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1458 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1459 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1460 capacity *= MMC_MAX_BLOCK_LEN;
1461 if ((capacity >> 20) > 2 * 1024)
1462 mmc->capacity_user = capacity;
1465 switch (ext_csd[EXT_CSD_REV]) {
1467 mmc->version = MMC_VERSION_4_1;
1470 mmc->version = MMC_VERSION_4_2;
1473 mmc->version = MMC_VERSION_4_3;
1476 mmc->version = MMC_VERSION_4_41;
1479 mmc->version = MMC_VERSION_4_5;
1482 mmc->version = MMC_VERSION_5_0;
1485 mmc->version = MMC_VERSION_5_1;
1489 /* The partition data may be non-zero but it is only
1490 * effective if PARTITION_SETTING_COMPLETED is set in
1491 * EXT_CSD, so ignore any data if this bit is not set,
1492 * except for enabling the high-capacity group size
1493 * definition (see below).
1495 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1496 EXT_CSD_PARTITION_SETTING_COMPLETED);
1498 /* store the partition info of emmc */
1499 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1500 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1501 ext_csd[EXT_CSD_BOOT_MULT])
1502 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1503 if (part_completed &&
1504 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1505 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1507 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1509 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1511 for (i = 0; i < 4; i++) {
1512 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1513 uint mult = (ext_csd[idx + 2] << 16) +
1514 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1517 if (!part_completed)
1519 mmc->capacity_gp[i] = mult;
1520 mmc->capacity_gp[i] *=
1521 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1522 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1523 mmc->capacity_gp[i] <<= 19;
1526 if (part_completed) {
1527 mmc->enh_user_size =
1528 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1529 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1530 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1531 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1532 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1533 mmc->enh_user_size <<= 19;
1534 mmc->enh_user_start =
1535 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1536 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1537 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1538 ext_csd[EXT_CSD_ENH_START_ADDR];
1539 if (mmc->high_capacity)
1540 mmc->enh_user_start <<= 9;
1544 * Host needs to enable ERASE_GRP_DEF bit if device is
1545 * partitioned. This bit will be lost every time after a reset
1546 * or power off. This will affect erase size.
1550 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1551 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1554 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1555 EXT_CSD_ERASE_GROUP_DEF, 1);
1560 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1563 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1564 /* Read out group size from ext_csd */
1565 mmc->erase_grp_size =
1566 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1568 * if high capacity and partition setting completed
1569 * SEC_COUNT is valid even if it is smaller than 2 GiB
1570 * JEDEC Standard JESD84-B45, 6.2.4
1572 if (mmc->high_capacity && part_completed) {
1573 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1574 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1575 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1576 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1577 capacity *= MMC_MAX_BLOCK_LEN;
1578 mmc->capacity_user = capacity;
1581 /* Calculate the group size from the csd value. */
1582 int erase_gsz, erase_gmul;
1584 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1585 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1586 mmc->erase_grp_size = (erase_gsz + 1)
1590 mmc->hc_wp_grp_size = 1024
1591 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1592 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1594 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1599 static int mmc_startup(struct mmc *mmc)
1605 struct blk_desc *bdesc;
1607 #ifdef CONFIG_MMC_SPI_CRC_ON
1608 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1609 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1610 cmd.resp_type = MMC_RSP_R1;
1612 err = mmc_send_cmd(mmc, &cmd, NULL);
1619 /* Put the Card in Identify Mode */
1620 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1621 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1622 cmd.resp_type = MMC_RSP_R2;
1625 err = mmc_send_cmd(mmc, &cmd, NULL);
1630 memcpy(mmc->cid, cmd.response, 16);
1633 * For MMC cards, set the Relative Address.
1634 * For SD cards, get the Relatvie Address.
1635 * This also puts the cards into Standby State
1637 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1638 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1639 cmd.cmdarg = mmc->rca << 16;
1640 cmd.resp_type = MMC_RSP_R6;
1642 err = mmc_send_cmd(mmc, &cmd, NULL);
1648 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1651 /* Get the Card-Specific Data */
1652 cmd.cmdidx = MMC_CMD_SEND_CSD;
1653 cmd.resp_type = MMC_RSP_R2;
1654 cmd.cmdarg = mmc->rca << 16;
1656 err = mmc_send_cmd(mmc, &cmd, NULL);
1661 mmc->csd[0] = cmd.response[0];
1662 mmc->csd[1] = cmd.response[1];
1663 mmc->csd[2] = cmd.response[2];
1664 mmc->csd[3] = cmd.response[3];
1666 if (mmc->version == MMC_VERSION_UNKNOWN) {
1667 int version = (cmd.response[0] >> 26) & 0xf;
1671 mmc->version = MMC_VERSION_1_2;
1674 mmc->version = MMC_VERSION_1_4;
1677 mmc->version = MMC_VERSION_2_2;
1680 mmc->version = MMC_VERSION_3;
1683 mmc->version = MMC_VERSION_4;
1686 mmc->version = MMC_VERSION_1_2;
1691 /* divide frequency by 10, since the mults are 10x bigger */
1692 freq = fbase[(cmd.response[0] & 0x7)];
1693 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1695 mmc->legacy_speed = freq * mult;
1696 mmc_select_mode(mmc, MMC_LEGACY);
1698 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1699 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1702 mmc->write_bl_len = mmc->read_bl_len;
1704 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1706 if (mmc->high_capacity) {
1707 csize = (mmc->csd[1] & 0x3f) << 16
1708 | (mmc->csd[2] & 0xffff0000) >> 16;
1711 csize = (mmc->csd[1] & 0x3ff) << 2
1712 | (mmc->csd[2] & 0xc0000000) >> 30;
1713 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1716 mmc->capacity_user = (csize + 1) << (cmult + 2);
1717 mmc->capacity_user *= mmc->read_bl_len;
1718 mmc->capacity_boot = 0;
1719 mmc->capacity_rpmb = 0;
1720 for (i = 0; i < 4; i++)
1721 mmc->capacity_gp[i] = 0;
1723 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1724 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1726 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1727 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1729 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1730 cmd.cmdidx = MMC_CMD_SET_DSR;
1731 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1732 cmd.resp_type = MMC_RSP_NONE;
1733 if (mmc_send_cmd(mmc, &cmd, NULL))
1734 printf("MMC: SET_DSR failed\n");
1737 /* Select the card, and put it into Transfer Mode */
1738 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1739 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1740 cmd.resp_type = MMC_RSP_R1;
1741 cmd.cmdarg = mmc->rca << 16;
1742 err = mmc_send_cmd(mmc, &cmd, NULL);
1749 * For SD, its erase group is always one sector
1751 mmc->erase_grp_size = 1;
1752 mmc->part_config = MMCPART_NOAVAILABLE;
1754 err = mmc_startup_v4(mmc);
1758 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1763 err = sd_select_mode_and_width(mmc);
1765 err = mmc_select_bus_freq_width(mmc);
1771 /* Fix the block length for DDR mode */
1772 if (mmc->ddr_mode) {
1773 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1774 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1777 /* fill in device description */
1778 bdesc = mmc_get_blk_desc(mmc);
1782 bdesc->blksz = mmc->read_bl_len;
1783 bdesc->log2blksz = LOG2(bdesc->blksz);
1784 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1785 #if !defined(CONFIG_SPL_BUILD) || \
1786 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1787 !defined(CONFIG_USE_TINY_PRINTF))
1788 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1789 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1790 (mmc->cid[3] >> 16) & 0xffff);
1791 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1792 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1793 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1794 (mmc->cid[2] >> 24) & 0xff);
1795 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1796 (mmc->cid[2] >> 16) & 0xf);
1798 bdesc->vendor[0] = 0;
1799 bdesc->product[0] = 0;
1800 bdesc->revision[0] = 0;
1802 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1809 static int mmc_send_if_cond(struct mmc *mmc)
1814 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1815 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1816 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1817 cmd.resp_type = MMC_RSP_R7;
1819 err = mmc_send_cmd(mmc, &cmd, NULL);
1824 if ((cmd.response[0] & 0xff) != 0xaa)
1827 mmc->version = SD_VERSION_2;
1832 #if !CONFIG_IS_ENABLED(DM_MMC)
1833 /* board-specific MMC power initializations. */
1834 __weak void board_mmc_power_init(void)
1839 static int mmc_power_init(struct mmc *mmc)
1841 #if CONFIG_IS_ENABLED(DM_MMC)
1842 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1845 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
1848 debug("%s: No vmmc supply\n", mmc->dev->name);
1850 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
1851 &mmc->vqmmc_supply);
1853 debug("%s: No vqmmc supply\n", mmc->dev->name);
1855 if (mmc->vmmc_supply) {
1856 ret = regulator_set_enable(mmc->vmmc_supply, true);
1858 puts("Error enabling VMMC supply\n");
1863 #else /* !CONFIG_DM_MMC */
1865 * Driver model should use a regulator, as above, rather than calling
1866 * out to board code.
1868 board_mmc_power_init();
1873 int mmc_start_init(struct mmc *mmc)
1878 /* we pretend there's no card when init is NULL */
1879 no_card = mmc_getcd(mmc) == 0;
1880 #if !CONFIG_IS_ENABLED(DM_MMC)
1881 no_card = no_card || (mmc->cfg->ops->init == NULL);
1885 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1886 printf("MMC: no card present\n");
1894 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1895 mmc_adapter_card_type_ident();
1897 err = mmc_power_init(mmc);
1901 #if CONFIG_IS_ENABLED(DM_MMC)
1902 /* The device has already been probed ready for use */
1904 /* made sure it's not NULL earlier */
1905 err = mmc->cfg->ops->init(mmc);
1910 mmc_set_bus_width(mmc, 1);
1911 mmc_set_clock(mmc, 1);
1913 /* Reset the Card */
1914 err = mmc_go_idle(mmc);
1919 /* The internal partition reset to user partition(0) at every CMD0*/
1920 mmc_get_blk_desc(mmc)->hwpart = 0;
1922 /* Test for SD version 2 */
1923 err = mmc_send_if_cond(mmc);
1925 /* Now try to get the SD card's operating condition */
1926 err = sd_send_op_cond(mmc);
1928 /* If the command timed out, we check for an MMC card */
1929 if (err == -ETIMEDOUT) {
1930 err = mmc_send_op_cond(mmc);
1933 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1934 printf("Card did not respond to voltage select!\n");
1941 mmc->init_in_progress = 1;
1946 static int mmc_complete_init(struct mmc *mmc)
1950 mmc->init_in_progress = 0;
1951 if (mmc->op_cond_pending)
1952 err = mmc_complete_op_cond(mmc);
1955 err = mmc_startup(mmc);
1963 int mmc_init(struct mmc *mmc)
1966 __maybe_unused unsigned start;
1967 #if CONFIG_IS_ENABLED(DM_MMC)
1968 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1975 start = get_timer(0);
1977 if (!mmc->init_in_progress)
1978 err = mmc_start_init(mmc);
1981 err = mmc_complete_init(mmc);
1983 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
1988 int mmc_set_dsr(struct mmc *mmc, u16 val)
1994 /* CPU-specific MMC initializations */
1995 __weak int cpu_mmc_init(bd_t *bis)
2000 /* board-specific MMC initializations. */
2001 __weak int board_mmc_init(bd_t *bis)
2006 void mmc_set_preinit(struct mmc *mmc, int preinit)
2008 mmc->preinit = preinit;
2011 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2012 static int mmc_probe(bd_t *bis)
2016 #elif CONFIG_IS_ENABLED(DM_MMC)
2017 static int mmc_probe(bd_t *bis)
2021 struct udevice *dev;
2023 ret = uclass_get(UCLASS_MMC, &uc);
2028 * Try to add them in sequence order. Really with driver model we
2029 * should allow holes, but the current MMC list does not allow that.
2030 * So if we request 0, 1, 3 we will get 0, 1, 2.
2032 for (i = 0; ; i++) {
2033 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2037 uclass_foreach_dev(dev, uc) {
2038 ret = device_probe(dev);
2040 printf("%s - probe failed: %d\n", dev->name, ret);
2046 static int mmc_probe(bd_t *bis)
2048 if (board_mmc_init(bis) < 0)
2055 int mmc_initialize(bd_t *bis)
2057 static int initialized = 0;
2059 if (initialized) /* Avoid initializing mmc multiple times */
2063 #if !CONFIG_IS_ENABLED(BLK)
2064 #if !CONFIG_IS_ENABLED(MMC_TINY)
2068 ret = mmc_probe(bis);
2072 #ifndef CONFIG_SPL_BUILD
2073 print_mmc_devices(',');
2080 #ifdef CONFIG_CMD_BKOPS_ENABLE
2081 int mmc_set_bkops_enable(struct mmc *mmc)
2084 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2086 err = mmc_send_ext_csd(mmc, ext_csd);
2088 puts("Could not get ext_csd register values\n");
2092 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2093 puts("Background operations not supported on device\n");
2094 return -EMEDIUMTYPE;
2097 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2098 puts("Background operations already enabled\n");
2102 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2104 puts("Failed to enable manual background operations\n");
2108 puts("Enabled manual background operations\n");