2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
33 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
34 static int mmc_power_cycle(struct mmc *mmc);
36 #if CONFIG_IS_ENABLED(MMC_TINY)
37 static struct mmc mmc_static;
38 struct mmc *find_mmc_device(int dev_num)
43 void mmc_do_preinit(void)
45 struct mmc *m = &mmc_static;
46 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
47 mmc_set_preinit(m, 1);
53 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
55 return &mmc->block_dev;
59 #if !CONFIG_IS_ENABLED(DM_MMC)
61 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
66 __weak int board_mmc_getwp(struct mmc *mmc)
71 int mmc_getwp(struct mmc *mmc)
75 wp = board_mmc_getwp(mmc);
78 if (mmc->cfg->ops->getwp)
79 wp = mmc->cfg->ops->getwp(mmc);
87 __weak int board_mmc_getcd(struct mmc *mmc)
93 #ifdef CONFIG_MMC_TRACE
94 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
96 printf("CMD_SEND:%d\n", cmd->cmdidx);
97 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
100 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
106 printf("\t\tRET\t\t\t %d\n", ret);
108 switch (cmd->resp_type) {
110 printf("\t\tMMC_RSP_NONE\n");
113 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
117 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
121 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
123 printf("\t\t \t\t 0x%08X \n",
125 printf("\t\t \t\t 0x%08X \n",
127 printf("\t\t \t\t 0x%08X \n",
130 printf("\t\t\t\t\tDUMPING DATA\n");
131 for (i = 0; i < 4; i++) {
133 printf("\t\t\t\t\t%03d - ", i*4);
134 ptr = (u8 *)&cmd->response[i];
136 for (j = 0; j < 4; j++)
137 printf("%02X ", *ptr--);
142 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
146 printf("\t\tERROR MMC rsp not supported\n");
152 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
156 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
157 printf("CURR STATE:%d\n", status);
161 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
162 const char *mmc_mode_name(enum bus_mode mode)
164 static const char *const names[] = {
165 [MMC_LEGACY] = "MMC legacy",
166 [SD_LEGACY] = "SD Legacy",
167 [MMC_HS] = "MMC High Speed (26MHz)",
168 [SD_HS] = "SD High Speed (50MHz)",
169 [UHS_SDR12] = "UHS SDR12 (25MHz)",
170 [UHS_SDR25] = "UHS SDR25 (50MHz)",
171 [UHS_SDR50] = "UHS SDR50 (100MHz)",
172 [UHS_SDR104] = "UHS SDR104 (208MHz)",
173 [UHS_DDR50] = "UHS DDR50 (50MHz)",
174 [MMC_HS_52] = "MMC High Speed (52MHz)",
175 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
176 [MMC_HS_200] = "HS200 (200MHz)",
179 if (mode >= MMC_MODES_END)
180 return "Unknown mode";
186 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
188 static const int freqs[] = {
189 [SD_LEGACY] = 25000000,
192 [UHS_SDR12] = 25000000,
193 [UHS_SDR25] = 50000000,
194 [UHS_SDR50] = 100000000,
195 [UHS_SDR104] = 208000000,
196 [UHS_DDR50] = 50000000,
197 [MMC_HS_52] = 52000000,
198 [MMC_DDR_52] = 52000000,
199 [MMC_HS_200] = 200000000,
202 if (mode == MMC_LEGACY)
203 return mmc->legacy_speed;
204 else if (mode >= MMC_MODES_END)
210 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
212 mmc->selected_mode = mode;
213 mmc->tran_speed = mmc_mode2freq(mmc, mode);
214 mmc->ddr_mode = mmc_is_mode_ddr(mode);
215 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
216 mmc->tran_speed / 1000000);
220 #if !CONFIG_IS_ENABLED(DM_MMC)
221 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
225 mmmc_trace_before_send(mmc, cmd);
226 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
227 mmmc_trace_after_send(mmc, cmd, ret);
233 int mmc_send_status(struct mmc *mmc, int timeout)
236 int err, retries = 5;
238 cmd.cmdidx = MMC_CMD_SEND_STATUS;
239 cmd.resp_type = MMC_RSP_R1;
240 if (!mmc_host_is_spi(mmc))
241 cmd.cmdarg = mmc->rca << 16;
244 err = mmc_send_cmd(mmc, &cmd, NULL);
246 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
247 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
251 if (cmd.response[0] & MMC_STATUS_MASK) {
252 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
253 printf("Status Error: 0x%08X\n",
258 } else if (--retries < 0)
267 mmc_trace_state(mmc, &cmd);
269 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
270 printf("Timeout waiting card ready\n");
278 int mmc_set_blocklen(struct mmc *mmc, int len)
285 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
286 cmd.resp_type = MMC_RSP_R1;
289 return mmc_send_cmd(mmc, &cmd, NULL);
292 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
296 struct mmc_data data;
299 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
301 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
303 if (mmc->high_capacity)
306 cmd.cmdarg = start * mmc->read_bl_len;
308 cmd.resp_type = MMC_RSP_R1;
311 data.blocks = blkcnt;
312 data.blocksize = mmc->read_bl_len;
313 data.flags = MMC_DATA_READ;
315 if (mmc_send_cmd(mmc, &cmd, &data))
319 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
321 cmd.resp_type = MMC_RSP_R1b;
322 if (mmc_send_cmd(mmc, &cmd, NULL)) {
323 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
324 printf("mmc fail to send stop cmd\n");
333 #if CONFIG_IS_ENABLED(BLK)
334 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
336 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
340 #if CONFIG_IS_ENABLED(BLK)
341 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
343 int dev_num = block_dev->devnum;
345 lbaint_t cur, blocks_todo = blkcnt;
350 struct mmc *mmc = find_mmc_device(dev_num);
354 if (CONFIG_IS_ENABLED(MMC_TINY))
355 err = mmc_switch_part(mmc, block_dev->hwpart);
357 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
362 if ((start + blkcnt) > block_dev->lba) {
363 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
364 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
365 start + blkcnt, block_dev->lba);
370 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
371 debug("%s: Failed to set blocklen\n", __func__);
376 cur = (blocks_todo > mmc->cfg->b_max) ?
377 mmc->cfg->b_max : blocks_todo;
378 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
379 debug("%s: Failed to read blocks\n", __func__);
384 dst += cur * mmc->read_bl_len;
385 } while (blocks_todo > 0);
390 static int mmc_go_idle(struct mmc *mmc)
397 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
399 cmd.resp_type = MMC_RSP_NONE;
401 err = mmc_send_cmd(mmc, &cmd, NULL);
411 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
417 * Send CMD11 only if the request is to switch the card to
420 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
421 return mmc_set_signal_voltage(mmc, signal_voltage);
423 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
425 cmd.resp_type = MMC_RSP_R1;
427 err = mmc_send_cmd(mmc, &cmd, NULL);
431 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
435 * The card should drive cmd and dat[0:3] low immediately
436 * after the response of cmd11, but wait 100 us to be sure
438 err = mmc_wait_dat0(mmc, 0, 100);
445 * During a signal voltage level switch, the clock must be gated
446 * for 5 ms according to the SD spec
448 mmc_set_clock(mmc, mmc->clock, true);
450 err = mmc_set_signal_voltage(mmc, signal_voltage);
454 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
456 mmc_set_clock(mmc, mmc->clock, false);
459 * Failure to switch is indicated by the card holding
460 * dat[0:3] low. Wait for at least 1 ms according to spec
462 err = mmc_wait_dat0(mmc, 1, 1000);
471 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
478 cmd.cmdidx = MMC_CMD_APP_CMD;
479 cmd.resp_type = MMC_RSP_R1;
482 err = mmc_send_cmd(mmc, &cmd, NULL);
487 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
488 cmd.resp_type = MMC_RSP_R3;
491 * Most cards do not answer if some reserved bits
492 * in the ocr are set. However, Some controller
493 * can set bit 7 (reserved for low voltages), but
494 * how to manage low voltages SD card is not yet
497 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
498 (mmc->cfg->voltages & 0xff8000);
500 if (mmc->version == SD_VERSION_2)
501 cmd.cmdarg |= OCR_HCS;
504 cmd.cmdarg |= OCR_S18R;
506 err = mmc_send_cmd(mmc, &cmd, NULL);
511 if (cmd.response[0] & OCR_BUSY)
520 if (mmc->version != SD_VERSION_2)
521 mmc->version = SD_VERSION_1_0;
523 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
524 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
525 cmd.resp_type = MMC_RSP_R3;
528 err = mmc_send_cmd(mmc, &cmd, NULL);
534 mmc->ocr = cmd.response[0];
536 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
538 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
543 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
549 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
554 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
555 cmd.resp_type = MMC_RSP_R3;
557 if (use_arg && !mmc_host_is_spi(mmc))
558 cmd.cmdarg = OCR_HCS |
559 (mmc->cfg->voltages &
560 (mmc->ocr & OCR_VOLTAGE_MASK)) |
561 (mmc->ocr & OCR_ACCESS_MODE);
563 err = mmc_send_cmd(mmc, &cmd, NULL);
566 mmc->ocr = cmd.response[0];
570 static int mmc_send_op_cond(struct mmc *mmc)
574 /* Some cards seem to need this */
577 /* Asking to the card its capabilities */
578 for (i = 0; i < 2; i++) {
579 err = mmc_send_op_cond_iter(mmc, i != 0);
583 /* exit if not busy (flag seems to be inverted) */
584 if (mmc->ocr & OCR_BUSY)
587 mmc->op_cond_pending = 1;
591 static int mmc_complete_op_cond(struct mmc *mmc)
598 mmc->op_cond_pending = 0;
599 if (!(mmc->ocr & OCR_BUSY)) {
600 /* Some cards seem to need this */
603 start = get_timer(0);
605 err = mmc_send_op_cond_iter(mmc, 1);
608 if (mmc->ocr & OCR_BUSY)
610 if (get_timer(start) > timeout)
616 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
617 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
618 cmd.resp_type = MMC_RSP_R3;
621 err = mmc_send_cmd(mmc, &cmd, NULL);
626 mmc->ocr = cmd.response[0];
629 mmc->version = MMC_VERSION_UNKNOWN;
631 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
638 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
641 struct mmc_data data;
644 /* Get the Card Status Register */
645 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
646 cmd.resp_type = MMC_RSP_R1;
649 data.dest = (char *)ext_csd;
651 data.blocksize = MMC_MAX_BLOCK_LEN;
652 data.flags = MMC_DATA_READ;
654 err = mmc_send_cmd(mmc, &cmd, &data);
659 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
666 cmd.cmdidx = MMC_CMD_SWITCH;
667 cmd.resp_type = MMC_RSP_R1b;
668 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
672 while (retries > 0) {
673 ret = mmc_send_cmd(mmc, &cmd, NULL);
675 /* Waiting for the ready status */
677 ret = mmc_send_status(mmc, timeout);
688 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
693 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
699 speed_bits = EXT_CSD_TIMING_HS;
702 speed_bits = EXT_CSD_TIMING_HS200;
705 speed_bits = EXT_CSD_TIMING_LEGACY;
710 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
715 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
716 /* Now check to see that it worked */
717 err = mmc_send_ext_csd(mmc, test_csd);
721 /* No high-speed support */
722 if (!test_csd[EXT_CSD_HS_TIMING])
729 static int mmc_get_capabilities(struct mmc *mmc)
731 u8 *ext_csd = mmc->ext_csd;
734 mmc->card_caps = MMC_MODE_1BIT;
736 if (mmc_host_is_spi(mmc))
739 /* Only version 4 supports high-speed */
740 if (mmc->version < MMC_VERSION_4)
744 printf("No ext_csd found!\n"); /* this should enver happen */
748 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
750 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
752 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
753 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
754 mmc->card_caps |= MMC_MODE_HS200;
756 if (cardtype & EXT_CSD_CARD_TYPE_52) {
757 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
758 mmc->card_caps |= MMC_MODE_DDR_52MHz;
759 mmc->card_caps |= MMC_MODE_HS_52MHz;
761 if (cardtype & EXT_CSD_CARD_TYPE_26)
762 mmc->card_caps |= MMC_MODE_HS;
767 static int mmc_set_capacity(struct mmc *mmc, int part_num)
771 mmc->capacity = mmc->capacity_user;
775 mmc->capacity = mmc->capacity_boot;
778 mmc->capacity = mmc->capacity_rpmb;
784 mmc->capacity = mmc->capacity_gp[part_num - 4];
790 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
795 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
799 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
800 (mmc->part_config & ~PART_ACCESS_MASK)
801 | (part_num & PART_ACCESS_MASK));
804 * Set the capacity if the switch succeeded or was intended
805 * to return to representing the raw device.
807 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
808 ret = mmc_set_capacity(mmc, part_num);
809 mmc_get_blk_desc(mmc)->hwpart = part_num;
815 int mmc_hwpart_config(struct mmc *mmc,
816 const struct mmc_hwpart_conf *conf,
817 enum mmc_hwpart_conf_mode mode)
823 u32 max_enh_size_mult;
824 u32 tot_enh_size_mult = 0;
827 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
829 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
832 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
833 printf("eMMC >= 4.4 required for enhanced user data area\n");
837 if (!(mmc->part_support & PART_SUPPORT)) {
838 printf("Card does not support partitioning\n");
842 if (!mmc->hc_wp_grp_size) {
843 printf("Card does not define HC WP group size\n");
847 /* check partition alignment and total enhanced size */
848 if (conf->user.enh_size) {
849 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
850 conf->user.enh_start % mmc->hc_wp_grp_size) {
851 printf("User data enhanced area not HC WP group "
855 part_attrs |= EXT_CSD_ENH_USR;
856 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
857 if (mmc->high_capacity) {
858 enh_start_addr = conf->user.enh_start;
860 enh_start_addr = (conf->user.enh_start << 9);
866 tot_enh_size_mult += enh_size_mult;
868 for (pidx = 0; pidx < 4; pidx++) {
869 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
870 printf("GP%i partition not HC WP group size "
871 "aligned\n", pidx+1);
874 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
875 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
876 part_attrs |= EXT_CSD_ENH_GP(pidx);
877 tot_enh_size_mult += gp_size_mult[pidx];
881 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
882 printf("Card does not support enhanced attribute\n");
886 err = mmc_send_ext_csd(mmc, ext_csd);
891 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
892 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
893 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
894 if (tot_enh_size_mult > max_enh_size_mult) {
895 printf("Total enhanced size exceeds maximum (%u > %u)\n",
896 tot_enh_size_mult, max_enh_size_mult);
900 /* The default value of EXT_CSD_WR_REL_SET is device
901 * dependent, the values can only be changed if the
902 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
903 * changed only once and before partitioning is completed. */
904 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
905 if (conf->user.wr_rel_change) {
906 if (conf->user.wr_rel_set)
907 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
909 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
911 for (pidx = 0; pidx < 4; pidx++) {
912 if (conf->gp_part[pidx].wr_rel_change) {
913 if (conf->gp_part[pidx].wr_rel_set)
914 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
916 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
920 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
921 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
922 puts("Card does not support host controlled partition write "
923 "reliability settings\n");
927 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
928 EXT_CSD_PARTITION_SETTING_COMPLETED) {
929 printf("Card already partitioned\n");
933 if (mode == MMC_HWPART_CONF_CHECK)
936 /* Partitioning requires high-capacity size definitions */
937 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
938 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
939 EXT_CSD_ERASE_GROUP_DEF, 1);
944 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
946 /* update erase group size to be high-capacity */
947 mmc->erase_grp_size =
948 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
952 /* all OK, write the configuration */
953 for (i = 0; i < 4; i++) {
954 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
955 EXT_CSD_ENH_START_ADDR+i,
956 (enh_start_addr >> (i*8)) & 0xFF);
960 for (i = 0; i < 3; i++) {
961 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
962 EXT_CSD_ENH_SIZE_MULT+i,
963 (enh_size_mult >> (i*8)) & 0xFF);
967 for (pidx = 0; pidx < 4; pidx++) {
968 for (i = 0; i < 3; i++) {
969 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
970 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
971 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
976 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
977 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
981 if (mode == MMC_HWPART_CONF_SET)
984 /* The WR_REL_SET is a write-once register but shall be
985 * written before setting PART_SETTING_COMPLETED. As it is
986 * write-once we can only write it when completing the
988 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
989 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
990 EXT_CSD_WR_REL_SET, wr_rel_set);
995 /* Setting PART_SETTING_COMPLETED confirms the partition
996 * configuration but it only becomes effective after power
997 * cycle, so we do not adjust the partition related settings
998 * in the mmc struct. */
1000 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1001 EXT_CSD_PARTITION_SETTING,
1002 EXT_CSD_PARTITION_SETTING_COMPLETED);
1009 #if !CONFIG_IS_ENABLED(DM_MMC)
1010 int mmc_getcd(struct mmc *mmc)
1014 cd = board_mmc_getcd(mmc);
1017 if (mmc->cfg->ops->getcd)
1018 cd = mmc->cfg->ops->getcd(mmc);
1027 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1030 struct mmc_data data;
1032 /* Switch the frequency */
1033 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1034 cmd.resp_type = MMC_RSP_R1;
1035 cmd.cmdarg = (mode << 31) | 0xffffff;
1036 cmd.cmdarg &= ~(0xf << (group * 4));
1037 cmd.cmdarg |= value << (group * 4);
1039 data.dest = (char *)resp;
1040 data.blocksize = 64;
1042 data.flags = MMC_DATA_READ;
1044 return mmc_send_cmd(mmc, &cmd, &data);
1048 static int sd_get_capabilities(struct mmc *mmc)
1052 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1053 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1054 struct mmc_data data;
1058 mmc->card_caps = MMC_MODE_1BIT;
1060 if (mmc_host_is_spi(mmc))
1063 /* Read the SCR to find out if this card supports higher speeds */
1064 cmd.cmdidx = MMC_CMD_APP_CMD;
1065 cmd.resp_type = MMC_RSP_R1;
1066 cmd.cmdarg = mmc->rca << 16;
1068 err = mmc_send_cmd(mmc, &cmd, NULL);
1073 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1074 cmd.resp_type = MMC_RSP_R1;
1080 data.dest = (char *)scr;
1083 data.flags = MMC_DATA_READ;
1085 err = mmc_send_cmd(mmc, &cmd, &data);
1094 mmc->scr[0] = __be32_to_cpu(scr[0]);
1095 mmc->scr[1] = __be32_to_cpu(scr[1]);
1097 switch ((mmc->scr[0] >> 24) & 0xf) {
1099 mmc->version = SD_VERSION_1_0;
1102 mmc->version = SD_VERSION_1_10;
1105 mmc->version = SD_VERSION_2;
1106 if ((mmc->scr[0] >> 15) & 0x1)
1107 mmc->version = SD_VERSION_3;
1110 mmc->version = SD_VERSION_1_0;
1114 if (mmc->scr[0] & SD_DATA_4BIT)
1115 mmc->card_caps |= MMC_MODE_4BIT;
1117 /* Version 1.0 doesn't support switching */
1118 if (mmc->version == SD_VERSION_1_0)
1123 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1124 (u8 *)switch_status);
1129 /* The high-speed function is busy. Try again */
1130 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1134 /* If high-speed isn't supported, we return */
1135 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1136 mmc->card_caps |= MMC_CAP(SD_HS);
1138 /* Version before 3.0 don't support UHS modes */
1139 if (mmc->version < SD_VERSION_3)
1142 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1143 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1144 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1145 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1146 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1147 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1148 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1149 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1150 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1151 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1152 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1157 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1161 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1167 speed = UHS_SDR12_BUS_SPEED;
1171 speed = UHS_SDR25_BUS_SPEED;
1174 speed = UHS_SDR50_BUS_SPEED;
1177 speed = UHS_DDR50_BUS_SPEED;
1180 speed = UHS_SDR104_BUS_SPEED;
1186 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1190 if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
1196 int sd_select_bus_width(struct mmc *mmc, int w)
1201 if ((w != 4) && (w != 1))
1204 cmd.cmdidx = MMC_CMD_APP_CMD;
1205 cmd.resp_type = MMC_RSP_R1;
1206 cmd.cmdarg = mmc->rca << 16;
1208 err = mmc_send_cmd(mmc, &cmd, NULL);
1212 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1213 cmd.resp_type = MMC_RSP_R1;
1218 err = mmc_send_cmd(mmc, &cmd, NULL);
1225 static int sd_read_ssr(struct mmc *mmc)
1229 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1230 struct mmc_data data;
1232 unsigned int au, eo, et, es;
1234 cmd.cmdidx = MMC_CMD_APP_CMD;
1235 cmd.resp_type = MMC_RSP_R1;
1236 cmd.cmdarg = mmc->rca << 16;
1238 err = mmc_send_cmd(mmc, &cmd, NULL);
1242 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1243 cmd.resp_type = MMC_RSP_R1;
1247 data.dest = (char *)ssr;
1248 data.blocksize = 64;
1250 data.flags = MMC_DATA_READ;
1252 err = mmc_send_cmd(mmc, &cmd, &data);
1260 for (i = 0; i < 16; i++)
1261 ssr[i] = be32_to_cpu(ssr[i]);
1263 au = (ssr[2] >> 12) & 0xF;
1264 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1265 mmc->ssr.au = sd_au_size[au];
1266 es = (ssr[3] >> 24) & 0xFF;
1267 es |= (ssr[2] & 0xFF) << 8;
1268 et = (ssr[3] >> 18) & 0x3F;
1270 eo = (ssr[3] >> 16) & 0x3;
1271 mmc->ssr.erase_timeout = (et * 1000) / es;
1272 mmc->ssr.erase_offset = eo * 1000;
1275 debug("Invalid Allocation Unit Size.\n");
1281 /* frequency bases */
1282 /* divided by 10 to be nice to platforms without floating point */
1283 static const int fbase[] = {
1290 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1291 * to platforms without floating point.
1293 static const u8 multipliers[] = {
1312 static inline int bus_width(uint cap)
1314 if (cap == MMC_MODE_8BIT)
1316 if (cap == MMC_MODE_4BIT)
1318 if (cap == MMC_MODE_1BIT)
1320 printf("invalid bus witdh capability 0x%x\n", cap);
1324 #if !CONFIG_IS_ENABLED(DM_MMC)
1325 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1330 static void mmc_send_init_stream(struct mmc *mmc)
1334 static int mmc_set_ios(struct mmc *mmc)
1338 if (mmc->cfg->ops->set_ios)
1339 ret = mmc->cfg->ops->set_ios(mmc);
1345 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1347 if (clock > mmc->cfg->f_max)
1348 clock = mmc->cfg->f_max;
1350 if (clock < mmc->cfg->f_min)
1351 clock = mmc->cfg->f_min;
1354 mmc->clk_disable = disable;
1356 return mmc_set_ios(mmc);
1359 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1361 mmc->bus_width = width;
1363 return mmc_set_ios(mmc);
1366 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1368 * helper function to display the capabilities in a human
1369 * friendly manner. The capabilities include bus width and
1372 void mmc_dump_capabilities(const char *text, uint caps)
1376 printf("%s: widths [", text);
1377 if (caps & MMC_MODE_8BIT)
1379 if (caps & MMC_MODE_4BIT)
1381 if (caps & MMC_MODE_1BIT)
1383 printf("\b\b] modes [");
1384 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1385 if (MMC_CAP(mode) & caps)
1386 printf("%s, ", mmc_mode_name(mode));
1391 struct mode_width_tuning {
1397 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1399 mmc->signal_voltage = signal_voltage;
1400 return mmc_set_ios(mmc);
1403 static const struct mode_width_tuning sd_modes_by_pref[] = {
1406 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1407 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1411 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1415 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1419 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1423 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1427 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1431 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1435 #define for_each_sd_mode_by_pref(caps, mwt) \
1436 for (mwt = sd_modes_by_pref;\
1437 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1439 if (caps & MMC_CAP(mwt->mode))
1441 static int sd_select_mode_and_width(struct mmc *mmc)
1444 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1445 const struct mode_width_tuning *mwt;
1446 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1450 err = sd_get_capabilities(mmc);
1453 /* Restrict card's capabilities by what the host can do */
1454 caps = mmc->card_caps & (mmc->cfg->host_caps | MMC_MODE_1BIT);
1459 for_each_sd_mode_by_pref(caps, mwt) {
1462 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1463 if (*w & caps & mwt->widths) {
1464 debug("trying mode %s width %d (at %d MHz)\n",
1465 mmc_mode_name(mwt->mode),
1467 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1469 /* configure the bus width (card + host) */
1470 err = sd_select_bus_width(mmc, bus_width(*w));
1473 mmc_set_bus_width(mmc, bus_width(*w));
1475 /* configure the bus mode (card) */
1476 err = sd_set_card_speed(mmc, mwt->mode);
1480 /* configure the bus mode (host) */
1481 mmc_select_mode(mmc, mwt->mode);
1482 mmc_set_clock(mmc, mmc->tran_speed, false);
1484 /* execute tuning if needed */
1485 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1486 err = mmc_execute_tuning(mmc,
1489 debug("tuning failed\n");
1494 err = sd_read_ssr(mmc);
1498 printf("bad ssr\n");
1501 /* revert to a safer bus speed */
1502 mmc_select_mode(mmc, SD_LEGACY);
1503 mmc_set_clock(mmc, mmc->tran_speed, false);
1508 printf("unable to select a mode\n");
1513 * read the compare the part of ext csd that is constant.
1514 * This can be used to check that the transfer is working
1517 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1520 const u8 *ext_csd = mmc->ext_csd;
1521 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1523 err = mmc_send_ext_csd(mmc, test_csd);
1527 /* Only compare read only fields */
1528 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1529 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1530 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1531 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1532 ext_csd[EXT_CSD_REV]
1533 == test_csd[EXT_CSD_REV] &&
1534 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1535 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1536 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1537 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1543 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1546 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1547 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1551 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1555 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1559 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1563 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1567 #define for_each_mmc_mode_by_pref(caps, mwt) \
1568 for (mwt = mmc_modes_by_pref;\
1569 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1571 if (caps & MMC_CAP(mwt->mode))
1573 static const struct ext_csd_bus_width {
1577 } ext_csd_bus_width[] = {
1578 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1579 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1580 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1581 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1582 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1585 #define for_each_supported_width(caps, ddr, ecbv) \
1586 for (ecbv = ext_csd_bus_width;\
1587 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1589 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1591 static int mmc_select_mode_and_width(struct mmc *mmc)
1594 const struct mode_width_tuning *mwt;
1595 const struct ext_csd_bus_width *ecbw;
1597 err = mmc_get_capabilities(mmc);
1601 /* Restrict card's capabilities by what the host can do */
1602 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1604 /* Only version 4 of MMC supports wider bus widths */
1605 if (mmc->version < MMC_VERSION_4)
1608 if (!mmc->ext_csd) {
1609 debug("No ext_csd found!\n"); /* this should enver happen */
1613 for_each_mmc_mode_by_pref(mmc->card_caps, mwt) {
1614 for_each_supported_width(mmc->card_caps & mwt->widths,
1615 mmc_is_mode_ddr(mwt->mode), ecbw) {
1616 debug("trying mode %s width %d (at %d MHz)\n",
1617 mmc_mode_name(mwt->mode),
1618 bus_width(ecbw->cap),
1619 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1620 /* configure the bus width (card + host) */
1621 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1623 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1626 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1628 /* configure the bus speed (card) */
1629 err = mmc_set_card_speed(mmc, mwt->mode);
1634 * configure the bus width AND the ddr mode (card)
1635 * The host side will be taken care of in the next step
1637 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1638 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1640 ecbw->ext_csd_bits);
1645 /* configure the bus mode (host) */
1646 mmc_select_mode(mmc, mwt->mode);
1647 mmc_set_clock(mmc, mmc->tran_speed, false);
1649 /* execute tuning if needed */
1651 err = mmc_execute_tuning(mmc, mwt->tuning);
1653 debug("tuning failed\n");
1658 /* do a transfer to check the configuration */
1659 err = mmc_read_and_compare_ext_csd(mmc);
1663 /* if an error occured, revert to a safer bus mode */
1664 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1665 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1666 mmc_select_mode(mmc, MMC_LEGACY);
1667 mmc_set_bus_width(mmc, 1);
1671 printf("unable to select a mode\n");
1676 static int mmc_startup_v4(struct mmc *mmc)
1680 bool has_parts = false;
1681 bool part_completed;
1684 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1687 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1691 mmc->ext_csd = ext_csd;
1693 /* check ext_csd version and capacity */
1694 err = mmc_send_ext_csd(mmc, ext_csd);
1697 if (ext_csd[EXT_CSD_REV] >= 2) {
1699 * According to the JEDEC Standard, the value of
1700 * ext_csd's capacity is valid if the value is more
1703 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1704 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1705 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1706 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1707 capacity *= MMC_MAX_BLOCK_LEN;
1708 if ((capacity >> 20) > 2 * 1024)
1709 mmc->capacity_user = capacity;
1712 switch (ext_csd[EXT_CSD_REV]) {
1714 mmc->version = MMC_VERSION_4_1;
1717 mmc->version = MMC_VERSION_4_2;
1720 mmc->version = MMC_VERSION_4_3;
1723 mmc->version = MMC_VERSION_4_41;
1726 mmc->version = MMC_VERSION_4_5;
1729 mmc->version = MMC_VERSION_5_0;
1732 mmc->version = MMC_VERSION_5_1;
1736 /* The partition data may be non-zero but it is only
1737 * effective if PARTITION_SETTING_COMPLETED is set in
1738 * EXT_CSD, so ignore any data if this bit is not set,
1739 * except for enabling the high-capacity group size
1740 * definition (see below).
1742 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1743 EXT_CSD_PARTITION_SETTING_COMPLETED);
1745 /* store the partition info of emmc */
1746 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1747 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1748 ext_csd[EXT_CSD_BOOT_MULT])
1749 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1750 if (part_completed &&
1751 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1752 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1754 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1756 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1758 for (i = 0; i < 4; i++) {
1759 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1760 uint mult = (ext_csd[idx + 2] << 16) +
1761 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1764 if (!part_completed)
1766 mmc->capacity_gp[i] = mult;
1767 mmc->capacity_gp[i] *=
1768 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1769 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1770 mmc->capacity_gp[i] <<= 19;
1773 if (part_completed) {
1774 mmc->enh_user_size =
1775 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1776 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1777 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1778 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1779 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1780 mmc->enh_user_size <<= 19;
1781 mmc->enh_user_start =
1782 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1783 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1784 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1785 ext_csd[EXT_CSD_ENH_START_ADDR];
1786 if (mmc->high_capacity)
1787 mmc->enh_user_start <<= 9;
1791 * Host needs to enable ERASE_GRP_DEF bit if device is
1792 * partitioned. This bit will be lost every time after a reset
1793 * or power off. This will affect erase size.
1797 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1798 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1801 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1802 EXT_CSD_ERASE_GROUP_DEF, 1);
1807 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1810 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1811 /* Read out group size from ext_csd */
1812 mmc->erase_grp_size =
1813 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1815 * if high capacity and partition setting completed
1816 * SEC_COUNT is valid even if it is smaller than 2 GiB
1817 * JEDEC Standard JESD84-B45, 6.2.4
1819 if (mmc->high_capacity && part_completed) {
1820 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1821 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1822 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1823 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1824 capacity *= MMC_MAX_BLOCK_LEN;
1825 mmc->capacity_user = capacity;
1828 /* Calculate the group size from the csd value. */
1829 int erase_gsz, erase_gmul;
1831 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1832 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1833 mmc->erase_grp_size = (erase_gsz + 1)
1837 mmc->hc_wp_grp_size = 1024
1838 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1839 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1841 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1846 static int mmc_startup(struct mmc *mmc)
1852 struct blk_desc *bdesc;
1854 #ifdef CONFIG_MMC_SPI_CRC_ON
1855 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1856 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1857 cmd.resp_type = MMC_RSP_R1;
1859 err = mmc_send_cmd(mmc, &cmd, NULL);
1866 /* Put the Card in Identify Mode */
1867 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1868 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1869 cmd.resp_type = MMC_RSP_R2;
1872 err = mmc_send_cmd(mmc, &cmd, NULL);
1877 memcpy(mmc->cid, cmd.response, 16);
1880 * For MMC cards, set the Relative Address.
1881 * For SD cards, get the Relatvie Address.
1882 * This also puts the cards into Standby State
1884 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1885 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1886 cmd.cmdarg = mmc->rca << 16;
1887 cmd.resp_type = MMC_RSP_R6;
1889 err = mmc_send_cmd(mmc, &cmd, NULL);
1895 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1898 /* Get the Card-Specific Data */
1899 cmd.cmdidx = MMC_CMD_SEND_CSD;
1900 cmd.resp_type = MMC_RSP_R2;
1901 cmd.cmdarg = mmc->rca << 16;
1903 err = mmc_send_cmd(mmc, &cmd, NULL);
1908 mmc->csd[0] = cmd.response[0];
1909 mmc->csd[1] = cmd.response[1];
1910 mmc->csd[2] = cmd.response[2];
1911 mmc->csd[3] = cmd.response[3];
1913 if (mmc->version == MMC_VERSION_UNKNOWN) {
1914 int version = (cmd.response[0] >> 26) & 0xf;
1918 mmc->version = MMC_VERSION_1_2;
1921 mmc->version = MMC_VERSION_1_4;
1924 mmc->version = MMC_VERSION_2_2;
1927 mmc->version = MMC_VERSION_3;
1930 mmc->version = MMC_VERSION_4;
1933 mmc->version = MMC_VERSION_1_2;
1938 /* divide frequency by 10, since the mults are 10x bigger */
1939 freq = fbase[(cmd.response[0] & 0x7)];
1940 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1942 mmc->legacy_speed = freq * mult;
1943 mmc_select_mode(mmc, MMC_LEGACY);
1945 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1946 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1949 mmc->write_bl_len = mmc->read_bl_len;
1951 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1953 if (mmc->high_capacity) {
1954 csize = (mmc->csd[1] & 0x3f) << 16
1955 | (mmc->csd[2] & 0xffff0000) >> 16;
1958 csize = (mmc->csd[1] & 0x3ff) << 2
1959 | (mmc->csd[2] & 0xc0000000) >> 30;
1960 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1963 mmc->capacity_user = (csize + 1) << (cmult + 2);
1964 mmc->capacity_user *= mmc->read_bl_len;
1965 mmc->capacity_boot = 0;
1966 mmc->capacity_rpmb = 0;
1967 for (i = 0; i < 4; i++)
1968 mmc->capacity_gp[i] = 0;
1970 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1971 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1973 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1974 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1976 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1977 cmd.cmdidx = MMC_CMD_SET_DSR;
1978 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1979 cmd.resp_type = MMC_RSP_NONE;
1980 if (mmc_send_cmd(mmc, &cmd, NULL))
1981 printf("MMC: SET_DSR failed\n");
1984 /* Select the card, and put it into Transfer Mode */
1985 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1986 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1987 cmd.resp_type = MMC_RSP_R1;
1988 cmd.cmdarg = mmc->rca << 16;
1989 err = mmc_send_cmd(mmc, &cmd, NULL);
1996 * For SD, its erase group is always one sector
1998 mmc->erase_grp_size = 1;
1999 mmc->part_config = MMCPART_NOAVAILABLE;
2001 err = mmc_startup_v4(mmc);
2005 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2010 err = sd_select_mode_and_width(mmc);
2012 err = mmc_select_mode_and_width(mmc);
2018 /* Fix the block length for DDR mode */
2019 if (mmc->ddr_mode) {
2020 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2021 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2024 /* fill in device description */
2025 bdesc = mmc_get_blk_desc(mmc);
2029 bdesc->blksz = mmc->read_bl_len;
2030 bdesc->log2blksz = LOG2(bdesc->blksz);
2031 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2032 #if !defined(CONFIG_SPL_BUILD) || \
2033 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2034 !defined(CONFIG_USE_TINY_PRINTF))
2035 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2036 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2037 (mmc->cid[3] >> 16) & 0xffff);
2038 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2039 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2040 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2041 (mmc->cid[2] >> 24) & 0xff);
2042 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2043 (mmc->cid[2] >> 16) & 0xf);
2045 bdesc->vendor[0] = 0;
2046 bdesc->product[0] = 0;
2047 bdesc->revision[0] = 0;
2049 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
2056 static int mmc_send_if_cond(struct mmc *mmc)
2061 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2062 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2063 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2064 cmd.resp_type = MMC_RSP_R7;
2066 err = mmc_send_cmd(mmc, &cmd, NULL);
2071 if ((cmd.response[0] & 0xff) != 0xaa)
2074 mmc->version = SD_VERSION_2;
2079 #if !CONFIG_IS_ENABLED(DM_MMC)
2080 /* board-specific MMC power initializations. */
2081 __weak void board_mmc_power_init(void)
2086 static int mmc_power_init(struct mmc *mmc)
2088 #if CONFIG_IS_ENABLED(DM_MMC)
2089 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2092 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2095 debug("%s: No vmmc supply\n", mmc->dev->name);
2097 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2098 &mmc->vqmmc_supply);
2100 debug("%s: No vqmmc supply\n", mmc->dev->name);
2102 #else /* !CONFIG_DM_MMC */
2104 * Driver model should use a regulator, as above, rather than calling
2105 * out to board code.
2107 board_mmc_power_init();
2113 * put the host in the initial state:
2114 * - turn on Vdd (card power supply)
2115 * - configure the bus width and clock to minimal values
2117 static void mmc_set_initial_state(struct mmc *mmc)
2121 /* First try to set 3.3V. If it fails set to 1.8V */
2122 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2124 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2126 printf("mmc: failed to set signal voltage\n");
2128 mmc_select_mode(mmc, MMC_LEGACY);
2129 mmc_set_bus_width(mmc, 1);
2130 mmc_set_clock(mmc, 0, false);
2133 static int mmc_power_on(struct mmc *mmc)
2135 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2136 if (mmc->vmmc_supply) {
2137 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2140 puts("Error enabling VMMC supply\n");
2148 static int mmc_power_off(struct mmc *mmc)
2150 mmc_set_clock(mmc, 1, true);
2151 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2152 if (mmc->vmmc_supply) {
2153 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2156 debug("Error disabling VMMC supply\n");
2164 static int mmc_power_cycle(struct mmc *mmc)
2168 ret = mmc_power_off(mmc);
2172 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2173 * to be on the safer side.
2176 return mmc_power_on(mmc);
2179 int mmc_start_init(struct mmc *mmc)
2182 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2185 /* we pretend there's no card when init is NULL */
2186 no_card = mmc_getcd(mmc) == 0;
2187 #if !CONFIG_IS_ENABLED(DM_MMC)
2188 no_card = no_card || (mmc->cfg->ops->init == NULL);
2192 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2193 printf("MMC: no card present\n");
2201 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2202 mmc_adapter_card_type_ident();
2204 err = mmc_power_init(mmc);
2208 err = mmc_power_on(mmc);
2212 #if CONFIG_IS_ENABLED(DM_MMC)
2213 /* The device has already been probed ready for use */
2215 /* made sure it's not NULL earlier */
2216 err = mmc->cfg->ops->init(mmc);
2223 mmc_set_initial_state(mmc);
2224 mmc_send_init_stream(mmc);
2226 /* Reset the Card */
2227 err = mmc_go_idle(mmc);
2232 /* The internal partition reset to user partition(0) at every CMD0*/
2233 mmc_get_blk_desc(mmc)->hwpart = 0;
2235 /* Test for SD version 2 */
2236 err = mmc_send_if_cond(mmc);
2238 /* Now try to get the SD card's operating condition */
2239 err = sd_send_op_cond(mmc, uhs_en);
2240 if (err && uhs_en) {
2242 mmc_power_cycle(mmc);
2246 /* If the command timed out, we check for an MMC card */
2247 if (err == -ETIMEDOUT) {
2248 err = mmc_send_op_cond(mmc);
2251 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2252 printf("Card did not respond to voltage select!\n");
2259 mmc->init_in_progress = 1;
2264 static int mmc_complete_init(struct mmc *mmc)
2268 mmc->init_in_progress = 0;
2269 if (mmc->op_cond_pending)
2270 err = mmc_complete_op_cond(mmc);
2273 err = mmc_startup(mmc);
2281 int mmc_init(struct mmc *mmc)
2284 __maybe_unused unsigned start;
2285 #if CONFIG_IS_ENABLED(DM_MMC)
2286 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2293 start = get_timer(0);
2295 if (!mmc->init_in_progress)
2296 err = mmc_start_init(mmc);
2299 err = mmc_complete_init(mmc);
2301 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2306 int mmc_set_dsr(struct mmc *mmc, u16 val)
2312 /* CPU-specific MMC initializations */
2313 __weak int cpu_mmc_init(bd_t *bis)
2318 /* board-specific MMC initializations. */
2319 __weak int board_mmc_init(bd_t *bis)
2324 void mmc_set_preinit(struct mmc *mmc, int preinit)
2326 mmc->preinit = preinit;
2329 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2330 static int mmc_probe(bd_t *bis)
2334 #elif CONFIG_IS_ENABLED(DM_MMC)
2335 static int mmc_probe(bd_t *bis)
2339 struct udevice *dev;
2341 ret = uclass_get(UCLASS_MMC, &uc);
2346 * Try to add them in sequence order. Really with driver model we
2347 * should allow holes, but the current MMC list does not allow that.
2348 * So if we request 0, 1, 3 we will get 0, 1, 2.
2350 for (i = 0; ; i++) {
2351 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2355 uclass_foreach_dev(dev, uc) {
2356 ret = device_probe(dev);
2358 printf("%s - probe failed: %d\n", dev->name, ret);
2364 static int mmc_probe(bd_t *bis)
2366 if (board_mmc_init(bis) < 0)
2373 int mmc_initialize(bd_t *bis)
2375 static int initialized = 0;
2377 if (initialized) /* Avoid initializing mmc multiple times */
2381 #if !CONFIG_IS_ENABLED(BLK)
2382 #if !CONFIG_IS_ENABLED(MMC_TINY)
2386 ret = mmc_probe(bis);
2390 #ifndef CONFIG_SPL_BUILD
2391 print_mmc_devices(',');
2398 #ifdef CONFIG_CMD_BKOPS_ENABLE
2399 int mmc_set_bkops_enable(struct mmc *mmc)
2402 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2404 err = mmc_send_ext_csd(mmc, ext_csd);
2406 puts("Could not get ext_csd register values\n");
2410 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2411 puts("Background operations not supported on device\n");
2412 return -EMEDIUMTYPE;
2415 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2416 puts("Background operations already enabled\n");
2420 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2422 puts("Failed to enable manual background operations\n");
2426 puts("Enabled manual background operations\n");