drivers/mmc/mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008, Freescale Semiconductor, Inc
   4  * Copyright 2020 NXP
   5  * Andy Fleming
   6  *
   7  * Based vaguely on the Linux code
   8  */
   9
  10 #include <config.h>
  11 #include <common.h>
  12 #include <blk.h>
  13 #include <command.h>
  14 #include <dm.h>
  15 #include <log.h>
  16 #include <dm/device-internal.h>
  17 #include <errno.h>
  18 #include <mmc.h>
  19 #include <part.h>
  20 #include <linux/bitops.h>
  21 #include <linux/delay.h>
  22 #include <power/regulator.h>
  23 #include <malloc.h>
  24 #include <memalign.h>
  25 #include <linux/list.h>
  26 #include <div64.h>
  27 #include "mmc_private.h"
  28
  29 #define DEFAULT_CMD6_TIMEOUT_MS  500
  30
  31 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  32
  33 #if !CONFIG_IS_ENABLED(DM_MMC)
  34
  35 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
  36 {
  37         if (mmc->cfg->ops->wait_dat0)
  38                 return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us);
  39
  40         return -ENOSYS;
  41 }
  42
  43 __weak int board_mmc_getwp(struct mmc *mmc)
  44 {
  45         return -1;
  46 }
  47
  48 int mmc_getwp(struct mmc *mmc)
  49 {
  50         int wp;
  51
  52         wp = board_mmc_getwp(mmc);
  53
  54         if (wp < 0) {
  55                 if (mmc->cfg->ops->getwp)
  56                         wp = mmc->cfg->ops->getwp(mmc);
  57                 else
  58                         wp = 0;
  59         }
  60
  61         return wp;
  62 }
  63
  64 __weak int board_mmc_getcd(struct mmc *mmc)
  65 {
  66         return -1;
  67 }
  68 #endif
  69
  70 #ifdef CONFIG_MMC_TRACE
  71 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  72 {
  73         printf("CMD_SEND:%d\n", cmd->cmdidx);
  74         printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  75 }
  76
  77 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  78 {
  79         int i;
  80         u8 *ptr;
  81
  82         if (ret) {
  83                 printf("\t\tRET\t\t\t %d\n", ret);
  84         } else {
  85                 switch (cmd->resp_type) {
  86                 case MMC_RSP_NONE:
  87                         printf("\t\tMMC_RSP_NONE\n");
  88                         break;
  89                 case MMC_RSP_R1:
  90                         printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  91                                 cmd->response[0]);
  92                         break;
  93                 case MMC_RSP_R1b:
  94                         printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  95                                 cmd->response[0]);
  96                         break;
  97                 case MMC_RSP_R2:
  98                         printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  99                                 cmd->response[0]);
 100                         printf("\t\t          \t\t 0x%08x \n",
 101                                 cmd->response[1]);
 102                         printf("\t\t          \t\t 0x%08x \n",
 103                                 cmd->response[2]);
 104                         printf("\t\t          \t\t 0x%08x \n",
 105                                 cmd->response[3]);
 106                         printf("\n");
 107                         printf("\t\t\t\t\tDUMPING DATA\n");
 108                         for (i = 0; i < 4; i++) {
 109                                 int j;
 110                                 printf("\t\t\t\t\t%03d - ", i*4);
 111                                 ptr = (u8 *)&cmd->response[i];
 112                                 ptr += 3;
 113                                 for (j = 0; j < 4; j++)
 114                                         printf("%02x ", *ptr--);
 115                                 printf("\n");
 116                         }
 117                         break;
 118                 case MMC_RSP_R3:
 119                         printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
 120                                 cmd->response[0]);
 121                         break;
 122                 default:
 123                         printf("\t\tERROR MMC rsp not supported\n");
 124                         break;
 125                 }
 126         }
 127 }
 128
 129 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
 130 {
 131         int status;
 132
 133         status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
 134         printf("CURR STATE:%d\n", status);
 135 }
 136 #endif
 137
 138 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) || CONFIG_VAL(LOGLEVEL) >= LOGL_DEBUG
 139 const char *mmc_mode_name(enum bus_mode mode)
 140 {
 141         static const char *const names[] = {
 142               [MMC_LEGACY]      = "MMC legacy",
 143               [MMC_HS]          = "MMC High Speed (26MHz)",
 144               [SD_HS]           = "SD High Speed (50MHz)",
 145               [UHS_SDR12]       = "UHS SDR12 (25MHz)",
 146               [UHS_SDR25]       = "UHS SDR25 (50MHz)",
 147               [UHS_SDR50]       = "UHS SDR50 (100MHz)",
 148               [UHS_SDR104]      = "UHS SDR104 (208MHz)",
 149               [UHS_DDR50]       = "UHS DDR50 (50MHz)",
 150               [MMC_HS_52]       = "MMC High Speed (52MHz)",
 151               [MMC_DDR_52]      = "MMC DDR52 (52MHz)",
 152               [MMC_HS_200]      = "HS200 (200MHz)",
 153               [MMC_HS_400]      = "HS400 (200MHz)",
 154               [MMC_HS_400_ES]   = "HS400ES (200MHz)",
 155         };
 156
 157         if (mode >= MMC_MODES_END)
 158                 return "Unknown mode";
 159         else
 160                 return names[mode];
 161 }
 162 #endif
 163
 164 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
 165 {
 166         static const int freqs[] = {
 167               [MMC_LEGACY]      = 25000000,
 168               [MMC_HS]          = 26000000,
 169               [SD_HS]           = 50000000,
 170               [MMC_HS_52]       = 52000000,
 171               [MMC_DDR_52]      = 52000000,
 172               [UHS_SDR12]       = 25000000,
 173               [UHS_SDR25]       = 50000000,
 174               [UHS_SDR50]       = 100000000,
 175               [UHS_DDR50]       = 50000000,
 176               [UHS_SDR104]      = 208000000,
 177               [MMC_HS_200]      = 200000000,
 178               [MMC_HS_400]      = 200000000,
 179               [MMC_HS_400_ES]   = 200000000,
 180         };
 181
 182         if (mode == MMC_LEGACY)
 183                 return mmc->legacy_speed;
 184         else if (mode >= MMC_MODES_END)
 185                 return 0;
 186         else
 187                 return freqs[mode];
 188 }
 189
 190 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
 191 {
 192         mmc->selected_mode = mode;
 193         mmc->tran_speed = mmc_mode2freq(mmc, mode);
 194         mmc->ddr_mode = mmc_is_mode_ddr(mode);
 195         pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
 196                  mmc->tran_speed / 1000000);
 197         return 0;
 198 }
 199
 200 #if !CONFIG_IS_ENABLED(DM_MMC)
 201 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 202 {
 203         int ret;
 204
 205         mmmc_trace_before_send(mmc, cmd);
 206         ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 207         mmmc_trace_after_send(mmc, cmd, ret);
 208
 209         return ret;
 210 }
 211 #endif
 212
 213 /**
 214  * mmc_send_cmd_retry() - send a command to the mmc device, retrying on error
 215  *
 216  * @dev:        device to receive the command
 217  * @cmd:        command to send
 218  * @data:       additional data to send/receive
 219  * @retries:    how many times to retry; mmc_send_cmd is always called at least
 220  *              once
 221  * Return: 0 if ok, -ve on error
 222  */
 223 static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd,
 224                               struct mmc_data *data, uint retries)
 225 {
 226         int ret;
 227
 228         do {
 229                 ret = mmc_send_cmd(mmc, cmd, data);
 230         } while (ret && retries--);
 231
 232         return ret;
 233 }
 234
 235 /**
 236  * mmc_send_cmd_quirks() - send a command to the mmc device, retrying if a
 237  *                         specific quirk is enabled
 238  *
 239  * @dev:        device to receive the command
 240  * @cmd:        command to send
 241  * @data:       additional data to send/receive
 242  * @quirk:      retry only if this quirk is enabled
 243  * @retries:    how many times to retry; mmc_send_cmd is always called at least
 244  *              once
 245  * Return: 0 if ok, -ve on error
 246  */
 247 static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd,
 248                                struct mmc_data *data, u32 quirk, uint retries)
 249 {
 250         if (IS_ENABLED(CONFIG_MMC_QUIRKS) && mmc->quirks & quirk)
 251                 return mmc_send_cmd_retry(mmc, cmd, data, retries);
 252         else
 253                 return mmc_send_cmd(mmc, cmd, data);
 254 }
 255
 256 int mmc_send_status(struct mmc *mmc, unsigned int *status)
 257 {
 258         struct mmc_cmd cmd;
 259         int ret;
 260
 261         cmd.cmdidx = MMC_CMD_SEND_STATUS;
 262         cmd.resp_type = MMC_RSP_R1;
 263         if (!mmc_host_is_spi(mmc))
 264                 cmd.cmdarg = mmc->rca << 16;
 265
 266         ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 4);
 267         mmc_trace_state(mmc, &cmd);
 268         if (!ret)
 269                 *status = cmd.response[0];
 270
 271         return ret;
 272 }
 273
 274 int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
 275 {
 276         unsigned int status;
 277         int err;
 278
 279         err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 280         if (err != -ENOSYS)
 281                 return err;
 282
 283         while (1) {
 284                 err = mmc_send_status(mmc, &status);
 285                 if (err)
 286                         return err;
 287
 288                 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
 289                     (status & MMC_STATUS_CURR_STATE) !=
 290                      MMC_STATE_PRG)
 291                         break;
 292
 293                 if (status & MMC_STATUS_MASK) {
 294 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 295                         pr_err("Status Error: 0x%08x\n", status);
 296 #endif
 297                         return -ECOMM;
 298                 }
 299
 300                 if (timeout_ms-- <= 0)
 301                         break;
 302
 303                 udelay(1000);
 304         }
 305
 306         if (timeout_ms <= 0) {
 307 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 308                 pr_err("Timeout waiting card ready\n");
 309 #endif
 310                 return -ETIMEDOUT;
 311         }
 312
 313         return 0;
 314 }
 315
 316 int mmc_set_blocklen(struct mmc *mmc, int len)
 317 {
 318         struct mmc_cmd cmd;
 319
 320         if (mmc->ddr_mode)
 321                 return 0;
 322
 323         cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
 324         cmd.resp_type = MMC_RSP_R1;
 325         cmd.cmdarg = len;
 326
 327         return mmc_send_cmd_quirks(mmc, &cmd, NULL,
 328                                    MMC_QUIRK_RETRY_SET_BLOCKLEN, 4);
 329 }
 330
 331 #ifdef MMC_SUPPORTS_TUNING
 332 static const u8 tuning_blk_pattern_4bit[] = {
 333         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 334         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 335         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 336         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 337         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 338         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 339         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 340         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 341 };
 342
 343 static const u8 tuning_blk_pattern_8bit[] = {
 344         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 345         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 346         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 347         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 348         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 349         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 350         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 351         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 352         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 353         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 354         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 355         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 356         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 357         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 358         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 359         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 360 };
 361
 362 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
 363 {
 364         struct mmc_cmd cmd;
 365         struct mmc_data data;
 366         const u8 *tuning_block_pattern;
 367         int size, err;
 368
 369         if (mmc->bus_width == 8) {
 370                 tuning_block_pattern = tuning_blk_pattern_8bit;
 371                 size = sizeof(tuning_blk_pattern_8bit);
 372         } else if (mmc->bus_width == 4) {
 373                 tuning_block_pattern = tuning_blk_pattern_4bit;
 374                 size = sizeof(tuning_blk_pattern_4bit);
 375         } else {
 376                 return -EINVAL;
 377         }
 378
 379         ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
 380
 381         cmd.cmdidx = opcode;
 382         cmd.cmdarg = 0;
 383         cmd.resp_type = MMC_RSP_R1;
 384
 385         data.dest = (void *)data_buf;
 386         data.blocks = 1;
 387         data.blocksize = size;
 388         data.flags = MMC_DATA_READ;
 389
 390         err = mmc_send_cmd(mmc, &cmd, &data);
 391         if (err)
 392                 return err;
 393
 394         if (memcmp(data_buf, tuning_block_pattern, size))
 395                 return -EIO;
 396
 397         return 0;
 398 }
 399 #endif
 400
 401 int mmc_send_stop_transmission(struct mmc *mmc, bool write)
 402 {
 403         struct mmc_cmd cmd;
 404
 405         cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 406         cmd.cmdarg = 0;
 407         /*
 408          * JEDEC Standard No. 84-B51 Page 126
 409          * CMD12 STOP_TRANSMISSION R1/R1b[3]
 410          * NOTE 3 R1 for read cases and R1b for write cases.
 411          *
 412          * Physical Layer Simplified Specification Version 9.00
 413          * 7.3.1.3 Detailed Command Description
 414          * CMD12 R1b
 415          */
 416         cmd.resp_type = (IS_SD(mmc) || write) ? MMC_RSP_R1b : MMC_RSP_R1;
 417
 418         return mmc_send_cmd(mmc, &cmd, NULL);
 419 }
 420
 421 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 422                            lbaint_t blkcnt)
 423 {
 424         struct mmc_cmd cmd;
 425         struct mmc_data data;
 426
 427         if (blkcnt > 1)
 428                 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
 429         else
 430                 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
 431
 432         if (mmc->high_capacity)
 433                 cmd.cmdarg = start;
 434         else
 435                 cmd.cmdarg = start * mmc->read_bl_len;
 436
 437         cmd.resp_type = MMC_RSP_R1;
 438
 439         data.dest = dst;
 440         data.blocks = blkcnt;
 441         data.blocksize = mmc->read_bl_len;
 442         data.flags = MMC_DATA_READ;
 443
 444         if (mmc_send_cmd(mmc, &cmd, &data))
 445                 return 0;
 446
 447         if (blkcnt > 1) {
 448                 if (mmc_send_stop_transmission(mmc, false)) {
 449 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 450                         pr_err("mmc fail to send stop cmd\n");
 451 #endif
 452                         return 0;
 453                 }
 454         }
 455
 456         return blkcnt;
 457 }
 458
 459 #if !CONFIG_IS_ENABLED(DM_MMC)
 460 static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
 461 {
 462         if (mmc->cfg->ops->get_b_max)
 463                 return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
 464         else
 465                 return mmc->cfg->b_max;
 466 }
 467 #endif
 468
 469 #if CONFIG_IS_ENABLED(BLK)
 470 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
 471 #else
 472 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 473                 void *dst)
 474 #endif
 475 {
 476 #if CONFIG_IS_ENABLED(BLK)
 477         struct blk_desc *block_dev = dev_get_uclass_plat(dev);
 478 #endif
 479         int dev_num = block_dev->devnum;
 480         int err;
 481         lbaint_t cur, blocks_todo = blkcnt;
 482         uint b_max;
 483
 484         if (blkcnt == 0)
 485                 return 0;
 486
 487         struct mmc *mmc = find_mmc_device(dev_num);
 488         if (!mmc)
 489                 return 0;
 490
 491         if (CONFIG_IS_ENABLED(MMC_TINY))
 492                 err = mmc_switch_part(mmc, block_dev->hwpart);
 493         else
 494                 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
 495
 496         if (err < 0)
 497                 return 0;
 498
 499         if ((start + blkcnt) > block_dev->lba) {
 500 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 501                 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
 502                        start + blkcnt, block_dev->lba);
 503 #endif
 504                 return 0;
 505         }
 506
 507         if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
 508                 pr_debug("%s: Failed to set blocklen\n", __func__);
 509                 return 0;
 510         }
 511
 512         b_max = mmc_get_b_max(mmc, dst, blkcnt);
 513
 514         do {
 515                 cur = (blocks_todo > b_max) ? b_max : blocks_todo;
 516                 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
 517                         pr_debug("%s: Failed to read blocks\n", __func__);
 518                         return 0;
 519                 }
 520                 blocks_todo -= cur;
 521                 start += cur;
 522                 dst += cur * mmc->read_bl_len;
 523         } while (blocks_todo > 0);
 524
 525         return blkcnt;
 526 }
 527
 528 static int mmc_go_idle(struct mmc *mmc)
 529 {
 530         struct mmc_cmd cmd;
 531         int err;
 532
 533         udelay(1000);
 534
 535         cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
 536         cmd.cmdarg = 0;
 537         cmd.resp_type = MMC_RSP_NONE;
 538
 539         err = mmc_send_cmd(mmc, &cmd, NULL);
 540
 541         if (err)
 542                 return err;
 543
 544         udelay(2000);
 545
 546         return 0;
 547 }
 548
 549 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 550 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
 551 {
 552         struct mmc_cmd cmd;
 553         int err = 0;
 554
 555         /*
 556          * Send CMD11 only if the request is to switch the card to
 557          * 1.8V signalling.
 558          */
 559         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 560                 return mmc_set_signal_voltage(mmc, signal_voltage);
 561
 562         cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
 563         cmd.cmdarg = 0;
 564         cmd.resp_type = MMC_RSP_R1;
 565
 566         err = mmc_send_cmd(mmc, &cmd, NULL);
 567         if (err)
 568                 return err;
 569
 570         if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
 571                 return -EIO;
 572
 573         /*
 574          * The card should drive cmd and dat[0:3] low immediately
 575          * after the response of cmd11, but wait 100 us to be sure
 576          */
 577         err = mmc_wait_dat0(mmc, 0, 100);
 578         if (err == -ENOSYS)
 579                 udelay(100);
 580         else if (err)
 581                 return -ETIMEDOUT;
 582
 583         /*
 584          * During a signal voltage level switch, the clock must be gated
 585          * for 5 ms according to the SD spec
 586          */
 587         mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
 588
 589         err = mmc_set_signal_voltage(mmc, signal_voltage);
 590         if (err)
 591                 return err;
 592
 593         /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
 594         mdelay(10);
 595         mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
 596
 597         /*
 598          * Failure to switch is indicated by the card holding
 599          * dat[0:3] low. Wait for at least 1 ms according to spec
 600          */
 601         err = mmc_wait_dat0(mmc, 1, 1000);
 602         if (err == -ENOSYS)
 603                 udelay(1000);
 604         else if (err)
 605                 return -ETIMEDOUT;
 606
 607         return 0;
 608 }
 609 #endif
 610
 611 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
 612 {
 613         int timeout = 1000;
 614         int err;
 615         struct mmc_cmd cmd;
 616
 617         while (1) {
 618                 cmd.cmdidx = MMC_CMD_APP_CMD;
 619                 cmd.resp_type = MMC_RSP_R1;
 620                 cmd.cmdarg = 0;
 621
 622                 err = mmc_send_cmd(mmc, &cmd, NULL);
 623
 624                 if (err)
 625                         return err;
 626
 627                 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
 628                 cmd.resp_type = MMC_RSP_R3;
 629
 630                 /*
 631                  * Most cards do not answer if some reserved bits
 632                  * in the ocr are set. However, Some controller
 633                  * can set bit 7 (reserved for low voltages), but
 634                  * how to manage low voltages SD card is not yet
 635                  * specified.
 636                  */
 637                 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
 638                         (mmc->cfg->voltages & 0xff8000);
 639
 640                 if (mmc->version == SD_VERSION_2)
 641                         cmd.cmdarg |= OCR_HCS;
 642
 643                 if (uhs_en)
 644                         cmd.cmdarg |= OCR_S18R;
 645
 646                 err = mmc_send_cmd(mmc, &cmd, NULL);
 647
 648                 if (err)
 649                         return err;
 650
 651                 if (cmd.response[0] & OCR_BUSY)
 652                         break;
 653
 654                 if (timeout-- <= 0)
 655                         return -EOPNOTSUPP;
 656
 657                 udelay(1000);
 658         }
 659
 660         if (mmc->version != SD_VERSION_2)
 661                 mmc->version = SD_VERSION_1_0;
 662
 663         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 664                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 665                 cmd.resp_type = MMC_RSP_R3;
 666                 cmd.cmdarg = 0;
 667
 668                 err = mmc_send_cmd(mmc, &cmd, NULL);
 669
 670                 if (err)
 671                         return err;
 672         }
 673
 674         mmc->ocr = cmd.response[0];
 675
 676 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 677         if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
 678             == 0x41000000) {
 679                 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
 680                 if (err)
 681                         return err;
 682         }
 683 #endif
 684
 685         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 686         mmc->rca = 0;
 687
 688         return 0;
 689 }
 690
 691 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
 692 {
 693         struct mmc_cmd cmd;
 694         int err;
 695
 696         cmd.cmdidx = MMC_CMD_SEND_OP_COND;
 697         cmd.resp_type = MMC_RSP_R3;
 698         cmd.cmdarg = 0;
 699         if (use_arg && !mmc_host_is_spi(mmc))
 700                 cmd.cmdarg = OCR_HCS |
 701                         (mmc->cfg->voltages &
 702                         (mmc->ocr & OCR_VOLTAGE_MASK)) |
 703                         (mmc->ocr & OCR_ACCESS_MODE);
 704
 705         err = mmc_send_cmd(mmc, &cmd, NULL);
 706         if (err)
 707                 return err;
 708         mmc->ocr = cmd.response[0];
 709         return 0;
 710 }
 711
 712 static int mmc_send_op_cond(struct mmc *mmc)
 713 {
 714         int err, i;
 715         int timeout = 1000;
 716         uint start;
 717
 718         /* Some cards seem to need this */
 719         mmc_go_idle(mmc);
 720
 721         start = get_timer(0);
 722         /* Asking to the card its capabilities */
 723         for (i = 0; ; i++) {
 724                 err = mmc_send_op_cond_iter(mmc, i != 0);
 725                 if (err)
 726                         return err;
 727
 728                 /* exit if not busy (flag seems to be inverted) */
 729                 if (mmc->ocr & OCR_BUSY)
 730                         break;
 731
 732                 if (get_timer(start) > timeout)
 733                         return -ETIMEDOUT;
 734                 udelay(100);
 735         }
 736         mmc->op_cond_pending = 1;
 737         return 0;
 738 }
 739
 740 static int mmc_complete_op_cond(struct mmc *mmc)
 741 {
 742         struct mmc_cmd cmd;
 743         int timeout = 1000;
 744         ulong start;
 745         int err;
 746
 747         mmc->op_cond_pending = 0;
 748         if (!(mmc->ocr & OCR_BUSY)) {
 749                 /* Some cards seem to need this */
 750                 mmc_go_idle(mmc);
 751
 752                 start = get_timer(0);
 753                 while (1) {
 754                         err = mmc_send_op_cond_iter(mmc, 1);
 755                         if (err)
 756                                 return err;
 757                         if (mmc->ocr & OCR_BUSY)
 758                                 break;
 759                         if (get_timer(start) > timeout)
 760                                 return -EOPNOTSUPP;
 761                         udelay(100);
 762                 }
 763         }
 764
 765         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 766                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 767                 cmd.resp_type = MMC_RSP_R3;
 768                 cmd.cmdarg = 0;
 769
 770                 err = mmc_send_cmd(mmc, &cmd, NULL);
 771
 772                 if (err)
 773                         return err;
 774
 775                 mmc->ocr = cmd.response[0];
 776         }
 777
 778         mmc->version = MMC_VERSION_UNKNOWN;
 779
 780         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 781         mmc->rca = 1;
 782
 783         return 0;
 784 }
 785
 786
 787 int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 788 {
 789         struct mmc_cmd cmd;
 790         struct mmc_data data;
 791         int err;
 792
 793         /* Get the Card Status Register */
 794         cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
 795         cmd.resp_type = MMC_RSP_R1;
 796         cmd.cmdarg = 0;
 797
 798         data.dest = (char *)ext_csd;
 799         data.blocks = 1;
 800         data.blocksize = MMC_MAX_BLOCK_LEN;
 801         data.flags = MMC_DATA_READ;
 802
 803         err = mmc_send_cmd(mmc, &cmd, &data);
 804
 805         return err;
 806 }
 807
 808 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 809                         bool send_status)
 810 {
 811         unsigned int status, start;
 812         struct mmc_cmd cmd;
 813         int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
 814         bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
 815                               (index == EXT_CSD_PART_CONF);
 816         int ret;
 817
 818         if (mmc->gen_cmd6_time)
 819                 timeout_ms = mmc->gen_cmd6_time * 10;
 820
 821         if (is_part_switch  && mmc->part_switch_time)
 822                 timeout_ms = mmc->part_switch_time * 10;
 823
 824         cmd.cmdidx = MMC_CMD_SWITCH;
 825         cmd.resp_type = MMC_RSP_R1b;
 826         cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
 827                                  (index << 16) |
 828                                  (value << 8);
 829
 830         ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 3);
 831         if (ret)
 832                 return ret;
 833
 834         start = get_timer(0);
 835
 836         /* poll dat0 for rdy/buys status */
 837         ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 838         if (ret && ret != -ENOSYS)
 839                 return ret;
 840
 841         /*
 842          * In cases when neiter allowed to poll by using CMD13 nor we are
 843          * capable of polling by using mmc_wait_dat0, then rely on waiting the
 844          * stated timeout to be sufficient.
 845          */
 846         if (ret == -ENOSYS && !send_status) {
 847                 mdelay(timeout_ms);
 848                 return 0;
 849         }
 850
 851         if (!send_status)
 852                 return 0;
 853
 854         /* Finally wait until the card is ready or indicates a failure
 855          * to switch. It doesn't hurt to use CMD13 here even if send_status
 856          * is false, because by now (after 'timeout_ms' ms) the bus should be
 857          * reliable.
 858          */
 859         do {
 860                 ret = mmc_send_status(mmc, &status);
 861
 862                 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
 863                         pr_debug("switch failed %d/%d/0x%x !\n", set, index,
 864                                  value);
 865                         return -EIO;
 866                 }
 867                 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA) &&
 868                     (status & MMC_STATUS_CURR_STATE) == MMC_STATE_TRANS)
 869                         return 0;
 870                 udelay(100);
 871         } while (get_timer(start) < timeout_ms);
 872
 873         return -ETIMEDOUT;
 874 }
 875
 876 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 877 {
 878         return __mmc_switch(mmc, set, index, value, true);
 879 }
 880
 881 int mmc_boot_wp(struct mmc *mmc)
 882 {
 883         return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
 884 }
 885
 886 int mmc_boot_wp_single_partition(struct mmc *mmc, int partition)
 887 {
 888         u8 value;
 889         int ret;
 890
 891         value = EXT_CSD_BOOT_WP_B_PWR_WP_EN;
 892
 893         if (partition == 0) {
 894                 value |= EXT_CSD_BOOT_WP_B_SEC_WP_SEL;
 895                 ret = mmc_switch(mmc,
 896                                  EXT_CSD_CMD_SET_NORMAL,
 897                                  EXT_CSD_BOOT_WP,
 898                                  value);
 899         } else if (partition == 1) {
 900                 value |= EXT_CSD_BOOT_WP_B_SEC_WP_SEL;
 901                 value |= EXT_CSD_BOOT_WP_B_PWR_WP_SEC_SEL;
 902                 ret = mmc_switch(mmc,
 903                                  EXT_CSD_CMD_SET_NORMAL,
 904                                  EXT_CSD_BOOT_WP,
 905                                  value);
 906         } else {
 907                 ret = mmc_boot_wp(mmc);
 908         }
 909
 910         return ret;
 911 }
 912
 913 #if !CONFIG_IS_ENABLED(MMC_TINY)
 914 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
 915                               bool hsdowngrade)
 916 {
 917         int err;
 918         int speed_bits;
 919
 920         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 921
 922         switch (mode) {
 923         case MMC_HS:
 924         case MMC_HS_52:
 925         case MMC_DDR_52:
 926                 speed_bits = EXT_CSD_TIMING_HS;
 927                 break;
 928 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 929         case MMC_HS_200:
 930                 speed_bits = EXT_CSD_TIMING_HS200;
 931                 break;
 932 #endif
 933 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 934         case MMC_HS_400:
 935                 speed_bits = EXT_CSD_TIMING_HS400;
 936                 break;
 937 #endif
 938 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 939         case MMC_HS_400_ES:
 940                 speed_bits = EXT_CSD_TIMING_HS400;
 941                 break;
 942 #endif
 943         case MMC_LEGACY:
 944                 speed_bits = EXT_CSD_TIMING_LEGACY;
 945                 break;
 946         default:
 947                 return -EINVAL;
 948         }
 949
 950         err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
 951                            speed_bits, !hsdowngrade);
 952         if (err)
 953                 return err;
 954
 955 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 956     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 957         /*
 958          * In case the eMMC is in HS200/HS400 mode and we are downgrading
 959          * to HS mode, the card clock are still running much faster than
 960          * the supported HS mode clock, so we can not reliably read out
 961          * Extended CSD. Reconfigure the controller to run at HS mode.
 962          */
 963         if (hsdowngrade) {
 964                 mmc_select_mode(mmc, MMC_HS);
 965                 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
 966         }
 967 #endif
 968
 969         if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
 970                 /* Now check to see that it worked */
 971                 err = mmc_send_ext_csd(mmc, test_csd);
 972                 if (err)
 973                         return err;
 974
 975                 /* No high-speed support */
 976                 if (!test_csd[EXT_CSD_HS_TIMING])
 977                         return -ENOTSUPP;
 978         }
 979
 980         return 0;
 981 }
 982
 983 static int mmc_get_capabilities(struct mmc *mmc)
 984 {
 985         u8 *ext_csd = mmc->ext_csd;
 986         char cardtype;
 987
 988         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
 989
 990         if (mmc_host_is_spi(mmc))
 991                 return 0;
 992
 993         /* Only version 4 supports high-speed */
 994         if (mmc->version < MMC_VERSION_4)
 995                 return 0;
 996
 997         if (!ext_csd) {
 998                 pr_err("No ext_csd found!\n"); /* this should enver happen */
 999                 return -ENOTSUPP;
1000         }
1001
1002         mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
1003
1004         cardtype = ext_csd[EXT_CSD_CARD_TYPE];
1005         mmc->cardtype = cardtype;
1006
1007 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1008         if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1009                         EXT_CSD_CARD_TYPE_HS200_1_8V)) {
1010                 mmc->card_caps |= MMC_MODE_HS200;
1011         }
1012 #endif
1013 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
1014         CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1015         if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
1016                         EXT_CSD_CARD_TYPE_HS400_1_8V)) {
1017                 mmc->card_caps |= MMC_MODE_HS400;
1018         }
1019 #endif
1020         if (cardtype & EXT_CSD_CARD_TYPE_52) {
1021                 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
1022                         mmc->card_caps |= MMC_MODE_DDR_52MHz;
1023                 mmc->card_caps |= MMC_MODE_HS_52MHz;
1024         }
1025         if (cardtype & EXT_CSD_CARD_TYPE_26)
1026                 mmc->card_caps |= MMC_MODE_HS;
1027
1028 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1029         if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
1030             (mmc->card_caps & MMC_MODE_HS400)) {
1031                 mmc->card_caps |= MMC_MODE_HS400_ES;
1032         }
1033 #endif
1034
1035         return 0;
1036 }
1037 #endif
1038
1039 static int mmc_set_capacity(struct mmc *mmc, int part_num)
1040 {
1041         switch (part_num) {
1042         case 0:
1043                 mmc->capacity = mmc->capacity_user;
1044                 break;
1045         case 1:
1046         case 2:
1047                 mmc->capacity = mmc->capacity_boot;
1048                 break;
1049         case 3:
1050                 mmc->capacity = mmc->capacity_rpmb;
1051                 break;
1052         case 4:
1053         case 5:
1054         case 6:
1055         case 7:
1056                 mmc->capacity = mmc->capacity_gp[part_num - 4];
1057                 break;
1058         default:
1059                 return -1;
1060         }
1061
1062         mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1063
1064         return 0;
1065 }
1066
1067 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
1068 {
1069         int ret;
1070         int retry = 3;
1071
1072         do {
1073                 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1074                                  EXT_CSD_PART_CONF,
1075                                  (mmc->part_config & ~PART_ACCESS_MASK)
1076                                  | (part_num & PART_ACCESS_MASK));
1077         } while (ret && retry--);
1078
1079         /*
1080          * Set the capacity if the switch succeeded or was intended
1081          * to return to representing the raw device.
1082          */
1083         if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
1084                 ret = mmc_set_capacity(mmc, part_num);
1085                 mmc_get_blk_desc(mmc)->hwpart = part_num;
1086         }
1087
1088         return ret;
1089 }
1090
1091 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
1092 int mmc_hwpart_config(struct mmc *mmc,
1093                       const struct mmc_hwpart_conf *conf,
1094                       enum mmc_hwpart_conf_mode mode)
1095 {
1096         u8 part_attrs = 0;
1097         u32 enh_size_mult;
1098         u32 enh_start_addr;
1099         u32 gp_size_mult[4];
1100         u32 max_enh_size_mult;
1101         u32 tot_enh_size_mult = 0;
1102         u8 wr_rel_set;
1103         int i, pidx, err;
1104         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1105
1106         if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1107                 return -EINVAL;
1108
1109         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
1110                 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
1111                 return -EMEDIUMTYPE;
1112         }
1113
1114         if (!(mmc->part_support & PART_SUPPORT)) {
1115                 pr_err("Card does not support partitioning\n");
1116                 return -EMEDIUMTYPE;
1117         }
1118
1119         if (!mmc->hc_wp_grp_size) {
1120                 pr_err("Card does not define HC WP group size\n");
1121                 return -EMEDIUMTYPE;
1122         }
1123
1124         /* check partition alignment and total enhanced size */
1125         if (conf->user.enh_size) {
1126                 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1127                     conf->user.enh_start % mmc->hc_wp_grp_size) {
1128                         pr_err("User data enhanced area not HC WP group "
1129                                "size aligned\n");
1130                         return -EINVAL;
1131                 }
1132                 part_attrs |= EXT_CSD_ENH_USR;
1133                 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1134                 if (mmc->high_capacity) {
1135                         enh_start_addr = conf->user.enh_start;
1136                 } else {
1137                         enh_start_addr = (conf->user.enh_start << 9);
1138                 }
1139         } else {
1140                 enh_size_mult = 0;
1141                 enh_start_addr = 0;
1142         }
1143         tot_enh_size_mult += enh_size_mult;
1144
1145         for (pidx = 0; pidx < 4; pidx++) {
1146                 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1147                         pr_err("GP%i partition not HC WP group size "
1148                                "aligned\n", pidx+1);
1149                         return -EINVAL;
1150                 }
1151                 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1152                 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1153                         part_attrs |= EXT_CSD_ENH_GP(pidx);
1154                         tot_enh_size_mult += gp_size_mult[pidx];
1155                 }
1156         }
1157
1158         if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1159                 pr_err("Card does not support enhanced attribute\n");
1160                 return -EMEDIUMTYPE;
1161         }
1162
1163         err = mmc_send_ext_csd(mmc, ext_csd);
1164         if (err)
1165                 return err;
1166
1167         max_enh_size_mult =
1168                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1169                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1170                 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1171         if (tot_enh_size_mult > max_enh_size_mult) {
1172                 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1173                        tot_enh_size_mult, max_enh_size_mult);
1174                 return -EMEDIUMTYPE;
1175         }
1176
1177         /* The default value of EXT_CSD_WR_REL_SET is device
1178          * dependent, the values can only be changed if the
1179          * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1180          * changed only once and before partitioning is completed. */
1181         wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1182         if (conf->user.wr_rel_change) {
1183                 if (conf->user.wr_rel_set)
1184                         wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1185                 else
1186                         wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1187         }
1188         for (pidx = 0; pidx < 4; pidx++) {
1189                 if (conf->gp_part[pidx].wr_rel_change) {
1190                         if (conf->gp_part[pidx].wr_rel_set)
1191                                 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1192                         else
1193                                 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1194                 }
1195         }
1196
1197         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1198             !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1199                 puts("Card does not support host controlled partition write "
1200                      "reliability settings\n");
1201                 return -EMEDIUMTYPE;
1202         }
1203
1204         if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1205             EXT_CSD_PARTITION_SETTING_COMPLETED) {
1206                 pr_err("Card already partitioned\n");
1207                 return -EPERM;
1208         }
1209
1210         if (mode == MMC_HWPART_CONF_CHECK)
1211                 return 0;
1212
1213         /* Partitioning requires high-capacity size definitions */
1214         if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1215                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1216                                  EXT_CSD_ERASE_GROUP_DEF, 1);
1217
1218                 if (err)
1219                         return err;
1220
1221                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1222
1223 #if CONFIG_IS_ENABLED(MMC_WRITE)
1224                 /* update erase group size to be high-capacity */
1225                 mmc->erase_grp_size =
1226                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1227 #endif
1228
1229         }
1230
1231         /* all OK, write the configuration */
1232         for (i = 0; i < 4; i++) {
1233                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1234                                  EXT_CSD_ENH_START_ADDR+i,
1235                                  (enh_start_addr >> (i*8)) & 0xFF);
1236                 if (err)
1237                         return err;
1238         }
1239         for (i = 0; i < 3; i++) {
1240                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1241                                  EXT_CSD_ENH_SIZE_MULT+i,
1242                                  (enh_size_mult >> (i*8)) & 0xFF);
1243                 if (err)
1244                         return err;
1245         }
1246         for (pidx = 0; pidx < 4; pidx++) {
1247                 for (i = 0; i < 3; i++) {
1248                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1249                                          EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1250                                          (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1251                         if (err)
1252                                 return err;
1253                 }
1254         }
1255         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1256                          EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1257         if (err)
1258                 return err;
1259
1260         if (mode == MMC_HWPART_CONF_SET)
1261                 return 0;
1262
1263         /* The WR_REL_SET is a write-once register but shall be
1264          * written before setting PART_SETTING_COMPLETED. As it is
1265          * write-once we can only write it when completing the
1266          * partitioning. */
1267         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1268                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1269                                  EXT_CSD_WR_REL_SET, wr_rel_set);
1270                 if (err)
1271                         return err;
1272         }
1273
1274         /* Setting PART_SETTING_COMPLETED confirms the partition
1275          * configuration but it only becomes effective after power
1276          * cycle, so we do not adjust the partition related settings
1277          * in the mmc struct. */
1278
1279         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1280                          EXT_CSD_PARTITION_SETTING,
1281                          EXT_CSD_PARTITION_SETTING_COMPLETED);
1282         if (err)
1283                 return err;
1284
1285         return 0;
1286 }
1287 #endif
1288
1289 #if !CONFIG_IS_ENABLED(DM_MMC)
1290 int mmc_getcd(struct mmc *mmc)
1291 {
1292         int cd;
1293
1294         cd = board_mmc_getcd(mmc);
1295
1296         if (cd < 0) {
1297                 if (mmc->cfg->ops->getcd)
1298                         cd = mmc->cfg->ops->getcd(mmc);
1299                 else
1300                         cd = 1;
1301         }
1302
1303         return cd;
1304 }
1305 #endif
1306
1307 #if !CONFIG_IS_ENABLED(MMC_TINY)
1308 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1309 {
1310         struct mmc_cmd cmd;
1311         struct mmc_data data;
1312
1313         /* Switch the frequency */
1314         cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1315         cmd.resp_type = MMC_RSP_R1;
1316         cmd.cmdarg = (mode << 31) | 0xffffff;
1317         cmd.cmdarg &= ~(0xf << (group * 4));
1318         cmd.cmdarg |= value << (group * 4);
1319
1320         data.dest = (char *)resp;
1321         data.blocksize = 64;
1322         data.blocks = 1;
1323         data.flags = MMC_DATA_READ;
1324
1325         return mmc_send_cmd(mmc, &cmd, &data);
1326 }
1327
1328 static int sd_get_capabilities(struct mmc *mmc)
1329 {
1330         int err;
1331         struct mmc_cmd cmd;
1332         ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1333         ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1334         struct mmc_data data;
1335         int timeout;
1336 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1337         u32 sd3_bus_mode;
1338 #endif
1339
1340         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
1341
1342         if (mmc_host_is_spi(mmc))
1343                 return 0;
1344
1345         /* Read the SCR to find out if this card supports higher speeds */
1346         cmd.cmdidx = MMC_CMD_APP_CMD;
1347         cmd.resp_type = MMC_RSP_R1;
1348         cmd.cmdarg = mmc->rca << 16;
1349
1350         err = mmc_send_cmd(mmc, &cmd, NULL);
1351
1352         if (err)
1353                 return err;
1354
1355         cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1356         cmd.resp_type = MMC_RSP_R1;
1357         cmd.cmdarg = 0;
1358
1359         data.dest = (char *)scr;
1360         data.blocksize = 8;
1361         data.blocks = 1;
1362         data.flags = MMC_DATA_READ;
1363
1364         err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
1365
1366         if (err)
1367                 return err;
1368
1369         mmc->scr[0] = __be32_to_cpu(scr[0]);
1370         mmc->scr[1] = __be32_to_cpu(scr[1]);
1371
1372         switch ((mmc->scr[0] >> 24) & 0xf) {
1373         case 0:
1374                 mmc->version = SD_VERSION_1_0;
1375                 break;
1376         case 1:
1377                 mmc->version = SD_VERSION_1_10;
1378                 break;
1379         case 2:
1380                 mmc->version = SD_VERSION_2;
1381                 if ((mmc->scr[0] >> 15) & 0x1)
1382                         mmc->version = SD_VERSION_3;
1383                 break;
1384         default:
1385                 mmc->version = SD_VERSION_1_0;
1386                 break;
1387         }
1388
1389         if (mmc->scr[0] & SD_DATA_4BIT)
1390                 mmc->card_caps |= MMC_MODE_4BIT;
1391
1392         /* Version 1.0 doesn't support switching */
1393         if (mmc->version == SD_VERSION_1_0)
1394                 return 0;
1395
1396         timeout = 4;
1397         while (timeout--) {
1398                 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1399                                 (u8 *)switch_status);
1400
1401                 if (err)
1402                         return err;
1403
1404                 /* The high-speed function is busy.  Try again */
1405                 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1406                         break;
1407         }
1408
1409         /* If high-speed isn't supported, we return */
1410         if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1411                 mmc->card_caps |= MMC_CAP(SD_HS);
1412
1413 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1414         /* Version before 3.0 don't support UHS modes */
1415         if (mmc->version < SD_VERSION_3)
1416                 return 0;
1417
1418         sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1419         if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1420                 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1421         if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1422                 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1423         if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1424                 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1425         if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1426                 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1427         if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1428                 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1429 #endif
1430
1431         return 0;
1432 }
1433
1434 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1435 {
1436         int err;
1437
1438         ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1439         int speed;
1440
1441         /* SD version 1.00 and 1.01 does not support CMD 6 */
1442         if (mmc->version == SD_VERSION_1_0)
1443                 return 0;
1444
1445         switch (mode) {
1446         case MMC_LEGACY:
1447                 speed = UHS_SDR12_BUS_SPEED;
1448                 break;
1449         case SD_HS:
1450                 speed = HIGH_SPEED_BUS_SPEED;
1451                 break;
1452 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1453         case UHS_SDR12:
1454                 speed = UHS_SDR12_BUS_SPEED;
1455                 break;
1456         case UHS_SDR25:
1457                 speed = UHS_SDR25_BUS_SPEED;
1458                 break;
1459         case UHS_SDR50:
1460                 speed = UHS_SDR50_BUS_SPEED;
1461                 break;
1462         case UHS_DDR50:
1463                 speed = UHS_DDR50_BUS_SPEED;
1464                 break;
1465         case UHS_SDR104:
1466                 speed = UHS_SDR104_BUS_SPEED;
1467                 break;
1468 #endif
1469         default:
1470                 return -EINVAL;
1471         }
1472
1473         err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1474         if (err)
1475                 return err;
1476
1477         if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1478                 return -ENOTSUPP;
1479
1480         return 0;
1481 }
1482
1483 static int sd_select_bus_width(struct mmc *mmc, int w)
1484 {
1485         int err;
1486         struct mmc_cmd cmd;
1487
1488         if ((w != 4) && (w != 1))
1489                 return -EINVAL;
1490
1491         cmd.cmdidx = MMC_CMD_APP_CMD;
1492         cmd.resp_type = MMC_RSP_R1;
1493         cmd.cmdarg = mmc->rca << 16;
1494
1495         err = mmc_send_cmd(mmc, &cmd, NULL);
1496         if (err)
1497                 return err;
1498
1499         cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1500         cmd.resp_type = MMC_RSP_R1;
1501         if (w == 4)
1502                 cmd.cmdarg = 2;
1503         else if (w == 1)
1504                 cmd.cmdarg = 0;
1505         err = mmc_send_cmd(mmc, &cmd, NULL);
1506         if (err)
1507                 return err;
1508
1509         return 0;
1510 }
1511 #endif
1512
1513 #if CONFIG_IS_ENABLED(MMC_WRITE)
1514 static int sd_read_ssr(struct mmc *mmc)
1515 {
1516         static const unsigned int sd_au_size[] = {
1517                 0,              SZ_16K / 512,           SZ_32K / 512,
1518                 SZ_64K / 512,   SZ_128K / 512,          SZ_256K / 512,
1519                 SZ_512K / 512,  SZ_1M / 512,            SZ_2M / 512,
1520                 SZ_4M / 512,    SZ_8M / 512,            (SZ_8M + SZ_4M) / 512,
1521                 SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1522                 SZ_64M / 512,
1523         };
1524         int err, i;
1525         struct mmc_cmd cmd;
1526         ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1527         struct mmc_data data;
1528         unsigned int au, eo, et, es;
1529
1530         cmd.cmdidx = MMC_CMD_APP_CMD;
1531         cmd.resp_type = MMC_RSP_R1;
1532         cmd.cmdarg = mmc->rca << 16;
1533
1534         err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_APP_CMD, 4);
1535         if (err)
1536                 return err;
1537
1538         cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1539         cmd.resp_type = MMC_RSP_R1;
1540         cmd.cmdarg = 0;
1541
1542         data.dest = (char *)ssr;
1543         data.blocksize = 64;
1544         data.blocks = 1;
1545         data.flags = MMC_DATA_READ;
1546
1547         err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
1548         if (err)
1549                 return err;
1550
1551         for (i = 0; i < 16; i++)
1552                 ssr[i] = be32_to_cpu(ssr[i]);
1553
1554         au = (ssr[2] >> 12) & 0xF;
1555         if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1556                 mmc->ssr.au = sd_au_size[au];
1557                 es = (ssr[3] >> 24) & 0xFF;
1558                 es |= (ssr[2] & 0xFF) << 8;
1559                 et = (ssr[3] >> 18) & 0x3F;
1560                 if (es && et) {
1561                         eo = (ssr[3] >> 16) & 0x3;
1562                         mmc->ssr.erase_timeout = (et * 1000) / es;
1563                         mmc->ssr.erase_offset = eo * 1000;
1564                 }
1565         } else {
1566                 pr_debug("Invalid Allocation Unit Size.\n");
1567         }
1568
1569         return 0;
1570 }
1571 #endif
1572 /* frequency bases */
1573 /* divided by 10 to be nice to platforms without floating point */
1574 static const int fbase[] = {
1575         10000,
1576         100000,
1577         1000000,
1578         10000000,
1579 };
1580
1581 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
1582  * to platforms without floating point.
1583  */
1584 static const u8 multipliers[] = {
1585         0,      /* reserved */
1586         10,
1587         12,
1588         13,
1589         15,
1590         20,
1591         25,
1592         30,
1593         35,
1594         40,
1595         45,
1596         50,
1597         55,
1598         60,
1599         70,
1600         80,
1601 };
1602
1603 static inline int bus_width(uint cap)
1604 {
1605         if (cap == MMC_MODE_8BIT)
1606                 return 8;
1607         if (cap == MMC_MODE_4BIT)
1608                 return 4;
1609         if (cap == MMC_MODE_1BIT)
1610                 return 1;
1611         pr_warn("invalid bus witdh capability 0x%x\n", cap);
1612         return 0;
1613 }
1614
1615 #if !CONFIG_IS_ENABLED(DM_MMC)
1616 #ifdef MMC_SUPPORTS_TUNING
1617 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1618 {
1619         return -ENOTSUPP;
1620 }
1621 #endif
1622
1623 static int mmc_set_ios(struct mmc *mmc)
1624 {
1625         int ret = 0;
1626
1627         if (mmc->cfg->ops->set_ios)
1628                 ret = mmc->cfg->ops->set_ios(mmc);
1629
1630         return ret;
1631 }
1632
1633 static int mmc_host_power_cycle(struct mmc *mmc)
1634 {
1635         int ret = 0;
1636
1637         if (mmc->cfg->ops->host_power_cycle)
1638                 ret = mmc->cfg->ops->host_power_cycle(mmc);
1639
1640         return ret;
1641 }
1642 #endif
1643
1644 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1645 {
1646         if (!disable) {
1647                 if (clock > mmc->cfg->f_max)
1648                         clock = mmc->cfg->f_max;
1649
1650                 if (clock < mmc->cfg->f_min)
1651                         clock = mmc->cfg->f_min;
1652         }
1653
1654         mmc->clock = clock;
1655         mmc->clk_disable = disable;
1656
1657         debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1658
1659         return mmc_set_ios(mmc);
1660 }
1661
1662 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1663 {
1664         mmc->bus_width = width;
1665
1666         return mmc_set_ios(mmc);
1667 }
1668
1669 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1670 /*
1671  * helper function to display the capabilities in a human
1672  * friendly manner. The capabilities include bus width and
1673  * supported modes.
1674  */
1675 void mmc_dump_capabilities(const char *text, uint caps)
1676 {
1677         enum bus_mode mode;
1678
1679         pr_debug("%s: widths [", text);
1680         if (caps & MMC_MODE_8BIT)
1681                 pr_debug("8, ");
1682         if (caps & MMC_MODE_4BIT)
1683                 pr_debug("4, ");
1684         if (caps & MMC_MODE_1BIT)
1685                 pr_debug("1, ");
1686         pr_debug("\b\b] modes [");
1687         for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1688                 if (MMC_CAP(mode) & caps)
1689                         pr_debug("%s, ", mmc_mode_name(mode));
1690         pr_debug("\b\b]\n");
1691 }
1692 #endif
1693
1694 struct mode_width_tuning {
1695         enum bus_mode mode;
1696         uint widths;
1697 #ifdef MMC_SUPPORTS_TUNING
1698         uint tuning;
1699 #endif
1700 };
1701
1702 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1703 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1704 {
1705         switch (voltage) {
1706         case MMC_SIGNAL_VOLTAGE_000: return 0;
1707         case MMC_SIGNAL_VOLTAGE_330: return 3300;
1708         case MMC_SIGNAL_VOLTAGE_180: return 1800;
1709         case MMC_SIGNAL_VOLTAGE_120: return 1200;
1710         }
1711         return -EINVAL;
1712 }
1713
1714 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1715 {
1716         int err;
1717
1718         if (mmc->signal_voltage == signal_voltage)
1719                 return 0;
1720
1721         mmc->signal_voltage = signal_voltage;
1722         err = mmc_set_ios(mmc);
1723         if (err)
1724                 pr_debug("unable to set voltage (err %d)\n", err);
1725
1726         return err;
1727 }
1728 #else
1729 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1730 {
1731         return 0;
1732 }
1733 #endif
1734
1735 #if !CONFIG_IS_ENABLED(MMC_TINY)
1736 static const struct mode_width_tuning sd_modes_by_pref[] = {
1737 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1738 #ifdef MMC_SUPPORTS_TUNING
1739         {
1740                 .mode = UHS_SDR104,
1741                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1742                 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1743         },
1744 #endif
1745         {
1746                 .mode = UHS_SDR50,
1747                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1748         },
1749         {
1750                 .mode = UHS_DDR50,
1751                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1752         },
1753         {
1754                 .mode = UHS_SDR25,
1755                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1756         },
1757 #endif
1758         {
1759                 .mode = SD_HS,
1760                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1761         },
1762 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1763         {
1764                 .mode = UHS_SDR12,
1765                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1766         },
1767 #endif
1768         {
1769                 .mode = MMC_LEGACY,
1770                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1771         }
1772 };
1773
1774 #define for_each_sd_mode_by_pref(caps, mwt) \
1775         for (mwt = sd_modes_by_pref;\
1776              mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1777              mwt++) \
1778                 if (caps & MMC_CAP(mwt->mode))
1779
1780 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1781 {
1782         int err;
1783         uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1784         const struct mode_width_tuning *mwt;
1785 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1786         bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1787 #else
1788         bool uhs_en = false;
1789 #endif
1790         uint caps;
1791
1792 #ifdef DEBUG
1793         mmc_dump_capabilities("sd card", card_caps);
1794         mmc_dump_capabilities("host", mmc->host_caps);
1795 #endif
1796
1797         if (mmc_host_is_spi(mmc)) {
1798                 mmc_set_bus_width(mmc, 1);
1799                 mmc_select_mode(mmc, MMC_LEGACY);
1800                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1801 #if CONFIG_IS_ENABLED(MMC_WRITE)
1802                 err = sd_read_ssr(mmc);
1803                 if (err)
1804                         pr_warn("unable to read ssr\n");
1805 #endif
1806                 return 0;
1807         }
1808
1809         /* Restrict card's capabilities by what the host can do */
1810         caps = card_caps & mmc->host_caps;
1811
1812         if (!uhs_en)
1813                 caps &= ~UHS_CAPS;
1814
1815         for_each_sd_mode_by_pref(caps, mwt) {
1816                 uint *w;
1817
1818                 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1819                         if (*w & caps & mwt->widths) {
1820                                 pr_debug("trying mode %s width %d (at %d MHz)\n",
1821                                          mmc_mode_name(mwt->mode),
1822                                          bus_width(*w),
1823                                          mmc_mode2freq(mmc, mwt->mode) / 1000000);
1824
1825                                 /* configure the bus width (card + host) */
1826                                 err = sd_select_bus_width(mmc, bus_width(*w));
1827                                 if (err)
1828                                         goto error;
1829                                 mmc_set_bus_width(mmc, bus_width(*w));
1830
1831                                 /* configure the bus mode (card) */
1832                                 err = sd_set_card_speed(mmc, mwt->mode);
1833                                 if (err)
1834                                         goto error;
1835
1836                                 /* configure the bus mode (host) */
1837                                 mmc_select_mode(mmc, mwt->mode);
1838                                 mmc_set_clock(mmc, mmc->tran_speed,
1839                                                 MMC_CLK_ENABLE);
1840
1841 #ifdef MMC_SUPPORTS_TUNING
1842                                 /* execute tuning if needed */
1843                                 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1844                                         err = mmc_execute_tuning(mmc,
1845                                                                  mwt->tuning);
1846                                         if (err) {
1847                                                 pr_debug("tuning failed\n");
1848                                                 goto error;
1849                                         }
1850                                 }
1851 #endif
1852
1853 #if CONFIG_IS_ENABLED(MMC_WRITE)
1854                                 err = sd_read_ssr(mmc);
1855                                 if (err)
1856                                         pr_warn("unable to read ssr\n");
1857 #endif
1858                                 if (!err)
1859                                         return 0;
1860
1861 error:
1862                                 /* revert to a safer bus speed */
1863                                 mmc_select_mode(mmc, MMC_LEGACY);
1864                                 mmc_set_clock(mmc, mmc->tran_speed,
1865                                                 MMC_CLK_ENABLE);
1866                         }
1867                 }
1868         }
1869
1870         pr_err("unable to select a mode\n");
1871         return -ENOTSUPP;
1872 }
1873
1874 /*
1875  * read the compare the part of ext csd that is constant.
1876  * This can be used to check that the transfer is working
1877  * as expected.
1878  */
1879 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1880 {
1881         int err;
1882         const u8 *ext_csd = mmc->ext_csd;
1883         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1884
1885         if (mmc->version < MMC_VERSION_4)
1886                 return 0;
1887
1888         err = mmc_send_ext_csd(mmc, test_csd);
1889         if (err)
1890                 return err;
1891
1892         /* Only compare read only fields */
1893         if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1894                 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1895             ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1896                 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1897             ext_csd[EXT_CSD_REV]
1898                 == test_csd[EXT_CSD_REV] &&
1899             ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1900                 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1901             memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1902                    &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1903                 return 0;
1904
1905         return -EBADMSG;
1906 }
1907
1908 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1909 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1910                                   uint32_t allowed_mask)
1911 {
1912         u32 card_mask = 0;
1913
1914         switch (mode) {
1915         case MMC_HS_400_ES:
1916         case MMC_HS_400:
1917         case MMC_HS_200:
1918                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1919                     EXT_CSD_CARD_TYPE_HS400_1_8V))
1920                         card_mask |= MMC_SIGNAL_VOLTAGE_180;
1921                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1922                     EXT_CSD_CARD_TYPE_HS400_1_2V))
1923                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1924                 break;
1925         case MMC_DDR_52:
1926                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1927                         card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1928                                      MMC_SIGNAL_VOLTAGE_180;
1929                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1930                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1931                 break;
1932         default:
1933                 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1934                 break;
1935         }
1936
1937         while (card_mask & allowed_mask) {
1938                 enum mmc_voltage best_match;
1939
1940                 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1941                 if (!mmc_set_signal_voltage(mmc,  best_match))
1942                         return 0;
1943
1944                 allowed_mask &= ~best_match;
1945         }
1946
1947         return -ENOTSUPP;
1948 }
1949 #else
1950 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1951                                          uint32_t allowed_mask)
1952 {
1953         return 0;
1954 }
1955 #endif
1956
1957 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1958 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1959         {
1960                 .mode = MMC_HS_400_ES,
1961                 .widths = MMC_MODE_8BIT,
1962         },
1963 #endif
1964 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1965         {
1966                 .mode = MMC_HS_400,
1967                 .widths = MMC_MODE_8BIT,
1968                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1969         },
1970 #endif
1971 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1972         {
1973                 .mode = MMC_HS_200,
1974                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1975                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1976         },
1977 #endif
1978         {
1979                 .mode = MMC_DDR_52,
1980                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1981         },
1982         {
1983                 .mode = MMC_HS_52,
1984                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1985         },
1986         {
1987                 .mode = MMC_HS,
1988                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1989         },
1990         {
1991                 .mode = MMC_LEGACY,
1992                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1993         }
1994 };
1995
1996 #define for_each_mmc_mode_by_pref(caps, mwt) \
1997         for (mwt = mmc_modes_by_pref;\
1998             mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1999             mwt++) \
2000                 if (caps & MMC_CAP(mwt->mode))
2001
2002 static const struct ext_csd_bus_width {
2003         uint cap;
2004         bool is_ddr;
2005         uint ext_csd_bits;
2006 } ext_csd_bus_width[] = {
2007         {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
2008         {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
2009         {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
2010         {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
2011         {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
2012 };
2013
2014 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2015 static int mmc_select_hs400(struct mmc *mmc)
2016 {
2017         int err;
2018
2019         /* Set timing to HS200 for tuning */
2020         err = mmc_set_card_speed(mmc, MMC_HS_200, false);
2021         if (err)
2022                 return err;
2023
2024         /* configure the bus mode (host) */
2025         mmc_select_mode(mmc, MMC_HS_200);
2026         mmc_set_clock(mmc, mmc->tran_speed, false);
2027
2028         /* execute tuning if needed */
2029         mmc->hs400_tuning = 1;
2030         err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
2031         mmc->hs400_tuning = 0;
2032         if (err) {
2033                 debug("tuning failed\n");
2034                 return err;
2035         }
2036
2037         /* Set back to HS */
2038         mmc_set_card_speed(mmc, MMC_HS, true);
2039
2040         err = mmc_hs400_prepare_ddr(mmc);
2041         if (err)
2042                 return err;
2043
2044         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2045                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
2046         if (err)
2047                 return err;
2048
2049         err = mmc_set_card_speed(mmc, MMC_HS_400, false);
2050         if (err)
2051                 return err;
2052
2053         mmc_select_mode(mmc, MMC_HS_400);
2054         err = mmc_set_clock(mmc, mmc->tran_speed, false);
2055         if (err)
2056                 return err;
2057
2058         return 0;
2059 }
2060 #else
2061 static int mmc_select_hs400(struct mmc *mmc)
2062 {
2063         return -ENOTSUPP;
2064 }
2065 #endif
2066
2067 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
2068 #if !CONFIG_IS_ENABLED(DM_MMC)
2069 static int mmc_set_enhanced_strobe(struct mmc *mmc)
2070 {
2071         return -ENOTSUPP;
2072 }
2073 #endif
2074 static int mmc_select_hs400es(struct mmc *mmc)
2075 {
2076         int err;
2077
2078         err = mmc_set_card_speed(mmc, MMC_HS, true);
2079         if (err)
2080                 return err;
2081
2082         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2083                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2084                          EXT_CSD_BUS_WIDTH_STROBE);
2085         if (err) {
2086                 printf("switch to bus width for hs400 failed\n");
2087                 return err;
2088         }
2089         /* TODO: driver strength */
2090         err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2091         if (err)
2092                 return err;
2093
2094         mmc_select_mode(mmc, MMC_HS_400_ES);
2095         err = mmc_set_clock(mmc, mmc->tran_speed, false);
2096         if (err)
2097                 return err;
2098
2099         return mmc_set_enhanced_strobe(mmc);
2100 }
2101 #else
2102 static int mmc_select_hs400es(struct mmc *mmc)
2103 {
2104         return -ENOTSUPP;
2105 }
2106 #endif
2107
2108 #define for_each_supported_width(caps, ddr, ecbv) \
2109         for (ecbv = ext_csd_bus_width;\
2110             ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2111             ecbv++) \
2112                 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2113
2114 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
2115 {
2116         int err = 0;
2117         const struct mode_width_tuning *mwt;
2118         const struct ext_csd_bus_width *ecbw;
2119
2120 #ifdef DEBUG
2121         mmc_dump_capabilities("mmc", card_caps);
2122         mmc_dump_capabilities("host", mmc->host_caps);
2123 #endif
2124
2125         if (mmc_host_is_spi(mmc)) {
2126                 mmc_set_bus_width(mmc, 1);
2127                 mmc_select_mode(mmc, MMC_LEGACY);
2128                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2129                 return 0;
2130         }
2131
2132         /* Restrict card's capabilities by what the host can do */
2133         card_caps &= mmc->host_caps;
2134
2135         /* Only version 4 of MMC supports wider bus widths */
2136         if (mmc->version < MMC_VERSION_4)
2137                 return 0;
2138
2139         if (!mmc->ext_csd) {
2140                 pr_debug("No ext_csd found!\n"); /* this should enver happen */
2141                 return -ENOTSUPP;
2142         }
2143
2144 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2145     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
2146     CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
2147         /*
2148          * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2149          * before doing anything else, since a transition from either of
2150          * the HS200/HS400 mode directly to legacy mode is not supported.
2151          */
2152         if (mmc->selected_mode == MMC_HS_200 ||
2153             mmc->selected_mode == MMC_HS_400 ||
2154             mmc->selected_mode == MMC_HS_400_ES)
2155                 mmc_set_card_speed(mmc, MMC_HS, true);
2156         else
2157 #endif
2158                 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
2159
2160         for_each_mmc_mode_by_pref(card_caps, mwt) {
2161                 for_each_supported_width(card_caps & mwt->widths,
2162                                          mmc_is_mode_ddr(mwt->mode), ecbw) {
2163                         enum mmc_voltage old_voltage;
2164                         pr_debug("trying mode %s width %d (at %d MHz)\n",
2165                                  mmc_mode_name(mwt->mode),
2166                                  bus_width(ecbw->cap),
2167                                  mmc_mode2freq(mmc, mwt->mode) / 1000000);
2168                         old_voltage = mmc->signal_voltage;
2169                         err = mmc_set_lowest_voltage(mmc, mwt->mode,
2170                                                      MMC_ALL_SIGNAL_VOLTAGE);
2171                         if (err)
2172                                 continue;
2173
2174                         /* configure the bus width (card + host) */
2175                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2176                                     EXT_CSD_BUS_WIDTH,
2177                                     ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2178                         if (err)
2179                                 goto error;
2180                         mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2181
2182                         if (mwt->mode == MMC_HS_400) {
2183                                 err = mmc_select_hs400(mmc);
2184                                 if (err) {
2185                                         printf("Select HS400 failed %d\n", err);
2186                                         goto error;
2187                                 }
2188                         } else if (mwt->mode == MMC_HS_400_ES) {
2189                                 err = mmc_select_hs400es(mmc);
2190                                 if (err) {
2191                                         printf("Select HS400ES failed %d\n",
2192                                                err);
2193                                         goto error;
2194                                 }
2195                         } else {
2196                                 /* configure the bus speed (card) */
2197                                 err = mmc_set_card_speed(mmc, mwt->mode, false);
2198                                 if (err)
2199                                         goto error;
2200
2201                                 /*
2202                                  * configure the bus width AND the ddr mode
2203                                  * (card). The host side will be taken care
2204                                  * of in the next step
2205                                  */
2206                                 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2207                                         err = mmc_switch(mmc,
2208                                                          EXT_CSD_CMD_SET_NORMAL,
2209                                                          EXT_CSD_BUS_WIDTH,
2210                                                          ecbw->ext_csd_bits);
2211                                         if (err)
2212                                                 goto error;
2213                                 }
2214
2215                                 /* configure the bus mode (host) */
2216                                 mmc_select_mode(mmc, mwt->mode);
2217                                 mmc_set_clock(mmc, mmc->tran_speed,
2218                                               MMC_CLK_ENABLE);
2219 #ifdef MMC_SUPPORTS_TUNING
2220
2221                                 /* execute tuning if needed */
2222                                 if (mwt->tuning) {
2223                                         err = mmc_execute_tuning(mmc,
2224                                                                  mwt->tuning);
2225                                         if (err) {
2226                                                 pr_debug("tuning failed : %d\n", err);
2227                                                 goto error;
2228                                         }
2229                                 }
2230 #endif
2231                         }
2232
2233                         /* do a transfer to check the configuration */
2234                         err = mmc_read_and_compare_ext_csd(mmc);
2235                         if (!err)
2236                                 return 0;
2237 error:
2238                         mmc_set_signal_voltage(mmc, old_voltage);
2239                         /* if an error occurred, revert to a safer bus mode */
2240                         mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2241                                    EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2242                         mmc_select_mode(mmc, MMC_LEGACY);
2243                         mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
2244                         mmc_set_bus_width(mmc, 1);
2245                 }
2246         }
2247
2248         pr_err("unable to select a mode : %d\n", err);
2249
2250         return -ENOTSUPP;
2251 }
2252 #endif
2253
2254 #if CONFIG_IS_ENABLED(MMC_TINY)
2255 DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2256 #endif
2257
2258 static int mmc_startup_v4(struct mmc *mmc)
2259 {
2260         int err, i;
2261         u64 capacity;
2262         bool has_parts = false;
2263         bool part_completed;
2264         static const u32 mmc_versions[] = {
2265                 MMC_VERSION_4,
2266                 MMC_VERSION_4_1,
2267                 MMC_VERSION_4_2,
2268                 MMC_VERSION_4_3,
2269                 MMC_VERSION_4_4,
2270                 MMC_VERSION_4_41,
2271                 MMC_VERSION_4_5,
2272                 MMC_VERSION_5_0,
2273                 MMC_VERSION_5_1
2274         };
2275
2276 #if CONFIG_IS_ENABLED(MMC_TINY)
2277         u8 *ext_csd = ext_csd_bkup;
2278
2279         if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2280                 return 0;
2281
2282         if (!mmc->ext_csd)
2283                 memset(ext_csd_bkup, 0, MMC_MAX_BLOCK_LEN);
2284
2285         err = mmc_send_ext_csd(mmc, ext_csd);
2286         if (err)
2287                 goto error;
2288
2289         /* store the ext csd for future reference */
2290         if (!mmc->ext_csd)
2291                 mmc->ext_csd = ext_csd;
2292 #else
2293         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2294
2295         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2296                 return 0;
2297
2298         /* check  ext_csd version and capacity */
2299         err = mmc_send_ext_csd(mmc, ext_csd);
2300         if (err)
2301                 goto error;
2302
2303         /* store the ext csd for future reference */
2304         if (!mmc->ext_csd)
2305                 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2306         if (!mmc->ext_csd)
2307                 return -ENOMEM;
2308         memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2309 #endif
2310         if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2311                 return -EINVAL;
2312
2313         mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2314
2315         if (mmc->version >= MMC_VERSION_4_2) {
2316                 /*
2317                  * According to the JEDEC Standard, the value of
2318                  * ext_csd's capacity is valid if the value is more
2319                  * than 2GB
2320                  */
2321                 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2322                                 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2323                                 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2324                                 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2325                 capacity *= MMC_MAX_BLOCK_LEN;
2326                 if ((capacity >> 20) > 2 * 1024)
2327                         mmc->capacity_user = capacity;
2328         }
2329
2330         if (mmc->version >= MMC_VERSION_4_5)
2331                 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2332
2333         /* The partition data may be non-zero but it is only
2334          * effective if PARTITION_SETTING_COMPLETED is set in
2335          * EXT_CSD, so ignore any data if this bit is not set,
2336          * except for enabling the high-capacity group size
2337          * definition (see below).
2338          */
2339         part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2340                             EXT_CSD_PARTITION_SETTING_COMPLETED);
2341
2342         mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2343         /* Some eMMC set the value too low so set a minimum */
2344         if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2345                 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2346
2347         /* store the partition info of emmc */
2348         mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2349         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2350             ext_csd[EXT_CSD_BOOT_MULT])
2351                 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2352         if (part_completed &&
2353             (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2354                 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2355
2356         mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2357
2358         mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2359
2360         for (i = 0; i < 4; i++) {
2361                 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2362                 uint mult = (ext_csd[idx + 2] << 16) +
2363                         (ext_csd[idx + 1] << 8) + ext_csd[idx];
2364                 if (mult)
2365                         has_parts = true;
2366                 if (!part_completed)
2367                         continue;
2368                 mmc->capacity_gp[i] = mult;
2369                 mmc->capacity_gp[i] *=
2370                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2371                 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2372                 mmc->capacity_gp[i] <<= 19;
2373         }
2374
2375 #ifndef CONFIG_SPL_BUILD
2376         if (part_completed) {
2377                 mmc->enh_user_size =
2378                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2379                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2380                         ext_csd[EXT_CSD_ENH_SIZE_MULT];
2381                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2382                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2383                 mmc->enh_user_size <<= 19;
2384                 mmc->enh_user_start =
2385                         (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2386                         (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2387                         (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2388                         ext_csd[EXT_CSD_ENH_START_ADDR];
2389                 if (mmc->high_capacity)
2390                         mmc->enh_user_start <<= 9;
2391         }
2392 #endif
2393
2394         /*
2395          * Host needs to enable ERASE_GRP_DEF bit if device is
2396          * partitioned. This bit will be lost every time after a reset
2397          * or power off. This will affect erase size.
2398          */
2399         if (part_completed)
2400                 has_parts = true;
2401         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2402             (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2403                 has_parts = true;
2404         if (has_parts) {
2405                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2406                                  EXT_CSD_ERASE_GROUP_DEF, 1);
2407
2408                 if (err)
2409                         goto error;
2410
2411                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2412         }
2413
2414         if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2415 #if CONFIG_IS_ENABLED(MMC_WRITE)
2416                 /* Read out group size from ext_csd */
2417                 mmc->erase_grp_size =
2418                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2419 #endif
2420                 /*
2421                  * if high capacity and partition setting completed
2422                  * SEC_COUNT is valid even if it is smaller than 2 GiB
2423                  * JEDEC Standard JESD84-B45, 6.2.4
2424                  */
2425                 if (mmc->high_capacity && part_completed) {
2426                         capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2427                                 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2428                                 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2429                                 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2430                         capacity *= MMC_MAX_BLOCK_LEN;
2431                         mmc->capacity_user = capacity;
2432                 }
2433         }
2434 #if CONFIG_IS_ENABLED(MMC_WRITE)
2435         else {
2436                 /* Calculate the group size from the csd value. */
2437                 int erase_gsz, erase_gmul;
2438
2439                 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2440                 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2441                 mmc->erase_grp_size = (erase_gsz + 1)
2442                         * (erase_gmul + 1);
2443         }
2444 #endif
2445 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2446         mmc->hc_wp_grp_size = 1024
2447                 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2448                 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2449 #endif
2450
2451         mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2452
2453         mmc->can_trim =
2454                 !!(ext_csd[EXT_CSD_SEC_FEATURE] & EXT_CSD_SEC_FEATURE_TRIM_EN);
2455
2456         return 0;
2457 error:
2458         if (mmc->ext_csd) {
2459 #if !CONFIG_IS_ENABLED(MMC_TINY)
2460                 free(mmc->ext_csd);
2461 #endif
2462                 mmc->ext_csd = NULL;
2463         }
2464         return err;
2465 }
2466
2467 static int mmc_startup(struct mmc *mmc)
2468 {
2469         int err, i;
2470         uint mult, freq;
2471         u64 cmult, csize;
2472         struct mmc_cmd cmd;
2473         struct blk_desc *bdesc;
2474
2475 #ifdef CONFIG_MMC_SPI_CRC_ON
2476         if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2477                 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2478                 cmd.resp_type = MMC_RSP_R1;
2479                 cmd.cmdarg = 1;
2480                 err = mmc_send_cmd(mmc, &cmd, NULL);
2481                 if (err)
2482                         return err;
2483         }
2484 #endif
2485
2486         /* Put the Card in Identify Mode */
2487         cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2488                 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2489         cmd.resp_type = MMC_RSP_R2;
2490         cmd.cmdarg = 0;
2491
2492         err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_SEND_CID, 4);
2493         if (err)
2494                 return err;
2495
2496         memcpy(mmc->cid, cmd.response, 16);
2497
2498         /*
2499          * For MMC cards, set the Relative Address.
2500          * For SD cards, get the Relatvie Address.
2501          * This also puts the cards into Standby State
2502          */
2503         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2504                 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2505                 cmd.cmdarg = mmc->rca << 16;
2506                 cmd.resp_type = MMC_RSP_R6;
2507
2508                 err = mmc_send_cmd(mmc, &cmd, NULL);
2509
2510                 if (err)
2511                         return err;
2512
2513                 if (IS_SD(mmc))
2514                         mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2515         }
2516
2517         /* Get the Card-Specific Data */
2518         cmd.cmdidx = MMC_CMD_SEND_CSD;
2519         cmd.resp_type = MMC_RSP_R2;
2520         cmd.cmdarg = mmc->rca << 16;
2521
2522         err = mmc_send_cmd(mmc, &cmd, NULL);
2523
2524         if (err)
2525                 return err;
2526
2527         mmc->csd[0] = cmd.response[0];
2528         mmc->csd[1] = cmd.response[1];
2529         mmc->csd[2] = cmd.response[2];
2530         mmc->csd[3] = cmd.response[3];
2531
2532         if (mmc->version == MMC_VERSION_UNKNOWN) {
2533                 int version = (cmd.response[0] >> 26) & 0xf;
2534
2535                 switch (version) {
2536                 case 0:
2537                         mmc->version = MMC_VERSION_1_2;
2538                         break;
2539                 case 1:
2540                         mmc->version = MMC_VERSION_1_4;
2541                         break;
2542                 case 2:
2543                         mmc->version = MMC_VERSION_2_2;
2544                         break;
2545                 case 3:
2546                         mmc->version = MMC_VERSION_3;
2547                         break;
2548                 case 4:
2549                         mmc->version = MMC_VERSION_4;
2550                         break;
2551                 default:
2552                         mmc->version = MMC_VERSION_1_2;
2553                         break;
2554                 }
2555         }
2556
2557         /* divide frequency by 10, since the mults are 10x bigger */
2558         freq = fbase[(cmd.response[0] & 0x7)];
2559         mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2560
2561         mmc->legacy_speed = freq * mult;
2562         mmc_select_mode(mmc, MMC_LEGACY);
2563
2564         mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2565         mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2566 #if CONFIG_IS_ENABLED(MMC_WRITE)
2567
2568         if (IS_SD(mmc))
2569                 mmc->write_bl_len = mmc->read_bl_len;
2570         else
2571                 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2572 #endif
2573
2574         if (mmc->high_capacity) {
2575                 csize = (mmc->csd[1] & 0x3f) << 16
2576                         | (mmc->csd[2] & 0xffff0000) >> 16;
2577                 cmult = 8;
2578         } else {
2579                 csize = (mmc->csd[1] & 0x3ff) << 2
2580                         | (mmc->csd[2] & 0xc0000000) >> 30;
2581                 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2582         }
2583
2584         mmc->capacity_user = (csize + 1) << (cmult + 2);
2585         mmc->capacity_user *= mmc->read_bl_len;
2586         mmc->capacity_boot = 0;
2587         mmc->capacity_rpmb = 0;
2588         for (i = 0; i < 4; i++)
2589                 mmc->capacity_gp[i] = 0;
2590
2591         if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2592                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2593
2594 #if CONFIG_IS_ENABLED(MMC_WRITE)
2595         if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2596                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2597 #endif
2598
2599         if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2600                 cmd.cmdidx = MMC_CMD_SET_DSR;
2601                 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2602                 cmd.resp_type = MMC_RSP_NONE;
2603                 if (mmc_send_cmd(mmc, &cmd, NULL))
2604                         pr_warn("MMC: SET_DSR failed\n");
2605         }
2606
2607         /* Select the card, and put it into Transfer Mode */
2608         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2609                 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2610                 cmd.resp_type = MMC_RSP_R1;
2611                 cmd.cmdarg = mmc->rca << 16;
2612                 err = mmc_send_cmd(mmc, &cmd, NULL);
2613
2614                 if (err)
2615                         return err;
2616         }
2617
2618         /*
2619          * For SD, its erase group is always one sector
2620          */
2621 #if CONFIG_IS_ENABLED(MMC_WRITE)
2622         mmc->erase_grp_size = 1;
2623 #endif
2624         mmc->part_config = MMCPART_NOAVAILABLE;
2625
2626         err = mmc_startup_v4(mmc);
2627         if (err)
2628                 return err;
2629
2630         err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2631         if (err)
2632                 return err;
2633
2634 #if CONFIG_IS_ENABLED(MMC_TINY)
2635         mmc_set_clock(mmc, mmc->legacy_speed, false);
2636         mmc_select_mode(mmc, MMC_LEGACY);
2637         mmc_set_bus_width(mmc, 1);
2638 #else
2639         if (IS_SD(mmc)) {
2640                 err = sd_get_capabilities(mmc);
2641                 if (err)
2642                         return err;
2643                 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2644         } else {
2645                 err = mmc_get_capabilities(mmc);
2646                 if (err)
2647                         return err;
2648                 err = mmc_select_mode_and_width(mmc, mmc->card_caps);
2649         }
2650 #endif
2651         if (err)
2652                 return err;
2653
2654         mmc->best_mode = mmc->selected_mode;
2655
2656         /* Fix the block length for DDR mode */
2657         if (mmc->ddr_mode) {
2658                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2659 #if CONFIG_IS_ENABLED(MMC_WRITE)
2660                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2661 #endif
2662         }
2663
2664         /* fill in device description */
2665         bdesc = mmc_get_blk_desc(mmc);
2666         bdesc->lun = 0;
2667         bdesc->hwpart = 0;
2668         bdesc->type = 0;
2669         bdesc->blksz = mmc->read_bl_len;
2670         bdesc->log2blksz = LOG2(bdesc->blksz);
2671         bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2672 #if !defined(CONFIG_SPL_BUILD) || \
2673                 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2674                 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
2675         sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2676                 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2677                 (mmc->cid[3] >> 16) & 0xffff);
2678         sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2679                 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2680                 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2681                 (mmc->cid[2] >> 24) & 0xff);
2682         sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2683                 (mmc->cid[2] >> 16) & 0xf);
2684 #else
2685         bdesc->vendor[0] = 0;
2686         bdesc->product[0] = 0;
2687         bdesc->revision[0] = 0;
2688 #endif
2689
2690 #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2691         part_init(bdesc);
2692 #endif
2693
2694         return 0;
2695 }
2696
2697 static int mmc_send_if_cond(struct mmc *mmc)
2698 {
2699         struct mmc_cmd cmd;
2700         int err;
2701
2702         cmd.cmdidx = SD_CMD_SEND_IF_COND;
2703         /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2704         cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2705         cmd.resp_type = MMC_RSP_R7;
2706
2707         err = mmc_send_cmd(mmc, &cmd, NULL);
2708
2709         if (err)
2710                 return err;
2711
2712         if ((cmd.response[0] & 0xff) != 0xaa)
2713                 return -EOPNOTSUPP;
2714         else
2715                 mmc->version = SD_VERSION_2;
2716
2717         return 0;
2718 }
2719
2720 #if !CONFIG_IS_ENABLED(DM_MMC)
2721 /* board-specific MMC power initializations. */
2722 __weak void board_mmc_power_init(void)
2723 {
2724 }
2725 #endif
2726
2727 static int mmc_power_init(struct mmc *mmc)
2728 {
2729 #if CONFIG_IS_ENABLED(DM_MMC)
2730 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2731         int ret;
2732
2733         ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2734                                           &mmc->vmmc_supply);
2735         if (ret)
2736                 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2737
2738         ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2739                                           &mmc->vqmmc_supply);
2740         if (ret)
2741                 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2742 #endif
2743 #else /* !CONFIG_DM_MMC */
2744         /*
2745          * Driver model should use a regulator, as above, rather than calling
2746          * out to board code.
2747          */
2748         board_mmc_power_init();
2749 #endif
2750         return 0;
2751 }
2752
2753 /*
2754  * put the host in the initial state:
2755  * - turn on Vdd (card power supply)
2756  * - configure the bus width and clock to minimal values
2757  */
2758 static void mmc_set_initial_state(struct mmc *mmc)
2759 {
2760         int err;
2761
2762         /* First try to set 3.3V. If it fails set to 1.8V */
2763         err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2764         if (err != 0)
2765                 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2766         if (err != 0)
2767                 pr_warn("mmc: failed to set signal voltage\n");
2768
2769         mmc_select_mode(mmc, MMC_LEGACY);
2770         mmc_set_bus_width(mmc, 1);
2771         mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2772 }
2773
2774 static int mmc_power_on(struct mmc *mmc)
2775 {
2776 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2777         if (mmc->vmmc_supply) {
2778                 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2779
2780                 if (ret && ret != -EACCES) {
2781                         printf("Error enabling VMMC supply : %d\n", ret);
2782                         return ret;
2783                 }
2784         }
2785 #endif
2786         return 0;
2787 }
2788
2789 static int mmc_power_off(struct mmc *mmc)
2790 {
2791         mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
2792 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2793         if (mmc->vmmc_supply) {
2794                 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2795
2796                 if (ret && ret != -EACCES) {
2797                         pr_debug("Error disabling VMMC supply : %d\n", ret);
2798                         return ret;
2799                 }
2800         }
2801 #endif
2802         return 0;
2803 }
2804
2805 static int mmc_power_cycle(struct mmc *mmc)
2806 {
2807         int ret;
2808
2809         ret = mmc_power_off(mmc);
2810         if (ret)
2811                 return ret;
2812
2813         ret = mmc_host_power_cycle(mmc);
2814         if (ret)
2815                 return ret;
2816
2817         /*
2818          * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2819          * to be on the safer side.
2820          */
2821         udelay(2000);
2822         return mmc_power_on(mmc);
2823 }
2824
2825 int mmc_get_op_cond(struct mmc *mmc, bool quiet)
2826 {
2827         bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2828         int err;
2829
2830         if (mmc->has_init)
2831                 return 0;
2832
2833         err = mmc_power_init(mmc);
2834         if (err)
2835                 return err;
2836
2837 #ifdef CONFIG_MMC_QUIRKS
2838         mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2839                       MMC_QUIRK_RETRY_SEND_CID |
2840                       MMC_QUIRK_RETRY_APP_CMD;
2841 #endif
2842
2843         err = mmc_power_cycle(mmc);
2844         if (err) {
2845                 /*
2846                  * if power cycling is not supported, we should not try
2847                  * to use the UHS modes, because we wouldn't be able to
2848                  * recover from an error during the UHS initialization.
2849                  */
2850                 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2851                 uhs_en = false;
2852                 mmc->host_caps &= ~UHS_CAPS;
2853                 err = mmc_power_on(mmc);
2854         }
2855         if (err)
2856                 return err;
2857
2858 #if CONFIG_IS_ENABLED(DM_MMC)
2859         /*
2860          * Re-initialization is needed to clear old configuration for
2861          * mmc rescan.
2862          */
2863         err = mmc_reinit(mmc);
2864 #else
2865         /* made sure it's not NULL earlier */
2866         err = mmc->cfg->ops->init(mmc);
2867 #endif
2868         if (err)
2869                 return err;
2870         mmc->ddr_mode = 0;
2871
2872 retry:
2873         mmc_set_initial_state(mmc);
2874
2875         /* Reset the Card */
2876         err = mmc_go_idle(mmc);
2877
2878         if (err)
2879                 return err;
2880
2881         /* The internal partition reset to user partition(0) at every CMD0 */
2882         mmc_get_blk_desc(mmc)->hwpart = 0;
2883
2884         /* Test for SD version 2 */
2885         err = mmc_send_if_cond(mmc);
2886
2887         /* Now try to get the SD card's operating condition */
2888         err = sd_send_op_cond(mmc, uhs_en);
2889         if (err && uhs_en) {
2890                 uhs_en = false;
2891                 mmc_power_cycle(mmc);
2892                 goto retry;
2893         }
2894
2895         /* If the command timed out, we check for an MMC card */
2896         if (err == -ETIMEDOUT) {
2897                 err = mmc_send_op_cond(mmc);
2898
2899                 if (err) {
2900 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2901                         if (!quiet)
2902                                 pr_err("Card did not respond to voltage select! : %d\n", err);
2903 #endif
2904                         return -EOPNOTSUPP;
2905                 }
2906         }
2907
2908         return err;
2909 }
2910
2911 int mmc_start_init(struct mmc *mmc)
2912 {
2913         bool no_card;
2914         int err = 0;
2915
2916         /*
2917          * all hosts are capable of 1 bit bus-width and able to use the legacy
2918          * timings.
2919          */
2920         mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
2921                          MMC_MODE_1BIT;
2922
2923         if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) {
2924                 if (mmc->user_speed_mode != MMC_MODES_END) {
2925                         int i;
2926                         /* set host caps */
2927                         if (mmc->host_caps & MMC_CAP(mmc->user_speed_mode)) {
2928                                 /* Remove all existing speed capabilities */
2929                                 for (i = MMC_LEGACY; i < MMC_MODES_END; i++)
2930                                         mmc->host_caps &= ~MMC_CAP(i);
2931                                 mmc->host_caps |= (MMC_CAP(mmc->user_speed_mode)
2932                                                    | MMC_CAP(MMC_LEGACY) |
2933                                                    MMC_MODE_1BIT);
2934                         } else {
2935                                 pr_err("bus_mode requested is not supported\n");
2936                                 return -EINVAL;
2937                         }
2938                 }
2939         }
2940 #if CONFIG_IS_ENABLED(DM_MMC)
2941         mmc_deferred_probe(mmc);
2942 #endif
2943 #if !defined(CONFIG_MMC_BROKEN_CD)
2944         no_card = mmc_getcd(mmc) == 0;
2945 #else
2946         no_card = 0;
2947 #endif
2948 #if !CONFIG_IS_ENABLED(DM_MMC)
2949         /* we pretend there's no card when init is NULL */
2950         no_card = no_card || (mmc->cfg->ops->init == NULL);
2951 #endif
2952         if (no_card) {
2953                 mmc->has_init = 0;
2954 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2955                 pr_err("MMC: no card present\n");
2956 #endif
2957                 return -ENOMEDIUM;
2958         }
2959
2960         err = mmc_get_op_cond(mmc, false);
2961
2962         if (!err)
2963                 mmc->init_in_progress = 1;
2964
2965         return err;
2966 }
2967
2968 static int mmc_complete_init(struct mmc *mmc)
2969 {
2970         int err = 0;
2971
2972         mmc->init_in_progress = 0;
2973         if (mmc->op_cond_pending)
2974                 err = mmc_complete_op_cond(mmc);
2975
2976         if (!err)
2977                 err = mmc_startup(mmc);
2978         if (err)
2979                 mmc->has_init = 0;
2980         else
2981                 mmc->has_init = 1;
2982         return err;
2983 }
2984
2985 int mmc_init(struct mmc *mmc)
2986 {
2987         int err = 0;
2988         __maybe_unused ulong start;
2989 #if CONFIG_IS_ENABLED(DM_MMC)
2990         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2991
2992         upriv->mmc = mmc;
2993 #endif
2994         if (mmc->has_init)
2995                 return 0;
2996
2997         start = get_timer(0);
2998
2999         if (!mmc->init_in_progress)
3000                 err = mmc_start_init(mmc);
3001
3002         if (!err)
3003                 err = mmc_complete_init(mmc);
3004         if (err)
3005                 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
3006
3007         return err;
3008 }
3009
3010 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
3011     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
3012     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
3013 int mmc_deinit(struct mmc *mmc)
3014 {
3015         u32 caps_filtered;
3016
3017         if (!mmc->has_init)
3018                 return 0;
3019
3020         if (IS_SD(mmc)) {
3021                 caps_filtered = mmc->card_caps &
3022                         ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
3023                           MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
3024                           MMC_CAP(UHS_SDR104));
3025
3026                 return sd_select_mode_and_width(mmc, caps_filtered);
3027         } else {
3028                 caps_filtered = mmc->card_caps &
3029                         ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES));
3030
3031                 return mmc_select_mode_and_width(mmc, caps_filtered);
3032         }
3033 }
3034 #endif
3035
3036 int mmc_set_dsr(struct mmc *mmc, u16 val)
3037 {
3038         mmc->dsr = val;
3039         return 0;
3040 }
3041
3042 /* CPU-specific MMC initializations */
3043 __weak int cpu_mmc_init(struct bd_info *bis)
3044 {
3045         return -1;
3046 }
3047
3048 /* board-specific MMC initializations. */
3049 __weak int board_mmc_init(struct bd_info *bis)
3050 {
3051         return -1;
3052 }
3053
3054 void mmc_set_preinit(struct mmc *mmc, int preinit)
3055 {
3056         mmc->preinit = preinit;
3057 }
3058
3059 #if CONFIG_IS_ENABLED(DM_MMC)
3060 static int mmc_probe(struct bd_info *bis)
3061 {
3062         int ret, i;
3063         struct uclass *uc;
3064         struct udevice *dev;
3065
3066         ret = uclass_get(UCLASS_MMC, &uc);
3067         if (ret)
3068                 return ret;
3069
3070         /*
3071          * Try to add them in sequence order. Really with driver model we
3072          * should allow holes, but the current MMC list does not allow that.
3073          * So if we request 0, 1, 3 we will get 0, 1, 2.
3074          */
3075         for (i = 0; ; i++) {
3076                 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
3077                 if (ret == -ENODEV)
3078                         break;
3079         }
3080         uclass_foreach_dev(dev, uc) {
3081                 ret = device_probe(dev);
3082                 if (ret)
3083                         pr_err("%s - probe failed: %d\n", dev->name, ret);
3084         }
3085
3086         return 0;
3087 }
3088 #else
3089 static int mmc_probe(struct bd_info *bis)
3090 {
3091         if (board_mmc_init(bis) < 0)
3092                 cpu_mmc_init(bis);
3093
3094         return 0;
3095 }
3096 #endif
3097
3098 int mmc_initialize(struct bd_info *bis)
3099 {
3100         static int initialized = 0;
3101         int ret;
3102         if (initialized)        /* Avoid initializing mmc multiple times */
3103                 return 0;
3104         initialized = 1;
3105
3106 #if !CONFIG_IS_ENABLED(BLK)
3107 #if !CONFIG_IS_ENABLED(MMC_TINY)
3108         mmc_list_init();
3109 #endif
3110 #endif
3111         ret = mmc_probe(bis);
3112         if (ret)
3113                 return ret;
3114
3115 #ifndef CONFIG_SPL_BUILD
3116         print_mmc_devices(',');
3117 #endif
3118
3119         mmc_do_preinit();
3120         return 0;
3121 }
3122
3123 #if CONFIG_IS_ENABLED(DM_MMC)
3124 int mmc_init_device(int num)
3125 {
3126         struct udevice *dev;
3127         struct mmc *m;
3128         int ret;
3129
3130         if (uclass_get_device_by_seq(UCLASS_MMC, num, &dev)) {
3131                 ret = uclass_get_device(UCLASS_MMC, num, &dev);
3132                 if (ret)
3133                         return ret;
3134         }
3135
3136         m = mmc_get_mmc_dev(dev);
3137         if (!m)
3138                 return 0;
3139
3140         /* Initialising user set speed mode */
3141         m->user_speed_mode = MMC_MODES_END;
3142
3143         if (m->preinit)
3144                 mmc_start_init(m);
3145
3146         return 0;
3147 }
3148 #endif
3149
3150 #ifdef CONFIG_CMD_BKOPS_ENABLE
3151 int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable)
3152 {
3153         int err;
3154         u32 bit = autobkops ? BIT(1) : BIT(0);
3155         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3156
3157         err = mmc_send_ext_csd(mmc, ext_csd);
3158         if (err) {
3159                 puts("Could not get ext_csd register values\n");
3160                 return err;
3161         }
3162
3163         if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3164                 puts("Background operations not supported on device\n");
3165                 return -EMEDIUMTYPE;
3166         }
3167
3168         if (enable && (ext_csd[EXT_CSD_BKOPS_EN] & bit)) {
3169                 puts("Background operations already enabled\n");
3170                 return 0;
3171         }
3172
3173         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN,
3174                          enable ? bit : 0);
3175         if (err) {
3176                 printf("Failed to %sable manual background operations\n",
3177                        enable ? "en" : "dis");
3178                 return err;
3179         }
3180
3181         printf("%sabled %s background operations\n",
3182                enable ? "En" : "Dis", autobkops ? "auto" : "manual");
3183
3184         return 0;
3185 }
3186 #endif
3187
3188 __weak int mmc_get_env_dev(void)
3189 {
3190 #ifdef CONFIG_SYS_MMC_ENV_DEV
3191         return CONFIG_SYS_MMC_ENV_DEV;
3192 #else
3193         return 0;
3194 #endif
3195 }