drivers/mmc/mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008, Freescale Semiconductor, Inc
   4  * Andy Fleming
   5  *
   6  * Based vaguely on the Linux code
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <command.h>
  12 #include <dm.h>
  13 #include <dm/device-internal.h>
  14 #include <errno.h>
  15 #include <mmc.h>
  16 #include <part.h>
  17 #include <power/regulator.h>
  18 #include <malloc.h>
  19 #include <memalign.h>
  20 #include <linux/list.h>
  21 #include <div64.h>
  22 #include "mmc_private.h"
  23
  24 #define DEFAULT_CMD6_TIMEOUT_MS  500
  25
  26 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  27
  28 #if !CONFIG_IS_ENABLED(DM_MMC)
  29
  30 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
  31 {
  32         return -ENOSYS;
  33 }
  34
  35 __weak int board_mmc_getwp(struct mmc *mmc)
  36 {
  37         return -1;
  38 }
  39
  40 int mmc_getwp(struct mmc *mmc)
  41 {
  42         int wp;
  43
  44         wp = board_mmc_getwp(mmc);
  45
  46         if (wp < 0) {
  47                 if (mmc->cfg->ops->getwp)
  48                         wp = mmc->cfg->ops->getwp(mmc);
  49                 else
  50                         wp = 0;
  51         }
  52
  53         return wp;
  54 }
  55
  56 __weak int board_mmc_getcd(struct mmc *mmc)
  57 {
  58         return -1;
  59 }
  60 #endif
  61
  62 #ifdef CONFIG_MMC_TRACE
  63 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  64 {
  65         printf("CMD_SEND:%d\n", cmd->cmdidx);
  66         printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  67 }
  68
  69 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  70 {
  71         int i;
  72         u8 *ptr;
  73
  74         if (ret) {
  75                 printf("\t\tRET\t\t\t %d\n", ret);
  76         } else {
  77                 switch (cmd->resp_type) {
  78                 case MMC_RSP_NONE:
  79                         printf("\t\tMMC_RSP_NONE\n");
  80                         break;
  81                 case MMC_RSP_R1:
  82                         printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  83                                 cmd->response[0]);
  84                         break;
  85                 case MMC_RSP_R1b:
  86                         printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  87                                 cmd->response[0]);
  88                         break;
  89                 case MMC_RSP_R2:
  90                         printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  91                                 cmd->response[0]);
  92                         printf("\t\t          \t\t 0x%08x \n",
  93                                 cmd->response[1]);
  94                         printf("\t\t          \t\t 0x%08x \n",
  95                                 cmd->response[2]);
  96                         printf("\t\t          \t\t 0x%08x \n",
  97                                 cmd->response[3]);
  98                         printf("\n");
  99                         printf("\t\t\t\t\tDUMPING DATA\n");
 100                         for (i = 0; i < 4; i++) {
 101                                 int j;
 102                                 printf("\t\t\t\t\t%03d - ", i*4);
 103                                 ptr = (u8 *)&cmd->response[i];
 104                                 ptr += 3;
 105                                 for (j = 0; j < 4; j++)
 106                                         printf("%02x ", *ptr--);
 107                                 printf("\n");
 108                         }
 109                         break;
 110                 case MMC_RSP_R3:
 111                         printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
 112                                 cmd->response[0]);
 113                         break;
 114                 default:
 115                         printf("\t\tERROR MMC rsp not supported\n");
 116                         break;
 117                 }
 118         }
 119 }
 120
 121 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
 122 {
 123         int status;
 124
 125         status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
 126         printf("CURR STATE:%d\n", status);
 127 }
 128 #endif
 129
 130 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
 131 const char *mmc_mode_name(enum bus_mode mode)
 132 {
 133         static const char *const names[] = {
 134               [MMC_LEGACY]      = "MMC legacy",
 135               [SD_LEGACY]       = "SD Legacy",
 136               [MMC_HS]          = "MMC High Speed (26MHz)",
 137               [SD_HS]           = "SD High Speed (50MHz)",
 138               [UHS_SDR12]       = "UHS SDR12 (25MHz)",
 139               [UHS_SDR25]       = "UHS SDR25 (50MHz)",
 140               [UHS_SDR50]       = "UHS SDR50 (100MHz)",
 141               [UHS_SDR104]      = "UHS SDR104 (208MHz)",
 142               [UHS_DDR50]       = "UHS DDR50 (50MHz)",
 143               [MMC_HS_52]       = "MMC High Speed (52MHz)",
 144               [MMC_DDR_52]      = "MMC DDR52 (52MHz)",
 145               [MMC_HS_200]      = "HS200 (200MHz)",
 146               [MMC_HS_400]      = "HS400 (200MHz)",
 147               [MMC_HS_400_ES]   = "HS400ES (200MHz)",
 148         };
 149
 150         if (mode >= MMC_MODES_END)
 151                 return "Unknown mode";
 152         else
 153                 return names[mode];
 154 }
 155 #endif
 156
 157 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
 158 {
 159         static const int freqs[] = {
 160               [MMC_LEGACY]      = 25000000,
 161               [SD_LEGACY]       = 25000000,
 162               [MMC_HS]          = 26000000,
 163               [SD_HS]           = 50000000,
 164               [MMC_HS_52]       = 52000000,
 165               [MMC_DDR_52]      = 52000000,
 166               [UHS_SDR12]       = 25000000,
 167               [UHS_SDR25]       = 50000000,
 168               [UHS_SDR50]       = 100000000,
 169               [UHS_DDR50]       = 50000000,
 170               [UHS_SDR104]      = 208000000,
 171               [MMC_HS_200]      = 200000000,
 172               [MMC_HS_400]      = 200000000,
 173               [MMC_HS_400_ES]   = 200000000,
 174         };
 175
 176         if (mode == MMC_LEGACY)
 177                 return mmc->legacy_speed;
 178         else if (mode >= MMC_MODES_END)
 179                 return 0;
 180         else
 181                 return freqs[mode];
 182 }
 183
 184 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
 185 {
 186         mmc->selected_mode = mode;
 187         mmc->tran_speed = mmc_mode2freq(mmc, mode);
 188         mmc->ddr_mode = mmc_is_mode_ddr(mode);
 189         pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
 190                  mmc->tran_speed / 1000000);
 191         return 0;
 192 }
 193
 194 #if !CONFIG_IS_ENABLED(DM_MMC)
 195 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 196 {
 197         int ret;
 198
 199         mmmc_trace_before_send(mmc, cmd);
 200         ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 201         mmmc_trace_after_send(mmc, cmd, ret);
 202
 203         return ret;
 204 }
 205 #endif
 206
 207 int mmc_send_status(struct mmc *mmc, unsigned int *status)
 208 {
 209         struct mmc_cmd cmd;
 210         int err, retries = 5;
 211
 212         cmd.cmdidx = MMC_CMD_SEND_STATUS;
 213         cmd.resp_type = MMC_RSP_R1;
 214         if (!mmc_host_is_spi(mmc))
 215                 cmd.cmdarg = mmc->rca << 16;
 216
 217         while (retries--) {
 218                 err = mmc_send_cmd(mmc, &cmd, NULL);
 219                 if (!err) {
 220                         mmc_trace_state(mmc, &cmd);
 221                         *status = cmd.response[0];
 222                         return 0;
 223                 }
 224         }
 225         mmc_trace_state(mmc, &cmd);
 226         return -ECOMM;
 227 }
 228
 229 int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
 230 {
 231         unsigned int status;
 232         int err;
 233
 234         err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 235         if (err != -ENOSYS)
 236                 return err;
 237
 238         while (1) {
 239                 err = mmc_send_status(mmc, &status);
 240                 if (err)
 241                         return err;
 242
 243                 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
 244                     (status & MMC_STATUS_CURR_STATE) !=
 245                      MMC_STATE_PRG)
 246                         break;
 247
 248                 if (status & MMC_STATUS_MASK) {
 249 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 250                         pr_err("Status Error: 0x%08x\n", status);
 251 #endif
 252                         return -ECOMM;
 253                 }
 254
 255                 if (timeout_ms-- <= 0)
 256                         break;
 257
 258                 udelay(1000);
 259         }
 260
 261         if (timeout_ms <= 0) {
 262 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 263                 pr_err("Timeout waiting card ready\n");
 264 #endif
 265                 return -ETIMEDOUT;
 266         }
 267
 268         return 0;
 269 }
 270
 271 int mmc_set_blocklen(struct mmc *mmc, int len)
 272 {
 273         struct mmc_cmd cmd;
 274         int err;
 275
 276         if (mmc->ddr_mode)
 277                 return 0;
 278
 279         cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
 280         cmd.resp_type = MMC_RSP_R1;
 281         cmd.cmdarg = len;
 282
 283         err = mmc_send_cmd(mmc, &cmd, NULL);
 284
 285 #ifdef CONFIG_MMC_QUIRKS
 286         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
 287                 int retries = 4;
 288                 /*
 289                  * It has been seen that SET_BLOCKLEN may fail on the first
 290                  * attempt, let's try a few more time
 291                  */
 292                 do {
 293                         err = mmc_send_cmd(mmc, &cmd, NULL);
 294                         if (!err)
 295                                 break;
 296                 } while (retries--);
 297         }
 298 #endif
 299
 300         return err;
 301 }
 302
 303 #ifdef MMC_SUPPORTS_TUNING
 304 static const u8 tuning_blk_pattern_4bit[] = {
 305         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 306         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 307         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 308         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 309         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 310         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 311         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 312         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 313 };
 314
 315 static const u8 tuning_blk_pattern_8bit[] = {
 316         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 317         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 318         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 319         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 320         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 321         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 322         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 323         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 324         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 325         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 326         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 327         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 328         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 329         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 330         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 331         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 332 };
 333
 334 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
 335 {
 336         struct mmc_cmd cmd;
 337         struct mmc_data data;
 338         const u8 *tuning_block_pattern;
 339         int size, err;
 340
 341         if (mmc->bus_width == 8) {
 342                 tuning_block_pattern = tuning_blk_pattern_8bit;
 343                 size = sizeof(tuning_blk_pattern_8bit);
 344         } else if (mmc->bus_width == 4) {
 345                 tuning_block_pattern = tuning_blk_pattern_4bit;
 346                 size = sizeof(tuning_blk_pattern_4bit);
 347         } else {
 348                 return -EINVAL;
 349         }
 350
 351         ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
 352
 353         cmd.cmdidx = opcode;
 354         cmd.cmdarg = 0;
 355         cmd.resp_type = MMC_RSP_R1;
 356
 357         data.dest = (void *)data_buf;
 358         data.blocks = 1;
 359         data.blocksize = size;
 360         data.flags = MMC_DATA_READ;
 361
 362         err = mmc_send_cmd(mmc, &cmd, &data);
 363         if (err)
 364                 return err;
 365
 366         if (memcmp(data_buf, tuning_block_pattern, size))
 367                 return -EIO;
 368
 369         return 0;
 370 }
 371 #endif
 372
 373 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 374                            lbaint_t blkcnt)
 375 {
 376         struct mmc_cmd cmd;
 377         struct mmc_data data;
 378
 379         if (blkcnt > 1)
 380                 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
 381         else
 382                 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
 383
 384         if (mmc->high_capacity)
 385                 cmd.cmdarg = start;
 386         else
 387                 cmd.cmdarg = start * mmc->read_bl_len;
 388
 389         cmd.resp_type = MMC_RSP_R1;
 390
 391         data.dest = dst;
 392         data.blocks = blkcnt;
 393         data.blocksize = mmc->read_bl_len;
 394         data.flags = MMC_DATA_READ;
 395
 396         if (mmc_send_cmd(mmc, &cmd, &data))
 397                 return 0;
 398
 399         if (blkcnt > 1) {
 400                 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 401                 cmd.cmdarg = 0;
 402                 cmd.resp_type = MMC_RSP_R1b;
 403                 if (mmc_send_cmd(mmc, &cmd, NULL)) {
 404 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 405                         pr_err("mmc fail to send stop cmd\n");
 406 #endif
 407                         return 0;
 408                 }
 409         }
 410
 411         return blkcnt;
 412 }
 413
 414 #if CONFIG_IS_ENABLED(BLK)
 415 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
 416 #else
 417 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 418                 void *dst)
 419 #endif
 420 {
 421 #if CONFIG_IS_ENABLED(BLK)
 422         struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 423 #endif
 424         int dev_num = block_dev->devnum;
 425         int err;
 426         lbaint_t cur, blocks_todo = blkcnt;
 427
 428         if (blkcnt == 0)
 429                 return 0;
 430
 431         struct mmc *mmc = find_mmc_device(dev_num);
 432         if (!mmc)
 433                 return 0;
 434
 435         if (CONFIG_IS_ENABLED(MMC_TINY))
 436                 err = mmc_switch_part(mmc, block_dev->hwpart);
 437         else
 438                 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
 439
 440         if (err < 0)
 441                 return 0;
 442
 443         if ((start + blkcnt) > block_dev->lba) {
 444 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 445                 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
 446                        start + blkcnt, block_dev->lba);
 447 #endif
 448                 return 0;
 449         }
 450
 451         if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
 452                 pr_debug("%s: Failed to set blocklen\n", __func__);
 453                 return 0;
 454         }
 455
 456         do {
 457                 cur = (blocks_todo > mmc->cfg->b_max) ?
 458                         mmc->cfg->b_max : blocks_todo;
 459                 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
 460                         pr_debug("%s: Failed to read blocks\n", __func__);
 461                         return 0;
 462                 }
 463                 blocks_todo -= cur;
 464                 start += cur;
 465                 dst += cur * mmc->read_bl_len;
 466         } while (blocks_todo > 0);
 467
 468         return blkcnt;
 469 }
 470
 471 static int mmc_go_idle(struct mmc *mmc)
 472 {
 473         struct mmc_cmd cmd;
 474         int err;
 475
 476         udelay(1000);
 477
 478         cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
 479         cmd.cmdarg = 0;
 480         cmd.resp_type = MMC_RSP_NONE;
 481
 482         err = mmc_send_cmd(mmc, &cmd, NULL);
 483
 484         if (err)
 485                 return err;
 486
 487         udelay(2000);
 488
 489         return 0;
 490 }
 491
 492 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 493 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
 494 {
 495         struct mmc_cmd cmd;
 496         int err = 0;
 497
 498         /*
 499          * Send CMD11 only if the request is to switch the card to
 500          * 1.8V signalling.
 501          */
 502         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 503                 return mmc_set_signal_voltage(mmc, signal_voltage);
 504
 505         cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
 506         cmd.cmdarg = 0;
 507         cmd.resp_type = MMC_RSP_R1;
 508
 509         err = mmc_send_cmd(mmc, &cmd, NULL);
 510         if (err)
 511                 return err;
 512
 513         if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
 514                 return -EIO;
 515
 516         /*
 517          * The card should drive cmd and dat[0:3] low immediately
 518          * after the response of cmd11, but wait 100 us to be sure
 519          */
 520         err = mmc_wait_dat0(mmc, 0, 100);
 521         if (err == -ENOSYS)
 522                 udelay(100);
 523         else if (err)
 524                 return -ETIMEDOUT;
 525
 526         /*
 527          * During a signal voltage level switch, the clock must be gated
 528          * for 5 ms according to the SD spec
 529          */
 530         mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
 531
 532         err = mmc_set_signal_voltage(mmc, signal_voltage);
 533         if (err)
 534                 return err;
 535
 536         /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
 537         mdelay(10);
 538         mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
 539
 540         /*
 541          * Failure to switch is indicated by the card holding
 542          * dat[0:3] low. Wait for at least 1 ms according to spec
 543          */
 544         err = mmc_wait_dat0(mmc, 1, 1000);
 545         if (err == -ENOSYS)
 546                 udelay(1000);
 547         else if (err)
 548                 return -ETIMEDOUT;
 549
 550         return 0;
 551 }
 552 #endif
 553
 554 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
 555 {
 556         int timeout = 1000;
 557         int err;
 558         struct mmc_cmd cmd;
 559
 560         while (1) {
 561                 cmd.cmdidx = MMC_CMD_APP_CMD;
 562                 cmd.resp_type = MMC_RSP_R1;
 563                 cmd.cmdarg = 0;
 564
 565                 err = mmc_send_cmd(mmc, &cmd, NULL);
 566
 567                 if (err)
 568                         return err;
 569
 570                 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
 571                 cmd.resp_type = MMC_RSP_R3;
 572
 573                 /*
 574                  * Most cards do not answer if some reserved bits
 575                  * in the ocr are set. However, Some controller
 576                  * can set bit 7 (reserved for low voltages), but
 577                  * how to manage low voltages SD card is not yet
 578                  * specified.
 579                  */
 580                 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
 581                         (mmc->cfg->voltages & 0xff8000);
 582
 583                 if (mmc->version == SD_VERSION_2)
 584                         cmd.cmdarg |= OCR_HCS;
 585
 586                 if (uhs_en)
 587                         cmd.cmdarg |= OCR_S18R;
 588
 589                 err = mmc_send_cmd(mmc, &cmd, NULL);
 590
 591                 if (err)
 592                         return err;
 593
 594                 if (cmd.response[0] & OCR_BUSY)
 595                         break;
 596
 597                 if (timeout-- <= 0)
 598                         return -EOPNOTSUPP;
 599
 600                 udelay(1000);
 601         }
 602
 603         if (mmc->version != SD_VERSION_2)
 604                 mmc->version = SD_VERSION_1_0;
 605
 606         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 607                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 608                 cmd.resp_type = MMC_RSP_R3;
 609                 cmd.cmdarg = 0;
 610
 611                 err = mmc_send_cmd(mmc, &cmd, NULL);
 612
 613                 if (err)
 614                         return err;
 615         }
 616
 617         mmc->ocr = cmd.response[0];
 618
 619 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 620         if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
 621             == 0x41000000) {
 622                 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
 623                 if (err)
 624                         return err;
 625         }
 626 #endif
 627
 628         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 629         mmc->rca = 0;
 630
 631         return 0;
 632 }
 633
 634 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
 635 {
 636         struct mmc_cmd cmd;
 637         int err;
 638
 639         cmd.cmdidx = MMC_CMD_SEND_OP_COND;
 640         cmd.resp_type = MMC_RSP_R3;
 641         cmd.cmdarg = 0;
 642         if (use_arg && !mmc_host_is_spi(mmc))
 643                 cmd.cmdarg = OCR_HCS |
 644                         (mmc->cfg->voltages &
 645                         (mmc->ocr & OCR_VOLTAGE_MASK)) |
 646                         (mmc->ocr & OCR_ACCESS_MODE);
 647
 648         err = mmc_send_cmd(mmc, &cmd, NULL);
 649         if (err)
 650                 return err;
 651         mmc->ocr = cmd.response[0];
 652         return 0;
 653 }
 654
 655 static int mmc_send_op_cond(struct mmc *mmc)
 656 {
 657         int err, i;
 658
 659         /* Some cards seem to need this */
 660         mmc_go_idle(mmc);
 661
 662         /* Asking to the card its capabilities */
 663         for (i = 0; i < 2; i++) {
 664                 err = mmc_send_op_cond_iter(mmc, i != 0);
 665                 if (err)
 666                         return err;
 667
 668                 /* exit if not busy (flag seems to be inverted) */
 669                 if (mmc->ocr & OCR_BUSY)
 670                         break;
 671         }
 672         mmc->op_cond_pending = 1;
 673         return 0;
 674 }
 675
 676 static int mmc_complete_op_cond(struct mmc *mmc)
 677 {
 678         struct mmc_cmd cmd;
 679         int timeout = 1000;
 680         ulong start;
 681         int err;
 682
 683         mmc->op_cond_pending = 0;
 684         if (!(mmc->ocr & OCR_BUSY)) {
 685                 /* Some cards seem to need this */
 686                 mmc_go_idle(mmc);
 687
 688                 start = get_timer(0);
 689                 while (1) {
 690                         err = mmc_send_op_cond_iter(mmc, 1);
 691                         if (err)
 692                                 return err;
 693                         if (mmc->ocr & OCR_BUSY)
 694                                 break;
 695                         if (get_timer(start) > timeout)
 696                                 return -EOPNOTSUPP;
 697                         udelay(100);
 698                 }
 699         }
 700
 701         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 702                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 703                 cmd.resp_type = MMC_RSP_R3;
 704                 cmd.cmdarg = 0;
 705
 706                 err = mmc_send_cmd(mmc, &cmd, NULL);
 707
 708                 if (err)
 709                         return err;
 710
 711                 mmc->ocr = cmd.response[0];
 712         }
 713
 714         mmc->version = MMC_VERSION_UNKNOWN;
 715
 716         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 717         mmc->rca = 1;
 718
 719         return 0;
 720 }
 721
 722
 723 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 724 {
 725         struct mmc_cmd cmd;
 726         struct mmc_data data;
 727         int err;
 728
 729         /* Get the Card Status Register */
 730         cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
 731         cmd.resp_type = MMC_RSP_R1;
 732         cmd.cmdarg = 0;
 733
 734         data.dest = (char *)ext_csd;
 735         data.blocks = 1;
 736         data.blocksize = MMC_MAX_BLOCK_LEN;
 737         data.flags = MMC_DATA_READ;
 738
 739         err = mmc_send_cmd(mmc, &cmd, &data);
 740
 741         return err;
 742 }
 743
 744 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 745                         bool send_status)
 746 {
 747         unsigned int status, start;
 748         struct mmc_cmd cmd;
 749         int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
 750         bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
 751                               (index == EXT_CSD_PART_CONF);
 752         int retries = 3;
 753         int ret;
 754
 755         if (mmc->gen_cmd6_time)
 756                 timeout_ms = mmc->gen_cmd6_time * 10;
 757
 758         if (is_part_switch  && mmc->part_switch_time)
 759                 timeout_ms = mmc->part_switch_time * 10;
 760
 761         cmd.cmdidx = MMC_CMD_SWITCH;
 762         cmd.resp_type = MMC_RSP_R1b;
 763         cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
 764                                  (index << 16) |
 765                                  (value << 8);
 766
 767         do {
 768                 ret = mmc_send_cmd(mmc, &cmd, NULL);
 769         } while (ret && retries-- > 0);
 770
 771         if (ret)
 772                 return ret;
 773
 774         start = get_timer(0);
 775
 776         /* poll dat0 for rdy/buys status */
 777         ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 778         if (ret && ret != -ENOSYS)
 779                 return ret;
 780
 781         /*
 782          * In cases when not allowed to poll by using CMD13 or because we aren't
 783          * capable of polling by using mmc_wait_dat0, then rely on waiting the
 784          * stated timeout to be sufficient.
 785          */
 786         if (ret == -ENOSYS && !send_status)
 787                 mdelay(timeout_ms);
 788
 789         /* Finally wait until the card is ready or indicates a failure
 790          * to switch. It doesn't hurt to use CMD13 here even if send_status
 791          * is false, because by now (after 'timeout_ms' ms) the bus should be
 792          * reliable.
 793          */
 794         do {
 795                 ret = mmc_send_status(mmc, &status);
 796
 797                 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
 798                         pr_debug("switch failed %d/%d/0x%x !\n", set, index,
 799                                  value);
 800                         return -EIO;
 801                 }
 802                 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
 803                         return 0;
 804                 udelay(100);
 805         } while (get_timer(start) < timeout_ms);
 806
 807         return -ETIMEDOUT;
 808 }
 809
 810 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 811 {
 812         return __mmc_switch(mmc, set, index, value, true);
 813 }
 814
 815 #if !CONFIG_IS_ENABLED(MMC_TINY)
 816 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
 817                               bool hsdowngrade)
 818 {
 819         int err;
 820         int speed_bits;
 821
 822         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 823
 824         switch (mode) {
 825         case MMC_HS:
 826         case MMC_HS_52:
 827         case MMC_DDR_52:
 828                 speed_bits = EXT_CSD_TIMING_HS;
 829                 break;
 830 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 831         case MMC_HS_200:
 832                 speed_bits = EXT_CSD_TIMING_HS200;
 833                 break;
 834 #endif
 835 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 836         case MMC_HS_400:
 837                 speed_bits = EXT_CSD_TIMING_HS400;
 838                 break;
 839 #endif
 840 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 841         case MMC_HS_400_ES:
 842                 speed_bits = EXT_CSD_TIMING_HS400;
 843                 break;
 844 #endif
 845         case MMC_LEGACY:
 846                 speed_bits = EXT_CSD_TIMING_LEGACY;
 847                 break;
 848         default:
 849                 return -EINVAL;
 850         }
 851
 852         err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
 853                            speed_bits, !hsdowngrade);
 854         if (err)
 855                 return err;
 856
 857 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 858     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 859         /*
 860          * In case the eMMC is in HS200/HS400 mode and we are downgrading
 861          * to HS mode, the card clock are still running much faster than
 862          * the supported HS mode clock, so we can not reliably read out
 863          * Extended CSD. Reconfigure the controller to run at HS mode.
 864          */
 865         if (hsdowngrade) {
 866                 mmc_select_mode(mmc, MMC_HS);
 867                 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
 868         }
 869 #endif
 870
 871         if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
 872                 /* Now check to see that it worked */
 873                 err = mmc_send_ext_csd(mmc, test_csd);
 874                 if (err)
 875                         return err;
 876
 877                 /* No high-speed support */
 878                 if (!test_csd[EXT_CSD_HS_TIMING])
 879                         return -ENOTSUPP;
 880         }
 881
 882         return 0;
 883 }
 884
 885 static int mmc_get_capabilities(struct mmc *mmc)
 886 {
 887         u8 *ext_csd = mmc->ext_csd;
 888         char cardtype;
 889
 890         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
 891
 892         if (mmc_host_is_spi(mmc))
 893                 return 0;
 894
 895         /* Only version 4 supports high-speed */
 896         if (mmc->version < MMC_VERSION_4)
 897                 return 0;
 898
 899         if (!ext_csd) {
 900                 pr_err("No ext_csd found!\n"); /* this should enver happen */
 901                 return -ENOTSUPP;
 902         }
 903
 904         mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
 905
 906         cardtype = ext_csd[EXT_CSD_CARD_TYPE];
 907         mmc->cardtype = cardtype;
 908
 909 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 910         if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
 911                         EXT_CSD_CARD_TYPE_HS200_1_8V)) {
 912                 mmc->card_caps |= MMC_MODE_HS200;
 913         }
 914 #endif
 915 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
 916         CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 917         if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
 918                         EXT_CSD_CARD_TYPE_HS400_1_8V)) {
 919                 mmc->card_caps |= MMC_MODE_HS400;
 920         }
 921 #endif
 922         if (cardtype & EXT_CSD_CARD_TYPE_52) {
 923                 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
 924                         mmc->card_caps |= MMC_MODE_DDR_52MHz;
 925                 mmc->card_caps |= MMC_MODE_HS_52MHz;
 926         }
 927         if (cardtype & EXT_CSD_CARD_TYPE_26)
 928                 mmc->card_caps |= MMC_MODE_HS;
 929
 930 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 931         if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
 932             (mmc->card_caps & MMC_MODE_HS400)) {
 933                 mmc->card_caps |= MMC_MODE_HS400_ES;
 934         }
 935 #endif
 936
 937         return 0;
 938 }
 939 #endif
 940
 941 static int mmc_set_capacity(struct mmc *mmc, int part_num)
 942 {
 943         switch (part_num) {
 944         case 0:
 945                 mmc->capacity = mmc->capacity_user;
 946                 break;
 947         case 1:
 948         case 2:
 949                 mmc->capacity = mmc->capacity_boot;
 950                 break;
 951         case 3:
 952                 mmc->capacity = mmc->capacity_rpmb;
 953                 break;
 954         case 4:
 955         case 5:
 956         case 6:
 957         case 7:
 958                 mmc->capacity = mmc->capacity_gp[part_num - 4];
 959                 break;
 960         default:
 961                 return -1;
 962         }
 963
 964         mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 965
 966         return 0;
 967 }
 968
 969 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 970 {
 971         int ret;
 972         int retry = 3;
 973
 974         do {
 975                 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 976                                  EXT_CSD_PART_CONF,
 977                                  (mmc->part_config & ~PART_ACCESS_MASK)
 978                                  | (part_num & PART_ACCESS_MASK));
 979         } while (ret && retry--);
 980
 981         /*
 982          * Set the capacity if the switch succeeded or was intended
 983          * to return to representing the raw device.
 984          */
 985         if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
 986                 ret = mmc_set_capacity(mmc, part_num);
 987                 mmc_get_blk_desc(mmc)->hwpart = part_num;
 988         }
 989
 990         return ret;
 991 }
 992
 993 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
 994 int mmc_hwpart_config(struct mmc *mmc,
 995                       const struct mmc_hwpart_conf *conf,
 996                       enum mmc_hwpart_conf_mode mode)
 997 {
 998         u8 part_attrs = 0;
 999         u32 enh_size_mult;
1000         u32 enh_start_addr;
1001         u32 gp_size_mult[4];
1002         u32 max_enh_size_mult;
1003         u32 tot_enh_size_mult = 0;
1004         u8 wr_rel_set;
1005         int i, pidx, err;
1006         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1007
1008         if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1009                 return -EINVAL;
1010
1011         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
1012                 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
1013                 return -EMEDIUMTYPE;
1014         }
1015
1016         if (!(mmc->part_support & PART_SUPPORT)) {
1017                 pr_err("Card does not support partitioning\n");
1018                 return -EMEDIUMTYPE;
1019         }
1020
1021         if (!mmc->hc_wp_grp_size) {
1022                 pr_err("Card does not define HC WP group size\n");
1023                 return -EMEDIUMTYPE;
1024         }
1025
1026         /* check partition alignment and total enhanced size */
1027         if (conf->user.enh_size) {
1028                 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1029                     conf->user.enh_start % mmc->hc_wp_grp_size) {
1030                         pr_err("User data enhanced area not HC WP group "
1031                                "size aligned\n");
1032                         return -EINVAL;
1033                 }
1034                 part_attrs |= EXT_CSD_ENH_USR;
1035                 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1036                 if (mmc->high_capacity) {
1037                         enh_start_addr = conf->user.enh_start;
1038                 } else {
1039                         enh_start_addr = (conf->user.enh_start << 9);
1040                 }
1041         } else {
1042                 enh_size_mult = 0;
1043                 enh_start_addr = 0;
1044         }
1045         tot_enh_size_mult += enh_size_mult;
1046
1047         for (pidx = 0; pidx < 4; pidx++) {
1048                 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1049                         pr_err("GP%i partition not HC WP group size "
1050                                "aligned\n", pidx+1);
1051                         return -EINVAL;
1052                 }
1053                 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1054                 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1055                         part_attrs |= EXT_CSD_ENH_GP(pidx);
1056                         tot_enh_size_mult += gp_size_mult[pidx];
1057                 }
1058         }
1059
1060         if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1061                 pr_err("Card does not support enhanced attribute\n");
1062                 return -EMEDIUMTYPE;
1063         }
1064
1065         err = mmc_send_ext_csd(mmc, ext_csd);
1066         if (err)
1067                 return err;
1068
1069         max_enh_size_mult =
1070                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1071                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1072                 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1073         if (tot_enh_size_mult > max_enh_size_mult) {
1074                 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1075                        tot_enh_size_mult, max_enh_size_mult);
1076                 return -EMEDIUMTYPE;
1077         }
1078
1079         /* The default value of EXT_CSD_WR_REL_SET is device
1080          * dependent, the values can only be changed if the
1081          * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1082          * changed only once and before partitioning is completed. */
1083         wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1084         if (conf->user.wr_rel_change) {
1085                 if (conf->user.wr_rel_set)
1086                         wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1087                 else
1088                         wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1089         }
1090         for (pidx = 0; pidx < 4; pidx++) {
1091                 if (conf->gp_part[pidx].wr_rel_change) {
1092                         if (conf->gp_part[pidx].wr_rel_set)
1093                                 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1094                         else
1095                                 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1096                 }
1097         }
1098
1099         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1100             !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1101                 puts("Card does not support host controlled partition write "
1102                      "reliability settings\n");
1103                 return -EMEDIUMTYPE;
1104         }
1105
1106         if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1107             EXT_CSD_PARTITION_SETTING_COMPLETED) {
1108                 pr_err("Card already partitioned\n");
1109                 return -EPERM;
1110         }
1111
1112         if (mode == MMC_HWPART_CONF_CHECK)
1113                 return 0;
1114
1115         /* Partitioning requires high-capacity size definitions */
1116         if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1117                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1118                                  EXT_CSD_ERASE_GROUP_DEF, 1);
1119
1120                 if (err)
1121                         return err;
1122
1123                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1124
1125 #if CONFIG_IS_ENABLED(MMC_WRITE)
1126                 /* update erase group size to be high-capacity */
1127                 mmc->erase_grp_size =
1128                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1129 #endif
1130
1131         }
1132
1133         /* all OK, write the configuration */
1134         for (i = 0; i < 4; i++) {
1135                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1136                                  EXT_CSD_ENH_START_ADDR+i,
1137                                  (enh_start_addr >> (i*8)) & 0xFF);
1138                 if (err)
1139                         return err;
1140         }
1141         for (i = 0; i < 3; i++) {
1142                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1143                                  EXT_CSD_ENH_SIZE_MULT+i,
1144                                  (enh_size_mult >> (i*8)) & 0xFF);
1145                 if (err)
1146                         return err;
1147         }
1148         for (pidx = 0; pidx < 4; pidx++) {
1149                 for (i = 0; i < 3; i++) {
1150                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1151                                          EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1152                                          (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1153                         if (err)
1154                                 return err;
1155                 }
1156         }
1157         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1158                          EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1159         if (err)
1160                 return err;
1161
1162         if (mode == MMC_HWPART_CONF_SET)
1163                 return 0;
1164
1165         /* The WR_REL_SET is a write-once register but shall be
1166          * written before setting PART_SETTING_COMPLETED. As it is
1167          * write-once we can only write it when completing the
1168          * partitioning. */
1169         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1170                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1171                                  EXT_CSD_WR_REL_SET, wr_rel_set);
1172                 if (err)
1173                         return err;
1174         }
1175
1176         /* Setting PART_SETTING_COMPLETED confirms the partition
1177          * configuration but it only becomes effective after power
1178          * cycle, so we do not adjust the partition related settings
1179          * in the mmc struct. */
1180
1181         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1182                          EXT_CSD_PARTITION_SETTING,
1183                          EXT_CSD_PARTITION_SETTING_COMPLETED);
1184         if (err)
1185                 return err;
1186
1187         return 0;
1188 }
1189 #endif
1190
1191 #if !CONFIG_IS_ENABLED(DM_MMC)
1192 int mmc_getcd(struct mmc *mmc)
1193 {
1194         int cd;
1195
1196         cd = board_mmc_getcd(mmc);
1197
1198         if (cd < 0) {
1199                 if (mmc->cfg->ops->getcd)
1200                         cd = mmc->cfg->ops->getcd(mmc);
1201                 else
1202                         cd = 1;
1203         }
1204
1205         return cd;
1206 }
1207 #endif
1208
1209 #if !CONFIG_IS_ENABLED(MMC_TINY)
1210 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1211 {
1212         struct mmc_cmd cmd;
1213         struct mmc_data data;
1214
1215         /* Switch the frequency */
1216         cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1217         cmd.resp_type = MMC_RSP_R1;
1218         cmd.cmdarg = (mode << 31) | 0xffffff;
1219         cmd.cmdarg &= ~(0xf << (group * 4));
1220         cmd.cmdarg |= value << (group * 4);
1221
1222         data.dest = (char *)resp;
1223         data.blocksize = 64;
1224         data.blocks = 1;
1225         data.flags = MMC_DATA_READ;
1226
1227         return mmc_send_cmd(mmc, &cmd, &data);
1228 }
1229
1230 static int sd_get_capabilities(struct mmc *mmc)
1231 {
1232         int err;
1233         struct mmc_cmd cmd;
1234         ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1235         ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1236         struct mmc_data data;
1237         int timeout;
1238 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1239         u32 sd3_bus_mode;
1240 #endif
1241
1242         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1243
1244         if (mmc_host_is_spi(mmc))
1245                 return 0;
1246
1247         /* Read the SCR to find out if this card supports higher speeds */
1248         cmd.cmdidx = MMC_CMD_APP_CMD;
1249         cmd.resp_type = MMC_RSP_R1;
1250         cmd.cmdarg = mmc->rca << 16;
1251
1252         err = mmc_send_cmd(mmc, &cmd, NULL);
1253
1254         if (err)
1255                 return err;
1256
1257         cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1258         cmd.resp_type = MMC_RSP_R1;
1259         cmd.cmdarg = 0;
1260
1261         timeout = 3;
1262
1263 retry_scr:
1264         data.dest = (char *)scr;
1265         data.blocksize = 8;
1266         data.blocks = 1;
1267         data.flags = MMC_DATA_READ;
1268
1269         err = mmc_send_cmd(mmc, &cmd, &data);
1270
1271         if (err) {
1272                 if (timeout--)
1273                         goto retry_scr;
1274
1275                 return err;
1276         }
1277
1278         mmc->scr[0] = __be32_to_cpu(scr[0]);
1279         mmc->scr[1] = __be32_to_cpu(scr[1]);
1280
1281         switch ((mmc->scr[0] >> 24) & 0xf) {
1282         case 0:
1283                 mmc->version = SD_VERSION_1_0;
1284                 break;
1285         case 1:
1286                 mmc->version = SD_VERSION_1_10;
1287                 break;
1288         case 2:
1289                 mmc->version = SD_VERSION_2;
1290                 if ((mmc->scr[0] >> 15) & 0x1)
1291                         mmc->version = SD_VERSION_3;
1292                 break;
1293         default:
1294                 mmc->version = SD_VERSION_1_0;
1295                 break;
1296         }
1297
1298         if (mmc->scr[0] & SD_DATA_4BIT)
1299                 mmc->card_caps |= MMC_MODE_4BIT;
1300
1301         /* Version 1.0 doesn't support switching */
1302         if (mmc->version == SD_VERSION_1_0)
1303                 return 0;
1304
1305         timeout = 4;
1306         while (timeout--) {
1307                 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1308                                 (u8 *)switch_status);
1309
1310                 if (err)
1311                         return err;
1312
1313                 /* The high-speed function is busy.  Try again */
1314                 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1315                         break;
1316         }
1317
1318         /* If high-speed isn't supported, we return */
1319         if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1320                 mmc->card_caps |= MMC_CAP(SD_HS);
1321
1322 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1323         /* Version before 3.0 don't support UHS modes */
1324         if (mmc->version < SD_VERSION_3)
1325                 return 0;
1326
1327         sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1328         if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1329                 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1330         if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1331                 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1332         if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1333                 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1334         if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1335                 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1336         if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1337                 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1338 #endif
1339
1340         return 0;
1341 }
1342
1343 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1344 {
1345         int err;
1346
1347         ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1348         int speed;
1349
1350         /* SD version 1.00 and 1.01 does not support CMD 6 */
1351         if (mmc->version == SD_VERSION_1_0)
1352                 return 0;
1353
1354         switch (mode) {
1355         case SD_LEGACY:
1356                 speed = UHS_SDR12_BUS_SPEED;
1357                 break;
1358         case SD_HS:
1359                 speed = HIGH_SPEED_BUS_SPEED;
1360                 break;
1361 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1362         case UHS_SDR12:
1363                 speed = UHS_SDR12_BUS_SPEED;
1364                 break;
1365         case UHS_SDR25:
1366                 speed = UHS_SDR25_BUS_SPEED;
1367                 break;
1368         case UHS_SDR50:
1369                 speed = UHS_SDR50_BUS_SPEED;
1370                 break;
1371         case UHS_DDR50:
1372                 speed = UHS_DDR50_BUS_SPEED;
1373                 break;
1374         case UHS_SDR104:
1375                 speed = UHS_SDR104_BUS_SPEED;
1376                 break;
1377 #endif
1378         default:
1379                 return -EINVAL;
1380         }
1381
1382         err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1383         if (err)
1384                 return err;
1385
1386         if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1387                 return -ENOTSUPP;
1388
1389         return 0;
1390 }
1391
1392 static int sd_select_bus_width(struct mmc *mmc, int w)
1393 {
1394         int err;
1395         struct mmc_cmd cmd;
1396
1397         if ((w != 4) && (w != 1))
1398                 return -EINVAL;
1399
1400         cmd.cmdidx = MMC_CMD_APP_CMD;
1401         cmd.resp_type = MMC_RSP_R1;
1402         cmd.cmdarg = mmc->rca << 16;
1403
1404         err = mmc_send_cmd(mmc, &cmd, NULL);
1405         if (err)
1406                 return err;
1407
1408         cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1409         cmd.resp_type = MMC_RSP_R1;
1410         if (w == 4)
1411                 cmd.cmdarg = 2;
1412         else if (w == 1)
1413                 cmd.cmdarg = 0;
1414         err = mmc_send_cmd(mmc, &cmd, NULL);
1415         if (err)
1416                 return err;
1417
1418         return 0;
1419 }
1420 #endif
1421
1422 #if CONFIG_IS_ENABLED(MMC_WRITE)
1423 static int sd_read_ssr(struct mmc *mmc)
1424 {
1425         static const unsigned int sd_au_size[] = {
1426                 0,              SZ_16K / 512,           SZ_32K / 512,
1427                 SZ_64K / 512,   SZ_128K / 512,          SZ_256K / 512,
1428                 SZ_512K / 512,  SZ_1M / 512,            SZ_2M / 512,
1429                 SZ_4M / 512,    SZ_8M / 512,            (SZ_8M + SZ_4M) / 512,
1430                 SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1431                 SZ_64M / 512,
1432         };
1433         int err, i;
1434         struct mmc_cmd cmd;
1435         ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1436         struct mmc_data data;
1437         int timeout = 3;
1438         unsigned int au, eo, et, es;
1439
1440         cmd.cmdidx = MMC_CMD_APP_CMD;
1441         cmd.resp_type = MMC_RSP_R1;
1442         cmd.cmdarg = mmc->rca << 16;
1443
1444         err = mmc_send_cmd(mmc, &cmd, NULL);
1445 #ifdef CONFIG_MMC_QUIRKS
1446         if (err && (mmc->quirks & MMC_QUIRK_RETRY_APP_CMD)) {
1447                 int retries = 4;
1448                 /*
1449                  * It has been seen that APP_CMD may fail on the first
1450                  * attempt, let's try a few more times
1451                  */
1452                 do {
1453                         err = mmc_send_cmd(mmc, &cmd, NULL);
1454                         if (!err)
1455                                 break;
1456                 } while (retries--);
1457         }
1458 #endif
1459         if (err)
1460                 return err;
1461
1462         cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1463         cmd.resp_type = MMC_RSP_R1;
1464         cmd.cmdarg = 0;
1465
1466 retry_ssr:
1467         data.dest = (char *)ssr;
1468         data.blocksize = 64;
1469         data.blocks = 1;
1470         data.flags = MMC_DATA_READ;
1471
1472         err = mmc_send_cmd(mmc, &cmd, &data);
1473         if (err) {
1474                 if (timeout--)
1475                         goto retry_ssr;
1476
1477                 return err;
1478         }
1479
1480         for (i = 0; i < 16; i++)
1481                 ssr[i] = be32_to_cpu(ssr[i]);
1482
1483         au = (ssr[2] >> 12) & 0xF;
1484         if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1485                 mmc->ssr.au = sd_au_size[au];
1486                 es = (ssr[3] >> 24) & 0xFF;
1487                 es |= (ssr[2] & 0xFF) << 8;
1488                 et = (ssr[3] >> 18) & 0x3F;
1489                 if (es && et) {
1490                         eo = (ssr[3] >> 16) & 0x3;
1491                         mmc->ssr.erase_timeout = (et * 1000) / es;
1492                         mmc->ssr.erase_offset = eo * 1000;
1493                 }
1494         } else {
1495                 pr_debug("Invalid Allocation Unit Size.\n");
1496         }
1497
1498         return 0;
1499 }
1500 #endif
1501 /* frequency bases */
1502 /* divided by 10 to be nice to platforms without floating point */
1503 static const int fbase[] = {
1504         10000,
1505         100000,
1506         1000000,
1507         10000000,
1508 };
1509
1510 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
1511  * to platforms without floating point.
1512  */
1513 static const u8 multipliers[] = {
1514         0,      /* reserved */
1515         10,
1516         12,
1517         13,
1518         15,
1519         20,
1520         25,
1521         30,
1522         35,
1523         40,
1524         45,
1525         50,
1526         55,
1527         60,
1528         70,
1529         80,
1530 };
1531
1532 static inline int bus_width(uint cap)
1533 {
1534         if (cap == MMC_MODE_8BIT)
1535                 return 8;
1536         if (cap == MMC_MODE_4BIT)
1537                 return 4;
1538         if (cap == MMC_MODE_1BIT)
1539                 return 1;
1540         pr_warn("invalid bus witdh capability 0x%x\n", cap);
1541         return 0;
1542 }
1543
1544 #if !CONFIG_IS_ENABLED(DM_MMC)
1545 #ifdef MMC_SUPPORTS_TUNING
1546 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1547 {
1548         return -ENOTSUPP;
1549 }
1550 #endif
1551
1552 static int mmc_set_ios(struct mmc *mmc)
1553 {
1554         int ret = 0;
1555
1556         if (mmc->cfg->ops->set_ios)
1557                 ret = mmc->cfg->ops->set_ios(mmc);
1558
1559         return ret;
1560 }
1561
1562 static int mmc_host_power_cycle(struct mmc *mmc)
1563 {
1564         int ret = 0;
1565
1566         if (mmc->cfg->ops->host_power_cycle)
1567                 ret = mmc->cfg->ops->host_power_cycle(mmc);
1568
1569         return ret;
1570 }
1571 #endif
1572
1573 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1574 {
1575         if (!disable) {
1576                 if (clock > mmc->cfg->f_max)
1577                         clock = mmc->cfg->f_max;
1578
1579                 if (clock < mmc->cfg->f_min)
1580                         clock = mmc->cfg->f_min;
1581         }
1582
1583         mmc->clock = clock;
1584         mmc->clk_disable = disable;
1585
1586         debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1587
1588         return mmc_set_ios(mmc);
1589 }
1590
1591 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1592 {
1593         mmc->bus_width = width;
1594
1595         return mmc_set_ios(mmc);
1596 }
1597
1598 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1599 /*
1600  * helper function to display the capabilities in a human
1601  * friendly manner. The capabilities include bus width and
1602  * supported modes.
1603  */
1604 void mmc_dump_capabilities(const char *text, uint caps)
1605 {
1606         enum bus_mode mode;
1607
1608         pr_debug("%s: widths [", text);
1609         if (caps & MMC_MODE_8BIT)
1610                 pr_debug("8, ");
1611         if (caps & MMC_MODE_4BIT)
1612                 pr_debug("4, ");
1613         if (caps & MMC_MODE_1BIT)
1614                 pr_debug("1, ");
1615         pr_debug("\b\b] modes [");
1616         for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1617                 if (MMC_CAP(mode) & caps)
1618                         pr_debug("%s, ", mmc_mode_name(mode));
1619         pr_debug("\b\b]\n");
1620 }
1621 #endif
1622
1623 struct mode_width_tuning {
1624         enum bus_mode mode;
1625         uint widths;
1626 #ifdef MMC_SUPPORTS_TUNING
1627         uint tuning;
1628 #endif
1629 };
1630
1631 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1632 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1633 {
1634         switch (voltage) {
1635         case MMC_SIGNAL_VOLTAGE_000: return 0;
1636         case MMC_SIGNAL_VOLTAGE_330: return 3300;
1637         case MMC_SIGNAL_VOLTAGE_180: return 1800;
1638         case MMC_SIGNAL_VOLTAGE_120: return 1200;
1639         }
1640         return -EINVAL;
1641 }
1642
1643 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1644 {
1645         int err;
1646
1647         if (mmc->signal_voltage == signal_voltage)
1648                 return 0;
1649
1650         mmc->signal_voltage = signal_voltage;
1651         err = mmc_set_ios(mmc);
1652         if (err)
1653                 pr_debug("unable to set voltage (err %d)\n", err);
1654
1655         return err;
1656 }
1657 #else
1658 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1659 {
1660         return 0;
1661 }
1662 #endif
1663
1664 #if !CONFIG_IS_ENABLED(MMC_TINY)
1665 static const struct mode_width_tuning sd_modes_by_pref[] = {
1666 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1667 #ifdef MMC_SUPPORTS_TUNING
1668         {
1669                 .mode = UHS_SDR104,
1670                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1671                 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1672         },
1673 #endif
1674         {
1675                 .mode = UHS_SDR50,
1676                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1677         },
1678         {
1679                 .mode = UHS_DDR50,
1680                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1681         },
1682         {
1683                 .mode = UHS_SDR25,
1684                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1685         },
1686 #endif
1687         {
1688                 .mode = SD_HS,
1689                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1690         },
1691 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1692         {
1693                 .mode = UHS_SDR12,
1694                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1695         },
1696 #endif
1697         {
1698                 .mode = SD_LEGACY,
1699                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1700         }
1701 };
1702
1703 #define for_each_sd_mode_by_pref(caps, mwt) \
1704         for (mwt = sd_modes_by_pref;\
1705              mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1706              mwt++) \
1707                 if (caps & MMC_CAP(mwt->mode))
1708
1709 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1710 {
1711         int err;
1712         uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1713         const struct mode_width_tuning *mwt;
1714 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1715         bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1716 #else
1717         bool uhs_en = false;
1718 #endif
1719         uint caps;
1720
1721 #ifdef DEBUG
1722         mmc_dump_capabilities("sd card", card_caps);
1723         mmc_dump_capabilities("host", mmc->host_caps);
1724 #endif
1725
1726         if (mmc_host_is_spi(mmc)) {
1727                 mmc_set_bus_width(mmc, 1);
1728                 mmc_select_mode(mmc, SD_LEGACY);
1729                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1730                 return 0;
1731         }
1732
1733         /* Restrict card's capabilities by what the host can do */
1734         caps = card_caps & mmc->host_caps;
1735
1736         if (!uhs_en)
1737                 caps &= ~UHS_CAPS;
1738
1739         for_each_sd_mode_by_pref(caps, mwt) {
1740                 uint *w;
1741
1742                 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1743                         if (*w & caps & mwt->widths) {
1744                                 pr_debug("trying mode %s width %d (at %d MHz)\n",
1745                                          mmc_mode_name(mwt->mode),
1746                                          bus_width(*w),
1747                                          mmc_mode2freq(mmc, mwt->mode) / 1000000);
1748
1749                                 /* configure the bus width (card + host) */
1750                                 err = sd_select_bus_width(mmc, bus_width(*w));
1751                                 if (err)
1752                                         goto error;
1753                                 mmc_set_bus_width(mmc, bus_width(*w));
1754
1755                                 /* configure the bus mode (card) */
1756                                 err = sd_set_card_speed(mmc, mwt->mode);
1757                                 if (err)
1758                                         goto error;
1759
1760                                 /* configure the bus mode (host) */
1761                                 mmc_select_mode(mmc, mwt->mode);
1762                                 mmc_set_clock(mmc, mmc->tran_speed,
1763                                                 MMC_CLK_ENABLE);
1764
1765 #ifdef MMC_SUPPORTS_TUNING
1766                                 /* execute tuning if needed */
1767                                 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1768                                         err = mmc_execute_tuning(mmc,
1769                                                                  mwt->tuning);
1770                                         if (err) {
1771                                                 pr_debug("tuning failed\n");
1772                                                 goto error;
1773                                         }
1774                                 }
1775 #endif
1776
1777 #if CONFIG_IS_ENABLED(MMC_WRITE)
1778                                 err = sd_read_ssr(mmc);
1779                                 if (err)
1780                                         pr_warn("unable to read ssr\n");
1781 #endif
1782                                 if (!err)
1783                                         return 0;
1784
1785 error:
1786                                 /* revert to a safer bus speed */
1787                                 mmc_select_mode(mmc, SD_LEGACY);
1788                                 mmc_set_clock(mmc, mmc->tran_speed,
1789                                                 MMC_CLK_ENABLE);
1790                         }
1791                 }
1792         }
1793
1794         pr_err("unable to select a mode\n");
1795         return -ENOTSUPP;
1796 }
1797
1798 /*
1799  * read the compare the part of ext csd that is constant.
1800  * This can be used to check that the transfer is working
1801  * as expected.
1802  */
1803 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1804 {
1805         int err;
1806         const u8 *ext_csd = mmc->ext_csd;
1807         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1808
1809         if (mmc->version < MMC_VERSION_4)
1810                 return 0;
1811
1812         err = mmc_send_ext_csd(mmc, test_csd);
1813         if (err)
1814                 return err;
1815
1816         /* Only compare read only fields */
1817         if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1818                 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1819             ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1820                 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1821             ext_csd[EXT_CSD_REV]
1822                 == test_csd[EXT_CSD_REV] &&
1823             ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1824                 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1825             memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1826                    &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1827                 return 0;
1828
1829         return -EBADMSG;
1830 }
1831
1832 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1833 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1834                                   uint32_t allowed_mask)
1835 {
1836         u32 card_mask = 0;
1837
1838         switch (mode) {
1839         case MMC_HS_400_ES:
1840         case MMC_HS_400:
1841         case MMC_HS_200:
1842                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1843                     EXT_CSD_CARD_TYPE_HS400_1_8V))
1844                         card_mask |= MMC_SIGNAL_VOLTAGE_180;
1845                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1846                     EXT_CSD_CARD_TYPE_HS400_1_2V))
1847                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1848                 break;
1849         case MMC_DDR_52:
1850                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1851                         card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1852                                      MMC_SIGNAL_VOLTAGE_180;
1853                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1854                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1855                 break;
1856         default:
1857                 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1858                 break;
1859         }
1860
1861         while (card_mask & allowed_mask) {
1862                 enum mmc_voltage best_match;
1863
1864                 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1865                 if (!mmc_set_signal_voltage(mmc,  best_match))
1866                         return 0;
1867
1868                 allowed_mask &= ~best_match;
1869         }
1870
1871         return -ENOTSUPP;
1872 }
1873 #else
1874 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1875                                          uint32_t allowed_mask)
1876 {
1877         return 0;
1878 }
1879 #endif
1880
1881 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1882 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1883         {
1884                 .mode = MMC_HS_400_ES,
1885                 .widths = MMC_MODE_8BIT,
1886         },
1887 #endif
1888 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1889         {
1890                 .mode = MMC_HS_400,
1891                 .widths = MMC_MODE_8BIT,
1892                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1893         },
1894 #endif
1895 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1896         {
1897                 .mode = MMC_HS_200,
1898                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1899                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1900         },
1901 #endif
1902         {
1903                 .mode = MMC_DDR_52,
1904                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1905         },
1906         {
1907                 .mode = MMC_HS_52,
1908                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1909         },
1910         {
1911                 .mode = MMC_HS,
1912                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1913         },
1914         {
1915                 .mode = MMC_LEGACY,
1916                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1917         }
1918 };
1919
1920 #define for_each_mmc_mode_by_pref(caps, mwt) \
1921         for (mwt = mmc_modes_by_pref;\
1922             mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1923             mwt++) \
1924                 if (caps & MMC_CAP(mwt->mode))
1925
1926 static const struct ext_csd_bus_width {
1927         uint cap;
1928         bool is_ddr;
1929         uint ext_csd_bits;
1930 } ext_csd_bus_width[] = {
1931         {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1932         {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1933         {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1934         {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1935         {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1936 };
1937
1938 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1939 static int mmc_select_hs400(struct mmc *mmc)
1940 {
1941         int err;
1942
1943         /* Set timing to HS200 for tuning */
1944         err = mmc_set_card_speed(mmc, MMC_HS_200, false);
1945         if (err)
1946                 return err;
1947
1948         /* configure the bus mode (host) */
1949         mmc_select_mode(mmc, MMC_HS_200);
1950         mmc_set_clock(mmc, mmc->tran_speed, false);
1951
1952         /* execute tuning if needed */
1953         err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1954         if (err) {
1955                 debug("tuning failed\n");
1956                 return err;
1957         }
1958
1959         /* Set back to HS */
1960         mmc_set_card_speed(mmc, MMC_HS, true);
1961
1962         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1963                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1964         if (err)
1965                 return err;
1966
1967         err = mmc_set_card_speed(mmc, MMC_HS_400, false);
1968         if (err)
1969                 return err;
1970
1971         mmc_select_mode(mmc, MMC_HS_400);
1972         err = mmc_set_clock(mmc, mmc->tran_speed, false);
1973         if (err)
1974                 return err;
1975
1976         return 0;
1977 }
1978 #else
1979 static int mmc_select_hs400(struct mmc *mmc)
1980 {
1981         return -ENOTSUPP;
1982 }
1983 #endif
1984
1985 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1986 #if !CONFIG_IS_ENABLED(DM_MMC)
1987 static int mmc_set_enhanced_strobe(struct mmc *mmc)
1988 {
1989         return -ENOTSUPP;
1990 }
1991 #endif
1992 static int mmc_select_hs400es(struct mmc *mmc)
1993 {
1994         int err;
1995
1996         err = mmc_set_card_speed(mmc, MMC_HS, true);
1997         if (err)
1998                 return err;
1999
2000         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2001                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2002                          EXT_CSD_BUS_WIDTH_STROBE);
2003         if (err) {
2004                 printf("switch to bus width for hs400 failed\n");
2005                 return err;
2006         }
2007         /* TODO: driver strength */
2008         err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2009         if (err)
2010                 return err;
2011
2012         mmc_select_mode(mmc, MMC_HS_400_ES);
2013         err = mmc_set_clock(mmc, mmc->tran_speed, false);
2014         if (err)
2015                 return err;
2016
2017         return mmc_set_enhanced_strobe(mmc);
2018 }
2019 #else
2020 static int mmc_select_hs400es(struct mmc *mmc)
2021 {
2022         return -ENOTSUPP;
2023 }
2024 #endif
2025
2026 #define for_each_supported_width(caps, ddr, ecbv) \
2027         for (ecbv = ext_csd_bus_width;\
2028             ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2029             ecbv++) \
2030                 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2031
2032 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
2033 {
2034         int err;
2035         const struct mode_width_tuning *mwt;
2036         const struct ext_csd_bus_width *ecbw;
2037
2038 #ifdef DEBUG
2039         mmc_dump_capabilities("mmc", card_caps);
2040         mmc_dump_capabilities("host", mmc->host_caps);
2041 #endif
2042
2043         if (mmc_host_is_spi(mmc)) {
2044                 mmc_set_bus_width(mmc, 1);
2045                 mmc_select_mode(mmc, MMC_LEGACY);
2046                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2047                 return 0;
2048         }
2049
2050         /* Restrict card's capabilities by what the host can do */
2051         card_caps &= mmc->host_caps;
2052
2053         /* Only version 4 of MMC supports wider bus widths */
2054         if (mmc->version < MMC_VERSION_4)
2055                 return 0;
2056
2057         if (!mmc->ext_csd) {
2058                 pr_debug("No ext_csd found!\n"); /* this should enver happen */
2059                 return -ENOTSUPP;
2060         }
2061
2062 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2063     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2064         /*
2065          * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2066          * before doing anything else, since a transition from either of
2067          * the HS200/HS400 mode directly to legacy mode is not supported.
2068          */
2069         if (mmc->selected_mode == MMC_HS_200 ||
2070             mmc->selected_mode == MMC_HS_400)
2071                 mmc_set_card_speed(mmc, MMC_HS, true);
2072         else
2073 #endif
2074                 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
2075
2076         for_each_mmc_mode_by_pref(card_caps, mwt) {
2077                 for_each_supported_width(card_caps & mwt->widths,
2078                                          mmc_is_mode_ddr(mwt->mode), ecbw) {
2079                         enum mmc_voltage old_voltage;
2080                         pr_debug("trying mode %s width %d (at %d MHz)\n",
2081                                  mmc_mode_name(mwt->mode),
2082                                  bus_width(ecbw->cap),
2083                                  mmc_mode2freq(mmc, mwt->mode) / 1000000);
2084                         old_voltage = mmc->signal_voltage;
2085                         err = mmc_set_lowest_voltage(mmc, mwt->mode,
2086                                                      MMC_ALL_SIGNAL_VOLTAGE);
2087                         if (err)
2088                                 continue;
2089
2090                         /* configure the bus width (card + host) */
2091                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2092                                     EXT_CSD_BUS_WIDTH,
2093                                     ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2094                         if (err)
2095                                 goto error;
2096                         mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2097
2098                         if (mwt->mode == MMC_HS_400) {
2099                                 err = mmc_select_hs400(mmc);
2100                                 if (err) {
2101                                         printf("Select HS400 failed %d\n", err);
2102                                         goto error;
2103                                 }
2104                         } else if (mwt->mode == MMC_HS_400_ES) {
2105                                 err = mmc_select_hs400es(mmc);
2106                                 if (err) {
2107                                         printf("Select HS400ES failed %d\n",
2108                                                err);
2109                                         goto error;
2110                                 }
2111                         } else {
2112                                 /* configure the bus speed (card) */
2113                                 err = mmc_set_card_speed(mmc, mwt->mode, false);
2114                                 if (err)
2115                                         goto error;
2116
2117                                 /*
2118                                  * configure the bus width AND the ddr mode
2119                                  * (card). The host side will be taken care
2120                                  * of in the next step
2121                                  */
2122                                 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2123                                         err = mmc_switch(mmc,
2124                                                          EXT_CSD_CMD_SET_NORMAL,
2125                                                          EXT_CSD_BUS_WIDTH,
2126                                                          ecbw->ext_csd_bits);
2127                                         if (err)
2128                                                 goto error;
2129                                 }
2130
2131                                 /* configure the bus mode (host) */
2132                                 mmc_select_mode(mmc, mwt->mode);
2133                                 mmc_set_clock(mmc, mmc->tran_speed,
2134                                               MMC_CLK_ENABLE);
2135 #ifdef MMC_SUPPORTS_TUNING
2136
2137                                 /* execute tuning if needed */
2138                                 if (mwt->tuning) {
2139                                         err = mmc_execute_tuning(mmc,
2140                                                                  mwt->tuning);
2141                                         if (err) {
2142                                                 pr_debug("tuning failed\n");
2143                                                 goto error;
2144                                         }
2145                                 }
2146 #endif
2147                         }
2148
2149                         /* do a transfer to check the configuration */
2150                         err = mmc_read_and_compare_ext_csd(mmc);
2151                         if (!err)
2152                                 return 0;
2153 error:
2154                         mmc_set_signal_voltage(mmc, old_voltage);
2155                         /* if an error occured, revert to a safer bus mode */
2156                         mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2157                                    EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2158                         mmc_select_mode(mmc, MMC_LEGACY);
2159                         mmc_set_bus_width(mmc, 1);
2160                 }
2161         }
2162
2163         pr_err("unable to select a mode\n");
2164
2165         return -ENOTSUPP;
2166 }
2167 #endif
2168
2169 #if CONFIG_IS_ENABLED(MMC_TINY)
2170 DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2171 #endif
2172
2173 static int mmc_startup_v4(struct mmc *mmc)
2174 {
2175         int err, i;
2176         u64 capacity;
2177         bool has_parts = false;
2178         bool part_completed;
2179         static const u32 mmc_versions[] = {
2180                 MMC_VERSION_4,
2181                 MMC_VERSION_4_1,
2182                 MMC_VERSION_4_2,
2183                 MMC_VERSION_4_3,
2184                 MMC_VERSION_4_4,
2185                 MMC_VERSION_4_41,
2186                 MMC_VERSION_4_5,
2187                 MMC_VERSION_5_0,
2188                 MMC_VERSION_5_1
2189         };
2190
2191 #if CONFIG_IS_ENABLED(MMC_TINY)
2192         u8 *ext_csd = ext_csd_bkup;
2193
2194         if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2195                 return 0;
2196
2197         if (!mmc->ext_csd)
2198                 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2199
2200         err = mmc_send_ext_csd(mmc, ext_csd);
2201         if (err)
2202                 goto error;
2203
2204         /* store the ext csd for future reference */
2205         if (!mmc->ext_csd)
2206                 mmc->ext_csd = ext_csd;
2207 #else
2208         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2209
2210         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2211                 return 0;
2212
2213         /* check  ext_csd version and capacity */
2214         err = mmc_send_ext_csd(mmc, ext_csd);
2215         if (err)
2216                 goto error;
2217
2218         /* store the ext csd for future reference */
2219         if (!mmc->ext_csd)
2220                 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2221         if (!mmc->ext_csd)
2222                 return -ENOMEM;
2223         memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2224 #endif
2225         if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2226                 return -EINVAL;
2227
2228         mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2229
2230         if (mmc->version >= MMC_VERSION_4_2) {
2231                 /*
2232                  * According to the JEDEC Standard, the value of
2233                  * ext_csd's capacity is valid if the value is more
2234                  * than 2GB
2235                  */
2236                 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2237                                 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2238                                 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2239                                 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2240                 capacity *= MMC_MAX_BLOCK_LEN;
2241                 if ((capacity >> 20) > 2 * 1024)
2242                         mmc->capacity_user = capacity;
2243         }
2244
2245         if (mmc->version >= MMC_VERSION_4_5)
2246                 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2247
2248         /* The partition data may be non-zero but it is only
2249          * effective if PARTITION_SETTING_COMPLETED is set in
2250          * EXT_CSD, so ignore any data if this bit is not set,
2251          * except for enabling the high-capacity group size
2252          * definition (see below).
2253          */
2254         part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2255                             EXT_CSD_PARTITION_SETTING_COMPLETED);
2256
2257         mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2258         /* Some eMMC set the value too low so set a minimum */
2259         if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2260                 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2261
2262         /* store the partition info of emmc */
2263         mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2264         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2265             ext_csd[EXT_CSD_BOOT_MULT])
2266                 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2267         if (part_completed &&
2268             (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2269                 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2270
2271         mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2272
2273         mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2274
2275         for (i = 0; i < 4; i++) {
2276                 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2277                 uint mult = (ext_csd[idx + 2] << 16) +
2278                         (ext_csd[idx + 1] << 8) + ext_csd[idx];
2279                 if (mult)
2280                         has_parts = true;
2281                 if (!part_completed)
2282                         continue;
2283                 mmc->capacity_gp[i] = mult;
2284                 mmc->capacity_gp[i] *=
2285                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2286                 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2287                 mmc->capacity_gp[i] <<= 19;
2288         }
2289
2290 #ifndef CONFIG_SPL_BUILD
2291         if (part_completed) {
2292                 mmc->enh_user_size =
2293                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2294                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2295                         ext_csd[EXT_CSD_ENH_SIZE_MULT];
2296                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2297                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2298                 mmc->enh_user_size <<= 19;
2299                 mmc->enh_user_start =
2300                         (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2301                         (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2302                         (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2303                         ext_csd[EXT_CSD_ENH_START_ADDR];
2304                 if (mmc->high_capacity)
2305                         mmc->enh_user_start <<= 9;
2306         }
2307 #endif
2308
2309         /*
2310          * Host needs to enable ERASE_GRP_DEF bit if device is
2311          * partitioned. This bit will be lost every time after a reset
2312          * or power off. This will affect erase size.
2313          */
2314         if (part_completed)
2315                 has_parts = true;
2316         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2317             (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2318                 has_parts = true;
2319         if (has_parts) {
2320                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2321                                  EXT_CSD_ERASE_GROUP_DEF, 1);
2322
2323                 if (err)
2324                         goto error;
2325
2326                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2327         }
2328
2329         if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2330 #if CONFIG_IS_ENABLED(MMC_WRITE)
2331                 /* Read out group size from ext_csd */
2332                 mmc->erase_grp_size =
2333                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2334 #endif
2335                 /*
2336                  * if high capacity and partition setting completed
2337                  * SEC_COUNT is valid even if it is smaller than 2 GiB
2338                  * JEDEC Standard JESD84-B45, 6.2.4
2339                  */
2340                 if (mmc->high_capacity && part_completed) {
2341                         capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2342                                 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2343                                 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2344                                 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2345                         capacity *= MMC_MAX_BLOCK_LEN;
2346                         mmc->capacity_user = capacity;
2347                 }
2348         }
2349 #if CONFIG_IS_ENABLED(MMC_WRITE)
2350         else {
2351                 /* Calculate the group size from the csd value. */
2352                 int erase_gsz, erase_gmul;
2353
2354                 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2355                 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2356                 mmc->erase_grp_size = (erase_gsz + 1)
2357                         * (erase_gmul + 1);
2358         }
2359 #endif
2360 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2361         mmc->hc_wp_grp_size = 1024
2362                 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2363                 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2364 #endif
2365
2366         mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2367
2368         return 0;
2369 error:
2370         if (mmc->ext_csd) {
2371 #if !CONFIG_IS_ENABLED(MMC_TINY)
2372                 free(mmc->ext_csd);
2373 #endif
2374                 mmc->ext_csd = NULL;
2375         }
2376         return err;
2377 }
2378
2379 static int mmc_startup(struct mmc *mmc)
2380 {
2381         int err, i;
2382         uint mult, freq;
2383         u64 cmult, csize;
2384         struct mmc_cmd cmd;
2385         struct blk_desc *bdesc;
2386
2387 #ifdef CONFIG_MMC_SPI_CRC_ON
2388         if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2389                 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2390                 cmd.resp_type = MMC_RSP_R1;
2391                 cmd.cmdarg = 1;
2392                 err = mmc_send_cmd(mmc, &cmd, NULL);
2393                 if (err)
2394                         return err;
2395         }
2396 #endif
2397
2398         /* Put the Card in Identify Mode */
2399         cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2400                 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2401         cmd.resp_type = MMC_RSP_R2;
2402         cmd.cmdarg = 0;
2403
2404         err = mmc_send_cmd(mmc, &cmd, NULL);
2405
2406 #ifdef CONFIG_MMC_QUIRKS
2407         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2408                 int retries = 4;
2409                 /*
2410                  * It has been seen that SEND_CID may fail on the first
2411                  * attempt, let's try a few more time
2412                  */
2413                 do {
2414                         err = mmc_send_cmd(mmc, &cmd, NULL);
2415                         if (!err)
2416                                 break;
2417                 } while (retries--);
2418         }
2419 #endif
2420
2421         if (err)
2422                 return err;
2423
2424         memcpy(mmc->cid, cmd.response, 16);
2425
2426         /*
2427          * For MMC cards, set the Relative Address.
2428          * For SD cards, get the Relatvie Address.
2429          * This also puts the cards into Standby State
2430          */
2431         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2432                 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2433                 cmd.cmdarg = mmc->rca << 16;
2434                 cmd.resp_type = MMC_RSP_R6;
2435
2436                 err = mmc_send_cmd(mmc, &cmd, NULL);
2437
2438                 if (err)
2439                         return err;
2440
2441                 if (IS_SD(mmc))
2442                         mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2443         }
2444
2445         /* Get the Card-Specific Data */
2446         cmd.cmdidx = MMC_CMD_SEND_CSD;
2447         cmd.resp_type = MMC_RSP_R2;
2448         cmd.cmdarg = mmc->rca << 16;
2449
2450         err = mmc_send_cmd(mmc, &cmd, NULL);
2451
2452         if (err)
2453                 return err;
2454
2455         mmc->csd[0] = cmd.response[0];
2456         mmc->csd[1] = cmd.response[1];
2457         mmc->csd[2] = cmd.response[2];
2458         mmc->csd[3] = cmd.response[3];
2459
2460         if (mmc->version == MMC_VERSION_UNKNOWN) {
2461                 int version = (cmd.response[0] >> 26) & 0xf;
2462
2463                 switch (version) {
2464                 case 0:
2465                         mmc->version = MMC_VERSION_1_2;
2466                         break;
2467                 case 1:
2468                         mmc->version = MMC_VERSION_1_4;
2469                         break;
2470                 case 2:
2471                         mmc->version = MMC_VERSION_2_2;
2472                         break;
2473                 case 3:
2474                         mmc->version = MMC_VERSION_3;
2475                         break;
2476                 case 4:
2477                         mmc->version = MMC_VERSION_4;
2478                         break;
2479                 default:
2480                         mmc->version = MMC_VERSION_1_2;
2481                         break;
2482                 }
2483         }
2484
2485         /* divide frequency by 10, since the mults are 10x bigger */
2486         freq = fbase[(cmd.response[0] & 0x7)];
2487         mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2488
2489         mmc->legacy_speed = freq * mult;
2490         mmc_select_mode(mmc, MMC_LEGACY);
2491
2492         mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2493         mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2494 #if CONFIG_IS_ENABLED(MMC_WRITE)
2495
2496         if (IS_SD(mmc))
2497                 mmc->write_bl_len = mmc->read_bl_len;
2498         else
2499                 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2500 #endif
2501
2502         if (mmc->high_capacity) {
2503                 csize = (mmc->csd[1] & 0x3f) << 16
2504                         | (mmc->csd[2] & 0xffff0000) >> 16;
2505                 cmult = 8;
2506         } else {
2507                 csize = (mmc->csd[1] & 0x3ff) << 2
2508                         | (mmc->csd[2] & 0xc0000000) >> 30;
2509                 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2510         }
2511
2512         mmc->capacity_user = (csize + 1) << (cmult + 2);
2513         mmc->capacity_user *= mmc->read_bl_len;
2514         mmc->capacity_boot = 0;
2515         mmc->capacity_rpmb = 0;
2516         for (i = 0; i < 4; i++)
2517                 mmc->capacity_gp[i] = 0;
2518
2519         if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2520                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2521
2522 #if CONFIG_IS_ENABLED(MMC_WRITE)
2523         if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2524                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2525 #endif
2526
2527         if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2528                 cmd.cmdidx = MMC_CMD_SET_DSR;
2529                 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2530                 cmd.resp_type = MMC_RSP_NONE;
2531                 if (mmc_send_cmd(mmc, &cmd, NULL))
2532                         pr_warn("MMC: SET_DSR failed\n");
2533         }
2534
2535         /* Select the card, and put it into Transfer Mode */
2536         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2537                 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2538                 cmd.resp_type = MMC_RSP_R1;
2539                 cmd.cmdarg = mmc->rca << 16;
2540                 err = mmc_send_cmd(mmc, &cmd, NULL);
2541
2542                 if (err)
2543                         return err;
2544         }
2545
2546         /*
2547          * For SD, its erase group is always one sector
2548          */
2549 #if CONFIG_IS_ENABLED(MMC_WRITE)
2550         mmc->erase_grp_size = 1;
2551 #endif
2552         mmc->part_config = MMCPART_NOAVAILABLE;
2553
2554         err = mmc_startup_v4(mmc);
2555         if (err)
2556                 return err;
2557
2558         err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2559         if (err)
2560                 return err;
2561
2562 #if CONFIG_IS_ENABLED(MMC_TINY)
2563         mmc_set_clock(mmc, mmc->legacy_speed, false);
2564         mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2565         mmc_set_bus_width(mmc, 1);
2566 #else
2567         if (IS_SD(mmc)) {
2568                 err = sd_get_capabilities(mmc);
2569                 if (err)
2570                         return err;
2571                 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2572         } else {
2573                 err = mmc_get_capabilities(mmc);
2574                 if (err)
2575                         return err;
2576                 err = mmc_select_mode_and_width(mmc, mmc->card_caps);
2577         }
2578 #endif
2579         if (err)
2580                 return err;
2581
2582         mmc->best_mode = mmc->selected_mode;
2583
2584         /* Fix the block length for DDR mode */
2585         if (mmc->ddr_mode) {
2586                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2587 #if CONFIG_IS_ENABLED(MMC_WRITE)
2588                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2589 #endif
2590         }
2591
2592         /* fill in device description */
2593         bdesc = mmc_get_blk_desc(mmc);
2594         bdesc->lun = 0;
2595         bdesc->hwpart = 0;
2596         bdesc->type = 0;
2597         bdesc->blksz = mmc->read_bl_len;
2598         bdesc->log2blksz = LOG2(bdesc->blksz);
2599         bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2600 #if !defined(CONFIG_SPL_BUILD) || \
2601                 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2602                 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
2603         sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2604                 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2605                 (mmc->cid[3] >> 16) & 0xffff);
2606         sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2607                 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2608                 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2609                 (mmc->cid[2] >> 24) & 0xff);
2610         sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2611                 (mmc->cid[2] >> 16) & 0xf);
2612 #else
2613         bdesc->vendor[0] = 0;
2614         bdesc->product[0] = 0;
2615         bdesc->revision[0] = 0;
2616 #endif
2617
2618 #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2619         part_init(bdesc);
2620 #endif
2621
2622         return 0;
2623 }
2624
2625 static int mmc_send_if_cond(struct mmc *mmc)
2626 {
2627         struct mmc_cmd cmd;
2628         int err;
2629
2630         cmd.cmdidx = SD_CMD_SEND_IF_COND;
2631         /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2632         cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2633         cmd.resp_type = MMC_RSP_R7;
2634
2635         err = mmc_send_cmd(mmc, &cmd, NULL);
2636
2637         if (err)
2638                 return err;
2639
2640         if ((cmd.response[0] & 0xff) != 0xaa)
2641                 return -EOPNOTSUPP;
2642         else
2643                 mmc->version = SD_VERSION_2;
2644
2645         return 0;
2646 }
2647
2648 #if !CONFIG_IS_ENABLED(DM_MMC)
2649 /* board-specific MMC power initializations. */
2650 __weak void board_mmc_power_init(void)
2651 {
2652 }
2653 #endif
2654
2655 static int mmc_power_init(struct mmc *mmc)
2656 {
2657 #if CONFIG_IS_ENABLED(DM_MMC)
2658 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2659         int ret;
2660
2661         ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2662                                           &mmc->vmmc_supply);
2663         if (ret)
2664                 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2665
2666         ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2667                                           &mmc->vqmmc_supply);
2668         if (ret)
2669                 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2670 #endif
2671 #else /* !CONFIG_DM_MMC */
2672         /*
2673          * Driver model should use a regulator, as above, rather than calling
2674          * out to board code.
2675          */
2676         board_mmc_power_init();
2677 #endif
2678         return 0;
2679 }
2680
2681 /*
2682  * put the host in the initial state:
2683  * - turn on Vdd (card power supply)
2684  * - configure the bus width and clock to minimal values
2685  */
2686 static void mmc_set_initial_state(struct mmc *mmc)
2687 {
2688         int err;
2689
2690         /* First try to set 3.3V. If it fails set to 1.8V */
2691         err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2692         if (err != 0)
2693                 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2694         if (err != 0)
2695                 pr_warn("mmc: failed to set signal voltage\n");
2696
2697         mmc_select_mode(mmc, MMC_LEGACY);
2698         mmc_set_bus_width(mmc, 1);
2699         mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2700 }
2701
2702 static int mmc_power_on(struct mmc *mmc)
2703 {
2704 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2705         if (mmc->vmmc_supply) {
2706                 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2707
2708                 if (ret) {
2709                         puts("Error enabling VMMC supply\n");
2710                         return ret;
2711                 }
2712         }
2713 #endif
2714         return 0;
2715 }
2716
2717 static int mmc_power_off(struct mmc *mmc)
2718 {
2719         mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
2720 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2721         if (mmc->vmmc_supply) {
2722                 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2723
2724                 if (ret) {
2725                         pr_debug("Error disabling VMMC supply\n");
2726                         return ret;
2727                 }
2728         }
2729 #endif
2730         return 0;
2731 }
2732
2733 static int mmc_power_cycle(struct mmc *mmc)
2734 {
2735         int ret;
2736
2737         ret = mmc_power_off(mmc);
2738         if (ret)
2739                 return ret;
2740
2741         ret = mmc_host_power_cycle(mmc);
2742         if (ret)
2743                 return ret;
2744
2745         /*
2746          * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2747          * to be on the safer side.
2748          */
2749         udelay(2000);
2750         return mmc_power_on(mmc);
2751 }
2752
2753 int mmc_get_op_cond(struct mmc *mmc)
2754 {
2755         bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2756         int err;
2757
2758         if (mmc->has_init)
2759                 return 0;
2760
2761 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2762         mmc_adapter_card_type_ident();
2763 #endif
2764         err = mmc_power_init(mmc);
2765         if (err)
2766                 return err;
2767
2768 #ifdef CONFIG_MMC_QUIRKS
2769         mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2770                       MMC_QUIRK_RETRY_SEND_CID |
2771                       MMC_QUIRK_RETRY_APP_CMD;
2772 #endif
2773
2774         err = mmc_power_cycle(mmc);
2775         if (err) {
2776                 /*
2777                  * if power cycling is not supported, we should not try
2778                  * to use the UHS modes, because we wouldn't be able to
2779                  * recover from an error during the UHS initialization.
2780                  */
2781                 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2782                 uhs_en = false;
2783                 mmc->host_caps &= ~UHS_CAPS;
2784                 err = mmc_power_on(mmc);
2785         }
2786         if (err)
2787                 return err;
2788
2789 #if CONFIG_IS_ENABLED(DM_MMC)
2790         /* The device has already been probed ready for use */
2791 #else
2792         /* made sure it's not NULL earlier */
2793         err = mmc->cfg->ops->init(mmc);
2794         if (err)
2795                 return err;
2796 #endif
2797         mmc->ddr_mode = 0;
2798
2799 retry:
2800         mmc_set_initial_state(mmc);
2801
2802         /* Reset the Card */
2803         err = mmc_go_idle(mmc);
2804
2805         if (err)
2806                 return err;
2807
2808         /* The internal partition reset to user partition(0) at every CMD0*/
2809         mmc_get_blk_desc(mmc)->hwpart = 0;
2810
2811         /* Test for SD version 2 */
2812         err = mmc_send_if_cond(mmc);
2813
2814         /* Now try to get the SD card's operating condition */
2815         err = sd_send_op_cond(mmc, uhs_en);
2816         if (err && uhs_en) {
2817                 uhs_en = false;
2818                 mmc_power_cycle(mmc);
2819                 goto retry;
2820         }
2821
2822         /* If the command timed out, we check for an MMC card */
2823         if (err == -ETIMEDOUT) {
2824                 err = mmc_send_op_cond(mmc);
2825
2826                 if (err) {
2827 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2828                         pr_err("Card did not respond to voltage select!\n");
2829 #endif
2830                         return -EOPNOTSUPP;
2831                 }
2832         }
2833
2834         return err;
2835 }
2836
2837 int mmc_start_init(struct mmc *mmc)
2838 {
2839         bool no_card;
2840         int err = 0;
2841
2842         /*
2843          * all hosts are capable of 1 bit bus-width and able to use the legacy
2844          * timings.
2845          */
2846         mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2847                          MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2848
2849 #if !defined(CONFIG_MMC_BROKEN_CD)
2850         no_card = mmc_getcd(mmc) == 0;
2851 #else
2852         no_card = 0;
2853 #endif
2854 #if !CONFIG_IS_ENABLED(DM_MMC)
2855         /* we pretend there's no card when init is NULL */
2856         no_card = no_card || (mmc->cfg->ops->init == NULL);
2857 #endif
2858         if (no_card) {
2859                 mmc->has_init = 0;
2860 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2861                 pr_err("MMC: no card present\n");
2862 #endif
2863                 return -ENOMEDIUM;
2864         }
2865
2866         err = mmc_get_op_cond(mmc);
2867
2868         if (!err)
2869                 mmc->init_in_progress = 1;
2870
2871         return err;
2872 }
2873
2874 static int mmc_complete_init(struct mmc *mmc)
2875 {
2876         int err = 0;
2877
2878         mmc->init_in_progress = 0;
2879         if (mmc->op_cond_pending)
2880                 err = mmc_complete_op_cond(mmc);
2881
2882         if (!err)
2883                 err = mmc_startup(mmc);
2884         if (err)
2885                 mmc->has_init = 0;
2886         else
2887                 mmc->has_init = 1;
2888         return err;
2889 }
2890
2891 int mmc_init(struct mmc *mmc)
2892 {
2893         int err = 0;
2894         __maybe_unused ulong start;
2895 #if CONFIG_IS_ENABLED(DM_MMC)
2896         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2897
2898         upriv->mmc = mmc;
2899 #endif
2900         if (mmc->has_init)
2901                 return 0;
2902
2903         start = get_timer(0);
2904
2905         if (!mmc->init_in_progress)
2906                 err = mmc_start_init(mmc);
2907
2908         if (!err)
2909                 err = mmc_complete_init(mmc);
2910         if (err)
2911                 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2912
2913         return err;
2914 }
2915
2916 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2917     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2918     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2919 int mmc_deinit(struct mmc *mmc)
2920 {
2921         u32 caps_filtered;
2922
2923         if (!mmc->has_init)
2924                 return 0;
2925
2926         if (IS_SD(mmc)) {
2927                 caps_filtered = mmc->card_caps &
2928                         ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2929                           MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2930                           MMC_CAP(UHS_SDR104));
2931
2932                 return sd_select_mode_and_width(mmc, caps_filtered);
2933         } else {
2934                 caps_filtered = mmc->card_caps &
2935                         ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2936
2937                 return mmc_select_mode_and_width(mmc, caps_filtered);
2938         }
2939 }
2940 #endif
2941
2942 int mmc_set_dsr(struct mmc *mmc, u16 val)
2943 {
2944         mmc->dsr = val;
2945         return 0;
2946 }
2947
2948 /* CPU-specific MMC initializations */
2949 __weak int cpu_mmc_init(bd_t *bis)
2950 {
2951         return -1;
2952 }
2953
2954 /* board-specific MMC initializations. */
2955 __weak int board_mmc_init(bd_t *bis)
2956 {
2957         return -1;
2958 }
2959
2960 void mmc_set_preinit(struct mmc *mmc, int preinit)
2961 {
2962         mmc->preinit = preinit;
2963 }
2964
2965 #if CONFIG_IS_ENABLED(DM_MMC)
2966 static int mmc_probe(bd_t *bis)
2967 {
2968         int ret, i;
2969         struct uclass *uc;
2970         struct udevice *dev;
2971
2972         ret = uclass_get(UCLASS_MMC, &uc);
2973         if (ret)
2974                 return ret;
2975
2976         /*
2977          * Try to add them in sequence order. Really with driver model we
2978          * should allow holes, but the current MMC list does not allow that.
2979          * So if we request 0, 1, 3 we will get 0, 1, 2.
2980          */
2981         for (i = 0; ; i++) {
2982                 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2983                 if (ret == -ENODEV)
2984                         break;
2985         }
2986         uclass_foreach_dev(dev, uc) {
2987                 ret = device_probe(dev);
2988                 if (ret)
2989                         pr_err("%s - probe failed: %d\n", dev->name, ret);
2990         }
2991
2992         return 0;
2993 }
2994 #else
2995 static int mmc_probe(bd_t *bis)
2996 {
2997         if (board_mmc_init(bis) < 0)
2998                 cpu_mmc_init(bis);
2999
3000         return 0;
3001 }
3002 #endif
3003
3004 int mmc_initialize(bd_t *bis)
3005 {
3006         static int initialized = 0;
3007         int ret;
3008         if (initialized)        /* Avoid initializing mmc multiple times */
3009                 return 0;
3010         initialized = 1;
3011
3012 #if !CONFIG_IS_ENABLED(BLK)
3013 #if !CONFIG_IS_ENABLED(MMC_TINY)
3014         mmc_list_init();
3015 #endif
3016 #endif
3017         ret = mmc_probe(bis);
3018         if (ret)
3019                 return ret;
3020
3021 #ifndef CONFIG_SPL_BUILD
3022         print_mmc_devices(',');
3023 #endif
3024
3025         mmc_do_preinit();
3026         return 0;
3027 }
3028
3029 #if CONFIG_IS_ENABLED(DM_MMC)
3030 int mmc_init_device(int num)
3031 {
3032         struct udevice *dev;
3033         struct mmc *m;
3034         int ret;
3035
3036         ret = uclass_get_device(UCLASS_MMC, num, &dev);
3037         if (ret)
3038                 return ret;
3039
3040         m = mmc_get_mmc_dev(dev);
3041         if (!m)
3042                 return 0;
3043 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
3044         mmc_set_preinit(m, 1);
3045 #endif
3046         if (m->preinit)
3047                 mmc_start_init(m);
3048
3049         return 0;
3050 }
3051 #endif
3052
3053 #ifdef CONFIG_CMD_BKOPS_ENABLE
3054 int mmc_set_bkops_enable(struct mmc *mmc)
3055 {
3056         int err;
3057         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3058
3059         err = mmc_send_ext_csd(mmc, ext_csd);
3060         if (err) {
3061                 puts("Could not get ext_csd register values\n");
3062                 return err;
3063         }
3064
3065         if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3066                 puts("Background operations not supported on device\n");
3067                 return -EMEDIUMTYPE;
3068         }
3069
3070         if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
3071                 puts("Background operations already enabled\n");
3072                 return 0;
3073         }
3074
3075         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
3076         if (err) {
3077                 puts("Failed to enable manual background operations\n");
3078                 return err;
3079         }
3080
3081         puts("Enabled manual background operations\n");
3082
3083         return 0;
3084 }
3085 #endif