2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
33 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
34 static int mmc_power_cycle(struct mmc *mmc);
35 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
37 #if CONFIG_IS_ENABLED(MMC_TINY)
38 static struct mmc mmc_static;
39 struct mmc *find_mmc_device(int dev_num)
44 void mmc_do_preinit(void)
46 struct mmc *m = &mmc_static;
47 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
48 mmc_set_preinit(m, 1);
54 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
56 return &mmc->block_dev;
60 #if !CONFIG_IS_ENABLED(DM_MMC)
62 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
67 __weak int board_mmc_getwp(struct mmc *mmc)
72 int mmc_getwp(struct mmc *mmc)
76 wp = board_mmc_getwp(mmc);
79 if (mmc->cfg->ops->getwp)
80 wp = mmc->cfg->ops->getwp(mmc);
88 __weak int board_mmc_getcd(struct mmc *mmc)
94 #ifdef CONFIG_MMC_TRACE
95 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
97 printf("CMD_SEND:%d\n", cmd->cmdidx);
98 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
101 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
107 printf("\t\tRET\t\t\t %d\n", ret);
109 switch (cmd->resp_type) {
111 printf("\t\tMMC_RSP_NONE\n");
114 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
118 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
122 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
124 printf("\t\t \t\t 0x%08X \n",
126 printf("\t\t \t\t 0x%08X \n",
128 printf("\t\t \t\t 0x%08X \n",
131 printf("\t\t\t\t\tDUMPING DATA\n");
132 for (i = 0; i < 4; i++) {
134 printf("\t\t\t\t\t%03d - ", i*4);
135 ptr = (u8 *)&cmd->response[i];
137 for (j = 0; j < 4; j++)
138 printf("%02X ", *ptr--);
143 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
147 printf("\t\tERROR MMC rsp not supported\n");
153 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
157 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
158 printf("CURR STATE:%d\n", status);
162 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
163 const char *mmc_mode_name(enum bus_mode mode)
165 static const char *const names[] = {
166 [MMC_LEGACY] = "MMC legacy",
167 [SD_LEGACY] = "SD Legacy",
168 [MMC_HS] = "MMC High Speed (26MHz)",
169 [SD_HS] = "SD High Speed (50MHz)",
170 [UHS_SDR12] = "UHS SDR12 (25MHz)",
171 [UHS_SDR25] = "UHS SDR25 (50MHz)",
172 [UHS_SDR50] = "UHS SDR50 (100MHz)",
173 [UHS_SDR104] = "UHS SDR104 (208MHz)",
174 [UHS_DDR50] = "UHS DDR50 (50MHz)",
175 [MMC_HS_52] = "MMC High Speed (52MHz)",
176 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
177 [MMC_HS_200] = "HS200 (200MHz)",
180 if (mode >= MMC_MODES_END)
181 return "Unknown mode";
187 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
189 static const int freqs[] = {
190 [SD_LEGACY] = 25000000,
193 [UHS_SDR12] = 25000000,
194 [UHS_SDR25] = 50000000,
195 [UHS_SDR50] = 100000000,
196 [UHS_SDR104] = 208000000,
197 [UHS_DDR50] = 50000000,
198 [MMC_HS_52] = 52000000,
199 [MMC_DDR_52] = 52000000,
200 [MMC_HS_200] = 200000000,
203 if (mode == MMC_LEGACY)
204 return mmc->legacy_speed;
205 else if (mode >= MMC_MODES_END)
211 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
213 mmc->selected_mode = mode;
214 mmc->tran_speed = mmc_mode2freq(mmc, mode);
215 mmc->ddr_mode = mmc_is_mode_ddr(mode);
216 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
217 mmc->tran_speed / 1000000);
221 #if !CONFIG_IS_ENABLED(DM_MMC)
222 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
226 mmmc_trace_before_send(mmc, cmd);
227 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
228 mmmc_trace_after_send(mmc, cmd, ret);
234 int mmc_send_status(struct mmc *mmc, int timeout)
237 int err, retries = 5;
239 cmd.cmdidx = MMC_CMD_SEND_STATUS;
240 cmd.resp_type = MMC_RSP_R1;
241 if (!mmc_host_is_spi(mmc))
242 cmd.cmdarg = mmc->rca << 16;
245 err = mmc_send_cmd(mmc, &cmd, NULL);
247 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
248 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
252 if (cmd.response[0] & MMC_STATUS_MASK) {
253 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
254 printf("Status Error: 0x%08X\n",
259 } else if (--retries < 0)
268 mmc_trace_state(mmc, &cmd);
270 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
271 printf("Timeout waiting card ready\n");
279 int mmc_set_blocklen(struct mmc *mmc, int len)
287 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
288 cmd.resp_type = MMC_RSP_R1;
291 err = mmc_send_cmd(mmc, &cmd, NULL);
293 #ifdef CONFIG_MMC_QUIRKS
294 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
297 * It has been seen that SET_BLOCKLEN may fail on the first
298 * attempt, let's try a few more time
301 err = mmc_send_cmd(mmc, &cmd, NULL);
311 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
315 struct mmc_data data;
318 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
320 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
322 if (mmc->high_capacity)
325 cmd.cmdarg = start * mmc->read_bl_len;
327 cmd.resp_type = MMC_RSP_R1;
330 data.blocks = blkcnt;
331 data.blocksize = mmc->read_bl_len;
332 data.flags = MMC_DATA_READ;
334 if (mmc_send_cmd(mmc, &cmd, &data))
338 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
340 cmd.resp_type = MMC_RSP_R1b;
341 if (mmc_send_cmd(mmc, &cmd, NULL)) {
342 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
343 printf("mmc fail to send stop cmd\n");
352 #if CONFIG_IS_ENABLED(BLK)
353 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
355 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
359 #if CONFIG_IS_ENABLED(BLK)
360 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
362 int dev_num = block_dev->devnum;
364 lbaint_t cur, blocks_todo = blkcnt;
369 struct mmc *mmc = find_mmc_device(dev_num);
373 if (CONFIG_IS_ENABLED(MMC_TINY))
374 err = mmc_switch_part(mmc, block_dev->hwpart);
376 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
381 if ((start + blkcnt) > block_dev->lba) {
382 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
383 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
384 start + blkcnt, block_dev->lba);
389 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
390 debug("%s: Failed to set blocklen\n", __func__);
395 cur = (blocks_todo > mmc->cfg->b_max) ?
396 mmc->cfg->b_max : blocks_todo;
397 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
398 debug("%s: Failed to read blocks\n", __func__);
403 dst += cur * mmc->read_bl_len;
404 } while (blocks_todo > 0);
409 static int mmc_go_idle(struct mmc *mmc)
416 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
418 cmd.resp_type = MMC_RSP_NONE;
420 err = mmc_send_cmd(mmc, &cmd, NULL);
430 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
436 * Send CMD11 only if the request is to switch the card to
439 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
440 return mmc_set_signal_voltage(mmc, signal_voltage);
442 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
444 cmd.resp_type = MMC_RSP_R1;
446 err = mmc_send_cmd(mmc, &cmd, NULL);
450 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
454 * The card should drive cmd and dat[0:3] low immediately
455 * after the response of cmd11, but wait 100 us to be sure
457 err = mmc_wait_dat0(mmc, 0, 100);
464 * During a signal voltage level switch, the clock must be gated
465 * for 5 ms according to the SD spec
467 mmc_set_clock(mmc, mmc->clock, true);
469 err = mmc_set_signal_voltage(mmc, signal_voltage);
473 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
475 mmc_set_clock(mmc, mmc->clock, false);
478 * Failure to switch is indicated by the card holding
479 * dat[0:3] low. Wait for at least 1 ms according to spec
481 err = mmc_wait_dat0(mmc, 1, 1000);
490 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
497 cmd.cmdidx = MMC_CMD_APP_CMD;
498 cmd.resp_type = MMC_RSP_R1;
501 err = mmc_send_cmd(mmc, &cmd, NULL);
506 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
507 cmd.resp_type = MMC_RSP_R3;
510 * Most cards do not answer if some reserved bits
511 * in the ocr are set. However, Some controller
512 * can set bit 7 (reserved for low voltages), but
513 * how to manage low voltages SD card is not yet
516 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
517 (mmc->cfg->voltages & 0xff8000);
519 if (mmc->version == SD_VERSION_2)
520 cmd.cmdarg |= OCR_HCS;
523 cmd.cmdarg |= OCR_S18R;
525 err = mmc_send_cmd(mmc, &cmd, NULL);
530 if (cmd.response[0] & OCR_BUSY)
539 if (mmc->version != SD_VERSION_2)
540 mmc->version = SD_VERSION_1_0;
542 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
543 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
544 cmd.resp_type = MMC_RSP_R3;
547 err = mmc_send_cmd(mmc, &cmd, NULL);
553 mmc->ocr = cmd.response[0];
555 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
557 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
562 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
568 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
573 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
574 cmd.resp_type = MMC_RSP_R3;
576 if (use_arg && !mmc_host_is_spi(mmc))
577 cmd.cmdarg = OCR_HCS |
578 (mmc->cfg->voltages &
579 (mmc->ocr & OCR_VOLTAGE_MASK)) |
580 (mmc->ocr & OCR_ACCESS_MODE);
582 err = mmc_send_cmd(mmc, &cmd, NULL);
585 mmc->ocr = cmd.response[0];
589 static int mmc_send_op_cond(struct mmc *mmc)
593 /* Some cards seem to need this */
596 /* Asking to the card its capabilities */
597 for (i = 0; i < 2; i++) {
598 err = mmc_send_op_cond_iter(mmc, i != 0);
602 /* exit if not busy (flag seems to be inverted) */
603 if (mmc->ocr & OCR_BUSY)
606 mmc->op_cond_pending = 1;
610 static int mmc_complete_op_cond(struct mmc *mmc)
617 mmc->op_cond_pending = 0;
618 if (!(mmc->ocr & OCR_BUSY)) {
619 /* Some cards seem to need this */
622 start = get_timer(0);
624 err = mmc_send_op_cond_iter(mmc, 1);
627 if (mmc->ocr & OCR_BUSY)
629 if (get_timer(start) > timeout)
635 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
636 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
637 cmd.resp_type = MMC_RSP_R3;
640 err = mmc_send_cmd(mmc, &cmd, NULL);
645 mmc->ocr = cmd.response[0];
648 mmc->version = MMC_VERSION_UNKNOWN;
650 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
657 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
660 struct mmc_data data;
663 /* Get the Card Status Register */
664 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
665 cmd.resp_type = MMC_RSP_R1;
668 data.dest = (char *)ext_csd;
670 data.blocksize = MMC_MAX_BLOCK_LEN;
671 data.flags = MMC_DATA_READ;
673 err = mmc_send_cmd(mmc, &cmd, &data);
678 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
685 cmd.cmdidx = MMC_CMD_SWITCH;
686 cmd.resp_type = MMC_RSP_R1b;
687 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
691 while (retries > 0) {
692 ret = mmc_send_cmd(mmc, &cmd, NULL);
694 /* Waiting for the ready status */
696 ret = mmc_send_status(mmc, timeout);
707 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
712 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
718 speed_bits = EXT_CSD_TIMING_HS;
721 speed_bits = EXT_CSD_TIMING_HS200;
724 speed_bits = EXT_CSD_TIMING_LEGACY;
729 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
734 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
735 /* Now check to see that it worked */
736 err = mmc_send_ext_csd(mmc, test_csd);
740 /* No high-speed support */
741 if (!test_csd[EXT_CSD_HS_TIMING])
748 static int mmc_get_capabilities(struct mmc *mmc)
750 u8 *ext_csd = mmc->ext_csd;
753 mmc->card_caps = MMC_MODE_1BIT;
755 if (mmc_host_is_spi(mmc))
758 /* Only version 4 supports high-speed */
759 if (mmc->version < MMC_VERSION_4)
763 printf("No ext_csd found!\n"); /* this should enver happen */
767 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
769 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
771 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
772 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
773 mmc->card_caps |= MMC_MODE_HS200;
775 if (cardtype & EXT_CSD_CARD_TYPE_52) {
776 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
777 mmc->card_caps |= MMC_MODE_DDR_52MHz;
778 mmc->card_caps |= MMC_MODE_HS_52MHz;
780 if (cardtype & EXT_CSD_CARD_TYPE_26)
781 mmc->card_caps |= MMC_MODE_HS;
786 static int mmc_set_capacity(struct mmc *mmc, int part_num)
790 mmc->capacity = mmc->capacity_user;
794 mmc->capacity = mmc->capacity_boot;
797 mmc->capacity = mmc->capacity_rpmb;
803 mmc->capacity = mmc->capacity_gp[part_num - 4];
809 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
814 static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
819 if (part_num & PART_ACCESS_MASK)
820 forbidden = MMC_CAP(MMC_HS_200);
822 if (MMC_CAP(mmc->selected_mode) & forbidden) {
823 debug("selected mode (%s) is forbidden for part %d\n",
824 mmc_mode_name(mmc->selected_mode), part_num);
826 } else if (mmc->selected_mode != mmc->best_mode) {
827 debug("selected mode is not optimal\n");
832 return mmc_select_mode_and_width(mmc,
833 mmc->card_caps & ~forbidden);
838 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
842 ret = mmc_boot_part_access_chk(mmc, part_num);
846 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
847 (mmc->part_config & ~PART_ACCESS_MASK)
848 | (part_num & PART_ACCESS_MASK));
851 * Set the capacity if the switch succeeded or was intended
852 * to return to representing the raw device.
854 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
855 ret = mmc_set_capacity(mmc, part_num);
856 mmc_get_blk_desc(mmc)->hwpart = part_num;
862 int mmc_hwpart_config(struct mmc *mmc,
863 const struct mmc_hwpart_conf *conf,
864 enum mmc_hwpart_conf_mode mode)
870 u32 max_enh_size_mult;
871 u32 tot_enh_size_mult = 0;
874 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
876 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
879 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
880 printf("eMMC >= 4.4 required for enhanced user data area\n");
884 if (!(mmc->part_support & PART_SUPPORT)) {
885 printf("Card does not support partitioning\n");
889 if (!mmc->hc_wp_grp_size) {
890 printf("Card does not define HC WP group size\n");
894 /* check partition alignment and total enhanced size */
895 if (conf->user.enh_size) {
896 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
897 conf->user.enh_start % mmc->hc_wp_grp_size) {
898 printf("User data enhanced area not HC WP group "
902 part_attrs |= EXT_CSD_ENH_USR;
903 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
904 if (mmc->high_capacity) {
905 enh_start_addr = conf->user.enh_start;
907 enh_start_addr = (conf->user.enh_start << 9);
913 tot_enh_size_mult += enh_size_mult;
915 for (pidx = 0; pidx < 4; pidx++) {
916 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
917 printf("GP%i partition not HC WP group size "
918 "aligned\n", pidx+1);
921 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
922 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
923 part_attrs |= EXT_CSD_ENH_GP(pidx);
924 tot_enh_size_mult += gp_size_mult[pidx];
928 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
929 printf("Card does not support enhanced attribute\n");
933 err = mmc_send_ext_csd(mmc, ext_csd);
938 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
939 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
940 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
941 if (tot_enh_size_mult > max_enh_size_mult) {
942 printf("Total enhanced size exceeds maximum (%u > %u)\n",
943 tot_enh_size_mult, max_enh_size_mult);
947 /* The default value of EXT_CSD_WR_REL_SET is device
948 * dependent, the values can only be changed if the
949 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
950 * changed only once and before partitioning is completed. */
951 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
952 if (conf->user.wr_rel_change) {
953 if (conf->user.wr_rel_set)
954 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
956 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
958 for (pidx = 0; pidx < 4; pidx++) {
959 if (conf->gp_part[pidx].wr_rel_change) {
960 if (conf->gp_part[pidx].wr_rel_set)
961 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
963 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
967 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
968 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
969 puts("Card does not support host controlled partition write "
970 "reliability settings\n");
974 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
975 EXT_CSD_PARTITION_SETTING_COMPLETED) {
976 printf("Card already partitioned\n");
980 if (mode == MMC_HWPART_CONF_CHECK)
983 /* Partitioning requires high-capacity size definitions */
984 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
985 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
986 EXT_CSD_ERASE_GROUP_DEF, 1);
991 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
993 /* update erase group size to be high-capacity */
994 mmc->erase_grp_size =
995 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
999 /* all OK, write the configuration */
1000 for (i = 0; i < 4; i++) {
1001 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1002 EXT_CSD_ENH_START_ADDR+i,
1003 (enh_start_addr >> (i*8)) & 0xFF);
1007 for (i = 0; i < 3; i++) {
1008 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1009 EXT_CSD_ENH_SIZE_MULT+i,
1010 (enh_size_mult >> (i*8)) & 0xFF);
1014 for (pidx = 0; pidx < 4; pidx++) {
1015 for (i = 0; i < 3; i++) {
1016 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1017 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1018 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1023 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1024 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1028 if (mode == MMC_HWPART_CONF_SET)
1031 /* The WR_REL_SET is a write-once register but shall be
1032 * written before setting PART_SETTING_COMPLETED. As it is
1033 * write-once we can only write it when completing the
1035 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1036 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1037 EXT_CSD_WR_REL_SET, wr_rel_set);
1042 /* Setting PART_SETTING_COMPLETED confirms the partition
1043 * configuration but it only becomes effective after power
1044 * cycle, so we do not adjust the partition related settings
1045 * in the mmc struct. */
1047 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1048 EXT_CSD_PARTITION_SETTING,
1049 EXT_CSD_PARTITION_SETTING_COMPLETED);
1056 #if !CONFIG_IS_ENABLED(DM_MMC)
1057 int mmc_getcd(struct mmc *mmc)
1061 cd = board_mmc_getcd(mmc);
1064 if (mmc->cfg->ops->getcd)
1065 cd = mmc->cfg->ops->getcd(mmc);
1074 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1077 struct mmc_data data;
1079 /* Switch the frequency */
1080 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1081 cmd.resp_type = MMC_RSP_R1;
1082 cmd.cmdarg = (mode << 31) | 0xffffff;
1083 cmd.cmdarg &= ~(0xf << (group * 4));
1084 cmd.cmdarg |= value << (group * 4);
1086 data.dest = (char *)resp;
1087 data.blocksize = 64;
1089 data.flags = MMC_DATA_READ;
1091 return mmc_send_cmd(mmc, &cmd, &data);
1095 static int sd_get_capabilities(struct mmc *mmc)
1099 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1100 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1101 struct mmc_data data;
1105 mmc->card_caps = MMC_MODE_1BIT;
1107 if (mmc_host_is_spi(mmc))
1110 /* Read the SCR to find out if this card supports higher speeds */
1111 cmd.cmdidx = MMC_CMD_APP_CMD;
1112 cmd.resp_type = MMC_RSP_R1;
1113 cmd.cmdarg = mmc->rca << 16;
1115 err = mmc_send_cmd(mmc, &cmd, NULL);
1120 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1121 cmd.resp_type = MMC_RSP_R1;
1127 data.dest = (char *)scr;
1130 data.flags = MMC_DATA_READ;
1132 err = mmc_send_cmd(mmc, &cmd, &data);
1141 mmc->scr[0] = __be32_to_cpu(scr[0]);
1142 mmc->scr[1] = __be32_to_cpu(scr[1]);
1144 switch ((mmc->scr[0] >> 24) & 0xf) {
1146 mmc->version = SD_VERSION_1_0;
1149 mmc->version = SD_VERSION_1_10;
1152 mmc->version = SD_VERSION_2;
1153 if ((mmc->scr[0] >> 15) & 0x1)
1154 mmc->version = SD_VERSION_3;
1157 mmc->version = SD_VERSION_1_0;
1161 if (mmc->scr[0] & SD_DATA_4BIT)
1162 mmc->card_caps |= MMC_MODE_4BIT;
1164 /* Version 1.0 doesn't support switching */
1165 if (mmc->version == SD_VERSION_1_0)
1170 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1171 (u8 *)switch_status);
1176 /* The high-speed function is busy. Try again */
1177 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1181 /* If high-speed isn't supported, we return */
1182 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1183 mmc->card_caps |= MMC_CAP(SD_HS);
1185 /* Version before 3.0 don't support UHS modes */
1186 if (mmc->version < SD_VERSION_3)
1189 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1190 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1191 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1192 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1193 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1194 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1195 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1196 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1197 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1198 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1199 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1204 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1208 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1214 speed = UHS_SDR12_BUS_SPEED;
1218 speed = UHS_SDR25_BUS_SPEED;
1221 speed = UHS_SDR50_BUS_SPEED;
1224 speed = UHS_DDR50_BUS_SPEED;
1227 speed = UHS_SDR104_BUS_SPEED;
1233 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1237 if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
1243 int sd_select_bus_width(struct mmc *mmc, int w)
1248 if ((w != 4) && (w != 1))
1251 cmd.cmdidx = MMC_CMD_APP_CMD;
1252 cmd.resp_type = MMC_RSP_R1;
1253 cmd.cmdarg = mmc->rca << 16;
1255 err = mmc_send_cmd(mmc, &cmd, NULL);
1259 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1260 cmd.resp_type = MMC_RSP_R1;
1265 err = mmc_send_cmd(mmc, &cmd, NULL);
1272 static int sd_read_ssr(struct mmc *mmc)
1276 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1277 struct mmc_data data;
1279 unsigned int au, eo, et, es;
1281 cmd.cmdidx = MMC_CMD_APP_CMD;
1282 cmd.resp_type = MMC_RSP_R1;
1283 cmd.cmdarg = mmc->rca << 16;
1285 err = mmc_send_cmd(mmc, &cmd, NULL);
1289 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1290 cmd.resp_type = MMC_RSP_R1;
1294 data.dest = (char *)ssr;
1295 data.blocksize = 64;
1297 data.flags = MMC_DATA_READ;
1299 err = mmc_send_cmd(mmc, &cmd, &data);
1307 for (i = 0; i < 16; i++)
1308 ssr[i] = be32_to_cpu(ssr[i]);
1310 au = (ssr[2] >> 12) & 0xF;
1311 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1312 mmc->ssr.au = sd_au_size[au];
1313 es = (ssr[3] >> 24) & 0xFF;
1314 es |= (ssr[2] & 0xFF) << 8;
1315 et = (ssr[3] >> 18) & 0x3F;
1317 eo = (ssr[3] >> 16) & 0x3;
1318 mmc->ssr.erase_timeout = (et * 1000) / es;
1319 mmc->ssr.erase_offset = eo * 1000;
1322 debug("Invalid Allocation Unit Size.\n");
1328 /* frequency bases */
1329 /* divided by 10 to be nice to platforms without floating point */
1330 static const int fbase[] = {
1337 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1338 * to platforms without floating point.
1340 static const u8 multipliers[] = {
1359 static inline int bus_width(uint cap)
1361 if (cap == MMC_MODE_8BIT)
1363 if (cap == MMC_MODE_4BIT)
1365 if (cap == MMC_MODE_1BIT)
1367 printf("invalid bus witdh capability 0x%x\n", cap);
1371 #if !CONFIG_IS_ENABLED(DM_MMC)
1372 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1377 static void mmc_send_init_stream(struct mmc *mmc)
1381 static int mmc_set_ios(struct mmc *mmc)
1385 if (mmc->cfg->ops->set_ios)
1386 ret = mmc->cfg->ops->set_ios(mmc);
1392 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1394 if (clock > mmc->cfg->f_max)
1395 clock = mmc->cfg->f_max;
1397 if (clock < mmc->cfg->f_min)
1398 clock = mmc->cfg->f_min;
1401 mmc->clk_disable = disable;
1403 return mmc_set_ios(mmc);
1406 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1408 mmc->bus_width = width;
1410 return mmc_set_ios(mmc);
1413 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1415 * helper function to display the capabilities in a human
1416 * friendly manner. The capabilities include bus width and
1419 void mmc_dump_capabilities(const char *text, uint caps)
1423 printf("%s: widths [", text);
1424 if (caps & MMC_MODE_8BIT)
1426 if (caps & MMC_MODE_4BIT)
1428 if (caps & MMC_MODE_1BIT)
1430 printf("\b\b] modes [");
1431 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1432 if (MMC_CAP(mode) & caps)
1433 printf("%s, ", mmc_mode_name(mode));
1438 struct mode_width_tuning {
1444 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1446 mmc->signal_voltage = signal_voltage;
1447 return mmc_set_ios(mmc);
1450 static const struct mode_width_tuning sd_modes_by_pref[] = {
1453 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1454 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1458 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1462 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1466 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1470 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1474 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1478 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1482 #define for_each_sd_mode_by_pref(caps, mwt) \
1483 for (mwt = sd_modes_by_pref;\
1484 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1486 if (caps & MMC_CAP(mwt->mode))
1488 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1491 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1492 const struct mode_width_tuning *mwt;
1493 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1497 /* Restrict card's capabilities by what the host can do */
1498 caps = card_caps & (mmc->host_caps | MMC_MODE_1BIT);
1503 for_each_sd_mode_by_pref(caps, mwt) {
1506 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1507 if (*w & caps & mwt->widths) {
1508 debug("trying mode %s width %d (at %d MHz)\n",
1509 mmc_mode_name(mwt->mode),
1511 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1513 /* configure the bus width (card + host) */
1514 err = sd_select_bus_width(mmc, bus_width(*w));
1517 mmc_set_bus_width(mmc, bus_width(*w));
1519 /* configure the bus mode (card) */
1520 err = sd_set_card_speed(mmc, mwt->mode);
1524 /* configure the bus mode (host) */
1525 mmc_select_mode(mmc, mwt->mode);
1526 mmc_set_clock(mmc, mmc->tran_speed, false);
1528 /* execute tuning if needed */
1529 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1530 err = mmc_execute_tuning(mmc,
1533 debug("tuning failed\n");
1538 err = sd_read_ssr(mmc);
1542 printf("bad ssr\n");
1545 /* revert to a safer bus speed */
1546 mmc_select_mode(mmc, SD_LEGACY);
1547 mmc_set_clock(mmc, mmc->tran_speed, false);
1552 printf("unable to select a mode\n");
1557 * read the compare the part of ext csd that is constant.
1558 * This can be used to check that the transfer is working
1561 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1564 const u8 *ext_csd = mmc->ext_csd;
1565 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1567 err = mmc_send_ext_csd(mmc, test_csd);
1571 /* Only compare read only fields */
1572 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1573 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1574 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1575 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1576 ext_csd[EXT_CSD_REV]
1577 == test_csd[EXT_CSD_REV] &&
1578 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1579 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1580 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1581 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1587 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1590 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1591 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1595 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1599 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1603 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1607 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1611 #define for_each_mmc_mode_by_pref(caps, mwt) \
1612 for (mwt = mmc_modes_by_pref;\
1613 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1615 if (caps & MMC_CAP(mwt->mode))
1617 static const struct ext_csd_bus_width {
1621 } ext_csd_bus_width[] = {
1622 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1623 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1624 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1625 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1626 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1629 #define for_each_supported_width(caps, ddr, ecbv) \
1630 for (ecbv = ext_csd_bus_width;\
1631 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1633 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1635 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
1638 const struct mode_width_tuning *mwt;
1639 const struct ext_csd_bus_width *ecbw;
1641 /* Restrict card's capabilities by what the host can do */
1642 card_caps &= (mmc->host_caps | MMC_MODE_1BIT);
1644 /* Only version 4 of MMC supports wider bus widths */
1645 if (mmc->version < MMC_VERSION_4)
1648 if (!mmc->ext_csd) {
1649 debug("No ext_csd found!\n"); /* this should enver happen */
1653 mmc_set_clock(mmc, mmc->legacy_speed, false);
1655 for_each_mmc_mode_by_pref(card_caps, mwt) {
1656 for_each_supported_width(card_caps & mwt->widths,
1657 mmc_is_mode_ddr(mwt->mode), ecbw) {
1658 debug("trying mode %s width %d (at %d MHz)\n",
1659 mmc_mode_name(mwt->mode),
1660 bus_width(ecbw->cap),
1661 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1662 /* configure the bus width (card + host) */
1663 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1665 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1668 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1670 /* configure the bus speed (card) */
1671 err = mmc_set_card_speed(mmc, mwt->mode);
1676 * configure the bus width AND the ddr mode (card)
1677 * The host side will be taken care of in the next step
1679 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1680 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1682 ecbw->ext_csd_bits);
1687 /* configure the bus mode (host) */
1688 mmc_select_mode(mmc, mwt->mode);
1689 mmc_set_clock(mmc, mmc->tran_speed, false);
1691 /* execute tuning if needed */
1693 err = mmc_execute_tuning(mmc, mwt->tuning);
1695 debug("tuning failed\n");
1700 /* do a transfer to check the configuration */
1701 err = mmc_read_and_compare_ext_csd(mmc);
1705 /* if an error occured, revert to a safer bus mode */
1706 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1707 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1708 mmc_select_mode(mmc, MMC_LEGACY);
1709 mmc_set_bus_width(mmc, 1);
1713 printf("unable to select a mode\n");
1718 static int mmc_startup_v4(struct mmc *mmc)
1722 bool has_parts = false;
1723 bool part_completed;
1726 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1729 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1733 mmc->ext_csd = ext_csd;
1735 /* check ext_csd version and capacity */
1736 err = mmc_send_ext_csd(mmc, ext_csd);
1739 if (ext_csd[EXT_CSD_REV] >= 2) {
1741 * According to the JEDEC Standard, the value of
1742 * ext_csd's capacity is valid if the value is more
1745 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1746 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1747 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1748 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1749 capacity *= MMC_MAX_BLOCK_LEN;
1750 if ((capacity >> 20) > 2 * 1024)
1751 mmc->capacity_user = capacity;
1754 switch (ext_csd[EXT_CSD_REV]) {
1756 mmc->version = MMC_VERSION_4_1;
1759 mmc->version = MMC_VERSION_4_2;
1762 mmc->version = MMC_VERSION_4_3;
1765 mmc->version = MMC_VERSION_4_41;
1768 mmc->version = MMC_VERSION_4_5;
1771 mmc->version = MMC_VERSION_5_0;
1774 mmc->version = MMC_VERSION_5_1;
1778 /* The partition data may be non-zero but it is only
1779 * effective if PARTITION_SETTING_COMPLETED is set in
1780 * EXT_CSD, so ignore any data if this bit is not set,
1781 * except for enabling the high-capacity group size
1782 * definition (see below).
1784 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1785 EXT_CSD_PARTITION_SETTING_COMPLETED);
1787 /* store the partition info of emmc */
1788 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1789 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1790 ext_csd[EXT_CSD_BOOT_MULT])
1791 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1792 if (part_completed &&
1793 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1794 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1796 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1798 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1800 for (i = 0; i < 4; i++) {
1801 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1802 uint mult = (ext_csd[idx + 2] << 16) +
1803 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1806 if (!part_completed)
1808 mmc->capacity_gp[i] = mult;
1809 mmc->capacity_gp[i] *=
1810 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1811 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1812 mmc->capacity_gp[i] <<= 19;
1815 if (part_completed) {
1816 mmc->enh_user_size =
1817 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1818 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1819 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1820 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1821 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1822 mmc->enh_user_size <<= 19;
1823 mmc->enh_user_start =
1824 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1825 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1826 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1827 ext_csd[EXT_CSD_ENH_START_ADDR];
1828 if (mmc->high_capacity)
1829 mmc->enh_user_start <<= 9;
1833 * Host needs to enable ERASE_GRP_DEF bit if device is
1834 * partitioned. This bit will be lost every time after a reset
1835 * or power off. This will affect erase size.
1839 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1840 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1843 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1844 EXT_CSD_ERASE_GROUP_DEF, 1);
1849 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1852 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1853 /* Read out group size from ext_csd */
1854 mmc->erase_grp_size =
1855 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1857 * if high capacity and partition setting completed
1858 * SEC_COUNT is valid even if it is smaller than 2 GiB
1859 * JEDEC Standard JESD84-B45, 6.2.4
1861 if (mmc->high_capacity && part_completed) {
1862 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1863 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1864 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1865 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1866 capacity *= MMC_MAX_BLOCK_LEN;
1867 mmc->capacity_user = capacity;
1870 /* Calculate the group size from the csd value. */
1871 int erase_gsz, erase_gmul;
1873 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1874 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1875 mmc->erase_grp_size = (erase_gsz + 1)
1879 mmc->hc_wp_grp_size = 1024
1880 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1881 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1883 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1888 static int mmc_startup(struct mmc *mmc)
1894 struct blk_desc *bdesc;
1896 #ifdef CONFIG_MMC_SPI_CRC_ON
1897 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1898 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1899 cmd.resp_type = MMC_RSP_R1;
1901 err = mmc_send_cmd(mmc, &cmd, NULL);
1907 /* Put the Card in Identify Mode */
1908 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1909 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1910 cmd.resp_type = MMC_RSP_R2;
1913 err = mmc_send_cmd(mmc, &cmd, NULL);
1915 #ifdef CONFIG_MMC_QUIRKS
1916 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
1919 * It has been seen that SEND_CID may fail on the first
1920 * attempt, let's try a few more time
1923 err = mmc_send_cmd(mmc, &cmd, NULL);
1926 } while (retries--);
1933 memcpy(mmc->cid, cmd.response, 16);
1936 * For MMC cards, set the Relative Address.
1937 * For SD cards, get the Relatvie Address.
1938 * This also puts the cards into Standby State
1940 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1941 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1942 cmd.cmdarg = mmc->rca << 16;
1943 cmd.resp_type = MMC_RSP_R6;
1945 err = mmc_send_cmd(mmc, &cmd, NULL);
1951 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1954 /* Get the Card-Specific Data */
1955 cmd.cmdidx = MMC_CMD_SEND_CSD;
1956 cmd.resp_type = MMC_RSP_R2;
1957 cmd.cmdarg = mmc->rca << 16;
1959 err = mmc_send_cmd(mmc, &cmd, NULL);
1964 mmc->csd[0] = cmd.response[0];
1965 mmc->csd[1] = cmd.response[1];
1966 mmc->csd[2] = cmd.response[2];
1967 mmc->csd[3] = cmd.response[3];
1969 if (mmc->version == MMC_VERSION_UNKNOWN) {
1970 int version = (cmd.response[0] >> 26) & 0xf;
1974 mmc->version = MMC_VERSION_1_2;
1977 mmc->version = MMC_VERSION_1_4;
1980 mmc->version = MMC_VERSION_2_2;
1983 mmc->version = MMC_VERSION_3;
1986 mmc->version = MMC_VERSION_4;
1989 mmc->version = MMC_VERSION_1_2;
1994 /* divide frequency by 10, since the mults are 10x bigger */
1995 freq = fbase[(cmd.response[0] & 0x7)];
1996 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1998 mmc->legacy_speed = freq * mult;
1999 mmc_select_mode(mmc, MMC_LEGACY);
2001 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2002 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2005 mmc->write_bl_len = mmc->read_bl_len;
2007 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2009 if (mmc->high_capacity) {
2010 csize = (mmc->csd[1] & 0x3f) << 16
2011 | (mmc->csd[2] & 0xffff0000) >> 16;
2014 csize = (mmc->csd[1] & 0x3ff) << 2
2015 | (mmc->csd[2] & 0xc0000000) >> 30;
2016 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2019 mmc->capacity_user = (csize + 1) << (cmult + 2);
2020 mmc->capacity_user *= mmc->read_bl_len;
2021 mmc->capacity_boot = 0;
2022 mmc->capacity_rpmb = 0;
2023 for (i = 0; i < 4; i++)
2024 mmc->capacity_gp[i] = 0;
2026 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2027 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2029 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2030 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2032 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2033 cmd.cmdidx = MMC_CMD_SET_DSR;
2034 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2035 cmd.resp_type = MMC_RSP_NONE;
2036 if (mmc_send_cmd(mmc, &cmd, NULL))
2037 printf("MMC: SET_DSR failed\n");
2040 /* Select the card, and put it into Transfer Mode */
2041 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2042 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2043 cmd.resp_type = MMC_RSP_R1;
2044 cmd.cmdarg = mmc->rca << 16;
2045 err = mmc_send_cmd(mmc, &cmd, NULL);
2052 * For SD, its erase group is always one sector
2054 mmc->erase_grp_size = 1;
2055 mmc->part_config = MMCPART_NOAVAILABLE;
2057 err = mmc_startup_v4(mmc);
2061 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2066 err = sd_get_capabilities(mmc);
2069 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2071 err = mmc_get_capabilities(mmc);
2074 mmc_select_mode_and_width(mmc, mmc->card_caps);
2080 mmc->best_mode = mmc->selected_mode;
2082 /* Fix the block length for DDR mode */
2083 if (mmc->ddr_mode) {
2084 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2085 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2088 /* fill in device description */
2089 bdesc = mmc_get_blk_desc(mmc);
2093 bdesc->blksz = mmc->read_bl_len;
2094 bdesc->log2blksz = LOG2(bdesc->blksz);
2095 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2096 #if !defined(CONFIG_SPL_BUILD) || \
2097 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2098 !defined(CONFIG_USE_TINY_PRINTF))
2099 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2100 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2101 (mmc->cid[3] >> 16) & 0xffff);
2102 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2103 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2104 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2105 (mmc->cid[2] >> 24) & 0xff);
2106 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2107 (mmc->cid[2] >> 16) & 0xf);
2109 bdesc->vendor[0] = 0;
2110 bdesc->product[0] = 0;
2111 bdesc->revision[0] = 0;
2113 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
2120 static int mmc_send_if_cond(struct mmc *mmc)
2125 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2126 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2127 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2128 cmd.resp_type = MMC_RSP_R7;
2130 err = mmc_send_cmd(mmc, &cmd, NULL);
2135 if ((cmd.response[0] & 0xff) != 0xaa)
2138 mmc->version = SD_VERSION_2;
2143 #if !CONFIG_IS_ENABLED(DM_MMC)
2144 /* board-specific MMC power initializations. */
2145 __weak void board_mmc_power_init(void)
2150 static int mmc_power_init(struct mmc *mmc)
2152 #if CONFIG_IS_ENABLED(DM_MMC)
2153 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2156 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2159 debug("%s: No vmmc supply\n", mmc->dev->name);
2161 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2162 &mmc->vqmmc_supply);
2164 debug("%s: No vqmmc supply\n", mmc->dev->name);
2166 #else /* !CONFIG_DM_MMC */
2168 * Driver model should use a regulator, as above, rather than calling
2169 * out to board code.
2171 board_mmc_power_init();
2177 * put the host in the initial state:
2178 * - turn on Vdd (card power supply)
2179 * - configure the bus width and clock to minimal values
2181 static void mmc_set_initial_state(struct mmc *mmc)
2185 /* First try to set 3.3V. If it fails set to 1.8V */
2186 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2188 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2190 printf("mmc: failed to set signal voltage\n");
2192 mmc_select_mode(mmc, MMC_LEGACY);
2193 mmc_set_bus_width(mmc, 1);
2194 mmc_set_clock(mmc, 0, false);
2197 static int mmc_power_on(struct mmc *mmc)
2199 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2200 if (mmc->vmmc_supply) {
2201 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2204 puts("Error enabling VMMC supply\n");
2212 static int mmc_power_off(struct mmc *mmc)
2214 mmc_set_clock(mmc, 1, true);
2215 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2216 if (mmc->vmmc_supply) {
2217 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2220 debug("Error disabling VMMC supply\n");
2228 static int mmc_power_cycle(struct mmc *mmc)
2232 ret = mmc_power_off(mmc);
2236 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2237 * to be on the safer side.
2240 return mmc_power_on(mmc);
2243 int mmc_start_init(struct mmc *mmc)
2246 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2249 mmc->host_caps = mmc->cfg->host_caps;
2251 /* we pretend there's no card when init is NULL */
2252 no_card = mmc_getcd(mmc) == 0;
2253 #if !CONFIG_IS_ENABLED(DM_MMC)
2254 no_card = no_card || (mmc->cfg->ops->init == NULL);
2258 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2259 printf("MMC: no card present\n");
2267 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2268 mmc_adapter_card_type_ident();
2270 err = mmc_power_init(mmc);
2274 #ifdef CONFIG_MMC_QUIRKS
2275 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2276 MMC_QUIRK_RETRY_SEND_CID;
2279 err = mmc_power_cycle(mmc);
2282 * if power cycling is not supported, we should not try
2283 * to use the UHS modes, because we wouldn't be able to
2284 * recover from an error during the UHS initialization.
2286 debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2288 mmc->host_caps &= ~UHS_CAPS;
2289 err = mmc_power_on(mmc);
2294 #if CONFIG_IS_ENABLED(DM_MMC)
2295 /* The device has already been probed ready for use */
2297 /* made sure it's not NULL earlier */
2298 err = mmc->cfg->ops->init(mmc);
2305 mmc_set_initial_state(mmc);
2306 mmc_send_init_stream(mmc);
2308 /* Reset the Card */
2309 err = mmc_go_idle(mmc);
2314 /* The internal partition reset to user partition(0) at every CMD0*/
2315 mmc_get_blk_desc(mmc)->hwpart = 0;
2317 /* Test for SD version 2 */
2318 err = mmc_send_if_cond(mmc);
2320 /* Now try to get the SD card's operating condition */
2321 err = sd_send_op_cond(mmc, uhs_en);
2322 if (err && uhs_en) {
2324 mmc_power_cycle(mmc);
2328 /* If the command timed out, we check for an MMC card */
2329 if (err == -ETIMEDOUT) {
2330 err = mmc_send_op_cond(mmc);
2333 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2334 printf("Card did not respond to voltage select!\n");
2341 mmc->init_in_progress = 1;
2346 static int mmc_complete_init(struct mmc *mmc)
2350 mmc->init_in_progress = 0;
2351 if (mmc->op_cond_pending)
2352 err = mmc_complete_op_cond(mmc);
2355 err = mmc_startup(mmc);
2363 int mmc_init(struct mmc *mmc)
2366 __maybe_unused unsigned start;
2367 #if CONFIG_IS_ENABLED(DM_MMC)
2368 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2375 start = get_timer(0);
2377 if (!mmc->init_in_progress)
2378 err = mmc_start_init(mmc);
2381 err = mmc_complete_init(mmc);
2383 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2388 int mmc_set_dsr(struct mmc *mmc, u16 val)
2394 /* CPU-specific MMC initializations */
2395 __weak int cpu_mmc_init(bd_t *bis)
2400 /* board-specific MMC initializations. */
2401 __weak int board_mmc_init(bd_t *bis)
2406 void mmc_set_preinit(struct mmc *mmc, int preinit)
2408 mmc->preinit = preinit;
2411 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2412 static int mmc_probe(bd_t *bis)
2416 #elif CONFIG_IS_ENABLED(DM_MMC)
2417 static int mmc_probe(bd_t *bis)
2421 struct udevice *dev;
2423 ret = uclass_get(UCLASS_MMC, &uc);
2428 * Try to add them in sequence order. Really with driver model we
2429 * should allow holes, but the current MMC list does not allow that.
2430 * So if we request 0, 1, 3 we will get 0, 1, 2.
2432 for (i = 0; ; i++) {
2433 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2437 uclass_foreach_dev(dev, uc) {
2438 ret = device_probe(dev);
2440 printf("%s - probe failed: %d\n", dev->name, ret);
2446 static int mmc_probe(bd_t *bis)
2448 if (board_mmc_init(bis) < 0)
2455 int mmc_initialize(bd_t *bis)
2457 static int initialized = 0;
2459 if (initialized) /* Avoid initializing mmc multiple times */
2463 #if !CONFIG_IS_ENABLED(BLK)
2464 #if !CONFIG_IS_ENABLED(MMC_TINY)
2468 ret = mmc_probe(bis);
2472 #ifndef CONFIG_SPL_BUILD
2473 print_mmc_devices(',');
2480 #ifdef CONFIG_CMD_BKOPS_ENABLE
2481 int mmc_set_bkops_enable(struct mmc *mmc)
2484 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2486 err = mmc_send_ext_csd(mmc, ext_csd);
2488 puts("Could not get ext_csd register values\n");
2492 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2493 puts("Background operations not supported on device\n");
2494 return -EMEDIUMTYPE;
2497 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2498 puts("Background operations already enabled\n");
2502 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2504 puts("Failed to enable manual background operations\n");
2508 puts("Enabled manual background operations\n");