drivers/mmc/mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008, Freescale Semiconductor, Inc
   4  * Andy Fleming
   5  *
   6  * Based vaguely on the Linux code
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <command.h>
  12 #include <dm.h>
  13 #include <dm/device-internal.h>
  14 #include <errno.h>
  15 #include <mmc.h>
  16 #include <part.h>
  17 #include <power/regulator.h>
  18 #include <malloc.h>
  19 #include <memalign.h>
  20 #include <linux/list.h>
  21 #include <div64.h>
  22 #include "mmc_private.h"
  23
  24 #define DEFAULT_CMD6_TIMEOUT_MS  500
  25
  26 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  27 static int mmc_power_cycle(struct mmc *mmc);
  28 #if !CONFIG_IS_ENABLED(MMC_TINY)
  29 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
  30 #endif
  31
  32 #if !CONFIG_IS_ENABLED(DM_MMC)
  33
  34 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
  35 {
  36         return -ENOSYS;
  37 }
  38
  39 __weak int board_mmc_getwp(struct mmc *mmc)
  40 {
  41         return -1;
  42 }
  43
  44 int mmc_getwp(struct mmc *mmc)
  45 {
  46         int wp;
  47
  48         wp = board_mmc_getwp(mmc);
  49
  50         if (wp < 0) {
  51                 if (mmc->cfg->ops->getwp)
  52                         wp = mmc->cfg->ops->getwp(mmc);
  53                 else
  54                         wp = 0;
  55         }
  56
  57         return wp;
  58 }
  59
  60 __weak int board_mmc_getcd(struct mmc *mmc)
  61 {
  62         return -1;
  63 }
  64 #endif
  65
  66 #ifdef CONFIG_MMC_TRACE
  67 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  68 {
  69         printf("CMD_SEND:%d\n", cmd->cmdidx);
  70         printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  71 }
  72
  73 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  74 {
  75         int i;
  76         u8 *ptr;
  77
  78         if (ret) {
  79                 printf("\t\tRET\t\t\t %d\n", ret);
  80         } else {
  81                 switch (cmd->resp_type) {
  82                 case MMC_RSP_NONE:
  83                         printf("\t\tMMC_RSP_NONE\n");
  84                         break;
  85                 case MMC_RSP_R1:
  86                         printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  87                                 cmd->response[0]);
  88                         break;
  89                 case MMC_RSP_R1b:
  90                         printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  91                                 cmd->response[0]);
  92                         break;
  93                 case MMC_RSP_R2:
  94                         printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  95                                 cmd->response[0]);
  96                         printf("\t\t          \t\t 0x%08x \n",
  97                                 cmd->response[1]);
  98                         printf("\t\t          \t\t 0x%08x \n",
  99                                 cmd->response[2]);
 100                         printf("\t\t          \t\t 0x%08x \n",
 101                                 cmd->response[3]);
 102                         printf("\n");
 103                         printf("\t\t\t\t\tDUMPING DATA\n");
 104                         for (i = 0; i < 4; i++) {
 105                                 int j;
 106                                 printf("\t\t\t\t\t%03d - ", i*4);
 107                                 ptr = (u8 *)&cmd->response[i];
 108                                 ptr += 3;
 109                                 for (j = 0; j < 4; j++)
 110                                         printf("%02x ", *ptr--);
 111                                 printf("\n");
 112                         }
 113                         break;
 114                 case MMC_RSP_R3:
 115                         printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
 116                                 cmd->response[0]);
 117                         break;
 118                 default:
 119                         printf("\t\tERROR MMC rsp not supported\n");
 120                         break;
 121                 }
 122         }
 123 }
 124
 125 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
 126 {
 127         int status;
 128
 129         status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
 130         printf("CURR STATE:%d\n", status);
 131 }
 132 #endif
 133
 134 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
 135 const char *mmc_mode_name(enum bus_mode mode)
 136 {
 137         static const char *const names[] = {
 138               [MMC_LEGACY]      = "MMC legacy",
 139               [SD_LEGACY]       = "SD Legacy",
 140               [MMC_HS]          = "MMC High Speed (26MHz)",
 141               [SD_HS]           = "SD High Speed (50MHz)",
 142               [UHS_SDR12]       = "UHS SDR12 (25MHz)",
 143               [UHS_SDR25]       = "UHS SDR25 (50MHz)",
 144               [UHS_SDR50]       = "UHS SDR50 (100MHz)",
 145               [UHS_SDR104]      = "UHS SDR104 (208MHz)",
 146               [UHS_DDR50]       = "UHS DDR50 (50MHz)",
 147               [MMC_HS_52]       = "MMC High Speed (52MHz)",
 148               [MMC_DDR_52]      = "MMC DDR52 (52MHz)",
 149               [MMC_HS_200]      = "HS200 (200MHz)",
 150               [MMC_HS_400]      = "HS400 (200MHz)",
 151         };
 152
 153         if (mode >= MMC_MODES_END)
 154                 return "Unknown mode";
 155         else
 156                 return names[mode];
 157 }
 158 #endif
 159
 160 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
 161 {
 162         static const int freqs[] = {
 163               [MMC_LEGACY]      = 25000000,
 164               [SD_LEGACY]       = 25000000,
 165               [MMC_HS]          = 26000000,
 166               [SD_HS]           = 50000000,
 167               [MMC_HS_52]       = 52000000,
 168               [MMC_DDR_52]      = 52000000,
 169               [UHS_SDR12]       = 25000000,
 170               [UHS_SDR25]       = 50000000,
 171               [UHS_SDR50]       = 100000000,
 172               [UHS_DDR50]       = 50000000,
 173               [UHS_SDR104]      = 208000000,
 174               [MMC_HS_200]      = 200000000,
 175               [MMC_HS_400]      = 200000000,
 176         };
 177
 178         if (mode == MMC_LEGACY)
 179                 return mmc->legacy_speed;
 180         else if (mode >= MMC_MODES_END)
 181                 return 0;
 182         else
 183                 return freqs[mode];
 184 }
 185
 186 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
 187 {
 188         mmc->selected_mode = mode;
 189         mmc->tran_speed = mmc_mode2freq(mmc, mode);
 190         mmc->ddr_mode = mmc_is_mode_ddr(mode);
 191         pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
 192                  mmc->tran_speed / 1000000);
 193         return 0;
 194 }
 195
 196 #if !CONFIG_IS_ENABLED(DM_MMC)
 197 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 198 {
 199         int ret;
 200
 201         mmmc_trace_before_send(mmc, cmd);
 202         ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 203         mmmc_trace_after_send(mmc, cmd, ret);
 204
 205         return ret;
 206 }
 207 #endif
 208
 209 int mmc_send_status(struct mmc *mmc, unsigned int *status)
 210 {
 211         struct mmc_cmd cmd;
 212         int err, retries = 5;
 213
 214         cmd.cmdidx = MMC_CMD_SEND_STATUS;
 215         cmd.resp_type = MMC_RSP_R1;
 216         if (!mmc_host_is_spi(mmc))
 217                 cmd.cmdarg = mmc->rca << 16;
 218
 219         while (retries--) {
 220                 err = mmc_send_cmd(mmc, &cmd, NULL);
 221                 if (!err) {
 222                         mmc_trace_state(mmc, &cmd);
 223                         *status = cmd.response[0];
 224                         return 0;
 225                 }
 226         }
 227         mmc_trace_state(mmc, &cmd);
 228         return -ECOMM;
 229 }
 230
 231 int mmc_poll_for_busy(struct mmc *mmc, int timeout)
 232 {
 233         unsigned int status;
 234         int err;
 235
 236         err = mmc_wait_dat0(mmc, 1, timeout);
 237         if (err != -ENOSYS)
 238                 return err;
 239
 240         while (1) {
 241                 err = mmc_send_status(mmc, &status);
 242                 if (err)
 243                         return err;
 244
 245                 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
 246                     (status & MMC_STATUS_CURR_STATE) !=
 247                      MMC_STATE_PRG)
 248                         break;
 249
 250                 if (status & MMC_STATUS_MASK) {
 251 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 252                         pr_err("Status Error: 0x%08x\n", status);
 253 #endif
 254                         return -ECOMM;
 255                 }
 256
 257                 if (timeout-- <= 0)
 258                         break;
 259
 260                 udelay(1000);
 261         }
 262
 263         if (timeout <= 0) {
 264 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 265                 pr_err("Timeout waiting card ready\n");
 266 #endif
 267                 return -ETIMEDOUT;
 268         }
 269
 270         return 0;
 271 }
 272
 273 int mmc_set_blocklen(struct mmc *mmc, int len)
 274 {
 275         struct mmc_cmd cmd;
 276         int err;
 277
 278         if (mmc->ddr_mode)
 279                 return 0;
 280
 281         cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
 282         cmd.resp_type = MMC_RSP_R1;
 283         cmd.cmdarg = len;
 284
 285         err = mmc_send_cmd(mmc, &cmd, NULL);
 286
 287 #ifdef CONFIG_MMC_QUIRKS
 288         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
 289                 int retries = 4;
 290                 /*
 291                  * It has been seen that SET_BLOCKLEN may fail on the first
 292                  * attempt, let's try a few more time
 293                  */
 294                 do {
 295                         err = mmc_send_cmd(mmc, &cmd, NULL);
 296                         if (!err)
 297                                 break;
 298                 } while (retries--);
 299         }
 300 #endif
 301
 302         return err;
 303 }
 304
 305 #ifdef MMC_SUPPORTS_TUNING
 306 static const u8 tuning_blk_pattern_4bit[] = {
 307         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 308         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 309         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 310         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 311         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 312         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 313         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 314         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 315 };
 316
 317 static const u8 tuning_blk_pattern_8bit[] = {
 318         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 319         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 320         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 321         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 322         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 323         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 324         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 325         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 326         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 327         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 328         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 329         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 330         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 331         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 332         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 333         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 334 };
 335
 336 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
 337 {
 338         struct mmc_cmd cmd;
 339         struct mmc_data data;
 340         const u8 *tuning_block_pattern;
 341         int size, err;
 342
 343         if (mmc->bus_width == 8) {
 344                 tuning_block_pattern = tuning_blk_pattern_8bit;
 345                 size = sizeof(tuning_blk_pattern_8bit);
 346         } else if (mmc->bus_width == 4) {
 347                 tuning_block_pattern = tuning_blk_pattern_4bit;
 348                 size = sizeof(tuning_blk_pattern_4bit);
 349         } else {
 350                 return -EINVAL;
 351         }
 352
 353         ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
 354
 355         cmd.cmdidx = opcode;
 356         cmd.cmdarg = 0;
 357         cmd.resp_type = MMC_RSP_R1;
 358
 359         data.dest = (void *)data_buf;
 360         data.blocks = 1;
 361         data.blocksize = size;
 362         data.flags = MMC_DATA_READ;
 363
 364         err = mmc_send_cmd(mmc, &cmd, &data);
 365         if (err)
 366                 return err;
 367
 368         if (memcmp(data_buf, tuning_block_pattern, size))
 369                 return -EIO;
 370
 371         return 0;
 372 }
 373 #endif
 374
 375 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 376                            lbaint_t blkcnt)
 377 {
 378         struct mmc_cmd cmd;
 379         struct mmc_data data;
 380
 381         if (blkcnt > 1)
 382                 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
 383         else
 384                 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
 385
 386         if (mmc->high_capacity)
 387                 cmd.cmdarg = start;
 388         else
 389                 cmd.cmdarg = start * mmc->read_bl_len;
 390
 391         cmd.resp_type = MMC_RSP_R1;
 392
 393         data.dest = dst;
 394         data.blocks = blkcnt;
 395         data.blocksize = mmc->read_bl_len;
 396         data.flags = MMC_DATA_READ;
 397
 398         if (mmc_send_cmd(mmc, &cmd, &data))
 399                 return 0;
 400
 401         if (blkcnt > 1) {
 402                 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 403                 cmd.cmdarg = 0;
 404                 cmd.resp_type = MMC_RSP_R1b;
 405                 if (mmc_send_cmd(mmc, &cmd, NULL)) {
 406 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 407                         pr_err("mmc fail to send stop cmd\n");
 408 #endif
 409                         return 0;
 410                 }
 411         }
 412
 413         return blkcnt;
 414 }
 415
 416 #if CONFIG_IS_ENABLED(BLK)
 417 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
 418 #else
 419 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 420                 void *dst)
 421 #endif
 422 {
 423 #if CONFIG_IS_ENABLED(BLK)
 424         struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 425 #endif
 426         int dev_num = block_dev->devnum;
 427         int err;
 428         lbaint_t cur, blocks_todo = blkcnt;
 429
 430         if (blkcnt == 0)
 431                 return 0;
 432
 433         struct mmc *mmc = find_mmc_device(dev_num);
 434         if (!mmc)
 435                 return 0;
 436
 437         if (CONFIG_IS_ENABLED(MMC_TINY))
 438                 err = mmc_switch_part(mmc, block_dev->hwpart);
 439         else
 440                 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
 441
 442         if (err < 0)
 443                 return 0;
 444
 445         if ((start + blkcnt) > block_dev->lba) {
 446 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 447                 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
 448                        start + blkcnt, block_dev->lba);
 449 #endif
 450                 return 0;
 451         }
 452
 453         if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
 454                 pr_debug("%s: Failed to set blocklen\n", __func__);
 455                 return 0;
 456         }
 457
 458         do {
 459                 cur = (blocks_todo > mmc->cfg->b_max) ?
 460                         mmc->cfg->b_max : blocks_todo;
 461                 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
 462                         pr_debug("%s: Failed to read blocks\n", __func__);
 463                         return 0;
 464                 }
 465                 blocks_todo -= cur;
 466                 start += cur;
 467                 dst += cur * mmc->read_bl_len;
 468         } while (blocks_todo > 0);
 469
 470         return blkcnt;
 471 }
 472
 473 static int mmc_go_idle(struct mmc *mmc)
 474 {
 475         struct mmc_cmd cmd;
 476         int err;
 477
 478         udelay(1000);
 479
 480         cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
 481         cmd.cmdarg = 0;
 482         cmd.resp_type = MMC_RSP_NONE;
 483
 484         err = mmc_send_cmd(mmc, &cmd, NULL);
 485
 486         if (err)
 487                 return err;
 488
 489         udelay(2000);
 490
 491         return 0;
 492 }
 493
 494 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 495 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
 496 {
 497         struct mmc_cmd cmd;
 498         int err = 0;
 499
 500         /*
 501          * Send CMD11 only if the request is to switch the card to
 502          * 1.8V signalling.
 503          */
 504         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 505                 return mmc_set_signal_voltage(mmc, signal_voltage);
 506
 507         cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
 508         cmd.cmdarg = 0;
 509         cmd.resp_type = MMC_RSP_R1;
 510
 511         err = mmc_send_cmd(mmc, &cmd, NULL);
 512         if (err)
 513                 return err;
 514
 515         if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
 516                 return -EIO;
 517
 518         /*
 519          * The card should drive cmd and dat[0:3] low immediately
 520          * after the response of cmd11, but wait 100 us to be sure
 521          */
 522         err = mmc_wait_dat0(mmc, 0, 100);
 523         if (err == -ENOSYS)
 524                 udelay(100);
 525         else if (err)
 526                 return -ETIMEDOUT;
 527
 528         /*
 529          * During a signal voltage level switch, the clock must be gated
 530          * for 5 ms according to the SD spec
 531          */
 532         mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
 533
 534         err = mmc_set_signal_voltage(mmc, signal_voltage);
 535         if (err)
 536                 return err;
 537
 538         /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
 539         mdelay(10);
 540         mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
 541
 542         /*
 543          * Failure to switch is indicated by the card holding
 544          * dat[0:3] low. Wait for at least 1 ms according to spec
 545          */
 546         err = mmc_wait_dat0(mmc, 1, 1000);
 547         if (err == -ENOSYS)
 548                 udelay(1000);
 549         else if (err)
 550                 return -ETIMEDOUT;
 551
 552         return 0;
 553 }
 554 #endif
 555
 556 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
 557 {
 558         int timeout = 1000;
 559         int err;
 560         struct mmc_cmd cmd;
 561
 562         while (1) {
 563                 cmd.cmdidx = MMC_CMD_APP_CMD;
 564                 cmd.resp_type = MMC_RSP_R1;
 565                 cmd.cmdarg = 0;
 566
 567                 err = mmc_send_cmd(mmc, &cmd, NULL);
 568
 569                 if (err)
 570                         return err;
 571
 572                 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
 573                 cmd.resp_type = MMC_RSP_R3;
 574
 575                 /*
 576                  * Most cards do not answer if some reserved bits
 577                  * in the ocr are set. However, Some controller
 578                  * can set bit 7 (reserved for low voltages), but
 579                  * how to manage low voltages SD card is not yet
 580                  * specified.
 581                  */
 582                 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
 583                         (mmc->cfg->voltages & 0xff8000);
 584
 585                 if (mmc->version == SD_VERSION_2)
 586                         cmd.cmdarg |= OCR_HCS;
 587
 588                 if (uhs_en)
 589                         cmd.cmdarg |= OCR_S18R;
 590
 591                 err = mmc_send_cmd(mmc, &cmd, NULL);
 592
 593                 if (err)
 594                         return err;
 595
 596                 if (cmd.response[0] & OCR_BUSY)
 597                         break;
 598
 599                 if (timeout-- <= 0)
 600                         return -EOPNOTSUPP;
 601
 602                 udelay(1000);
 603         }
 604
 605         if (mmc->version != SD_VERSION_2)
 606                 mmc->version = SD_VERSION_1_0;
 607
 608         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 609                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 610                 cmd.resp_type = MMC_RSP_R3;
 611                 cmd.cmdarg = 0;
 612
 613                 err = mmc_send_cmd(mmc, &cmd, NULL);
 614
 615                 if (err)
 616                         return err;
 617         }
 618
 619         mmc->ocr = cmd.response[0];
 620
 621 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 622         if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
 623             == 0x41000000) {
 624                 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
 625                 if (err)
 626                         return err;
 627         }
 628 #endif
 629
 630         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 631         mmc->rca = 0;
 632
 633         return 0;
 634 }
 635
 636 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
 637 {
 638         struct mmc_cmd cmd;
 639         int err;
 640
 641         cmd.cmdidx = MMC_CMD_SEND_OP_COND;
 642         cmd.resp_type = MMC_RSP_R3;
 643         cmd.cmdarg = 0;
 644         if (use_arg && !mmc_host_is_spi(mmc))
 645                 cmd.cmdarg = OCR_HCS |
 646                         (mmc->cfg->voltages &
 647                         (mmc->ocr & OCR_VOLTAGE_MASK)) |
 648                         (mmc->ocr & OCR_ACCESS_MODE);
 649
 650         err = mmc_send_cmd(mmc, &cmd, NULL);
 651         if (err)
 652                 return err;
 653         mmc->ocr = cmd.response[0];
 654         return 0;
 655 }
 656
 657 static int mmc_send_op_cond(struct mmc *mmc)
 658 {
 659         int err, i;
 660
 661         /* Some cards seem to need this */
 662         mmc_go_idle(mmc);
 663
 664         /* Asking to the card its capabilities */
 665         for (i = 0; i < 2; i++) {
 666                 err = mmc_send_op_cond_iter(mmc, i != 0);
 667                 if (err)
 668                         return err;
 669
 670                 /* exit if not busy (flag seems to be inverted) */
 671                 if (mmc->ocr & OCR_BUSY)
 672                         break;
 673         }
 674         mmc->op_cond_pending = 1;
 675         return 0;
 676 }
 677
 678 static int mmc_complete_op_cond(struct mmc *mmc)
 679 {
 680         struct mmc_cmd cmd;
 681         int timeout = 1000;
 682         ulong start;
 683         int err;
 684
 685         mmc->op_cond_pending = 0;
 686         if (!(mmc->ocr & OCR_BUSY)) {
 687                 /* Some cards seem to need this */
 688                 mmc_go_idle(mmc);
 689
 690                 start = get_timer(0);
 691                 while (1) {
 692                         err = mmc_send_op_cond_iter(mmc, 1);
 693                         if (err)
 694                                 return err;
 695                         if (mmc->ocr & OCR_BUSY)
 696                                 break;
 697                         if (get_timer(start) > timeout)
 698                                 return -EOPNOTSUPP;
 699                         udelay(100);
 700                 }
 701         }
 702
 703         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 704                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 705                 cmd.resp_type = MMC_RSP_R3;
 706                 cmd.cmdarg = 0;
 707
 708                 err = mmc_send_cmd(mmc, &cmd, NULL);
 709
 710                 if (err)
 711                         return err;
 712
 713                 mmc->ocr = cmd.response[0];
 714         }
 715
 716         mmc->version = MMC_VERSION_UNKNOWN;
 717
 718         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 719         mmc->rca = 1;
 720
 721         return 0;
 722 }
 723
 724
 725 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 726 {
 727         struct mmc_cmd cmd;
 728         struct mmc_data data;
 729         int err;
 730
 731         /* Get the Card Status Register */
 732         cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
 733         cmd.resp_type = MMC_RSP_R1;
 734         cmd.cmdarg = 0;
 735
 736         data.dest = (char *)ext_csd;
 737         data.blocks = 1;
 738         data.blocksize = MMC_MAX_BLOCK_LEN;
 739         data.flags = MMC_DATA_READ;
 740
 741         err = mmc_send_cmd(mmc, &cmd, &data);
 742
 743         return err;
 744 }
 745
 746 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 747                         bool send_status)
 748 {
 749         struct mmc_cmd cmd;
 750         int timeout = DEFAULT_CMD6_TIMEOUT_MS;
 751         int retries = 3;
 752         int ret;
 753
 754         if (mmc->gen_cmd6_time)
 755                 timeout = mmc->gen_cmd6_time * 10;
 756
 757         cmd.cmdidx = MMC_CMD_SWITCH;
 758         cmd.resp_type = MMC_RSP_R1b;
 759         cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
 760                                  (index << 16) |
 761                                  (value << 8);
 762
 763         while (retries > 0) {
 764                 ret = mmc_send_cmd(mmc, &cmd, NULL);
 765
 766                 if (ret) {
 767                         retries--;
 768                         continue;
 769                 }
 770
 771                 if (!send_status) {
 772                         mdelay(50);
 773                         return 0;
 774                 }
 775
 776                 /* Waiting for the ready status */
 777                 return mmc_poll_for_busy(mmc, timeout);
 778         }
 779
 780         return ret;
 781
 782 }
 783
 784 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 785 {
 786         return __mmc_switch(mmc, set, index, value, true);
 787 }
 788
 789 #if !CONFIG_IS_ENABLED(MMC_TINY)
 790 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
 791                               bool hsdowngrade)
 792 {
 793         int err;
 794         int speed_bits;
 795
 796         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 797
 798         switch (mode) {
 799         case MMC_HS:
 800         case MMC_HS_52:
 801         case MMC_DDR_52:
 802                 speed_bits = EXT_CSD_TIMING_HS;
 803                 break;
 804 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 805         case MMC_HS_200:
 806                 speed_bits = EXT_CSD_TIMING_HS200;
 807                 break;
 808 #endif
 809 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 810         case MMC_HS_400:
 811                 speed_bits = EXT_CSD_TIMING_HS400;
 812                 break;
 813 #endif
 814         case MMC_LEGACY:
 815                 speed_bits = EXT_CSD_TIMING_LEGACY;
 816                 break;
 817         default:
 818                 return -EINVAL;
 819         }
 820
 821         err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
 822                            speed_bits, !hsdowngrade);
 823         if (err)
 824                 return err;
 825
 826 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 827     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 828         /*
 829          * In case the eMMC is in HS200/HS400 mode and we are downgrading
 830          * to HS mode, the card clock are still running much faster than
 831          * the supported HS mode clock, so we can not reliably read out
 832          * Extended CSD. Reconfigure the controller to run at HS mode.
 833          */
 834         if (hsdowngrade) {
 835                 mmc_select_mode(mmc, MMC_HS);
 836                 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
 837         }
 838 #endif
 839
 840         if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
 841                 /* Now check to see that it worked */
 842                 err = mmc_send_ext_csd(mmc, test_csd);
 843                 if (err)
 844                         return err;
 845
 846                 /* No high-speed support */
 847                 if (!test_csd[EXT_CSD_HS_TIMING])
 848                         return -ENOTSUPP;
 849         }
 850
 851         return 0;
 852 }
 853
 854 static int mmc_get_capabilities(struct mmc *mmc)
 855 {
 856         u8 *ext_csd = mmc->ext_csd;
 857         char cardtype;
 858
 859         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
 860
 861         if (mmc_host_is_spi(mmc))
 862                 return 0;
 863
 864         /* Only version 4 supports high-speed */
 865         if (mmc->version < MMC_VERSION_4)
 866                 return 0;
 867
 868         if (!ext_csd) {
 869                 pr_err("No ext_csd found!\n"); /* this should enver happen */
 870                 return -ENOTSUPP;
 871         }
 872
 873         mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
 874
 875         cardtype = ext_csd[EXT_CSD_CARD_TYPE];
 876         mmc->cardtype = cardtype;
 877
 878 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 879         if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
 880                         EXT_CSD_CARD_TYPE_HS200_1_8V)) {
 881                 mmc->card_caps |= MMC_MODE_HS200;
 882         }
 883 #endif
 884 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 885         if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
 886                         EXT_CSD_CARD_TYPE_HS400_1_8V)) {
 887                 mmc->card_caps |= MMC_MODE_HS400;
 888         }
 889 #endif
 890         if (cardtype & EXT_CSD_CARD_TYPE_52) {
 891                 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
 892                         mmc->card_caps |= MMC_MODE_DDR_52MHz;
 893                 mmc->card_caps |= MMC_MODE_HS_52MHz;
 894         }
 895         if (cardtype & EXT_CSD_CARD_TYPE_26)
 896                 mmc->card_caps |= MMC_MODE_HS;
 897
 898         return 0;
 899 }
 900 #endif
 901
 902 static int mmc_set_capacity(struct mmc *mmc, int part_num)
 903 {
 904         switch (part_num) {
 905         case 0:
 906                 mmc->capacity = mmc->capacity_user;
 907                 break;
 908         case 1:
 909         case 2:
 910                 mmc->capacity = mmc->capacity_boot;
 911                 break;
 912         case 3:
 913                 mmc->capacity = mmc->capacity_rpmb;
 914                 break;
 915         case 4:
 916         case 5:
 917         case 6:
 918         case 7:
 919                 mmc->capacity = mmc->capacity_gp[part_num - 4];
 920                 break;
 921         default:
 922                 return -1;
 923         }
 924
 925         mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 926
 927         return 0;
 928 }
 929
 930 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 931 static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
 932 {
 933         int forbidden = 0;
 934         bool change = false;
 935
 936         if (part_num & PART_ACCESS_MASK)
 937                 forbidden = MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400);
 938
 939         if (MMC_CAP(mmc->selected_mode) & forbidden) {
 940                 pr_debug("selected mode (%s) is forbidden for part %d\n",
 941                          mmc_mode_name(mmc->selected_mode), part_num);
 942                 change = true;
 943         } else if (mmc->selected_mode != mmc->best_mode) {
 944                 pr_debug("selected mode is not optimal\n");
 945                 change = true;
 946         }
 947
 948         if (change)
 949                 return mmc_select_mode_and_width(mmc,
 950                                                  mmc->card_caps & ~forbidden);
 951
 952         return 0;
 953 }
 954 #else
 955 static inline int mmc_boot_part_access_chk(struct mmc *mmc,
 956                                            unsigned int part_num)
 957 {
 958         return 0;
 959 }
 960 #endif
 961
 962 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 963 {
 964         int ret;
 965
 966         ret = mmc_boot_part_access_chk(mmc, part_num);
 967         if (ret)
 968                 return ret;
 969
 970         ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
 971                          (mmc->part_config & ~PART_ACCESS_MASK)
 972                          | (part_num & PART_ACCESS_MASK));
 973
 974         /*
 975          * Set the capacity if the switch succeeded or was intended
 976          * to return to representing the raw device.
 977          */
 978         if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
 979                 ret = mmc_set_capacity(mmc, part_num);
 980                 mmc_get_blk_desc(mmc)->hwpart = part_num;
 981         }
 982
 983         return ret;
 984 }
 985
 986 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
 987 int mmc_hwpart_config(struct mmc *mmc,
 988                       const struct mmc_hwpart_conf *conf,
 989                       enum mmc_hwpart_conf_mode mode)
 990 {
 991         u8 part_attrs = 0;
 992         u32 enh_size_mult;
 993         u32 enh_start_addr;
 994         u32 gp_size_mult[4];
 995         u32 max_enh_size_mult;
 996         u32 tot_enh_size_mult = 0;
 997         u8 wr_rel_set;
 998         int i, pidx, err;
 999         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1000
1001         if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1002                 return -EINVAL;
1003
1004         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
1005                 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
1006                 return -EMEDIUMTYPE;
1007         }
1008
1009         if (!(mmc->part_support & PART_SUPPORT)) {
1010                 pr_err("Card does not support partitioning\n");
1011                 return -EMEDIUMTYPE;
1012         }
1013
1014         if (!mmc->hc_wp_grp_size) {
1015                 pr_err("Card does not define HC WP group size\n");
1016                 return -EMEDIUMTYPE;
1017         }
1018
1019         /* check partition alignment and total enhanced size */
1020         if (conf->user.enh_size) {
1021                 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1022                     conf->user.enh_start % mmc->hc_wp_grp_size) {
1023                         pr_err("User data enhanced area not HC WP group "
1024                                "size aligned\n");
1025                         return -EINVAL;
1026                 }
1027                 part_attrs |= EXT_CSD_ENH_USR;
1028                 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1029                 if (mmc->high_capacity) {
1030                         enh_start_addr = conf->user.enh_start;
1031                 } else {
1032                         enh_start_addr = (conf->user.enh_start << 9);
1033                 }
1034         } else {
1035                 enh_size_mult = 0;
1036                 enh_start_addr = 0;
1037         }
1038         tot_enh_size_mult += enh_size_mult;
1039
1040         for (pidx = 0; pidx < 4; pidx++) {
1041                 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1042                         pr_err("GP%i partition not HC WP group size "
1043                                "aligned\n", pidx+1);
1044                         return -EINVAL;
1045                 }
1046                 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1047                 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1048                         part_attrs |= EXT_CSD_ENH_GP(pidx);
1049                         tot_enh_size_mult += gp_size_mult[pidx];
1050                 }
1051         }
1052
1053         if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1054                 pr_err("Card does not support enhanced attribute\n");
1055                 return -EMEDIUMTYPE;
1056         }
1057
1058         err = mmc_send_ext_csd(mmc, ext_csd);
1059         if (err)
1060                 return err;
1061
1062         max_enh_size_mult =
1063                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1064                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1065                 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1066         if (tot_enh_size_mult > max_enh_size_mult) {
1067                 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1068                        tot_enh_size_mult, max_enh_size_mult);
1069                 return -EMEDIUMTYPE;
1070         }
1071
1072         /* The default value of EXT_CSD_WR_REL_SET is device
1073          * dependent, the values can only be changed if the
1074          * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1075          * changed only once and before partitioning is completed. */
1076         wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1077         if (conf->user.wr_rel_change) {
1078                 if (conf->user.wr_rel_set)
1079                         wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1080                 else
1081                         wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1082         }
1083         for (pidx = 0; pidx < 4; pidx++) {
1084                 if (conf->gp_part[pidx].wr_rel_change) {
1085                         if (conf->gp_part[pidx].wr_rel_set)
1086                                 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1087                         else
1088                                 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1089                 }
1090         }
1091
1092         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1093             !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1094                 puts("Card does not support host controlled partition write "
1095                      "reliability settings\n");
1096                 return -EMEDIUMTYPE;
1097         }
1098
1099         if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1100             EXT_CSD_PARTITION_SETTING_COMPLETED) {
1101                 pr_err("Card already partitioned\n");
1102                 return -EPERM;
1103         }
1104
1105         if (mode == MMC_HWPART_CONF_CHECK)
1106                 return 0;
1107
1108         /* Partitioning requires high-capacity size definitions */
1109         if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1110                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1111                                  EXT_CSD_ERASE_GROUP_DEF, 1);
1112
1113                 if (err)
1114                         return err;
1115
1116                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1117
1118                 /* update erase group size to be high-capacity */
1119                 mmc->erase_grp_size =
1120                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1121
1122         }
1123
1124         /* all OK, write the configuration */
1125         for (i = 0; i < 4; i++) {
1126                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1127                                  EXT_CSD_ENH_START_ADDR+i,
1128                                  (enh_start_addr >> (i*8)) & 0xFF);
1129                 if (err)
1130                         return err;
1131         }
1132         for (i = 0; i < 3; i++) {
1133                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1134                                  EXT_CSD_ENH_SIZE_MULT+i,
1135                                  (enh_size_mult >> (i*8)) & 0xFF);
1136                 if (err)
1137                         return err;
1138         }
1139         for (pidx = 0; pidx < 4; pidx++) {
1140                 for (i = 0; i < 3; i++) {
1141                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1142                                          EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1143                                          (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1144                         if (err)
1145                                 return err;
1146                 }
1147         }
1148         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1149                          EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1150         if (err)
1151                 return err;
1152
1153         if (mode == MMC_HWPART_CONF_SET)
1154                 return 0;
1155
1156         /* The WR_REL_SET is a write-once register but shall be
1157          * written before setting PART_SETTING_COMPLETED. As it is
1158          * write-once we can only write it when completing the
1159          * partitioning. */
1160         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1161                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1162                                  EXT_CSD_WR_REL_SET, wr_rel_set);
1163                 if (err)
1164                         return err;
1165         }
1166
1167         /* Setting PART_SETTING_COMPLETED confirms the partition
1168          * configuration but it only becomes effective after power
1169          * cycle, so we do not adjust the partition related settings
1170          * in the mmc struct. */
1171
1172         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1173                          EXT_CSD_PARTITION_SETTING,
1174                          EXT_CSD_PARTITION_SETTING_COMPLETED);
1175         if (err)
1176                 return err;
1177
1178         return 0;
1179 }
1180 #endif
1181
1182 #if !CONFIG_IS_ENABLED(DM_MMC)
1183 int mmc_getcd(struct mmc *mmc)
1184 {
1185         int cd;
1186
1187         cd = board_mmc_getcd(mmc);
1188
1189         if (cd < 0) {
1190                 if (mmc->cfg->ops->getcd)
1191                         cd = mmc->cfg->ops->getcd(mmc);
1192                 else
1193                         cd = 1;
1194         }
1195
1196         return cd;
1197 }
1198 #endif
1199
1200 #if !CONFIG_IS_ENABLED(MMC_TINY)
1201 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1202 {
1203         struct mmc_cmd cmd;
1204         struct mmc_data data;
1205
1206         /* Switch the frequency */
1207         cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1208         cmd.resp_type = MMC_RSP_R1;
1209         cmd.cmdarg = (mode << 31) | 0xffffff;
1210         cmd.cmdarg &= ~(0xf << (group * 4));
1211         cmd.cmdarg |= value << (group * 4);
1212
1213         data.dest = (char *)resp;
1214         data.blocksize = 64;
1215         data.blocks = 1;
1216         data.flags = MMC_DATA_READ;
1217
1218         return mmc_send_cmd(mmc, &cmd, &data);
1219 }
1220
1221 static int sd_get_capabilities(struct mmc *mmc)
1222 {
1223         int err;
1224         struct mmc_cmd cmd;
1225         ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1226         ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1227         struct mmc_data data;
1228         int timeout;
1229 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1230         u32 sd3_bus_mode;
1231 #endif
1232
1233         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1234
1235         if (mmc_host_is_spi(mmc))
1236                 return 0;
1237
1238         /* Read the SCR to find out if this card supports higher speeds */
1239         cmd.cmdidx = MMC_CMD_APP_CMD;
1240         cmd.resp_type = MMC_RSP_R1;
1241         cmd.cmdarg = mmc->rca << 16;
1242
1243         err = mmc_send_cmd(mmc, &cmd, NULL);
1244
1245         if (err)
1246                 return err;
1247
1248         cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1249         cmd.resp_type = MMC_RSP_R1;
1250         cmd.cmdarg = 0;
1251
1252         timeout = 3;
1253
1254 retry_scr:
1255         data.dest = (char *)scr;
1256         data.blocksize = 8;
1257         data.blocks = 1;
1258         data.flags = MMC_DATA_READ;
1259
1260         err = mmc_send_cmd(mmc, &cmd, &data);
1261
1262         if (err) {
1263                 if (timeout--)
1264                         goto retry_scr;
1265
1266                 return err;
1267         }
1268
1269         mmc->scr[0] = __be32_to_cpu(scr[0]);
1270         mmc->scr[1] = __be32_to_cpu(scr[1]);
1271
1272         switch ((mmc->scr[0] >> 24) & 0xf) {
1273         case 0:
1274                 mmc->version = SD_VERSION_1_0;
1275                 break;
1276         case 1:
1277                 mmc->version = SD_VERSION_1_10;
1278                 break;
1279         case 2:
1280                 mmc->version = SD_VERSION_2;
1281                 if ((mmc->scr[0] >> 15) & 0x1)
1282                         mmc->version = SD_VERSION_3;
1283                 break;
1284         default:
1285                 mmc->version = SD_VERSION_1_0;
1286                 break;
1287         }
1288
1289         if (mmc->scr[0] & SD_DATA_4BIT)
1290                 mmc->card_caps |= MMC_MODE_4BIT;
1291
1292         /* Version 1.0 doesn't support switching */
1293         if (mmc->version == SD_VERSION_1_0)
1294                 return 0;
1295
1296         timeout = 4;
1297         while (timeout--) {
1298                 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1299                                 (u8 *)switch_status);
1300
1301                 if (err)
1302                         return err;
1303
1304                 /* The high-speed function is busy.  Try again */
1305                 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1306                         break;
1307         }
1308
1309         /* If high-speed isn't supported, we return */
1310         if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1311                 mmc->card_caps |= MMC_CAP(SD_HS);
1312
1313 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1314         /* Version before 3.0 don't support UHS modes */
1315         if (mmc->version < SD_VERSION_3)
1316                 return 0;
1317
1318         sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1319         if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1320                 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1321         if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1322                 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1323         if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1324                 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1325         if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1326                 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1327         if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1328                 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1329 #endif
1330
1331         return 0;
1332 }
1333
1334 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1335 {
1336         int err;
1337
1338         ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1339         int speed;
1340
1341         /* SD version 1.00 and 1.01 does not support CMD 6 */
1342         if (mmc->version == SD_VERSION_1_0)
1343                 return 0;
1344
1345         switch (mode) {
1346         case SD_LEGACY:
1347                 speed = UHS_SDR12_BUS_SPEED;
1348                 break;
1349         case SD_HS:
1350                 speed = HIGH_SPEED_BUS_SPEED;
1351                 break;
1352 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1353         case UHS_SDR12:
1354                 speed = UHS_SDR12_BUS_SPEED;
1355                 break;
1356         case UHS_SDR25:
1357                 speed = UHS_SDR25_BUS_SPEED;
1358                 break;
1359         case UHS_SDR50:
1360                 speed = UHS_SDR50_BUS_SPEED;
1361                 break;
1362         case UHS_DDR50:
1363                 speed = UHS_DDR50_BUS_SPEED;
1364                 break;
1365         case UHS_SDR104:
1366                 speed = UHS_SDR104_BUS_SPEED;
1367                 break;
1368 #endif
1369         default:
1370                 return -EINVAL;
1371         }
1372
1373         err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1374         if (err)
1375                 return err;
1376
1377         if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1378                 return -ENOTSUPP;
1379
1380         return 0;
1381 }
1382
1383 static int sd_select_bus_width(struct mmc *mmc, int w)
1384 {
1385         int err;
1386         struct mmc_cmd cmd;
1387
1388         if ((w != 4) && (w != 1))
1389                 return -EINVAL;
1390
1391         cmd.cmdidx = MMC_CMD_APP_CMD;
1392         cmd.resp_type = MMC_RSP_R1;
1393         cmd.cmdarg = mmc->rca << 16;
1394
1395         err = mmc_send_cmd(mmc, &cmd, NULL);
1396         if (err)
1397                 return err;
1398
1399         cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1400         cmd.resp_type = MMC_RSP_R1;
1401         if (w == 4)
1402                 cmd.cmdarg = 2;
1403         else if (w == 1)
1404                 cmd.cmdarg = 0;
1405         err = mmc_send_cmd(mmc, &cmd, NULL);
1406         if (err)
1407                 return err;
1408
1409         return 0;
1410 }
1411 #endif
1412
1413 #if CONFIG_IS_ENABLED(MMC_WRITE)
1414 static int sd_read_ssr(struct mmc *mmc)
1415 {
1416         static const unsigned int sd_au_size[] = {
1417                 0,              SZ_16K / 512,           SZ_32K / 512,
1418                 SZ_64K / 512,   SZ_128K / 512,          SZ_256K / 512,
1419                 SZ_512K / 512,  SZ_1M / 512,            SZ_2M / 512,
1420                 SZ_4M / 512,    SZ_8M / 512,            (SZ_8M + SZ_4M) / 512,
1421                 SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1422                 SZ_64M / 512,
1423         };
1424         int err, i;
1425         struct mmc_cmd cmd;
1426         ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1427         struct mmc_data data;
1428         int timeout = 3;
1429         unsigned int au, eo, et, es;
1430
1431         cmd.cmdidx = MMC_CMD_APP_CMD;
1432         cmd.resp_type = MMC_RSP_R1;
1433         cmd.cmdarg = mmc->rca << 16;
1434
1435         err = mmc_send_cmd(mmc, &cmd, NULL);
1436         if (err)
1437                 return err;
1438
1439         cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1440         cmd.resp_type = MMC_RSP_R1;
1441         cmd.cmdarg = 0;
1442
1443 retry_ssr:
1444         data.dest = (char *)ssr;
1445         data.blocksize = 64;
1446         data.blocks = 1;
1447         data.flags = MMC_DATA_READ;
1448
1449         err = mmc_send_cmd(mmc, &cmd, &data);
1450         if (err) {
1451                 if (timeout--)
1452                         goto retry_ssr;
1453
1454                 return err;
1455         }
1456
1457         for (i = 0; i < 16; i++)
1458                 ssr[i] = be32_to_cpu(ssr[i]);
1459
1460         au = (ssr[2] >> 12) & 0xF;
1461         if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1462                 mmc->ssr.au = sd_au_size[au];
1463                 es = (ssr[3] >> 24) & 0xFF;
1464                 es |= (ssr[2] & 0xFF) << 8;
1465                 et = (ssr[3] >> 18) & 0x3F;
1466                 if (es && et) {
1467                         eo = (ssr[3] >> 16) & 0x3;
1468                         mmc->ssr.erase_timeout = (et * 1000) / es;
1469                         mmc->ssr.erase_offset = eo * 1000;
1470                 }
1471         } else {
1472                 pr_debug("Invalid Allocation Unit Size.\n");
1473         }
1474
1475         return 0;
1476 }
1477 #endif
1478 /* frequency bases */
1479 /* divided by 10 to be nice to platforms without floating point */
1480 static const int fbase[] = {
1481         10000,
1482         100000,
1483         1000000,
1484         10000000,
1485 };
1486
1487 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
1488  * to platforms without floating point.
1489  */
1490 static const u8 multipliers[] = {
1491         0,      /* reserved */
1492         10,
1493         12,
1494         13,
1495         15,
1496         20,
1497         25,
1498         30,
1499         35,
1500         40,
1501         45,
1502         50,
1503         55,
1504         60,
1505         70,
1506         80,
1507 };
1508
1509 static inline int bus_width(uint cap)
1510 {
1511         if (cap == MMC_MODE_8BIT)
1512                 return 8;
1513         if (cap == MMC_MODE_4BIT)
1514                 return 4;
1515         if (cap == MMC_MODE_1BIT)
1516                 return 1;
1517         pr_warn("invalid bus witdh capability 0x%x\n", cap);
1518         return 0;
1519 }
1520
1521 #if !CONFIG_IS_ENABLED(DM_MMC)
1522 #ifdef MMC_SUPPORTS_TUNING
1523 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1524 {
1525         return -ENOTSUPP;
1526 }
1527 #endif
1528
1529 static int mmc_set_ios(struct mmc *mmc)
1530 {
1531         int ret = 0;
1532
1533         if (mmc->cfg->ops->set_ios)
1534                 ret = mmc->cfg->ops->set_ios(mmc);
1535
1536         return ret;
1537 }
1538 #endif
1539
1540 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1541 {
1542         if (!disable) {
1543                 if (clock > mmc->cfg->f_max)
1544                         clock = mmc->cfg->f_max;
1545
1546                 if (clock < mmc->cfg->f_min)
1547                         clock = mmc->cfg->f_min;
1548         }
1549
1550         mmc->clock = clock;
1551         mmc->clk_disable = disable;
1552
1553         debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1554
1555         return mmc_set_ios(mmc);
1556 }
1557
1558 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1559 {
1560         mmc->bus_width = width;
1561
1562         return mmc_set_ios(mmc);
1563 }
1564
1565 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1566 /*
1567  * helper function to display the capabilities in a human
1568  * friendly manner. The capabilities include bus width and
1569  * supported modes.
1570  */
1571 void mmc_dump_capabilities(const char *text, uint caps)
1572 {
1573         enum bus_mode mode;
1574
1575         pr_debug("%s: widths [", text);
1576         if (caps & MMC_MODE_8BIT)
1577                 pr_debug("8, ");
1578         if (caps & MMC_MODE_4BIT)
1579                 pr_debug("4, ");
1580         if (caps & MMC_MODE_1BIT)
1581                 pr_debug("1, ");
1582         pr_debug("\b\b] modes [");
1583         for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1584                 if (MMC_CAP(mode) & caps)
1585                         pr_debug("%s, ", mmc_mode_name(mode));
1586         pr_debug("\b\b]\n");
1587 }
1588 #endif
1589
1590 struct mode_width_tuning {
1591         enum bus_mode mode;
1592         uint widths;
1593 #ifdef MMC_SUPPORTS_TUNING
1594         uint tuning;
1595 #endif
1596 };
1597
1598 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1599 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1600 {
1601         switch (voltage) {
1602         case MMC_SIGNAL_VOLTAGE_000: return 0;
1603         case MMC_SIGNAL_VOLTAGE_330: return 3300;
1604         case MMC_SIGNAL_VOLTAGE_180: return 1800;
1605         case MMC_SIGNAL_VOLTAGE_120: return 1200;
1606         }
1607         return -EINVAL;
1608 }
1609
1610 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1611 {
1612         int err;
1613
1614         if (mmc->signal_voltage == signal_voltage)
1615                 return 0;
1616
1617         mmc->signal_voltage = signal_voltage;
1618         err = mmc_set_ios(mmc);
1619         if (err)
1620                 pr_debug("unable to set voltage (err %d)\n", err);
1621
1622         return err;
1623 }
1624 #else
1625 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1626 {
1627         return 0;
1628 }
1629 #endif
1630
1631 #if !CONFIG_IS_ENABLED(MMC_TINY)
1632 static const struct mode_width_tuning sd_modes_by_pref[] = {
1633 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1634 #ifdef MMC_SUPPORTS_TUNING
1635         {
1636                 .mode = UHS_SDR104,
1637                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1638                 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1639         },
1640 #endif
1641         {
1642                 .mode = UHS_SDR50,
1643                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1644         },
1645         {
1646                 .mode = UHS_DDR50,
1647                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1648         },
1649         {
1650                 .mode = UHS_SDR25,
1651                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1652         },
1653 #endif
1654         {
1655                 .mode = SD_HS,
1656                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1657         },
1658 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1659         {
1660                 .mode = UHS_SDR12,
1661                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1662         },
1663 #endif
1664         {
1665                 .mode = SD_LEGACY,
1666                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1667         }
1668 };
1669
1670 #define for_each_sd_mode_by_pref(caps, mwt) \
1671         for (mwt = sd_modes_by_pref;\
1672              mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1673              mwt++) \
1674                 if (caps & MMC_CAP(mwt->mode))
1675
1676 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1677 {
1678         int err;
1679         uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1680         const struct mode_width_tuning *mwt;
1681 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1682         bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1683 #else
1684         bool uhs_en = false;
1685 #endif
1686         uint caps;
1687
1688 #ifdef DEBUG
1689         mmc_dump_capabilities("sd card", card_caps);
1690         mmc_dump_capabilities("host", mmc->host_caps);
1691 #endif
1692
1693         /* Restrict card's capabilities by what the host can do */
1694         caps = card_caps & mmc->host_caps;
1695
1696         if (!uhs_en)
1697                 caps &= ~UHS_CAPS;
1698
1699         for_each_sd_mode_by_pref(caps, mwt) {
1700                 uint *w;
1701
1702                 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1703                         if (*w & caps & mwt->widths) {
1704                                 pr_debug("trying mode %s width %d (at %d MHz)\n",
1705                                          mmc_mode_name(mwt->mode),
1706                                          bus_width(*w),
1707                                          mmc_mode2freq(mmc, mwt->mode) / 1000000);
1708
1709                                 /* configure the bus width (card + host) */
1710                                 err = sd_select_bus_width(mmc, bus_width(*w));
1711                                 if (err)
1712                                         goto error;
1713                                 mmc_set_bus_width(mmc, bus_width(*w));
1714
1715                                 /* configure the bus mode (card) */
1716                                 err = sd_set_card_speed(mmc, mwt->mode);
1717                                 if (err)
1718                                         goto error;
1719
1720                                 /* configure the bus mode (host) */
1721                                 mmc_select_mode(mmc, mwt->mode);
1722                                 mmc_set_clock(mmc, mmc->tran_speed,
1723                                                 MMC_CLK_ENABLE);
1724
1725 #ifdef MMC_SUPPORTS_TUNING
1726                                 /* execute tuning if needed */
1727                                 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1728                                         err = mmc_execute_tuning(mmc,
1729                                                                  mwt->tuning);
1730                                         if (err) {
1731                                                 pr_debug("tuning failed\n");
1732                                                 goto error;
1733                                         }
1734                                 }
1735 #endif
1736
1737 #if CONFIG_IS_ENABLED(MMC_WRITE)
1738                                 err = sd_read_ssr(mmc);
1739                                 if (err)
1740                                         pr_warn("unable to read ssr\n");
1741 #endif
1742                                 if (!err)
1743                                         return 0;
1744
1745 error:
1746                                 /* revert to a safer bus speed */
1747                                 mmc_select_mode(mmc, SD_LEGACY);
1748                                 mmc_set_clock(mmc, mmc->tran_speed,
1749                                                 MMC_CLK_ENABLE);
1750                         }
1751                 }
1752         }
1753
1754         pr_err("unable to select a mode\n");
1755         return -ENOTSUPP;
1756 }
1757
1758 /*
1759  * read the compare the part of ext csd that is constant.
1760  * This can be used to check that the transfer is working
1761  * as expected.
1762  */
1763 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1764 {
1765         int err;
1766         const u8 *ext_csd = mmc->ext_csd;
1767         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1768
1769         if (mmc->version < MMC_VERSION_4)
1770                 return 0;
1771
1772         err = mmc_send_ext_csd(mmc, test_csd);
1773         if (err)
1774                 return err;
1775
1776         /* Only compare read only fields */
1777         if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1778                 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1779             ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1780                 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1781             ext_csd[EXT_CSD_REV]
1782                 == test_csd[EXT_CSD_REV] &&
1783             ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1784                 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1785             memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1786                    &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1787                 return 0;
1788
1789         return -EBADMSG;
1790 }
1791
1792 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1793 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1794                                   uint32_t allowed_mask)
1795 {
1796         u32 card_mask = 0;
1797
1798         switch (mode) {
1799         case MMC_HS_400:
1800         case MMC_HS_200:
1801                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1802                     EXT_CSD_CARD_TYPE_HS400_1_8V))
1803                         card_mask |= MMC_SIGNAL_VOLTAGE_180;
1804                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1805                     EXT_CSD_CARD_TYPE_HS400_1_2V))
1806                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1807                 break;
1808         case MMC_DDR_52:
1809                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1810                         card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1811                                      MMC_SIGNAL_VOLTAGE_180;
1812                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1813                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1814                 break;
1815         default:
1816                 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1817                 break;
1818         }
1819
1820         while (card_mask & allowed_mask) {
1821                 enum mmc_voltage best_match;
1822
1823                 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1824                 if (!mmc_set_signal_voltage(mmc,  best_match))
1825                         return 0;
1826
1827                 allowed_mask &= ~best_match;
1828         }
1829
1830         return -ENOTSUPP;
1831 }
1832 #else
1833 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1834                                          uint32_t allowed_mask)
1835 {
1836         return 0;
1837 }
1838 #endif
1839
1840 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1841 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1842         {
1843                 .mode = MMC_HS_400,
1844                 .widths = MMC_MODE_8BIT,
1845                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1846         },
1847 #endif
1848 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1849         {
1850                 .mode = MMC_HS_200,
1851                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1852                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1853         },
1854 #endif
1855         {
1856                 .mode = MMC_DDR_52,
1857                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1858         },
1859         {
1860                 .mode = MMC_HS_52,
1861                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1862         },
1863         {
1864                 .mode = MMC_HS,
1865                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1866         },
1867         {
1868                 .mode = MMC_LEGACY,
1869                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1870         }
1871 };
1872
1873 #define for_each_mmc_mode_by_pref(caps, mwt) \
1874         for (mwt = mmc_modes_by_pref;\
1875             mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1876             mwt++) \
1877                 if (caps & MMC_CAP(mwt->mode))
1878
1879 static const struct ext_csd_bus_width {
1880         uint cap;
1881         bool is_ddr;
1882         uint ext_csd_bits;
1883 } ext_csd_bus_width[] = {
1884         {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1885         {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1886         {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1887         {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1888         {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1889 };
1890
1891 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1892 static int mmc_select_hs400(struct mmc *mmc)
1893 {
1894         int err;
1895
1896         /* Set timing to HS200 for tuning */
1897         err = mmc_set_card_speed(mmc, MMC_HS_200, false);
1898         if (err)
1899                 return err;
1900
1901         /* configure the bus mode (host) */
1902         mmc_select_mode(mmc, MMC_HS_200);
1903         mmc_set_clock(mmc, mmc->tran_speed, false);
1904
1905         /* execute tuning if needed */
1906         err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1907         if (err) {
1908                 debug("tuning failed\n");
1909                 return err;
1910         }
1911
1912         /* Set back to HS */
1913         mmc_set_card_speed(mmc, MMC_HS, true);
1914
1915         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1916                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1917         if (err)
1918                 return err;
1919
1920         err = mmc_set_card_speed(mmc, MMC_HS_400, false);
1921         if (err)
1922                 return err;
1923
1924         mmc_select_mode(mmc, MMC_HS_400);
1925         err = mmc_set_clock(mmc, mmc->tran_speed, false);
1926         if (err)
1927                 return err;
1928
1929         return 0;
1930 }
1931 #else
1932 static int mmc_select_hs400(struct mmc *mmc)
1933 {
1934         return -ENOTSUPP;
1935 }
1936 #endif
1937
1938 #define for_each_supported_width(caps, ddr, ecbv) \
1939         for (ecbv = ext_csd_bus_width;\
1940             ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1941             ecbv++) \
1942                 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1943
1944 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
1945 {
1946         int err;
1947         const struct mode_width_tuning *mwt;
1948         const struct ext_csd_bus_width *ecbw;
1949
1950 #ifdef DEBUG
1951         mmc_dump_capabilities("mmc", card_caps);
1952         mmc_dump_capabilities("host", mmc->host_caps);
1953 #endif
1954
1955         /* Restrict card's capabilities by what the host can do */
1956         card_caps &= mmc->host_caps;
1957
1958         /* Only version 4 of MMC supports wider bus widths */
1959         if (mmc->version < MMC_VERSION_4)
1960                 return 0;
1961
1962         if (!mmc->ext_csd) {
1963                 pr_debug("No ext_csd found!\n"); /* this should enver happen */
1964                 return -ENOTSUPP;
1965         }
1966
1967 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
1968     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1969         /*
1970          * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
1971          * before doing anything else, since a transition from either of
1972          * the HS200/HS400 mode directly to legacy mode is not supported.
1973          */
1974         if (mmc->selected_mode == MMC_HS_200 ||
1975             mmc->selected_mode == MMC_HS_400)
1976                 mmc_set_card_speed(mmc, MMC_HS, true);
1977         else
1978 #endif
1979                 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
1980
1981         for_each_mmc_mode_by_pref(card_caps, mwt) {
1982                 for_each_supported_width(card_caps & mwt->widths,
1983                                          mmc_is_mode_ddr(mwt->mode), ecbw) {
1984                         enum mmc_voltage old_voltage;
1985                         pr_debug("trying mode %s width %d (at %d MHz)\n",
1986                                  mmc_mode_name(mwt->mode),
1987                                  bus_width(ecbw->cap),
1988                                  mmc_mode2freq(mmc, mwt->mode) / 1000000);
1989                         old_voltage = mmc->signal_voltage;
1990                         err = mmc_set_lowest_voltage(mmc, mwt->mode,
1991                                                      MMC_ALL_SIGNAL_VOLTAGE);
1992                         if (err)
1993                                 continue;
1994
1995                         /* configure the bus width (card + host) */
1996                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1997                                     EXT_CSD_BUS_WIDTH,
1998                                     ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1999                         if (err)
2000                                 goto error;
2001                         mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2002
2003                         if (mwt->mode == MMC_HS_400) {
2004                                 err = mmc_select_hs400(mmc);
2005                                 if (err) {
2006                                         printf("Select HS400 failed %d\n", err);
2007                                         goto error;
2008                                 }
2009                         } else {
2010                                 /* configure the bus speed (card) */
2011                                 err = mmc_set_card_speed(mmc, mwt->mode, false);
2012                                 if (err)
2013                                         goto error;
2014
2015                                 /*
2016                                  * configure the bus width AND the ddr mode
2017                                  * (card). The host side will be taken care
2018                                  * of in the next step
2019                                  */
2020                                 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2021                                         err = mmc_switch(mmc,
2022                                                          EXT_CSD_CMD_SET_NORMAL,
2023                                                          EXT_CSD_BUS_WIDTH,
2024                                                          ecbw->ext_csd_bits);
2025                                         if (err)
2026                                                 goto error;
2027                                 }
2028
2029                                 /* configure the bus mode (host) */
2030                                 mmc_select_mode(mmc, mwt->mode);
2031                                 mmc_set_clock(mmc, mmc->tran_speed,
2032                                               MMC_CLK_ENABLE);
2033 #ifdef MMC_SUPPORTS_TUNING
2034
2035                                 /* execute tuning if needed */
2036                                 if (mwt->tuning) {
2037                                         err = mmc_execute_tuning(mmc,
2038                                                                  mwt->tuning);
2039                                         if (err) {
2040                                                 pr_debug("tuning failed\n");
2041                                                 goto error;
2042                                         }
2043                                 }
2044 #endif
2045                         }
2046
2047                         /* do a transfer to check the configuration */
2048                         err = mmc_read_and_compare_ext_csd(mmc);
2049                         if (!err)
2050                                 return 0;
2051 error:
2052                         mmc_set_signal_voltage(mmc, old_voltage);
2053                         /* if an error occured, revert to a safer bus mode */
2054                         mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2055                                    EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2056                         mmc_select_mode(mmc, MMC_LEGACY);
2057                         mmc_set_bus_width(mmc, 1);
2058                 }
2059         }
2060
2061         pr_err("unable to select a mode\n");
2062
2063         return -ENOTSUPP;
2064 }
2065 #endif
2066
2067 #if CONFIG_IS_ENABLED(MMC_TINY)
2068 DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2069 #endif
2070
2071 static int mmc_startup_v4(struct mmc *mmc)
2072 {
2073         int err, i;
2074         u64 capacity;
2075         bool has_parts = false;
2076         bool part_completed;
2077         static const u32 mmc_versions[] = {
2078                 MMC_VERSION_4,
2079                 MMC_VERSION_4_1,
2080                 MMC_VERSION_4_2,
2081                 MMC_VERSION_4_3,
2082                 MMC_VERSION_4_4,
2083                 MMC_VERSION_4_41,
2084                 MMC_VERSION_4_5,
2085                 MMC_VERSION_5_0,
2086                 MMC_VERSION_5_1
2087         };
2088
2089 #if CONFIG_IS_ENABLED(MMC_TINY)
2090         u8 *ext_csd = ext_csd_bkup;
2091
2092         if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2093                 return 0;
2094
2095         if (!mmc->ext_csd)
2096                 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2097
2098         err = mmc_send_ext_csd(mmc, ext_csd);
2099         if (err)
2100                 goto error;
2101
2102         /* store the ext csd for future reference */
2103         if (!mmc->ext_csd)
2104                 mmc->ext_csd = ext_csd;
2105 #else
2106         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2107
2108         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2109                 return 0;
2110
2111         /* check  ext_csd version and capacity */
2112         err = mmc_send_ext_csd(mmc, ext_csd);
2113         if (err)
2114                 goto error;
2115
2116         /* store the ext csd for future reference */
2117         if (!mmc->ext_csd)
2118                 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2119         if (!mmc->ext_csd)
2120                 return -ENOMEM;
2121         memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2122 #endif
2123         if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2124                 return -EINVAL;
2125
2126         mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2127
2128         if (mmc->version >= MMC_VERSION_4_2) {
2129                 /*
2130                  * According to the JEDEC Standard, the value of
2131                  * ext_csd's capacity is valid if the value is more
2132                  * than 2GB
2133                  */
2134                 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2135                                 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2136                                 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2137                                 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2138                 capacity *= MMC_MAX_BLOCK_LEN;
2139                 if ((capacity >> 20) > 2 * 1024)
2140                         mmc->capacity_user = capacity;
2141         }
2142
2143         if (mmc->version >= MMC_VERSION_4_5)
2144                 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2145
2146         /* The partition data may be non-zero but it is only
2147          * effective if PARTITION_SETTING_COMPLETED is set in
2148          * EXT_CSD, so ignore any data if this bit is not set,
2149          * except for enabling the high-capacity group size
2150          * definition (see below).
2151          */
2152         part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2153                             EXT_CSD_PARTITION_SETTING_COMPLETED);
2154
2155         /* store the partition info of emmc */
2156         mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2157         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2158             ext_csd[EXT_CSD_BOOT_MULT])
2159                 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2160         if (part_completed &&
2161             (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2162                 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2163
2164         mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2165
2166         mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2167
2168         for (i = 0; i < 4; i++) {
2169                 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2170                 uint mult = (ext_csd[idx + 2] << 16) +
2171                         (ext_csd[idx + 1] << 8) + ext_csd[idx];
2172                 if (mult)
2173                         has_parts = true;
2174                 if (!part_completed)
2175                         continue;
2176                 mmc->capacity_gp[i] = mult;
2177                 mmc->capacity_gp[i] *=
2178                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2179                 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2180                 mmc->capacity_gp[i] <<= 19;
2181         }
2182
2183 #ifndef CONFIG_SPL_BUILD
2184         if (part_completed) {
2185                 mmc->enh_user_size =
2186                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2187                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2188                         ext_csd[EXT_CSD_ENH_SIZE_MULT];
2189                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2190                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2191                 mmc->enh_user_size <<= 19;
2192                 mmc->enh_user_start =
2193                         (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2194                         (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2195                         (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2196                         ext_csd[EXT_CSD_ENH_START_ADDR];
2197                 if (mmc->high_capacity)
2198                         mmc->enh_user_start <<= 9;
2199         }
2200 #endif
2201
2202         /*
2203          * Host needs to enable ERASE_GRP_DEF bit if device is
2204          * partitioned. This bit will be lost every time after a reset
2205          * or power off. This will affect erase size.
2206          */
2207         if (part_completed)
2208                 has_parts = true;
2209         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2210             (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2211                 has_parts = true;
2212         if (has_parts) {
2213                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2214                                  EXT_CSD_ERASE_GROUP_DEF, 1);
2215
2216                 if (err)
2217                         goto error;
2218
2219                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2220         }
2221
2222         if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2223 #if CONFIG_IS_ENABLED(MMC_WRITE)
2224                 /* Read out group size from ext_csd */
2225                 mmc->erase_grp_size =
2226                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2227 #endif
2228                 /*
2229                  * if high capacity and partition setting completed
2230                  * SEC_COUNT is valid even if it is smaller than 2 GiB
2231                  * JEDEC Standard JESD84-B45, 6.2.4
2232                  */
2233                 if (mmc->high_capacity && part_completed) {
2234                         capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2235                                 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2236                                 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2237                                 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2238                         capacity *= MMC_MAX_BLOCK_LEN;
2239                         mmc->capacity_user = capacity;
2240                 }
2241         }
2242 #if CONFIG_IS_ENABLED(MMC_WRITE)
2243         else {
2244                 /* Calculate the group size from the csd value. */
2245                 int erase_gsz, erase_gmul;
2246
2247                 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2248                 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2249                 mmc->erase_grp_size = (erase_gsz + 1)
2250                         * (erase_gmul + 1);
2251         }
2252 #endif
2253 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2254         mmc->hc_wp_grp_size = 1024
2255                 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2256                 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2257 #endif
2258
2259         mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2260
2261         return 0;
2262 error:
2263         if (mmc->ext_csd) {
2264 #if !CONFIG_IS_ENABLED(MMC_TINY)
2265                 free(mmc->ext_csd);
2266 #endif
2267                 mmc->ext_csd = NULL;
2268         }
2269         return err;
2270 }
2271
2272 static int mmc_startup(struct mmc *mmc)
2273 {
2274         int err, i;
2275         uint mult, freq;
2276         u64 cmult, csize;
2277         struct mmc_cmd cmd;
2278         struct blk_desc *bdesc;
2279
2280 #ifdef CONFIG_MMC_SPI_CRC_ON
2281         if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2282                 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2283                 cmd.resp_type = MMC_RSP_R1;
2284                 cmd.cmdarg = 1;
2285                 err = mmc_send_cmd(mmc, &cmd, NULL);
2286                 if (err)
2287                         return err;
2288         }
2289 #endif
2290
2291         /* Put the Card in Identify Mode */
2292         cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2293                 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2294         cmd.resp_type = MMC_RSP_R2;
2295         cmd.cmdarg = 0;
2296
2297         err = mmc_send_cmd(mmc, &cmd, NULL);
2298
2299 #ifdef CONFIG_MMC_QUIRKS
2300         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2301                 int retries = 4;
2302                 /*
2303                  * It has been seen that SEND_CID may fail on the first
2304                  * attempt, let's try a few more time
2305                  */
2306                 do {
2307                         err = mmc_send_cmd(mmc, &cmd, NULL);
2308                         if (!err)
2309                                 break;
2310                 } while (retries--);
2311         }
2312 #endif
2313
2314         if (err)
2315                 return err;
2316
2317         memcpy(mmc->cid, cmd.response, 16);
2318
2319         /*
2320          * For MMC cards, set the Relative Address.
2321          * For SD cards, get the Relatvie Address.
2322          * This also puts the cards into Standby State
2323          */
2324         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2325                 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2326                 cmd.cmdarg = mmc->rca << 16;
2327                 cmd.resp_type = MMC_RSP_R6;
2328
2329                 err = mmc_send_cmd(mmc, &cmd, NULL);
2330
2331                 if (err)
2332                         return err;
2333
2334                 if (IS_SD(mmc))
2335                         mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2336         }
2337
2338         /* Get the Card-Specific Data */
2339         cmd.cmdidx = MMC_CMD_SEND_CSD;
2340         cmd.resp_type = MMC_RSP_R2;
2341         cmd.cmdarg = mmc->rca << 16;
2342
2343         err = mmc_send_cmd(mmc, &cmd, NULL);
2344
2345         if (err)
2346                 return err;
2347
2348         mmc->csd[0] = cmd.response[0];
2349         mmc->csd[1] = cmd.response[1];
2350         mmc->csd[2] = cmd.response[2];
2351         mmc->csd[3] = cmd.response[3];
2352
2353         if (mmc->version == MMC_VERSION_UNKNOWN) {
2354                 int version = (cmd.response[0] >> 26) & 0xf;
2355
2356                 switch (version) {
2357                 case 0:
2358                         mmc->version = MMC_VERSION_1_2;
2359                         break;
2360                 case 1:
2361                         mmc->version = MMC_VERSION_1_4;
2362                         break;
2363                 case 2:
2364                         mmc->version = MMC_VERSION_2_2;
2365                         break;
2366                 case 3:
2367                         mmc->version = MMC_VERSION_3;
2368                         break;
2369                 case 4:
2370                         mmc->version = MMC_VERSION_4;
2371                         break;
2372                 default:
2373                         mmc->version = MMC_VERSION_1_2;
2374                         break;
2375                 }
2376         }
2377
2378         /* divide frequency by 10, since the mults are 10x bigger */
2379         freq = fbase[(cmd.response[0] & 0x7)];
2380         mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2381
2382         mmc->legacy_speed = freq * mult;
2383         mmc_select_mode(mmc, MMC_LEGACY);
2384
2385         mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2386         mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2387 #if CONFIG_IS_ENABLED(MMC_WRITE)
2388
2389         if (IS_SD(mmc))
2390                 mmc->write_bl_len = mmc->read_bl_len;
2391         else
2392                 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2393 #endif
2394
2395         if (mmc->high_capacity) {
2396                 csize = (mmc->csd[1] & 0x3f) << 16
2397                         | (mmc->csd[2] & 0xffff0000) >> 16;
2398                 cmult = 8;
2399         } else {
2400                 csize = (mmc->csd[1] & 0x3ff) << 2
2401                         | (mmc->csd[2] & 0xc0000000) >> 30;
2402                 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2403         }
2404
2405         mmc->capacity_user = (csize + 1) << (cmult + 2);
2406         mmc->capacity_user *= mmc->read_bl_len;
2407         mmc->capacity_boot = 0;
2408         mmc->capacity_rpmb = 0;
2409         for (i = 0; i < 4; i++)
2410                 mmc->capacity_gp[i] = 0;
2411
2412         if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2413                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2414
2415 #if CONFIG_IS_ENABLED(MMC_WRITE)
2416         if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2417                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2418 #endif
2419
2420         if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2421                 cmd.cmdidx = MMC_CMD_SET_DSR;
2422                 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2423                 cmd.resp_type = MMC_RSP_NONE;
2424                 if (mmc_send_cmd(mmc, &cmd, NULL))
2425                         pr_warn("MMC: SET_DSR failed\n");
2426         }
2427
2428         /* Select the card, and put it into Transfer Mode */
2429         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2430                 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2431                 cmd.resp_type = MMC_RSP_R1;
2432                 cmd.cmdarg = mmc->rca << 16;
2433                 err = mmc_send_cmd(mmc, &cmd, NULL);
2434
2435                 if (err)
2436                         return err;
2437         }
2438
2439         /*
2440          * For SD, its erase group is always one sector
2441          */
2442 #if CONFIG_IS_ENABLED(MMC_WRITE)
2443         mmc->erase_grp_size = 1;
2444 #endif
2445         mmc->part_config = MMCPART_NOAVAILABLE;
2446
2447         err = mmc_startup_v4(mmc);
2448         if (err)
2449                 return err;
2450
2451         err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2452         if (err)
2453                 return err;
2454
2455 #if CONFIG_IS_ENABLED(MMC_TINY)
2456         mmc_set_clock(mmc, mmc->legacy_speed, false);
2457         mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2458         mmc_set_bus_width(mmc, 1);
2459 #else
2460         if (IS_SD(mmc)) {
2461                 err = sd_get_capabilities(mmc);
2462                 if (err)
2463                         return err;
2464                 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2465         } else {
2466                 err = mmc_get_capabilities(mmc);
2467                 if (err)
2468                         return err;
2469                 mmc_select_mode_and_width(mmc, mmc->card_caps);
2470         }
2471 #endif
2472         if (err)
2473                 return err;
2474
2475         mmc->best_mode = mmc->selected_mode;
2476
2477         /* Fix the block length for DDR mode */
2478         if (mmc->ddr_mode) {
2479                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2480 #if CONFIG_IS_ENABLED(MMC_WRITE)
2481                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2482 #endif
2483         }
2484
2485         /* fill in device description */
2486         bdesc = mmc_get_blk_desc(mmc);
2487         bdesc->lun = 0;
2488         bdesc->hwpart = 0;
2489         bdesc->type = 0;
2490         bdesc->blksz = mmc->read_bl_len;
2491         bdesc->log2blksz = LOG2(bdesc->blksz);
2492         bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2493 #if !defined(CONFIG_SPL_BUILD) || \
2494                 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2495                 !defined(CONFIG_USE_TINY_PRINTF))
2496         sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2497                 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2498                 (mmc->cid[3] >> 16) & 0xffff);
2499         sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2500                 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2501                 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2502                 (mmc->cid[2] >> 24) & 0xff);
2503         sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2504                 (mmc->cid[2] >> 16) & 0xf);
2505 #else
2506         bdesc->vendor[0] = 0;
2507         bdesc->product[0] = 0;
2508         bdesc->revision[0] = 0;
2509 #endif
2510
2511 #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2512         part_init(bdesc);
2513 #endif
2514
2515         return 0;
2516 }
2517
2518 static int mmc_send_if_cond(struct mmc *mmc)
2519 {
2520         struct mmc_cmd cmd;
2521         int err;
2522
2523         cmd.cmdidx = SD_CMD_SEND_IF_COND;
2524         /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2525         cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2526         cmd.resp_type = MMC_RSP_R7;
2527
2528         err = mmc_send_cmd(mmc, &cmd, NULL);
2529
2530         if (err)
2531                 return err;
2532
2533         if ((cmd.response[0] & 0xff) != 0xaa)
2534                 return -EOPNOTSUPP;
2535         else
2536                 mmc->version = SD_VERSION_2;
2537
2538         return 0;
2539 }
2540
2541 #if !CONFIG_IS_ENABLED(DM_MMC)
2542 /* board-specific MMC power initializations. */
2543 __weak void board_mmc_power_init(void)
2544 {
2545 }
2546 #endif
2547
2548 static int mmc_power_init(struct mmc *mmc)
2549 {
2550 #if CONFIG_IS_ENABLED(DM_MMC)
2551 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2552         int ret;
2553
2554         ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2555                                           &mmc->vmmc_supply);
2556         if (ret)
2557                 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2558
2559         ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2560                                           &mmc->vqmmc_supply);
2561         if (ret)
2562                 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2563 #endif
2564 #else /* !CONFIG_DM_MMC */
2565         /*
2566          * Driver model should use a regulator, as above, rather than calling
2567          * out to board code.
2568          */
2569         board_mmc_power_init();
2570 #endif
2571         return 0;
2572 }
2573
2574 /*
2575  * put the host in the initial state:
2576  * - turn on Vdd (card power supply)
2577  * - configure the bus width and clock to minimal values
2578  */
2579 static void mmc_set_initial_state(struct mmc *mmc)
2580 {
2581         int err;
2582
2583         /* First try to set 3.3V. If it fails set to 1.8V */
2584         err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2585         if (err != 0)
2586                 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2587         if (err != 0)
2588                 pr_warn("mmc: failed to set signal voltage\n");
2589
2590         mmc_select_mode(mmc, MMC_LEGACY);
2591         mmc_set_bus_width(mmc, 1);
2592         mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2593 }
2594
2595 static int mmc_power_on(struct mmc *mmc)
2596 {
2597 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2598         if (mmc->vmmc_supply) {
2599                 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2600
2601                 if (ret) {
2602                         puts("Error enabling VMMC supply\n");
2603                         return ret;
2604                 }
2605         }
2606 #endif
2607         return 0;
2608 }
2609
2610 static int mmc_power_off(struct mmc *mmc)
2611 {
2612         mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
2613 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2614         if (mmc->vmmc_supply) {
2615                 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2616
2617                 if (ret) {
2618                         pr_debug("Error disabling VMMC supply\n");
2619                         return ret;
2620                 }
2621         }
2622 #endif
2623         return 0;
2624 }
2625
2626 static int mmc_power_cycle(struct mmc *mmc)
2627 {
2628         int ret;
2629
2630         ret = mmc_power_off(mmc);
2631         if (ret)
2632                 return ret;
2633         /*
2634          * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2635          * to be on the safer side.
2636          */
2637         udelay(2000);
2638         return mmc_power_on(mmc);
2639 }
2640
2641 int mmc_get_op_cond(struct mmc *mmc)
2642 {
2643         bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2644         int err;
2645
2646         if (mmc->has_init)
2647                 return 0;
2648
2649 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2650         mmc_adapter_card_type_ident();
2651 #endif
2652         err = mmc_power_init(mmc);
2653         if (err)
2654                 return err;
2655
2656 #ifdef CONFIG_MMC_QUIRKS
2657         mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2658                       MMC_QUIRK_RETRY_SEND_CID;
2659 #endif
2660
2661         err = mmc_power_cycle(mmc);
2662         if (err) {
2663                 /*
2664                  * if power cycling is not supported, we should not try
2665                  * to use the UHS modes, because we wouldn't be able to
2666                  * recover from an error during the UHS initialization.
2667                  */
2668                 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2669                 uhs_en = false;
2670                 mmc->host_caps &= ~UHS_CAPS;
2671                 err = mmc_power_on(mmc);
2672         }
2673         if (err)
2674                 return err;
2675
2676 #if CONFIG_IS_ENABLED(DM_MMC)
2677         /* The device has already been probed ready for use */
2678 #else
2679         /* made sure it's not NULL earlier */
2680         err = mmc->cfg->ops->init(mmc);
2681         if (err)
2682                 return err;
2683 #endif
2684         mmc->ddr_mode = 0;
2685
2686 retry:
2687         mmc_set_initial_state(mmc);
2688
2689         /* Reset the Card */
2690         err = mmc_go_idle(mmc);
2691
2692         if (err)
2693                 return err;
2694
2695         /* The internal partition reset to user partition(0) at every CMD0*/
2696         mmc_get_blk_desc(mmc)->hwpart = 0;
2697
2698         /* Test for SD version 2 */
2699         err = mmc_send_if_cond(mmc);
2700
2701         /* Now try to get the SD card's operating condition */
2702         err = sd_send_op_cond(mmc, uhs_en);
2703         if (err && uhs_en) {
2704                 uhs_en = false;
2705                 mmc_power_cycle(mmc);
2706                 goto retry;
2707         }
2708
2709         /* If the command timed out, we check for an MMC card */
2710         if (err == -ETIMEDOUT) {
2711                 err = mmc_send_op_cond(mmc);
2712
2713                 if (err) {
2714 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2715                         pr_err("Card did not respond to voltage select!\n");
2716 #endif
2717                         return -EOPNOTSUPP;
2718                 }
2719         }
2720
2721         return err;
2722 }
2723
2724 int mmc_start_init(struct mmc *mmc)
2725 {
2726         bool no_card;
2727         int err = 0;
2728
2729         /*
2730          * all hosts are capable of 1 bit bus-width and able to use the legacy
2731          * timings.
2732          */
2733         mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2734                          MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2735
2736 #if !defined(CONFIG_MMC_BROKEN_CD)
2737         /* we pretend there's no card when init is NULL */
2738         no_card = mmc_getcd(mmc) == 0;
2739 #else
2740         no_card = 0;
2741 #endif
2742 #if !CONFIG_IS_ENABLED(DM_MMC)
2743         no_card = no_card || (mmc->cfg->ops->init == NULL);
2744 #endif
2745         if (no_card) {
2746                 mmc->has_init = 0;
2747 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2748                 pr_err("MMC: no card present\n");
2749 #endif
2750                 return -ENOMEDIUM;
2751         }
2752
2753         err = mmc_get_op_cond(mmc);
2754
2755         if (!err)
2756                 mmc->init_in_progress = 1;
2757
2758         return err;
2759 }
2760
2761 static int mmc_complete_init(struct mmc *mmc)
2762 {
2763         int err = 0;
2764
2765         mmc->init_in_progress = 0;
2766         if (mmc->op_cond_pending)
2767                 err = mmc_complete_op_cond(mmc);
2768
2769         if (!err)
2770                 err = mmc_startup(mmc);
2771         if (err)
2772                 mmc->has_init = 0;
2773         else
2774                 mmc->has_init = 1;
2775         return err;
2776 }
2777
2778 int mmc_init(struct mmc *mmc)
2779 {
2780         int err = 0;
2781         __maybe_unused ulong start;
2782 #if CONFIG_IS_ENABLED(DM_MMC)
2783         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2784
2785         upriv->mmc = mmc;
2786 #endif
2787         if (mmc->has_init)
2788                 return 0;
2789
2790         start = get_timer(0);
2791
2792         if (!mmc->init_in_progress)
2793                 err = mmc_start_init(mmc);
2794
2795         if (!err)
2796                 err = mmc_complete_init(mmc);
2797         if (err)
2798                 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2799
2800         return err;
2801 }
2802
2803 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2804     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2805     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2806 int mmc_deinit(struct mmc *mmc)
2807 {
2808         u32 caps_filtered;
2809
2810         if (!mmc->has_init)
2811                 return 0;
2812
2813         if (IS_SD(mmc)) {
2814                 caps_filtered = mmc->card_caps &
2815                         ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2816                           MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2817                           MMC_CAP(UHS_SDR104));
2818
2819                 return sd_select_mode_and_width(mmc, caps_filtered);
2820         } else {
2821                 caps_filtered = mmc->card_caps &
2822                         ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2823
2824                 return mmc_select_mode_and_width(mmc, caps_filtered);
2825         }
2826 }
2827 #endif
2828
2829 int mmc_set_dsr(struct mmc *mmc, u16 val)
2830 {
2831         mmc->dsr = val;
2832         return 0;
2833 }
2834
2835 /* CPU-specific MMC initializations */
2836 __weak int cpu_mmc_init(bd_t *bis)
2837 {
2838         return -1;
2839 }
2840
2841 /* board-specific MMC initializations. */
2842 __weak int board_mmc_init(bd_t *bis)
2843 {
2844         return -1;
2845 }
2846
2847 void mmc_set_preinit(struct mmc *mmc, int preinit)
2848 {
2849         mmc->preinit = preinit;
2850 }
2851
2852 #if CONFIG_IS_ENABLED(DM_MMC)
2853 static int mmc_probe(bd_t *bis)
2854 {
2855         int ret, i;
2856         struct uclass *uc;
2857         struct udevice *dev;
2858
2859         ret = uclass_get(UCLASS_MMC, &uc);
2860         if (ret)
2861                 return ret;
2862
2863         /*
2864          * Try to add them in sequence order. Really with driver model we
2865          * should allow holes, but the current MMC list does not allow that.
2866          * So if we request 0, 1, 3 we will get 0, 1, 2.
2867          */
2868         for (i = 0; ; i++) {
2869                 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2870                 if (ret == -ENODEV)
2871                         break;
2872         }
2873         uclass_foreach_dev(dev, uc) {
2874                 ret = device_probe(dev);
2875                 if (ret)
2876                         pr_err("%s - probe failed: %d\n", dev->name, ret);
2877         }
2878
2879         return 0;
2880 }
2881 #else
2882 static int mmc_probe(bd_t *bis)
2883 {
2884         if (board_mmc_init(bis) < 0)
2885                 cpu_mmc_init(bis);
2886
2887         return 0;
2888 }
2889 #endif
2890
2891 int mmc_initialize(bd_t *bis)
2892 {
2893         static int initialized = 0;
2894         int ret;
2895         if (initialized)        /* Avoid initializing mmc multiple times */
2896                 return 0;
2897         initialized = 1;
2898
2899 #if !CONFIG_IS_ENABLED(BLK)
2900 #if !CONFIG_IS_ENABLED(MMC_TINY)
2901         mmc_list_init();
2902 #endif
2903 #endif
2904         ret = mmc_probe(bis);
2905         if (ret)
2906                 return ret;
2907
2908 #ifndef CONFIG_SPL_BUILD
2909         print_mmc_devices(',');
2910 #endif
2911
2912         mmc_do_preinit();
2913         return 0;
2914 }
2915
2916 #ifdef CONFIG_CMD_BKOPS_ENABLE
2917 int mmc_set_bkops_enable(struct mmc *mmc)
2918 {
2919         int err;
2920         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2921
2922         err = mmc_send_ext_csd(mmc, ext_csd);
2923         if (err) {
2924                 puts("Could not get ext_csd register values\n");
2925                 return err;
2926         }
2927
2928         if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2929                 puts("Background operations not supported on device\n");
2930                 return -EMEDIUMTYPE;
2931         }
2932
2933         if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2934                 puts("Background operations already enabled\n");
2935                 return 0;
2936         }
2937
2938         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2939         if (err) {
2940                 puts("Failed to enable manual background operations\n");
2941                 return err;
2942         }
2943
2944         puts("Enabled manual background operations\n");
2945
2946         return 0;
2947 }
2948 #endif