2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
33 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
35 #if CONFIG_IS_ENABLED(MMC_TINY)
36 static struct mmc mmc_static;
37 struct mmc *find_mmc_device(int dev_num)
42 void mmc_do_preinit(void)
44 struct mmc *m = &mmc_static;
45 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
46 mmc_set_preinit(m, 1);
52 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
54 return &mmc->block_dev;
58 #if !CONFIG_IS_ENABLED(DM_MMC)
59 __weak int board_mmc_getwp(struct mmc *mmc)
64 int mmc_getwp(struct mmc *mmc)
68 wp = board_mmc_getwp(mmc);
71 if (mmc->cfg->ops->getwp)
72 wp = mmc->cfg->ops->getwp(mmc);
80 __weak int board_mmc_getcd(struct mmc *mmc)
86 #ifdef CONFIG_MMC_TRACE
87 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
89 printf("CMD_SEND:%d\n", cmd->cmdidx);
90 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
99 printf("\t\tRET\t\t\t %d\n", ret);
101 switch (cmd->resp_type) {
103 printf("\t\tMMC_RSP_NONE\n");
106 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
110 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
114 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
116 printf("\t\t \t\t 0x%08X \n",
118 printf("\t\t \t\t 0x%08X \n",
120 printf("\t\t \t\t 0x%08X \n",
123 printf("\t\t\t\t\tDUMPING DATA\n");
124 for (i = 0; i < 4; i++) {
126 printf("\t\t\t\t\t%03d - ", i*4);
127 ptr = (u8 *)&cmd->response[i];
129 for (j = 0; j < 4; j++)
130 printf("%02X ", *ptr--);
135 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
139 printf("\t\tERROR MMC rsp not supported\n");
145 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
149 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
150 printf("CURR STATE:%d\n", status);
154 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
155 const char *mmc_mode_name(enum bus_mode mode)
157 static const char *const names[] = {
158 [MMC_LEGACY] = "MMC legacy",
159 [SD_LEGACY] = "SD Legacy",
160 [MMC_HS] = "MMC High Speed (26MHz)",
161 [SD_HS] = "SD High Speed (50MHz)",
162 [UHS_SDR12] = "UHS SDR12 (25MHz)",
163 [UHS_SDR25] = "UHS SDR25 (50MHz)",
164 [UHS_SDR50] = "UHS SDR50 (100MHz)",
165 [UHS_SDR104] = "UHS SDR104 (208MHz)",
166 [UHS_DDR50] = "UHS DDR50 (50MHz)",
167 [MMC_HS_52] = "MMC High Speed (52MHz)",
168 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
169 [MMC_HS_200] = "HS200 (200MHz)",
172 if (mode >= MMC_MODES_END)
173 return "Unknown mode";
179 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
181 static const int freqs[] = {
182 [SD_LEGACY] = 25000000,
185 [UHS_SDR12] = 25000000,
186 [UHS_SDR25] = 50000000,
187 [UHS_SDR50] = 100000000,
188 [UHS_SDR104] = 208000000,
189 [UHS_DDR50] = 50000000,
190 [MMC_HS_52] = 52000000,
191 [MMC_DDR_52] = 52000000,
192 [MMC_HS_200] = 200000000,
195 if (mode == MMC_LEGACY)
196 return mmc->legacy_speed;
197 else if (mode >= MMC_MODES_END)
203 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
205 mmc->selected_mode = mode;
206 mmc->tran_speed = mmc_mode2freq(mmc, mode);
207 mmc->ddr_mode = mmc_is_mode_ddr(mode);
208 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
209 mmc->tran_speed / 1000000);
213 #if !CONFIG_IS_ENABLED(DM_MMC)
214 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
218 mmmc_trace_before_send(mmc, cmd);
219 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
220 mmmc_trace_after_send(mmc, cmd, ret);
226 int mmc_send_status(struct mmc *mmc, int timeout)
229 int err, retries = 5;
231 cmd.cmdidx = MMC_CMD_SEND_STATUS;
232 cmd.resp_type = MMC_RSP_R1;
233 if (!mmc_host_is_spi(mmc))
234 cmd.cmdarg = mmc->rca << 16;
237 err = mmc_send_cmd(mmc, &cmd, NULL);
239 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
240 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
244 if (cmd.response[0] & MMC_STATUS_MASK) {
245 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
246 printf("Status Error: 0x%08X\n",
251 } else if (--retries < 0)
260 mmc_trace_state(mmc, &cmd);
262 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
263 printf("Timeout waiting card ready\n");
271 int mmc_set_blocklen(struct mmc *mmc, int len)
278 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
279 cmd.resp_type = MMC_RSP_R1;
282 return mmc_send_cmd(mmc, &cmd, NULL);
285 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
289 struct mmc_data data;
292 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
294 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
296 if (mmc->high_capacity)
299 cmd.cmdarg = start * mmc->read_bl_len;
301 cmd.resp_type = MMC_RSP_R1;
304 data.blocks = blkcnt;
305 data.blocksize = mmc->read_bl_len;
306 data.flags = MMC_DATA_READ;
308 if (mmc_send_cmd(mmc, &cmd, &data))
312 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
314 cmd.resp_type = MMC_RSP_R1b;
315 if (mmc_send_cmd(mmc, &cmd, NULL)) {
316 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
317 printf("mmc fail to send stop cmd\n");
326 #if CONFIG_IS_ENABLED(BLK)
327 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
329 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
333 #if CONFIG_IS_ENABLED(BLK)
334 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
336 int dev_num = block_dev->devnum;
338 lbaint_t cur, blocks_todo = blkcnt;
343 struct mmc *mmc = find_mmc_device(dev_num);
347 if (CONFIG_IS_ENABLED(MMC_TINY))
348 err = mmc_switch_part(mmc, block_dev->hwpart);
350 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
355 if ((start + blkcnt) > block_dev->lba) {
356 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
357 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
358 start + blkcnt, block_dev->lba);
363 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
364 debug("%s: Failed to set blocklen\n", __func__);
369 cur = (blocks_todo > mmc->cfg->b_max) ?
370 mmc->cfg->b_max : blocks_todo;
371 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
372 debug("%s: Failed to read blocks\n", __func__);
377 dst += cur * mmc->read_bl_len;
378 } while (blocks_todo > 0);
383 static int mmc_go_idle(struct mmc *mmc)
390 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
392 cmd.resp_type = MMC_RSP_NONE;
394 err = mmc_send_cmd(mmc, &cmd, NULL);
404 static int sd_send_op_cond(struct mmc *mmc)
411 cmd.cmdidx = MMC_CMD_APP_CMD;
412 cmd.resp_type = MMC_RSP_R1;
415 err = mmc_send_cmd(mmc, &cmd, NULL);
420 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
421 cmd.resp_type = MMC_RSP_R3;
424 * Most cards do not answer if some reserved bits
425 * in the ocr are set. However, Some controller
426 * can set bit 7 (reserved for low voltages), but
427 * how to manage low voltages SD card is not yet
430 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
431 (mmc->cfg->voltages & 0xff8000);
433 if (mmc->version == SD_VERSION_2)
434 cmd.cmdarg |= OCR_HCS;
436 err = mmc_send_cmd(mmc, &cmd, NULL);
441 if (cmd.response[0] & OCR_BUSY)
450 if (mmc->version != SD_VERSION_2)
451 mmc->version = SD_VERSION_1_0;
453 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
454 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
455 cmd.resp_type = MMC_RSP_R3;
458 err = mmc_send_cmd(mmc, &cmd, NULL);
464 mmc->ocr = cmd.response[0];
466 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
472 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
477 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
478 cmd.resp_type = MMC_RSP_R3;
480 if (use_arg && !mmc_host_is_spi(mmc))
481 cmd.cmdarg = OCR_HCS |
482 (mmc->cfg->voltages &
483 (mmc->ocr & OCR_VOLTAGE_MASK)) |
484 (mmc->ocr & OCR_ACCESS_MODE);
486 err = mmc_send_cmd(mmc, &cmd, NULL);
489 mmc->ocr = cmd.response[0];
493 static int mmc_send_op_cond(struct mmc *mmc)
497 /* Some cards seem to need this */
500 /* Asking to the card its capabilities */
501 for (i = 0; i < 2; i++) {
502 err = mmc_send_op_cond_iter(mmc, i != 0);
506 /* exit if not busy (flag seems to be inverted) */
507 if (mmc->ocr & OCR_BUSY)
510 mmc->op_cond_pending = 1;
514 static int mmc_complete_op_cond(struct mmc *mmc)
521 mmc->op_cond_pending = 0;
522 if (!(mmc->ocr & OCR_BUSY)) {
523 /* Some cards seem to need this */
526 start = get_timer(0);
528 err = mmc_send_op_cond_iter(mmc, 1);
531 if (mmc->ocr & OCR_BUSY)
533 if (get_timer(start) > timeout)
539 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
540 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
541 cmd.resp_type = MMC_RSP_R3;
544 err = mmc_send_cmd(mmc, &cmd, NULL);
549 mmc->ocr = cmd.response[0];
552 mmc->version = MMC_VERSION_UNKNOWN;
554 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
561 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
564 struct mmc_data data;
567 /* Get the Card Status Register */
568 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
569 cmd.resp_type = MMC_RSP_R1;
572 data.dest = (char *)ext_csd;
574 data.blocksize = MMC_MAX_BLOCK_LEN;
575 data.flags = MMC_DATA_READ;
577 err = mmc_send_cmd(mmc, &cmd, &data);
582 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
589 cmd.cmdidx = MMC_CMD_SWITCH;
590 cmd.resp_type = MMC_RSP_R1b;
591 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
595 while (retries > 0) {
596 ret = mmc_send_cmd(mmc, &cmd, NULL);
598 /* Waiting for the ready status */
600 ret = mmc_send_status(mmc, timeout);
611 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
616 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
622 speed_bits = EXT_CSD_TIMING_HS;
624 speed_bits = EXT_CSD_TIMING_LEGACY;
629 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
634 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
635 /* Now check to see that it worked */
636 err = mmc_send_ext_csd(mmc, test_csd);
640 /* No high-speed support */
641 if (!test_csd[EXT_CSD_HS_TIMING])
648 static int mmc_get_capabilities(struct mmc *mmc)
650 u8 *ext_csd = mmc->ext_csd;
653 mmc->card_caps = MMC_MODE_1BIT;
655 if (mmc_host_is_spi(mmc))
658 /* Only version 4 supports high-speed */
659 if (mmc->version < MMC_VERSION_4)
663 printf("No ext_csd found!\n"); /* this should enver happen */
667 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
669 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
671 /* High Speed is set, there are two types: 52MHz and 26MHz */
672 if (cardtype & EXT_CSD_CARD_TYPE_52) {
673 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
674 mmc->card_caps |= MMC_MODE_DDR_52MHz;
675 mmc->card_caps |= MMC_MODE_HS_52MHz;
677 if (cardtype & EXT_CSD_CARD_TYPE_26)
678 mmc->card_caps |= MMC_MODE_HS;
683 static int mmc_set_capacity(struct mmc *mmc, int part_num)
687 mmc->capacity = mmc->capacity_user;
691 mmc->capacity = mmc->capacity_boot;
694 mmc->capacity = mmc->capacity_rpmb;
700 mmc->capacity = mmc->capacity_gp[part_num - 4];
706 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
711 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
715 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
716 (mmc->part_config & ~PART_ACCESS_MASK)
717 | (part_num & PART_ACCESS_MASK));
720 * Set the capacity if the switch succeeded or was intended
721 * to return to representing the raw device.
723 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
724 ret = mmc_set_capacity(mmc, part_num);
725 mmc_get_blk_desc(mmc)->hwpart = part_num;
731 int mmc_hwpart_config(struct mmc *mmc,
732 const struct mmc_hwpart_conf *conf,
733 enum mmc_hwpart_conf_mode mode)
739 u32 max_enh_size_mult;
740 u32 tot_enh_size_mult = 0;
743 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
745 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
748 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
749 printf("eMMC >= 4.4 required for enhanced user data area\n");
753 if (!(mmc->part_support & PART_SUPPORT)) {
754 printf("Card does not support partitioning\n");
758 if (!mmc->hc_wp_grp_size) {
759 printf("Card does not define HC WP group size\n");
763 /* check partition alignment and total enhanced size */
764 if (conf->user.enh_size) {
765 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
766 conf->user.enh_start % mmc->hc_wp_grp_size) {
767 printf("User data enhanced area not HC WP group "
771 part_attrs |= EXT_CSD_ENH_USR;
772 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
773 if (mmc->high_capacity) {
774 enh_start_addr = conf->user.enh_start;
776 enh_start_addr = (conf->user.enh_start << 9);
782 tot_enh_size_mult += enh_size_mult;
784 for (pidx = 0; pidx < 4; pidx++) {
785 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
786 printf("GP%i partition not HC WP group size "
787 "aligned\n", pidx+1);
790 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
791 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
792 part_attrs |= EXT_CSD_ENH_GP(pidx);
793 tot_enh_size_mult += gp_size_mult[pidx];
797 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
798 printf("Card does not support enhanced attribute\n");
802 err = mmc_send_ext_csd(mmc, ext_csd);
807 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
808 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
809 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
810 if (tot_enh_size_mult > max_enh_size_mult) {
811 printf("Total enhanced size exceeds maximum (%u > %u)\n",
812 tot_enh_size_mult, max_enh_size_mult);
816 /* The default value of EXT_CSD_WR_REL_SET is device
817 * dependent, the values can only be changed if the
818 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
819 * changed only once and before partitioning is completed. */
820 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
821 if (conf->user.wr_rel_change) {
822 if (conf->user.wr_rel_set)
823 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
825 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
827 for (pidx = 0; pidx < 4; pidx++) {
828 if (conf->gp_part[pidx].wr_rel_change) {
829 if (conf->gp_part[pidx].wr_rel_set)
830 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
832 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
836 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
837 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
838 puts("Card does not support host controlled partition write "
839 "reliability settings\n");
843 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
844 EXT_CSD_PARTITION_SETTING_COMPLETED) {
845 printf("Card already partitioned\n");
849 if (mode == MMC_HWPART_CONF_CHECK)
852 /* Partitioning requires high-capacity size definitions */
853 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
854 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
855 EXT_CSD_ERASE_GROUP_DEF, 1);
860 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
862 /* update erase group size to be high-capacity */
863 mmc->erase_grp_size =
864 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
868 /* all OK, write the configuration */
869 for (i = 0; i < 4; i++) {
870 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
871 EXT_CSD_ENH_START_ADDR+i,
872 (enh_start_addr >> (i*8)) & 0xFF);
876 for (i = 0; i < 3; i++) {
877 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
878 EXT_CSD_ENH_SIZE_MULT+i,
879 (enh_size_mult >> (i*8)) & 0xFF);
883 for (pidx = 0; pidx < 4; pidx++) {
884 for (i = 0; i < 3; i++) {
885 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
886 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
887 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
892 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
893 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
897 if (mode == MMC_HWPART_CONF_SET)
900 /* The WR_REL_SET is a write-once register but shall be
901 * written before setting PART_SETTING_COMPLETED. As it is
902 * write-once we can only write it when completing the
904 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
905 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
906 EXT_CSD_WR_REL_SET, wr_rel_set);
911 /* Setting PART_SETTING_COMPLETED confirms the partition
912 * configuration but it only becomes effective after power
913 * cycle, so we do not adjust the partition related settings
914 * in the mmc struct. */
916 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
917 EXT_CSD_PARTITION_SETTING,
918 EXT_CSD_PARTITION_SETTING_COMPLETED);
925 #if !CONFIG_IS_ENABLED(DM_MMC)
926 int mmc_getcd(struct mmc *mmc)
930 cd = board_mmc_getcd(mmc);
933 if (mmc->cfg->ops->getcd)
934 cd = mmc->cfg->ops->getcd(mmc);
943 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
946 struct mmc_data data;
948 /* Switch the frequency */
949 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
950 cmd.resp_type = MMC_RSP_R1;
951 cmd.cmdarg = (mode << 31) | 0xffffff;
952 cmd.cmdarg &= ~(0xf << (group * 4));
953 cmd.cmdarg |= value << (group * 4);
955 data.dest = (char *)resp;
958 data.flags = MMC_DATA_READ;
960 return mmc_send_cmd(mmc, &cmd, &data);
964 static int sd_get_capabilities(struct mmc *mmc)
968 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
969 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
970 struct mmc_data data;
973 mmc->card_caps = MMC_MODE_1BIT;
975 if (mmc_host_is_spi(mmc))
978 /* Read the SCR to find out if this card supports higher speeds */
979 cmd.cmdidx = MMC_CMD_APP_CMD;
980 cmd.resp_type = MMC_RSP_R1;
981 cmd.cmdarg = mmc->rca << 16;
983 err = mmc_send_cmd(mmc, &cmd, NULL);
988 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
989 cmd.resp_type = MMC_RSP_R1;
995 data.dest = (char *)scr;
998 data.flags = MMC_DATA_READ;
1000 err = mmc_send_cmd(mmc, &cmd, &data);
1009 mmc->scr[0] = __be32_to_cpu(scr[0]);
1010 mmc->scr[1] = __be32_to_cpu(scr[1]);
1012 switch ((mmc->scr[0] >> 24) & 0xf) {
1014 mmc->version = SD_VERSION_1_0;
1017 mmc->version = SD_VERSION_1_10;
1020 mmc->version = SD_VERSION_2;
1021 if ((mmc->scr[0] >> 15) & 0x1)
1022 mmc->version = SD_VERSION_3;
1025 mmc->version = SD_VERSION_1_0;
1029 if (mmc->scr[0] & SD_DATA_4BIT)
1030 mmc->card_caps |= MMC_MODE_4BIT;
1032 /* Version 1.0 doesn't support switching */
1033 if (mmc->version == SD_VERSION_1_0)
1038 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1039 (u8 *)switch_status);
1044 /* The high-speed function is busy. Try again */
1045 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1049 /* If high-speed isn't supported, we return */
1050 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1051 mmc->card_caps |= MMC_CAP(SD_HS);
1056 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1060 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1062 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
1066 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) != 0x01000000)
1072 int sd_select_bus_width(struct mmc *mmc, int w)
1077 if ((w != 4) && (w != 1))
1080 cmd.cmdidx = MMC_CMD_APP_CMD;
1081 cmd.resp_type = MMC_RSP_R1;
1082 cmd.cmdarg = mmc->rca << 16;
1084 err = mmc_send_cmd(mmc, &cmd, NULL);
1088 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1089 cmd.resp_type = MMC_RSP_R1;
1094 err = mmc_send_cmd(mmc, &cmd, NULL);
1101 static int sd_read_ssr(struct mmc *mmc)
1105 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1106 struct mmc_data data;
1108 unsigned int au, eo, et, es;
1110 cmd.cmdidx = MMC_CMD_APP_CMD;
1111 cmd.resp_type = MMC_RSP_R1;
1112 cmd.cmdarg = mmc->rca << 16;
1114 err = mmc_send_cmd(mmc, &cmd, NULL);
1118 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1119 cmd.resp_type = MMC_RSP_R1;
1123 data.dest = (char *)ssr;
1124 data.blocksize = 64;
1126 data.flags = MMC_DATA_READ;
1128 err = mmc_send_cmd(mmc, &cmd, &data);
1136 for (i = 0; i < 16; i++)
1137 ssr[i] = be32_to_cpu(ssr[i]);
1139 au = (ssr[2] >> 12) & 0xF;
1140 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1141 mmc->ssr.au = sd_au_size[au];
1142 es = (ssr[3] >> 24) & 0xFF;
1143 es |= (ssr[2] & 0xFF) << 8;
1144 et = (ssr[3] >> 18) & 0x3F;
1146 eo = (ssr[3] >> 16) & 0x3;
1147 mmc->ssr.erase_timeout = (et * 1000) / es;
1148 mmc->ssr.erase_offset = eo * 1000;
1151 debug("Invalid Allocation Unit Size.\n");
1157 /* frequency bases */
1158 /* divided by 10 to be nice to platforms without floating point */
1159 static const int fbase[] = {
1166 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1167 * to platforms without floating point.
1169 static const u8 multipliers[] = {
1188 static inline int bus_width(uint cap)
1190 if (cap == MMC_MODE_8BIT)
1192 if (cap == MMC_MODE_4BIT)
1194 if (cap == MMC_MODE_1BIT)
1196 printf("invalid bus witdh capability 0x%x\n", cap);
1200 #if !CONFIG_IS_ENABLED(DM_MMC)
1201 static void mmc_send_init_stream(struct mmc *mmc)
1205 static int mmc_set_ios(struct mmc *mmc)
1209 if (mmc->cfg->ops->set_ios)
1210 ret = mmc->cfg->ops->set_ios(mmc);
1216 int mmc_set_clock(struct mmc *mmc, uint clock)
1218 if (clock > mmc->cfg->f_max)
1219 clock = mmc->cfg->f_max;
1221 if (clock < mmc->cfg->f_min)
1222 clock = mmc->cfg->f_min;
1226 return mmc_set_ios(mmc);
1229 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1231 mmc->bus_width = width;
1233 return mmc_set_ios(mmc);
1236 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1238 * helper function to display the capabilities in a human
1239 * friendly manner. The capabilities include bus width and
1242 void mmc_dump_capabilities(const char *text, uint caps)
1246 printf("%s: widths [", text);
1247 if (caps & MMC_MODE_8BIT)
1249 if (caps & MMC_MODE_4BIT)
1251 if (caps & MMC_MODE_1BIT)
1253 printf("\b\b] modes [");
1254 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1255 if (MMC_CAP(mode) & caps)
1256 printf("%s, ", mmc_mode_name(mode));
1261 struct mode_width_tuning {
1266 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1268 mmc->signal_voltage = signal_voltage;
1269 return mmc_set_ios(mmc);
1272 static const struct mode_width_tuning sd_modes_by_pref[] = {
1275 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1279 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1283 #define for_each_sd_mode_by_pref(caps, mwt) \
1284 for (mwt = sd_modes_by_pref;\
1285 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1287 if (caps & MMC_CAP(mwt->mode))
1289 static int sd_select_mode_and_width(struct mmc *mmc)
1292 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1293 const struct mode_width_tuning *mwt;
1295 err = sd_get_capabilities(mmc);
1298 /* Restrict card's capabilities by what the host can do */
1299 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1301 for_each_sd_mode_by_pref(mmc->card_caps, mwt) {
1304 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1305 if (*w & mmc->card_caps & mwt->widths) {
1306 debug("trying mode %s width %d (at %d MHz)\n",
1307 mmc_mode_name(mwt->mode),
1309 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1311 /* configure the bus width (card + host) */
1312 err = sd_select_bus_width(mmc, bus_width(*w));
1315 mmc_set_bus_width(mmc, bus_width(*w));
1317 /* configure the bus mode (card) */
1318 err = sd_set_card_speed(mmc, mwt->mode);
1322 /* configure the bus mode (host) */
1323 mmc_select_mode(mmc, mwt->mode);
1324 mmc_set_clock(mmc, mmc->tran_speed);
1326 err = sd_read_ssr(mmc);
1330 printf("bad ssr\n");
1333 /* revert to a safer bus speed */
1334 mmc_select_mode(mmc, SD_LEGACY);
1335 mmc_set_clock(mmc, mmc->tran_speed);
1340 printf("unable to select a mode\n");
1345 * read the compare the part of ext csd that is constant.
1346 * This can be used to check that the transfer is working
1349 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1352 const u8 *ext_csd = mmc->ext_csd;
1353 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1355 err = mmc_send_ext_csd(mmc, test_csd);
1359 /* Only compare read only fields */
1360 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1361 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1362 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1363 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1364 ext_csd[EXT_CSD_REV]
1365 == test_csd[EXT_CSD_REV] &&
1366 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1367 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1368 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1369 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1375 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1378 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1382 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1386 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1390 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1394 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1398 #define for_each_mmc_mode_by_pref(caps, mwt) \
1399 for (mwt = mmc_modes_by_pref;\
1400 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1402 if (caps & MMC_CAP(mwt->mode))
1404 static const struct ext_csd_bus_width {
1408 } ext_csd_bus_width[] = {
1409 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1410 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1411 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1412 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1413 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1416 #define for_each_supported_width(caps, ddr, ecbv) \
1417 for (ecbv = ext_csd_bus_width;\
1418 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1420 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1422 static int mmc_select_mode_and_width(struct mmc *mmc)
1425 const struct mode_width_tuning *mwt;
1426 const struct ext_csd_bus_width *ecbw;
1428 err = mmc_get_capabilities(mmc);
1432 /* Restrict card's capabilities by what the host can do */
1433 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1435 /* Only version 4 of MMC supports wider bus widths */
1436 if (mmc->version < MMC_VERSION_4)
1439 if (!mmc->ext_csd) {
1440 debug("No ext_csd found!\n"); /* this should enver happen */
1444 for_each_mmc_mode_by_pref(mmc->card_caps, mwt) {
1445 for_each_supported_width(mmc->card_caps & mwt->widths,
1446 mmc_is_mode_ddr(mwt->mode), ecbw) {
1447 debug("trying mode %s width %d (at %d MHz)\n",
1448 mmc_mode_name(mwt->mode),
1449 bus_width(ecbw->cap),
1450 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1451 /* configure the bus width (card + host) */
1452 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1454 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1457 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1459 /* configure the bus speed (card) */
1460 err = mmc_set_card_speed(mmc, mwt->mode);
1465 * configure the bus width AND the ddr mode (card)
1466 * The host side will be taken care of in the next step
1468 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1469 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1471 ecbw->ext_csd_bits);
1476 /* configure the bus mode (host) */
1477 mmc_select_mode(mmc, mwt->mode);
1478 mmc_set_clock(mmc, mmc->tran_speed);
1480 /* do a transfer to check the configuration */
1481 err = mmc_read_and_compare_ext_csd(mmc);
1485 /* if an error occured, revert to a safer bus mode */
1486 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1487 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1488 mmc_select_mode(mmc, MMC_LEGACY);
1489 mmc_set_bus_width(mmc, 1);
1493 printf("unable to select a mode\n");
1498 static int mmc_startup_v4(struct mmc *mmc)
1502 bool has_parts = false;
1503 bool part_completed;
1506 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1509 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1513 mmc->ext_csd = ext_csd;
1515 /* check ext_csd version and capacity */
1516 err = mmc_send_ext_csd(mmc, ext_csd);
1519 if (ext_csd[EXT_CSD_REV] >= 2) {
1521 * According to the JEDEC Standard, the value of
1522 * ext_csd's capacity is valid if the value is more
1525 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1526 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1527 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1528 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1529 capacity *= MMC_MAX_BLOCK_LEN;
1530 if ((capacity >> 20) > 2 * 1024)
1531 mmc->capacity_user = capacity;
1534 switch (ext_csd[EXT_CSD_REV]) {
1536 mmc->version = MMC_VERSION_4_1;
1539 mmc->version = MMC_VERSION_4_2;
1542 mmc->version = MMC_VERSION_4_3;
1545 mmc->version = MMC_VERSION_4_41;
1548 mmc->version = MMC_VERSION_4_5;
1551 mmc->version = MMC_VERSION_5_0;
1554 mmc->version = MMC_VERSION_5_1;
1558 /* The partition data may be non-zero but it is only
1559 * effective if PARTITION_SETTING_COMPLETED is set in
1560 * EXT_CSD, so ignore any data if this bit is not set,
1561 * except for enabling the high-capacity group size
1562 * definition (see below).
1564 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1565 EXT_CSD_PARTITION_SETTING_COMPLETED);
1567 /* store the partition info of emmc */
1568 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1569 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1570 ext_csd[EXT_CSD_BOOT_MULT])
1571 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1572 if (part_completed &&
1573 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1574 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1576 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1578 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1580 for (i = 0; i < 4; i++) {
1581 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1582 uint mult = (ext_csd[idx + 2] << 16) +
1583 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1586 if (!part_completed)
1588 mmc->capacity_gp[i] = mult;
1589 mmc->capacity_gp[i] *=
1590 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1591 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1592 mmc->capacity_gp[i] <<= 19;
1595 if (part_completed) {
1596 mmc->enh_user_size =
1597 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1598 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1599 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1600 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1601 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1602 mmc->enh_user_size <<= 19;
1603 mmc->enh_user_start =
1604 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1605 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1606 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1607 ext_csd[EXT_CSD_ENH_START_ADDR];
1608 if (mmc->high_capacity)
1609 mmc->enh_user_start <<= 9;
1613 * Host needs to enable ERASE_GRP_DEF bit if device is
1614 * partitioned. This bit will be lost every time after a reset
1615 * or power off. This will affect erase size.
1619 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1620 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1623 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1624 EXT_CSD_ERASE_GROUP_DEF, 1);
1629 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1632 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1633 /* Read out group size from ext_csd */
1634 mmc->erase_grp_size =
1635 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1637 * if high capacity and partition setting completed
1638 * SEC_COUNT is valid even if it is smaller than 2 GiB
1639 * JEDEC Standard JESD84-B45, 6.2.4
1641 if (mmc->high_capacity && part_completed) {
1642 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1643 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1644 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1645 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1646 capacity *= MMC_MAX_BLOCK_LEN;
1647 mmc->capacity_user = capacity;
1650 /* Calculate the group size from the csd value. */
1651 int erase_gsz, erase_gmul;
1653 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1654 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1655 mmc->erase_grp_size = (erase_gsz + 1)
1659 mmc->hc_wp_grp_size = 1024
1660 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1661 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1663 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1668 static int mmc_startup(struct mmc *mmc)
1674 struct blk_desc *bdesc;
1676 #ifdef CONFIG_MMC_SPI_CRC_ON
1677 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1678 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1679 cmd.resp_type = MMC_RSP_R1;
1681 err = mmc_send_cmd(mmc, &cmd, NULL);
1688 /* Put the Card in Identify Mode */
1689 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1690 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1691 cmd.resp_type = MMC_RSP_R2;
1694 err = mmc_send_cmd(mmc, &cmd, NULL);
1699 memcpy(mmc->cid, cmd.response, 16);
1702 * For MMC cards, set the Relative Address.
1703 * For SD cards, get the Relatvie Address.
1704 * This also puts the cards into Standby State
1706 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1707 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1708 cmd.cmdarg = mmc->rca << 16;
1709 cmd.resp_type = MMC_RSP_R6;
1711 err = mmc_send_cmd(mmc, &cmd, NULL);
1717 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1720 /* Get the Card-Specific Data */
1721 cmd.cmdidx = MMC_CMD_SEND_CSD;
1722 cmd.resp_type = MMC_RSP_R2;
1723 cmd.cmdarg = mmc->rca << 16;
1725 err = mmc_send_cmd(mmc, &cmd, NULL);
1730 mmc->csd[0] = cmd.response[0];
1731 mmc->csd[1] = cmd.response[1];
1732 mmc->csd[2] = cmd.response[2];
1733 mmc->csd[3] = cmd.response[3];
1735 if (mmc->version == MMC_VERSION_UNKNOWN) {
1736 int version = (cmd.response[0] >> 26) & 0xf;
1740 mmc->version = MMC_VERSION_1_2;
1743 mmc->version = MMC_VERSION_1_4;
1746 mmc->version = MMC_VERSION_2_2;
1749 mmc->version = MMC_VERSION_3;
1752 mmc->version = MMC_VERSION_4;
1755 mmc->version = MMC_VERSION_1_2;
1760 /* divide frequency by 10, since the mults are 10x bigger */
1761 freq = fbase[(cmd.response[0] & 0x7)];
1762 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1764 mmc->legacy_speed = freq * mult;
1765 mmc_select_mode(mmc, MMC_LEGACY);
1767 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1768 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1771 mmc->write_bl_len = mmc->read_bl_len;
1773 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1775 if (mmc->high_capacity) {
1776 csize = (mmc->csd[1] & 0x3f) << 16
1777 | (mmc->csd[2] & 0xffff0000) >> 16;
1780 csize = (mmc->csd[1] & 0x3ff) << 2
1781 | (mmc->csd[2] & 0xc0000000) >> 30;
1782 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1785 mmc->capacity_user = (csize + 1) << (cmult + 2);
1786 mmc->capacity_user *= mmc->read_bl_len;
1787 mmc->capacity_boot = 0;
1788 mmc->capacity_rpmb = 0;
1789 for (i = 0; i < 4; i++)
1790 mmc->capacity_gp[i] = 0;
1792 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1793 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1795 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1796 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1798 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1799 cmd.cmdidx = MMC_CMD_SET_DSR;
1800 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1801 cmd.resp_type = MMC_RSP_NONE;
1802 if (mmc_send_cmd(mmc, &cmd, NULL))
1803 printf("MMC: SET_DSR failed\n");
1806 /* Select the card, and put it into Transfer Mode */
1807 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1808 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1809 cmd.resp_type = MMC_RSP_R1;
1810 cmd.cmdarg = mmc->rca << 16;
1811 err = mmc_send_cmd(mmc, &cmd, NULL);
1818 * For SD, its erase group is always one sector
1820 mmc->erase_grp_size = 1;
1821 mmc->part_config = MMCPART_NOAVAILABLE;
1823 err = mmc_startup_v4(mmc);
1827 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1832 err = sd_select_mode_and_width(mmc);
1834 err = mmc_select_mode_and_width(mmc);
1840 /* Fix the block length for DDR mode */
1841 if (mmc->ddr_mode) {
1842 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1843 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1846 /* fill in device description */
1847 bdesc = mmc_get_blk_desc(mmc);
1851 bdesc->blksz = mmc->read_bl_len;
1852 bdesc->log2blksz = LOG2(bdesc->blksz);
1853 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1854 #if !defined(CONFIG_SPL_BUILD) || \
1855 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1856 !defined(CONFIG_USE_TINY_PRINTF))
1857 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1858 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1859 (mmc->cid[3] >> 16) & 0xffff);
1860 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1861 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1862 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1863 (mmc->cid[2] >> 24) & 0xff);
1864 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1865 (mmc->cid[2] >> 16) & 0xf);
1867 bdesc->vendor[0] = 0;
1868 bdesc->product[0] = 0;
1869 bdesc->revision[0] = 0;
1871 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1878 static int mmc_send_if_cond(struct mmc *mmc)
1883 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1884 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1885 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1886 cmd.resp_type = MMC_RSP_R7;
1888 err = mmc_send_cmd(mmc, &cmd, NULL);
1893 if ((cmd.response[0] & 0xff) != 0xaa)
1896 mmc->version = SD_VERSION_2;
1901 #if !CONFIG_IS_ENABLED(DM_MMC)
1902 /* board-specific MMC power initializations. */
1903 __weak void board_mmc_power_init(void)
1908 static int mmc_power_init(struct mmc *mmc)
1910 #if CONFIG_IS_ENABLED(DM_MMC)
1911 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1914 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
1917 debug("%s: No vmmc supply\n", mmc->dev->name);
1919 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
1920 &mmc->vqmmc_supply);
1922 debug("%s: No vqmmc supply\n", mmc->dev->name);
1924 if (mmc->vmmc_supply) {
1925 ret = regulator_set_enable(mmc->vmmc_supply, true);
1927 puts("Error enabling VMMC supply\n");
1932 #else /* !CONFIG_DM_MMC */
1934 * Driver model should use a regulator, as above, rather than calling
1935 * out to board code.
1937 board_mmc_power_init();
1942 int mmc_start_init(struct mmc *mmc)
1947 /* we pretend there's no card when init is NULL */
1948 no_card = mmc_getcd(mmc) == 0;
1949 #if !CONFIG_IS_ENABLED(DM_MMC)
1950 no_card = no_card || (mmc->cfg->ops->init == NULL);
1954 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1955 printf("MMC: no card present\n");
1963 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1964 mmc_adapter_card_type_ident();
1966 err = mmc_power_init(mmc);
1970 #if CONFIG_IS_ENABLED(DM_MMC)
1971 /* The device has already been probed ready for use */
1973 /* made sure it's not NULL earlier */
1974 err = mmc->cfg->ops->init(mmc);
1980 /* First try to set 3.3V. If it fails set to 1.8V */
1981 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
1983 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
1985 printf("failed to set signal voltage\n");
1987 mmc_set_bus_width(mmc, 1);
1988 mmc_set_clock(mmc, 1);
1990 mmc_send_init_stream(mmc);
1992 /* Reset the Card */
1993 err = mmc_go_idle(mmc);
1998 /* The internal partition reset to user partition(0) at every CMD0*/
1999 mmc_get_blk_desc(mmc)->hwpart = 0;
2001 /* Test for SD version 2 */
2002 err = mmc_send_if_cond(mmc);
2004 /* Now try to get the SD card's operating condition */
2005 err = sd_send_op_cond(mmc);
2007 /* If the command timed out, we check for an MMC card */
2008 if (err == -ETIMEDOUT) {
2009 err = mmc_send_op_cond(mmc);
2012 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2013 printf("Card did not respond to voltage select!\n");
2020 mmc->init_in_progress = 1;
2025 static int mmc_complete_init(struct mmc *mmc)
2029 mmc->init_in_progress = 0;
2030 if (mmc->op_cond_pending)
2031 err = mmc_complete_op_cond(mmc);
2034 err = mmc_startup(mmc);
2042 int mmc_init(struct mmc *mmc)
2045 __maybe_unused unsigned start;
2046 #if CONFIG_IS_ENABLED(DM_MMC)
2047 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2054 start = get_timer(0);
2056 if (!mmc->init_in_progress)
2057 err = mmc_start_init(mmc);
2060 err = mmc_complete_init(mmc);
2062 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2067 int mmc_set_dsr(struct mmc *mmc, u16 val)
2073 /* CPU-specific MMC initializations */
2074 __weak int cpu_mmc_init(bd_t *bis)
2079 /* board-specific MMC initializations. */
2080 __weak int board_mmc_init(bd_t *bis)
2085 void mmc_set_preinit(struct mmc *mmc, int preinit)
2087 mmc->preinit = preinit;
2090 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2091 static int mmc_probe(bd_t *bis)
2095 #elif CONFIG_IS_ENABLED(DM_MMC)
2096 static int mmc_probe(bd_t *bis)
2100 struct udevice *dev;
2102 ret = uclass_get(UCLASS_MMC, &uc);
2107 * Try to add them in sequence order. Really with driver model we
2108 * should allow holes, but the current MMC list does not allow that.
2109 * So if we request 0, 1, 3 we will get 0, 1, 2.
2111 for (i = 0; ; i++) {
2112 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2116 uclass_foreach_dev(dev, uc) {
2117 ret = device_probe(dev);
2119 printf("%s - probe failed: %d\n", dev->name, ret);
2125 static int mmc_probe(bd_t *bis)
2127 if (board_mmc_init(bis) < 0)
2134 int mmc_initialize(bd_t *bis)
2136 static int initialized = 0;
2138 if (initialized) /* Avoid initializing mmc multiple times */
2142 #if !CONFIG_IS_ENABLED(BLK)
2143 #if !CONFIG_IS_ENABLED(MMC_TINY)
2147 ret = mmc_probe(bis);
2151 #ifndef CONFIG_SPL_BUILD
2152 print_mmc_devices(',');
2159 #ifdef CONFIG_CMD_BKOPS_ENABLE
2160 int mmc_set_bkops_enable(struct mmc *mmc)
2163 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2165 err = mmc_send_ext_csd(mmc, ext_csd);
2167 puts("Could not get ext_csd register values\n");
2171 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2172 puts("Background operations not supported on device\n");
2173 return -EMEDIUMTYPE;
2176 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2177 puts("Background operations already enabled\n");
2181 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2183 puts("Failed to enable manual background operations\n");
2187 puts("Enabled manual background operations\n");