2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
33 #if CONFIG_IS_ENABLED(MMC_TINY)
34 static struct mmc mmc_static;
35 struct mmc *find_mmc_device(int dev_num)
40 void mmc_do_preinit(void)
42 struct mmc *m = &mmc_static;
43 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m, 1);
50 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
52 return &mmc->block_dev;
56 #if !CONFIG_IS_ENABLED(DM_MMC)
57 __weak int board_mmc_getwp(struct mmc *mmc)
62 int mmc_getwp(struct mmc *mmc)
66 wp = board_mmc_getwp(mmc);
69 if (mmc->cfg->ops->getwp)
70 wp = mmc->cfg->ops->getwp(mmc);
78 __weak int board_mmc_getcd(struct mmc *mmc)
84 #ifdef CONFIG_MMC_TRACE
85 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
87 printf("CMD_SEND:%d\n", cmd->cmdidx);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
91 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
97 printf("\t\tRET\t\t\t %d\n", ret);
99 switch (cmd->resp_type) {
101 printf("\t\tMMC_RSP_NONE\n");
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
114 printf("\t\t \t\t 0x%08X \n",
116 printf("\t\t \t\t 0x%08X \n",
118 printf("\t\t \t\t 0x%08X \n",
121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i = 0; i < 4; i++) {
124 printf("\t\t\t\t\t%03d - ", i*4);
125 ptr = (u8 *)&cmd->response[i];
127 for (j = 0; j < 4; j++)
128 printf("%02X ", *ptr--);
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
137 printf("\t\tERROR MMC rsp not supported\n");
143 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
147 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
148 printf("CURR STATE:%d\n", status);
152 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
153 const char *mmc_mode_name(enum bus_mode mode)
155 static const char *const names[] = {
156 [MMC_LEGACY] = "MMC legacy",
157 [SD_LEGACY] = "SD Legacy",
158 [MMC_HS] = "MMC High Speed (26MHz)",
159 [SD_HS] = "SD High Speed (50MHz)",
160 [UHS_SDR12] = "UHS SDR12 (25MHz)",
161 [UHS_SDR25] = "UHS SDR25 (50MHz)",
162 [UHS_SDR50] = "UHS SDR50 (100MHz)",
163 [UHS_SDR104] = "UHS SDR104 (208MHz)",
164 [UHS_DDR50] = "UHS DDR50 (50MHz)",
165 [MMC_HS_52] = "MMC High Speed (52MHz)",
166 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
167 [MMC_HS_200] = "HS200 (200MHz)",
170 if (mode >= MMC_MODES_END)
171 return "Unknown mode";
177 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
179 static const int freqs[] = {
180 [SD_LEGACY] = 25000000,
183 [UHS_SDR12] = 25000000,
184 [UHS_SDR25] = 50000000,
185 [UHS_SDR50] = 100000000,
186 [UHS_SDR104] = 208000000,
187 [UHS_DDR50] = 50000000,
188 [MMC_HS_52] = 52000000,
189 [MMC_DDR_52] = 52000000,
190 [MMC_HS_200] = 200000000,
193 if (mode == MMC_LEGACY)
194 return mmc->legacy_speed;
195 else if (mode >= MMC_MODES_END)
201 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
203 mmc->selected_mode = mode;
204 mmc->tran_speed = mmc_mode2freq(mmc, mode);
205 mmc->ddr_mode = mmc_is_mode_ddr(mode);
206 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
207 mmc->tran_speed / 1000000);
211 #if !CONFIG_IS_ENABLED(DM_MMC)
212 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
216 mmmc_trace_before_send(mmc, cmd);
217 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
218 mmmc_trace_after_send(mmc, cmd, ret);
224 int mmc_send_status(struct mmc *mmc, int timeout)
227 int err, retries = 5;
229 cmd.cmdidx = MMC_CMD_SEND_STATUS;
230 cmd.resp_type = MMC_RSP_R1;
231 if (!mmc_host_is_spi(mmc))
232 cmd.cmdarg = mmc->rca << 16;
235 err = mmc_send_cmd(mmc, &cmd, NULL);
237 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
238 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
242 if (cmd.response[0] & MMC_STATUS_MASK) {
243 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
244 printf("Status Error: 0x%08X\n",
249 } else if (--retries < 0)
258 mmc_trace_state(mmc, &cmd);
260 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
261 printf("Timeout waiting card ready\n");
269 int mmc_set_blocklen(struct mmc *mmc, int len)
276 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
277 cmd.resp_type = MMC_RSP_R1;
280 return mmc_send_cmd(mmc, &cmd, NULL);
283 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
287 struct mmc_data data;
290 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
292 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
294 if (mmc->high_capacity)
297 cmd.cmdarg = start * mmc->read_bl_len;
299 cmd.resp_type = MMC_RSP_R1;
302 data.blocks = blkcnt;
303 data.blocksize = mmc->read_bl_len;
304 data.flags = MMC_DATA_READ;
306 if (mmc_send_cmd(mmc, &cmd, &data))
310 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
312 cmd.resp_type = MMC_RSP_R1b;
313 if (mmc_send_cmd(mmc, &cmd, NULL)) {
314 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
315 printf("mmc fail to send stop cmd\n");
324 #if CONFIG_IS_ENABLED(BLK)
325 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
327 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
331 #if CONFIG_IS_ENABLED(BLK)
332 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
334 int dev_num = block_dev->devnum;
336 lbaint_t cur, blocks_todo = blkcnt;
341 struct mmc *mmc = find_mmc_device(dev_num);
345 if (CONFIG_IS_ENABLED(MMC_TINY))
346 err = mmc_switch_part(mmc, block_dev->hwpart);
348 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
353 if ((start + blkcnt) > block_dev->lba) {
354 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
355 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
356 start + blkcnt, block_dev->lba);
361 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
362 debug("%s: Failed to set blocklen\n", __func__);
367 cur = (blocks_todo > mmc->cfg->b_max) ?
368 mmc->cfg->b_max : blocks_todo;
369 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
370 debug("%s: Failed to read blocks\n", __func__);
375 dst += cur * mmc->read_bl_len;
376 } while (blocks_todo > 0);
381 static int mmc_go_idle(struct mmc *mmc)
388 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
390 cmd.resp_type = MMC_RSP_NONE;
392 err = mmc_send_cmd(mmc, &cmd, NULL);
402 static int sd_send_op_cond(struct mmc *mmc)
409 cmd.cmdidx = MMC_CMD_APP_CMD;
410 cmd.resp_type = MMC_RSP_R1;
413 err = mmc_send_cmd(mmc, &cmd, NULL);
418 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
419 cmd.resp_type = MMC_RSP_R3;
422 * Most cards do not answer if some reserved bits
423 * in the ocr are set. However, Some controller
424 * can set bit 7 (reserved for low voltages), but
425 * how to manage low voltages SD card is not yet
428 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
429 (mmc->cfg->voltages & 0xff8000);
431 if (mmc->version == SD_VERSION_2)
432 cmd.cmdarg |= OCR_HCS;
434 err = mmc_send_cmd(mmc, &cmd, NULL);
439 if (cmd.response[0] & OCR_BUSY)
448 if (mmc->version != SD_VERSION_2)
449 mmc->version = SD_VERSION_1_0;
451 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
452 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
453 cmd.resp_type = MMC_RSP_R3;
456 err = mmc_send_cmd(mmc, &cmd, NULL);
462 mmc->ocr = cmd.response[0];
464 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
470 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
475 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
476 cmd.resp_type = MMC_RSP_R3;
478 if (use_arg && !mmc_host_is_spi(mmc))
479 cmd.cmdarg = OCR_HCS |
480 (mmc->cfg->voltages &
481 (mmc->ocr & OCR_VOLTAGE_MASK)) |
482 (mmc->ocr & OCR_ACCESS_MODE);
484 err = mmc_send_cmd(mmc, &cmd, NULL);
487 mmc->ocr = cmd.response[0];
491 static int mmc_send_op_cond(struct mmc *mmc)
495 /* Some cards seem to need this */
498 /* Asking to the card its capabilities */
499 for (i = 0; i < 2; i++) {
500 err = mmc_send_op_cond_iter(mmc, i != 0);
504 /* exit if not busy (flag seems to be inverted) */
505 if (mmc->ocr & OCR_BUSY)
508 mmc->op_cond_pending = 1;
512 static int mmc_complete_op_cond(struct mmc *mmc)
519 mmc->op_cond_pending = 0;
520 if (!(mmc->ocr & OCR_BUSY)) {
521 /* Some cards seem to need this */
524 start = get_timer(0);
526 err = mmc_send_op_cond_iter(mmc, 1);
529 if (mmc->ocr & OCR_BUSY)
531 if (get_timer(start) > timeout)
537 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
538 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
539 cmd.resp_type = MMC_RSP_R3;
542 err = mmc_send_cmd(mmc, &cmd, NULL);
547 mmc->ocr = cmd.response[0];
550 mmc->version = MMC_VERSION_UNKNOWN;
552 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
559 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
562 struct mmc_data data;
565 /* Get the Card Status Register */
566 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
567 cmd.resp_type = MMC_RSP_R1;
570 data.dest = (char *)ext_csd;
572 data.blocksize = MMC_MAX_BLOCK_LEN;
573 data.flags = MMC_DATA_READ;
575 err = mmc_send_cmd(mmc, &cmd, &data);
580 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
587 cmd.cmdidx = MMC_CMD_SWITCH;
588 cmd.resp_type = MMC_RSP_R1b;
589 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
593 while (retries > 0) {
594 ret = mmc_send_cmd(mmc, &cmd, NULL);
596 /* Waiting for the ready status */
598 ret = mmc_send_status(mmc, timeout);
609 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
614 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
620 speed_bits = EXT_CSD_TIMING_HS;
622 speed_bits = EXT_CSD_TIMING_LEGACY;
627 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
632 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
633 /* Now check to see that it worked */
634 err = mmc_send_ext_csd(mmc, test_csd);
638 /* No high-speed support */
639 if (!test_csd[EXT_CSD_HS_TIMING])
646 static int mmc_get_capabilities(struct mmc *mmc)
648 u8 *ext_csd = mmc->ext_csd;
651 mmc->card_caps = MMC_MODE_1BIT;
653 if (mmc_host_is_spi(mmc))
656 /* Only version 4 supports high-speed */
657 if (mmc->version < MMC_VERSION_4)
661 printf("No ext_csd found!\n"); /* this should enver happen */
665 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
667 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
669 /* High Speed is set, there are two types: 52MHz and 26MHz */
670 if (cardtype & EXT_CSD_CARD_TYPE_52) {
671 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
672 mmc->card_caps |= MMC_MODE_DDR_52MHz;
673 mmc->card_caps |= MMC_MODE_HS_52MHz;
675 if (cardtype & EXT_CSD_CARD_TYPE_26)
676 mmc->card_caps |= MMC_MODE_HS;
681 static int mmc_set_capacity(struct mmc *mmc, int part_num)
685 mmc->capacity = mmc->capacity_user;
689 mmc->capacity = mmc->capacity_boot;
692 mmc->capacity = mmc->capacity_rpmb;
698 mmc->capacity = mmc->capacity_gp[part_num - 4];
704 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
709 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
713 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
714 (mmc->part_config & ~PART_ACCESS_MASK)
715 | (part_num & PART_ACCESS_MASK));
718 * Set the capacity if the switch succeeded or was intended
719 * to return to representing the raw device.
721 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
722 ret = mmc_set_capacity(mmc, part_num);
723 mmc_get_blk_desc(mmc)->hwpart = part_num;
729 int mmc_hwpart_config(struct mmc *mmc,
730 const struct mmc_hwpart_conf *conf,
731 enum mmc_hwpart_conf_mode mode)
737 u32 max_enh_size_mult;
738 u32 tot_enh_size_mult = 0;
741 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
743 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
746 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
747 printf("eMMC >= 4.4 required for enhanced user data area\n");
751 if (!(mmc->part_support & PART_SUPPORT)) {
752 printf("Card does not support partitioning\n");
756 if (!mmc->hc_wp_grp_size) {
757 printf("Card does not define HC WP group size\n");
761 /* check partition alignment and total enhanced size */
762 if (conf->user.enh_size) {
763 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
764 conf->user.enh_start % mmc->hc_wp_grp_size) {
765 printf("User data enhanced area not HC WP group "
769 part_attrs |= EXT_CSD_ENH_USR;
770 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
771 if (mmc->high_capacity) {
772 enh_start_addr = conf->user.enh_start;
774 enh_start_addr = (conf->user.enh_start << 9);
780 tot_enh_size_mult += enh_size_mult;
782 for (pidx = 0; pidx < 4; pidx++) {
783 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
784 printf("GP%i partition not HC WP group size "
785 "aligned\n", pidx+1);
788 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
789 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
790 part_attrs |= EXT_CSD_ENH_GP(pidx);
791 tot_enh_size_mult += gp_size_mult[pidx];
795 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
796 printf("Card does not support enhanced attribute\n");
800 err = mmc_send_ext_csd(mmc, ext_csd);
805 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
806 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
807 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
808 if (tot_enh_size_mult > max_enh_size_mult) {
809 printf("Total enhanced size exceeds maximum (%u > %u)\n",
810 tot_enh_size_mult, max_enh_size_mult);
814 /* The default value of EXT_CSD_WR_REL_SET is device
815 * dependent, the values can only be changed if the
816 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
817 * changed only once and before partitioning is completed. */
818 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
819 if (conf->user.wr_rel_change) {
820 if (conf->user.wr_rel_set)
821 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
823 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
825 for (pidx = 0; pidx < 4; pidx++) {
826 if (conf->gp_part[pidx].wr_rel_change) {
827 if (conf->gp_part[pidx].wr_rel_set)
828 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
830 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
834 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
835 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
836 puts("Card does not support host controlled partition write "
837 "reliability settings\n");
841 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
842 EXT_CSD_PARTITION_SETTING_COMPLETED) {
843 printf("Card already partitioned\n");
847 if (mode == MMC_HWPART_CONF_CHECK)
850 /* Partitioning requires high-capacity size definitions */
851 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
852 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
853 EXT_CSD_ERASE_GROUP_DEF, 1);
858 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
860 /* update erase group size to be high-capacity */
861 mmc->erase_grp_size =
862 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
866 /* all OK, write the configuration */
867 for (i = 0; i < 4; i++) {
868 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
869 EXT_CSD_ENH_START_ADDR+i,
870 (enh_start_addr >> (i*8)) & 0xFF);
874 for (i = 0; i < 3; i++) {
875 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
876 EXT_CSD_ENH_SIZE_MULT+i,
877 (enh_size_mult >> (i*8)) & 0xFF);
881 for (pidx = 0; pidx < 4; pidx++) {
882 for (i = 0; i < 3; i++) {
883 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
884 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
885 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
890 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
891 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
895 if (mode == MMC_HWPART_CONF_SET)
898 /* The WR_REL_SET is a write-once register but shall be
899 * written before setting PART_SETTING_COMPLETED. As it is
900 * write-once we can only write it when completing the
902 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
903 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
904 EXT_CSD_WR_REL_SET, wr_rel_set);
909 /* Setting PART_SETTING_COMPLETED confirms the partition
910 * configuration but it only becomes effective after power
911 * cycle, so we do not adjust the partition related settings
912 * in the mmc struct. */
914 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
915 EXT_CSD_PARTITION_SETTING,
916 EXT_CSD_PARTITION_SETTING_COMPLETED);
923 #if !CONFIG_IS_ENABLED(DM_MMC)
924 int mmc_getcd(struct mmc *mmc)
928 cd = board_mmc_getcd(mmc);
931 if (mmc->cfg->ops->getcd)
932 cd = mmc->cfg->ops->getcd(mmc);
941 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
944 struct mmc_data data;
946 /* Switch the frequency */
947 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
948 cmd.resp_type = MMC_RSP_R1;
949 cmd.cmdarg = (mode << 31) | 0xffffff;
950 cmd.cmdarg &= ~(0xf << (group * 4));
951 cmd.cmdarg |= value << (group * 4);
953 data.dest = (char *)resp;
956 data.flags = MMC_DATA_READ;
958 return mmc_send_cmd(mmc, &cmd, &data);
962 static int sd_get_capabilities(struct mmc *mmc)
966 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
967 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
968 struct mmc_data data;
971 mmc->card_caps = MMC_MODE_1BIT;
973 if (mmc_host_is_spi(mmc))
976 /* Read the SCR to find out if this card supports higher speeds */
977 cmd.cmdidx = MMC_CMD_APP_CMD;
978 cmd.resp_type = MMC_RSP_R1;
979 cmd.cmdarg = mmc->rca << 16;
981 err = mmc_send_cmd(mmc, &cmd, NULL);
986 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
987 cmd.resp_type = MMC_RSP_R1;
993 data.dest = (char *)scr;
996 data.flags = MMC_DATA_READ;
998 err = mmc_send_cmd(mmc, &cmd, &data);
1007 mmc->scr[0] = __be32_to_cpu(scr[0]);
1008 mmc->scr[1] = __be32_to_cpu(scr[1]);
1010 switch ((mmc->scr[0] >> 24) & 0xf) {
1012 mmc->version = SD_VERSION_1_0;
1015 mmc->version = SD_VERSION_1_10;
1018 mmc->version = SD_VERSION_2;
1019 if ((mmc->scr[0] >> 15) & 0x1)
1020 mmc->version = SD_VERSION_3;
1023 mmc->version = SD_VERSION_1_0;
1027 if (mmc->scr[0] & SD_DATA_4BIT)
1028 mmc->card_caps |= MMC_MODE_4BIT;
1030 /* Version 1.0 doesn't support switching */
1031 if (mmc->version == SD_VERSION_1_0)
1036 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1037 (u8 *)switch_status);
1042 /* The high-speed function is busy. Try again */
1043 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1047 /* If high-speed isn't supported, we return */
1048 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1049 mmc->card_caps |= MMC_CAP(SD_HS);
1054 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1058 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1060 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
1064 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) != 0x01000000)
1070 int sd_select_bus_width(struct mmc *mmc, int w)
1075 if ((w != 4) && (w != 1))
1078 cmd.cmdidx = MMC_CMD_APP_CMD;
1079 cmd.resp_type = MMC_RSP_R1;
1080 cmd.cmdarg = mmc->rca << 16;
1082 err = mmc_send_cmd(mmc, &cmd, NULL);
1086 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1087 cmd.resp_type = MMC_RSP_R1;
1092 err = mmc_send_cmd(mmc, &cmd, NULL);
1099 static int sd_read_ssr(struct mmc *mmc)
1103 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1104 struct mmc_data data;
1106 unsigned int au, eo, et, es;
1108 cmd.cmdidx = MMC_CMD_APP_CMD;
1109 cmd.resp_type = MMC_RSP_R1;
1110 cmd.cmdarg = mmc->rca << 16;
1112 err = mmc_send_cmd(mmc, &cmd, NULL);
1116 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1117 cmd.resp_type = MMC_RSP_R1;
1121 data.dest = (char *)ssr;
1122 data.blocksize = 64;
1124 data.flags = MMC_DATA_READ;
1126 err = mmc_send_cmd(mmc, &cmd, &data);
1134 for (i = 0; i < 16; i++)
1135 ssr[i] = be32_to_cpu(ssr[i]);
1137 au = (ssr[2] >> 12) & 0xF;
1138 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1139 mmc->ssr.au = sd_au_size[au];
1140 es = (ssr[3] >> 24) & 0xFF;
1141 es |= (ssr[2] & 0xFF) << 8;
1142 et = (ssr[3] >> 18) & 0x3F;
1144 eo = (ssr[3] >> 16) & 0x3;
1145 mmc->ssr.erase_timeout = (et * 1000) / es;
1146 mmc->ssr.erase_offset = eo * 1000;
1149 debug("Invalid Allocation Unit Size.\n");
1155 /* frequency bases */
1156 /* divided by 10 to be nice to platforms without floating point */
1157 static const int fbase[] = {
1164 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1165 * to platforms without floating point.
1167 static const u8 multipliers[] = {
1186 static inline int bus_width(uint cap)
1188 if (cap == MMC_MODE_8BIT)
1190 if (cap == MMC_MODE_4BIT)
1192 if (cap == MMC_MODE_1BIT)
1194 printf("invalid bus witdh capability 0x%x\n", cap);
1198 #if !CONFIG_IS_ENABLED(DM_MMC)
1199 static int mmc_set_ios(struct mmc *mmc)
1203 if (mmc->cfg->ops->set_ios)
1204 ret = mmc->cfg->ops->set_ios(mmc);
1210 int mmc_set_clock(struct mmc *mmc, uint clock)
1212 if (clock > mmc->cfg->f_max)
1213 clock = mmc->cfg->f_max;
1215 if (clock < mmc->cfg->f_min)
1216 clock = mmc->cfg->f_min;
1220 return mmc_set_ios(mmc);
1223 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1225 mmc->bus_width = width;
1227 return mmc_set_ios(mmc);
1230 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1232 * helper function to display the capabilities in a human
1233 * friendly manner. The capabilities include bus width and
1236 void mmc_dump_capabilities(const char *text, uint caps)
1240 printf("%s: widths [", text);
1241 if (caps & MMC_MODE_8BIT)
1243 if (caps & MMC_MODE_4BIT)
1245 if (caps & MMC_MODE_1BIT)
1247 printf("\b\b] modes [");
1248 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1249 if (MMC_CAP(mode) & caps)
1250 printf("%s, ", mmc_mode_name(mode));
1255 struct mode_width_tuning {
1260 static const struct mode_width_tuning sd_modes_by_pref[] = {
1263 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1267 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1271 #define for_each_sd_mode_by_pref(caps, mwt) \
1272 for (mwt = sd_modes_by_pref;\
1273 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1275 if (caps & MMC_CAP(mwt->mode))
1277 static int sd_select_mode_and_width(struct mmc *mmc)
1280 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1281 const struct mode_width_tuning *mwt;
1283 err = sd_get_capabilities(mmc);
1286 /* Restrict card's capabilities by what the host can do */
1287 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1289 for_each_sd_mode_by_pref(mmc->card_caps, mwt) {
1292 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1293 if (*w & mmc->card_caps & mwt->widths) {
1294 debug("trying mode %s width %d (at %d MHz)\n",
1295 mmc_mode_name(mwt->mode),
1297 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1299 /* configure the bus width (card + host) */
1300 err = sd_select_bus_width(mmc, bus_width(*w));
1303 mmc_set_bus_width(mmc, bus_width(*w));
1305 /* configure the bus mode (card) */
1306 err = sd_set_card_speed(mmc, mwt->mode);
1310 /* configure the bus mode (host) */
1311 mmc_select_mode(mmc, mwt->mode);
1312 mmc_set_clock(mmc, mmc->tran_speed);
1314 err = sd_read_ssr(mmc);
1318 printf("bad ssr\n");
1321 /* revert to a safer bus speed */
1322 mmc_select_mode(mmc, SD_LEGACY);
1323 mmc_set_clock(mmc, mmc->tran_speed);
1328 printf("unable to select a mode\n");
1333 * read the compare the part of ext csd that is constant.
1334 * This can be used to check that the transfer is working
1337 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1340 const u8 *ext_csd = mmc->ext_csd;
1341 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1343 err = mmc_send_ext_csd(mmc, test_csd);
1347 /* Only compare read only fields */
1348 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1349 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1350 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1351 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1352 ext_csd[EXT_CSD_REV]
1353 == test_csd[EXT_CSD_REV] &&
1354 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1355 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1356 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1357 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1363 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1366 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1370 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1374 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1378 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1382 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1386 #define for_each_mmc_mode_by_pref(caps, mwt) \
1387 for (mwt = mmc_modes_by_pref;\
1388 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1390 if (caps & MMC_CAP(mwt->mode))
1392 static const struct ext_csd_bus_width {
1396 } ext_csd_bus_width[] = {
1397 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1398 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1399 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1400 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1401 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1404 #define for_each_supported_width(caps, ddr, ecbv) \
1405 for (ecbv = ext_csd_bus_width;\
1406 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1408 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1410 static int mmc_select_mode_and_width(struct mmc *mmc)
1413 const struct mode_width_tuning *mwt;
1414 const struct ext_csd_bus_width *ecbw;
1416 err = mmc_get_capabilities(mmc);
1420 /* Restrict card's capabilities by what the host can do */
1421 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1423 /* Only version 4 of MMC supports wider bus widths */
1424 if (mmc->version < MMC_VERSION_4)
1427 if (!mmc->ext_csd) {
1428 debug("No ext_csd found!\n"); /* this should enver happen */
1432 for_each_mmc_mode_by_pref(mmc->card_caps, mwt) {
1433 for_each_supported_width(mmc->card_caps & mwt->widths,
1434 mmc_is_mode_ddr(mwt->mode), ecbw) {
1435 debug("trying mode %s width %d (at %d MHz)\n",
1436 mmc_mode_name(mwt->mode),
1437 bus_width(ecbw->cap),
1438 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1439 /* configure the bus width (card + host) */
1440 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1442 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1445 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1447 /* configure the bus speed (card) */
1448 err = mmc_set_card_speed(mmc, mwt->mode);
1453 * configure the bus width AND the ddr mode (card)
1454 * The host side will be taken care of in the next step
1456 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1457 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1459 ecbw->ext_csd_bits);
1464 /* configure the bus mode (host) */
1465 mmc_select_mode(mmc, mwt->mode);
1466 mmc_set_clock(mmc, mmc->tran_speed);
1468 /* do a transfer to check the configuration */
1469 err = mmc_read_and_compare_ext_csd(mmc);
1473 /* if an error occured, revert to a safer bus mode */
1474 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1475 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1476 mmc_select_mode(mmc, MMC_LEGACY);
1477 mmc_set_bus_width(mmc, 1);
1481 printf("unable to select a mode\n");
1486 static int mmc_startup_v4(struct mmc *mmc)
1490 bool has_parts = false;
1491 bool part_completed;
1494 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1497 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1501 mmc->ext_csd = ext_csd;
1503 /* check ext_csd version and capacity */
1504 err = mmc_send_ext_csd(mmc, ext_csd);
1507 if (ext_csd[EXT_CSD_REV] >= 2) {
1509 * According to the JEDEC Standard, the value of
1510 * ext_csd's capacity is valid if the value is more
1513 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1514 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1515 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1516 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1517 capacity *= MMC_MAX_BLOCK_LEN;
1518 if ((capacity >> 20) > 2 * 1024)
1519 mmc->capacity_user = capacity;
1522 switch (ext_csd[EXT_CSD_REV]) {
1524 mmc->version = MMC_VERSION_4_1;
1527 mmc->version = MMC_VERSION_4_2;
1530 mmc->version = MMC_VERSION_4_3;
1533 mmc->version = MMC_VERSION_4_41;
1536 mmc->version = MMC_VERSION_4_5;
1539 mmc->version = MMC_VERSION_5_0;
1542 mmc->version = MMC_VERSION_5_1;
1546 /* The partition data may be non-zero but it is only
1547 * effective if PARTITION_SETTING_COMPLETED is set in
1548 * EXT_CSD, so ignore any data if this bit is not set,
1549 * except for enabling the high-capacity group size
1550 * definition (see below).
1552 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1553 EXT_CSD_PARTITION_SETTING_COMPLETED);
1555 /* store the partition info of emmc */
1556 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1557 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1558 ext_csd[EXT_CSD_BOOT_MULT])
1559 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1560 if (part_completed &&
1561 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1562 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1564 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1566 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1568 for (i = 0; i < 4; i++) {
1569 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1570 uint mult = (ext_csd[idx + 2] << 16) +
1571 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1574 if (!part_completed)
1576 mmc->capacity_gp[i] = mult;
1577 mmc->capacity_gp[i] *=
1578 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1579 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1580 mmc->capacity_gp[i] <<= 19;
1583 if (part_completed) {
1584 mmc->enh_user_size =
1585 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1586 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1587 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1588 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1589 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1590 mmc->enh_user_size <<= 19;
1591 mmc->enh_user_start =
1592 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1593 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1594 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1595 ext_csd[EXT_CSD_ENH_START_ADDR];
1596 if (mmc->high_capacity)
1597 mmc->enh_user_start <<= 9;
1601 * Host needs to enable ERASE_GRP_DEF bit if device is
1602 * partitioned. This bit will be lost every time after a reset
1603 * or power off. This will affect erase size.
1607 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1608 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1611 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1612 EXT_CSD_ERASE_GROUP_DEF, 1);
1617 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1620 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1621 /* Read out group size from ext_csd */
1622 mmc->erase_grp_size =
1623 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1625 * if high capacity and partition setting completed
1626 * SEC_COUNT is valid even if it is smaller than 2 GiB
1627 * JEDEC Standard JESD84-B45, 6.2.4
1629 if (mmc->high_capacity && part_completed) {
1630 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1631 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1632 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1633 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1634 capacity *= MMC_MAX_BLOCK_LEN;
1635 mmc->capacity_user = capacity;
1638 /* Calculate the group size from the csd value. */
1639 int erase_gsz, erase_gmul;
1641 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1642 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1643 mmc->erase_grp_size = (erase_gsz + 1)
1647 mmc->hc_wp_grp_size = 1024
1648 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1649 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1651 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1656 static int mmc_startup(struct mmc *mmc)
1662 struct blk_desc *bdesc;
1664 #ifdef CONFIG_MMC_SPI_CRC_ON
1665 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1666 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1667 cmd.resp_type = MMC_RSP_R1;
1669 err = mmc_send_cmd(mmc, &cmd, NULL);
1676 /* Put the Card in Identify Mode */
1677 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1678 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1679 cmd.resp_type = MMC_RSP_R2;
1682 err = mmc_send_cmd(mmc, &cmd, NULL);
1687 memcpy(mmc->cid, cmd.response, 16);
1690 * For MMC cards, set the Relative Address.
1691 * For SD cards, get the Relatvie Address.
1692 * This also puts the cards into Standby State
1694 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1695 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1696 cmd.cmdarg = mmc->rca << 16;
1697 cmd.resp_type = MMC_RSP_R6;
1699 err = mmc_send_cmd(mmc, &cmd, NULL);
1705 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1708 /* Get the Card-Specific Data */
1709 cmd.cmdidx = MMC_CMD_SEND_CSD;
1710 cmd.resp_type = MMC_RSP_R2;
1711 cmd.cmdarg = mmc->rca << 16;
1713 err = mmc_send_cmd(mmc, &cmd, NULL);
1718 mmc->csd[0] = cmd.response[0];
1719 mmc->csd[1] = cmd.response[1];
1720 mmc->csd[2] = cmd.response[2];
1721 mmc->csd[3] = cmd.response[3];
1723 if (mmc->version == MMC_VERSION_UNKNOWN) {
1724 int version = (cmd.response[0] >> 26) & 0xf;
1728 mmc->version = MMC_VERSION_1_2;
1731 mmc->version = MMC_VERSION_1_4;
1734 mmc->version = MMC_VERSION_2_2;
1737 mmc->version = MMC_VERSION_3;
1740 mmc->version = MMC_VERSION_4;
1743 mmc->version = MMC_VERSION_1_2;
1748 /* divide frequency by 10, since the mults are 10x bigger */
1749 freq = fbase[(cmd.response[0] & 0x7)];
1750 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1752 mmc->legacy_speed = freq * mult;
1753 mmc_select_mode(mmc, MMC_LEGACY);
1755 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1756 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1759 mmc->write_bl_len = mmc->read_bl_len;
1761 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1763 if (mmc->high_capacity) {
1764 csize = (mmc->csd[1] & 0x3f) << 16
1765 | (mmc->csd[2] & 0xffff0000) >> 16;
1768 csize = (mmc->csd[1] & 0x3ff) << 2
1769 | (mmc->csd[2] & 0xc0000000) >> 30;
1770 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1773 mmc->capacity_user = (csize + 1) << (cmult + 2);
1774 mmc->capacity_user *= mmc->read_bl_len;
1775 mmc->capacity_boot = 0;
1776 mmc->capacity_rpmb = 0;
1777 for (i = 0; i < 4; i++)
1778 mmc->capacity_gp[i] = 0;
1780 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1781 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1783 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1784 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1786 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1787 cmd.cmdidx = MMC_CMD_SET_DSR;
1788 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1789 cmd.resp_type = MMC_RSP_NONE;
1790 if (mmc_send_cmd(mmc, &cmd, NULL))
1791 printf("MMC: SET_DSR failed\n");
1794 /* Select the card, and put it into Transfer Mode */
1795 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1796 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1797 cmd.resp_type = MMC_RSP_R1;
1798 cmd.cmdarg = mmc->rca << 16;
1799 err = mmc_send_cmd(mmc, &cmd, NULL);
1806 * For SD, its erase group is always one sector
1808 mmc->erase_grp_size = 1;
1809 mmc->part_config = MMCPART_NOAVAILABLE;
1811 err = mmc_startup_v4(mmc);
1815 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1820 err = sd_select_mode_and_width(mmc);
1822 err = mmc_select_mode_and_width(mmc);
1828 /* Fix the block length for DDR mode */
1829 if (mmc->ddr_mode) {
1830 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1831 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1834 /* fill in device description */
1835 bdesc = mmc_get_blk_desc(mmc);
1839 bdesc->blksz = mmc->read_bl_len;
1840 bdesc->log2blksz = LOG2(bdesc->blksz);
1841 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1842 #if !defined(CONFIG_SPL_BUILD) || \
1843 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1844 !defined(CONFIG_USE_TINY_PRINTF))
1845 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1846 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1847 (mmc->cid[3] >> 16) & 0xffff);
1848 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1849 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1850 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1851 (mmc->cid[2] >> 24) & 0xff);
1852 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1853 (mmc->cid[2] >> 16) & 0xf);
1855 bdesc->vendor[0] = 0;
1856 bdesc->product[0] = 0;
1857 bdesc->revision[0] = 0;
1859 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1866 static int mmc_send_if_cond(struct mmc *mmc)
1871 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1872 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1873 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1874 cmd.resp_type = MMC_RSP_R7;
1876 err = mmc_send_cmd(mmc, &cmd, NULL);
1881 if ((cmd.response[0] & 0xff) != 0xaa)
1884 mmc->version = SD_VERSION_2;
1889 #if !CONFIG_IS_ENABLED(DM_MMC)
1890 /* board-specific MMC power initializations. */
1891 __weak void board_mmc_power_init(void)
1896 static int mmc_power_init(struct mmc *mmc)
1898 #if CONFIG_IS_ENABLED(DM_MMC)
1899 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1902 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
1905 debug("%s: No vmmc supply\n", mmc->dev->name);
1907 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
1908 &mmc->vqmmc_supply);
1910 debug("%s: No vqmmc supply\n", mmc->dev->name);
1912 if (mmc->vmmc_supply) {
1913 ret = regulator_set_enable(mmc->vmmc_supply, true);
1915 puts("Error enabling VMMC supply\n");
1920 #else /* !CONFIG_DM_MMC */
1922 * Driver model should use a regulator, as above, rather than calling
1923 * out to board code.
1925 board_mmc_power_init();
1930 int mmc_start_init(struct mmc *mmc)
1935 /* we pretend there's no card when init is NULL */
1936 no_card = mmc_getcd(mmc) == 0;
1937 #if !CONFIG_IS_ENABLED(DM_MMC)
1938 no_card = no_card || (mmc->cfg->ops->init == NULL);
1942 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1943 printf("MMC: no card present\n");
1951 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1952 mmc_adapter_card_type_ident();
1954 err = mmc_power_init(mmc);
1958 #if CONFIG_IS_ENABLED(DM_MMC)
1959 /* The device has already been probed ready for use */
1961 /* made sure it's not NULL earlier */
1962 err = mmc->cfg->ops->init(mmc);
1967 mmc_set_bus_width(mmc, 1);
1968 mmc_set_clock(mmc, 1);
1970 /* Reset the Card */
1971 err = mmc_go_idle(mmc);
1976 /* The internal partition reset to user partition(0) at every CMD0*/
1977 mmc_get_blk_desc(mmc)->hwpart = 0;
1979 /* Test for SD version 2 */
1980 err = mmc_send_if_cond(mmc);
1982 /* Now try to get the SD card's operating condition */
1983 err = sd_send_op_cond(mmc);
1985 /* If the command timed out, we check for an MMC card */
1986 if (err == -ETIMEDOUT) {
1987 err = mmc_send_op_cond(mmc);
1990 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1991 printf("Card did not respond to voltage select!\n");
1998 mmc->init_in_progress = 1;
2003 static int mmc_complete_init(struct mmc *mmc)
2007 mmc->init_in_progress = 0;
2008 if (mmc->op_cond_pending)
2009 err = mmc_complete_op_cond(mmc);
2012 err = mmc_startup(mmc);
2020 int mmc_init(struct mmc *mmc)
2023 __maybe_unused unsigned start;
2024 #if CONFIG_IS_ENABLED(DM_MMC)
2025 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2032 start = get_timer(0);
2034 if (!mmc->init_in_progress)
2035 err = mmc_start_init(mmc);
2038 err = mmc_complete_init(mmc);
2040 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2045 int mmc_set_dsr(struct mmc *mmc, u16 val)
2051 /* CPU-specific MMC initializations */
2052 __weak int cpu_mmc_init(bd_t *bis)
2057 /* board-specific MMC initializations. */
2058 __weak int board_mmc_init(bd_t *bis)
2063 void mmc_set_preinit(struct mmc *mmc, int preinit)
2065 mmc->preinit = preinit;
2068 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2069 static int mmc_probe(bd_t *bis)
2073 #elif CONFIG_IS_ENABLED(DM_MMC)
2074 static int mmc_probe(bd_t *bis)
2078 struct udevice *dev;
2080 ret = uclass_get(UCLASS_MMC, &uc);
2085 * Try to add them in sequence order. Really with driver model we
2086 * should allow holes, but the current MMC list does not allow that.
2087 * So if we request 0, 1, 3 we will get 0, 1, 2.
2089 for (i = 0; ; i++) {
2090 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2094 uclass_foreach_dev(dev, uc) {
2095 ret = device_probe(dev);
2097 printf("%s - probe failed: %d\n", dev->name, ret);
2103 static int mmc_probe(bd_t *bis)
2105 if (board_mmc_init(bis) < 0)
2112 int mmc_initialize(bd_t *bis)
2114 static int initialized = 0;
2116 if (initialized) /* Avoid initializing mmc multiple times */
2120 #if !CONFIG_IS_ENABLED(BLK)
2121 #if !CONFIG_IS_ENABLED(MMC_TINY)
2125 ret = mmc_probe(bis);
2129 #ifndef CONFIG_SPL_BUILD
2130 print_mmc_devices(',');
2137 #ifdef CONFIG_CMD_BKOPS_ENABLE
2138 int mmc_set_bkops_enable(struct mmc *mmc)
2141 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2143 err = mmc_send_ext_csd(mmc, ext_csd);
2145 puts("Could not get ext_csd register values\n");
2149 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2150 puts("Background operations not supported on device\n");
2151 return -EMEDIUMTYPE;
2154 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2155 puts("Background operations already enabled\n");
2159 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2161 puts("Failed to enable manual background operations\n");
2165 puts("Enabled manual background operations\n");