2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
33 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
34 static int mmc_power_cycle(struct mmc *mmc);
35 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
37 #if CONFIG_IS_ENABLED(MMC_TINY)
38 static struct mmc mmc_static;
39 struct mmc *find_mmc_device(int dev_num)
44 void mmc_do_preinit(void)
46 struct mmc *m = &mmc_static;
47 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
48 mmc_set_preinit(m, 1);
54 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
56 return &mmc->block_dev;
60 #if !CONFIG_IS_ENABLED(DM_MMC)
62 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
67 __weak int board_mmc_getwp(struct mmc *mmc)
72 int mmc_getwp(struct mmc *mmc)
76 wp = board_mmc_getwp(mmc);
79 if (mmc->cfg->ops->getwp)
80 wp = mmc->cfg->ops->getwp(mmc);
88 __weak int board_mmc_getcd(struct mmc *mmc)
94 #ifdef CONFIG_MMC_TRACE
95 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
97 printf("CMD_SEND:%d\n", cmd->cmdidx);
98 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
101 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
107 printf("\t\tRET\t\t\t %d\n", ret);
109 switch (cmd->resp_type) {
111 printf("\t\tMMC_RSP_NONE\n");
114 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
118 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
122 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
124 printf("\t\t \t\t 0x%08X \n",
126 printf("\t\t \t\t 0x%08X \n",
128 printf("\t\t \t\t 0x%08X \n",
131 printf("\t\t\t\t\tDUMPING DATA\n");
132 for (i = 0; i < 4; i++) {
134 printf("\t\t\t\t\t%03d - ", i*4);
135 ptr = (u8 *)&cmd->response[i];
137 for (j = 0; j < 4; j++)
138 printf("%02X ", *ptr--);
143 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
147 printf("\t\tERROR MMC rsp not supported\n");
153 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
157 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
158 printf("CURR STATE:%d\n", status);
162 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
163 const char *mmc_mode_name(enum bus_mode mode)
165 static const char *const names[] = {
166 [MMC_LEGACY] = "MMC legacy",
167 [SD_LEGACY] = "SD Legacy",
168 [MMC_HS] = "MMC High Speed (26MHz)",
169 [SD_HS] = "SD High Speed (50MHz)",
170 [UHS_SDR12] = "UHS SDR12 (25MHz)",
171 [UHS_SDR25] = "UHS SDR25 (50MHz)",
172 [UHS_SDR50] = "UHS SDR50 (100MHz)",
173 [UHS_SDR104] = "UHS SDR104 (208MHz)",
174 [UHS_DDR50] = "UHS DDR50 (50MHz)",
175 [MMC_HS_52] = "MMC High Speed (52MHz)",
176 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
177 [MMC_HS_200] = "HS200 (200MHz)",
180 if (mode >= MMC_MODES_END)
181 return "Unknown mode";
187 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
189 static const int freqs[] = {
190 [SD_LEGACY] = 25000000,
193 [UHS_SDR12] = 25000000,
194 [UHS_SDR25] = 50000000,
195 [UHS_SDR50] = 100000000,
196 [UHS_SDR104] = 208000000,
197 [UHS_DDR50] = 50000000,
198 [MMC_HS_52] = 52000000,
199 [MMC_DDR_52] = 52000000,
200 [MMC_HS_200] = 200000000,
203 if (mode == MMC_LEGACY)
204 return mmc->legacy_speed;
205 else if (mode >= MMC_MODES_END)
211 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
213 mmc->selected_mode = mode;
214 mmc->tran_speed = mmc_mode2freq(mmc, mode);
215 mmc->ddr_mode = mmc_is_mode_ddr(mode);
216 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
217 mmc->tran_speed / 1000000);
221 #if !CONFIG_IS_ENABLED(DM_MMC)
222 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
226 mmmc_trace_before_send(mmc, cmd);
227 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
228 mmmc_trace_after_send(mmc, cmd, ret);
234 int mmc_send_status(struct mmc *mmc, int timeout)
237 int err, retries = 5;
239 cmd.cmdidx = MMC_CMD_SEND_STATUS;
240 cmd.resp_type = MMC_RSP_R1;
241 if (!mmc_host_is_spi(mmc))
242 cmd.cmdarg = mmc->rca << 16;
245 err = mmc_send_cmd(mmc, &cmd, NULL);
247 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
248 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
252 if (cmd.response[0] & MMC_STATUS_MASK) {
253 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
254 printf("Status Error: 0x%08X\n",
259 } else if (--retries < 0)
268 mmc_trace_state(mmc, &cmd);
270 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
271 printf("Timeout waiting card ready\n");
279 int mmc_set_blocklen(struct mmc *mmc, int len)
287 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
288 cmd.resp_type = MMC_RSP_R1;
291 err = mmc_send_cmd(mmc, &cmd, NULL);
293 #ifdef CONFIG_MMC_QUIRKS
294 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
297 * It has been seen that SET_BLOCKLEN may fail on the first
298 * attempt, let's try a few more time
301 err = mmc_send_cmd(mmc, &cmd, NULL);
311 static const u8 tuning_blk_pattern_4bit[] = {
312 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
313 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
314 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
315 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
316 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
317 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
318 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
319 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
322 static const u8 tuning_blk_pattern_8bit[] = {
323 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
324 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
325 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
326 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
327 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
328 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
329 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
330 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
331 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
332 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
333 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
334 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
335 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
336 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
337 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
338 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
341 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
344 struct mmc_data data;
345 const u8 *tuning_block_pattern;
348 if (mmc->bus_width == 8) {
349 tuning_block_pattern = tuning_blk_pattern_8bit;
350 size = sizeof(tuning_blk_pattern_8bit);
351 } else if (mmc->bus_width == 4) {
352 tuning_block_pattern = tuning_blk_pattern_4bit;
353 size = sizeof(tuning_blk_pattern_4bit);
358 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
362 cmd.resp_type = MMC_RSP_R1;
364 data.dest = (void *)data_buf;
366 data.blocksize = size;
367 data.flags = MMC_DATA_READ;
369 err = mmc_send_cmd(mmc, &cmd, &data);
373 if (memcmp(data_buf, tuning_block_pattern, size))
379 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
383 struct mmc_data data;
386 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
388 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
390 if (mmc->high_capacity)
393 cmd.cmdarg = start * mmc->read_bl_len;
395 cmd.resp_type = MMC_RSP_R1;
398 data.blocks = blkcnt;
399 data.blocksize = mmc->read_bl_len;
400 data.flags = MMC_DATA_READ;
402 if (mmc_send_cmd(mmc, &cmd, &data))
406 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
408 cmd.resp_type = MMC_RSP_R1b;
409 if (mmc_send_cmd(mmc, &cmd, NULL)) {
410 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
411 printf("mmc fail to send stop cmd\n");
420 #if CONFIG_IS_ENABLED(BLK)
421 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
423 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
427 #if CONFIG_IS_ENABLED(BLK)
428 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
430 int dev_num = block_dev->devnum;
432 lbaint_t cur, blocks_todo = blkcnt;
437 struct mmc *mmc = find_mmc_device(dev_num);
441 if (CONFIG_IS_ENABLED(MMC_TINY))
442 err = mmc_switch_part(mmc, block_dev->hwpart);
444 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
449 if ((start + blkcnt) > block_dev->lba) {
450 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
451 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
452 start + blkcnt, block_dev->lba);
457 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
458 debug("%s: Failed to set blocklen\n", __func__);
463 cur = (blocks_todo > mmc->cfg->b_max) ?
464 mmc->cfg->b_max : blocks_todo;
465 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
466 debug("%s: Failed to read blocks\n", __func__);
471 dst += cur * mmc->read_bl_len;
472 } while (blocks_todo > 0);
477 static int mmc_go_idle(struct mmc *mmc)
484 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
486 cmd.resp_type = MMC_RSP_NONE;
488 err = mmc_send_cmd(mmc, &cmd, NULL);
498 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
504 * Send CMD11 only if the request is to switch the card to
507 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
508 return mmc_set_signal_voltage(mmc, signal_voltage);
510 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
512 cmd.resp_type = MMC_RSP_R1;
514 err = mmc_send_cmd(mmc, &cmd, NULL);
518 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
522 * The card should drive cmd and dat[0:3] low immediately
523 * after the response of cmd11, but wait 100 us to be sure
525 err = mmc_wait_dat0(mmc, 0, 100);
532 * During a signal voltage level switch, the clock must be gated
533 * for 5 ms according to the SD spec
535 mmc_set_clock(mmc, mmc->clock, true);
537 err = mmc_set_signal_voltage(mmc, signal_voltage);
541 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
543 mmc_set_clock(mmc, mmc->clock, false);
546 * Failure to switch is indicated by the card holding
547 * dat[0:3] low. Wait for at least 1 ms according to spec
549 err = mmc_wait_dat0(mmc, 1, 1000);
558 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
565 cmd.cmdidx = MMC_CMD_APP_CMD;
566 cmd.resp_type = MMC_RSP_R1;
569 err = mmc_send_cmd(mmc, &cmd, NULL);
574 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
575 cmd.resp_type = MMC_RSP_R3;
578 * Most cards do not answer if some reserved bits
579 * in the ocr are set. However, Some controller
580 * can set bit 7 (reserved for low voltages), but
581 * how to manage low voltages SD card is not yet
584 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
585 (mmc->cfg->voltages & 0xff8000);
587 if (mmc->version == SD_VERSION_2)
588 cmd.cmdarg |= OCR_HCS;
591 cmd.cmdarg |= OCR_S18R;
593 err = mmc_send_cmd(mmc, &cmd, NULL);
598 if (cmd.response[0] & OCR_BUSY)
607 if (mmc->version != SD_VERSION_2)
608 mmc->version = SD_VERSION_1_0;
610 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
611 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
612 cmd.resp_type = MMC_RSP_R3;
615 err = mmc_send_cmd(mmc, &cmd, NULL);
621 mmc->ocr = cmd.response[0];
623 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
625 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
630 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
636 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
641 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
642 cmd.resp_type = MMC_RSP_R3;
644 if (use_arg && !mmc_host_is_spi(mmc))
645 cmd.cmdarg = OCR_HCS |
646 (mmc->cfg->voltages &
647 (mmc->ocr & OCR_VOLTAGE_MASK)) |
648 (mmc->ocr & OCR_ACCESS_MODE);
650 err = mmc_send_cmd(mmc, &cmd, NULL);
653 mmc->ocr = cmd.response[0];
657 static int mmc_send_op_cond(struct mmc *mmc)
661 /* Some cards seem to need this */
664 /* Asking to the card its capabilities */
665 for (i = 0; i < 2; i++) {
666 err = mmc_send_op_cond_iter(mmc, i != 0);
670 /* exit if not busy (flag seems to be inverted) */
671 if (mmc->ocr & OCR_BUSY)
674 mmc->op_cond_pending = 1;
678 static int mmc_complete_op_cond(struct mmc *mmc)
685 mmc->op_cond_pending = 0;
686 if (!(mmc->ocr & OCR_BUSY)) {
687 /* Some cards seem to need this */
690 start = get_timer(0);
692 err = mmc_send_op_cond_iter(mmc, 1);
695 if (mmc->ocr & OCR_BUSY)
697 if (get_timer(start) > timeout)
703 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
704 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
705 cmd.resp_type = MMC_RSP_R3;
708 err = mmc_send_cmd(mmc, &cmd, NULL);
713 mmc->ocr = cmd.response[0];
716 mmc->version = MMC_VERSION_UNKNOWN;
718 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
725 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
728 struct mmc_data data;
731 /* Get the Card Status Register */
732 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
733 cmd.resp_type = MMC_RSP_R1;
736 data.dest = (char *)ext_csd;
738 data.blocksize = MMC_MAX_BLOCK_LEN;
739 data.flags = MMC_DATA_READ;
741 err = mmc_send_cmd(mmc, &cmd, &data);
746 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
753 cmd.cmdidx = MMC_CMD_SWITCH;
754 cmd.resp_type = MMC_RSP_R1b;
755 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
759 while (retries > 0) {
760 ret = mmc_send_cmd(mmc, &cmd, NULL);
762 /* Waiting for the ready status */
764 ret = mmc_send_status(mmc, timeout);
775 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
780 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
786 speed_bits = EXT_CSD_TIMING_HS;
789 speed_bits = EXT_CSD_TIMING_HS200;
792 speed_bits = EXT_CSD_TIMING_LEGACY;
797 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
802 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
803 /* Now check to see that it worked */
804 err = mmc_send_ext_csd(mmc, test_csd);
808 /* No high-speed support */
809 if (!test_csd[EXT_CSD_HS_TIMING])
816 static int mmc_get_capabilities(struct mmc *mmc)
818 u8 *ext_csd = mmc->ext_csd;
821 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
823 if (mmc_host_is_spi(mmc))
826 /* Only version 4 supports high-speed */
827 if (mmc->version < MMC_VERSION_4)
831 printf("No ext_csd found!\n"); /* this should enver happen */
835 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
837 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
838 mmc->cardtype = cardtype;
840 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
841 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
842 mmc->card_caps |= MMC_MODE_HS200;
844 if (cardtype & EXT_CSD_CARD_TYPE_52) {
845 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
846 mmc->card_caps |= MMC_MODE_DDR_52MHz;
847 mmc->card_caps |= MMC_MODE_HS_52MHz;
849 if (cardtype & EXT_CSD_CARD_TYPE_26)
850 mmc->card_caps |= MMC_MODE_HS;
855 static int mmc_set_capacity(struct mmc *mmc, int part_num)
859 mmc->capacity = mmc->capacity_user;
863 mmc->capacity = mmc->capacity_boot;
866 mmc->capacity = mmc->capacity_rpmb;
872 mmc->capacity = mmc->capacity_gp[part_num - 4];
878 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
883 static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
888 if (part_num & PART_ACCESS_MASK)
889 forbidden = MMC_CAP(MMC_HS_200);
891 if (MMC_CAP(mmc->selected_mode) & forbidden) {
892 debug("selected mode (%s) is forbidden for part %d\n",
893 mmc_mode_name(mmc->selected_mode), part_num);
895 } else if (mmc->selected_mode != mmc->best_mode) {
896 debug("selected mode is not optimal\n");
901 return mmc_select_mode_and_width(mmc,
902 mmc->card_caps & ~forbidden);
907 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
911 ret = mmc_boot_part_access_chk(mmc, part_num);
915 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
916 (mmc->part_config & ~PART_ACCESS_MASK)
917 | (part_num & PART_ACCESS_MASK));
920 * Set the capacity if the switch succeeded or was intended
921 * to return to representing the raw device.
923 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
924 ret = mmc_set_capacity(mmc, part_num);
925 mmc_get_blk_desc(mmc)->hwpart = part_num;
931 int mmc_hwpart_config(struct mmc *mmc,
932 const struct mmc_hwpart_conf *conf,
933 enum mmc_hwpart_conf_mode mode)
939 u32 max_enh_size_mult;
940 u32 tot_enh_size_mult = 0;
943 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
945 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
948 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
949 printf("eMMC >= 4.4 required for enhanced user data area\n");
953 if (!(mmc->part_support & PART_SUPPORT)) {
954 printf("Card does not support partitioning\n");
958 if (!mmc->hc_wp_grp_size) {
959 printf("Card does not define HC WP group size\n");
963 /* check partition alignment and total enhanced size */
964 if (conf->user.enh_size) {
965 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
966 conf->user.enh_start % mmc->hc_wp_grp_size) {
967 printf("User data enhanced area not HC WP group "
971 part_attrs |= EXT_CSD_ENH_USR;
972 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
973 if (mmc->high_capacity) {
974 enh_start_addr = conf->user.enh_start;
976 enh_start_addr = (conf->user.enh_start << 9);
982 tot_enh_size_mult += enh_size_mult;
984 for (pidx = 0; pidx < 4; pidx++) {
985 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
986 printf("GP%i partition not HC WP group size "
987 "aligned\n", pidx+1);
990 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
991 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
992 part_attrs |= EXT_CSD_ENH_GP(pidx);
993 tot_enh_size_mult += gp_size_mult[pidx];
997 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
998 printf("Card does not support enhanced attribute\n");
1002 err = mmc_send_ext_csd(mmc, ext_csd);
1007 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1008 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1009 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1010 if (tot_enh_size_mult > max_enh_size_mult) {
1011 printf("Total enhanced size exceeds maximum (%u > %u)\n",
1012 tot_enh_size_mult, max_enh_size_mult);
1013 return -EMEDIUMTYPE;
1016 /* The default value of EXT_CSD_WR_REL_SET is device
1017 * dependent, the values can only be changed if the
1018 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1019 * changed only once and before partitioning is completed. */
1020 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1021 if (conf->user.wr_rel_change) {
1022 if (conf->user.wr_rel_set)
1023 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1025 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1027 for (pidx = 0; pidx < 4; pidx++) {
1028 if (conf->gp_part[pidx].wr_rel_change) {
1029 if (conf->gp_part[pidx].wr_rel_set)
1030 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1032 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1036 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1037 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1038 puts("Card does not support host controlled partition write "
1039 "reliability settings\n");
1040 return -EMEDIUMTYPE;
1043 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1044 EXT_CSD_PARTITION_SETTING_COMPLETED) {
1045 printf("Card already partitioned\n");
1049 if (mode == MMC_HWPART_CONF_CHECK)
1052 /* Partitioning requires high-capacity size definitions */
1053 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1054 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1055 EXT_CSD_ERASE_GROUP_DEF, 1);
1060 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1062 /* update erase group size to be high-capacity */
1063 mmc->erase_grp_size =
1064 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1068 /* all OK, write the configuration */
1069 for (i = 0; i < 4; i++) {
1070 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1071 EXT_CSD_ENH_START_ADDR+i,
1072 (enh_start_addr >> (i*8)) & 0xFF);
1076 for (i = 0; i < 3; i++) {
1077 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1078 EXT_CSD_ENH_SIZE_MULT+i,
1079 (enh_size_mult >> (i*8)) & 0xFF);
1083 for (pidx = 0; pidx < 4; pidx++) {
1084 for (i = 0; i < 3; i++) {
1085 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1086 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1087 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1092 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1093 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1097 if (mode == MMC_HWPART_CONF_SET)
1100 /* The WR_REL_SET is a write-once register but shall be
1101 * written before setting PART_SETTING_COMPLETED. As it is
1102 * write-once we can only write it when completing the
1104 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1105 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1106 EXT_CSD_WR_REL_SET, wr_rel_set);
1111 /* Setting PART_SETTING_COMPLETED confirms the partition
1112 * configuration but it only becomes effective after power
1113 * cycle, so we do not adjust the partition related settings
1114 * in the mmc struct. */
1116 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1117 EXT_CSD_PARTITION_SETTING,
1118 EXT_CSD_PARTITION_SETTING_COMPLETED);
1125 #if !CONFIG_IS_ENABLED(DM_MMC)
1126 int mmc_getcd(struct mmc *mmc)
1130 cd = board_mmc_getcd(mmc);
1133 if (mmc->cfg->ops->getcd)
1134 cd = mmc->cfg->ops->getcd(mmc);
1143 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1146 struct mmc_data data;
1148 /* Switch the frequency */
1149 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1150 cmd.resp_type = MMC_RSP_R1;
1151 cmd.cmdarg = (mode << 31) | 0xffffff;
1152 cmd.cmdarg &= ~(0xf << (group * 4));
1153 cmd.cmdarg |= value << (group * 4);
1155 data.dest = (char *)resp;
1156 data.blocksize = 64;
1158 data.flags = MMC_DATA_READ;
1160 return mmc_send_cmd(mmc, &cmd, &data);
1164 static int sd_get_capabilities(struct mmc *mmc)
1168 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1169 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1170 struct mmc_data data;
1174 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1176 if (mmc_host_is_spi(mmc))
1179 /* Read the SCR to find out if this card supports higher speeds */
1180 cmd.cmdidx = MMC_CMD_APP_CMD;
1181 cmd.resp_type = MMC_RSP_R1;
1182 cmd.cmdarg = mmc->rca << 16;
1184 err = mmc_send_cmd(mmc, &cmd, NULL);
1189 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1190 cmd.resp_type = MMC_RSP_R1;
1196 data.dest = (char *)scr;
1199 data.flags = MMC_DATA_READ;
1201 err = mmc_send_cmd(mmc, &cmd, &data);
1210 mmc->scr[0] = __be32_to_cpu(scr[0]);
1211 mmc->scr[1] = __be32_to_cpu(scr[1]);
1213 switch ((mmc->scr[0] >> 24) & 0xf) {
1215 mmc->version = SD_VERSION_1_0;
1218 mmc->version = SD_VERSION_1_10;
1221 mmc->version = SD_VERSION_2;
1222 if ((mmc->scr[0] >> 15) & 0x1)
1223 mmc->version = SD_VERSION_3;
1226 mmc->version = SD_VERSION_1_0;
1230 if (mmc->scr[0] & SD_DATA_4BIT)
1231 mmc->card_caps |= MMC_MODE_4BIT;
1233 /* Version 1.0 doesn't support switching */
1234 if (mmc->version == SD_VERSION_1_0)
1239 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1240 (u8 *)switch_status);
1245 /* The high-speed function is busy. Try again */
1246 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1250 /* If high-speed isn't supported, we return */
1251 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1252 mmc->card_caps |= MMC_CAP(SD_HS);
1254 /* Version before 3.0 don't support UHS modes */
1255 if (mmc->version < SD_VERSION_3)
1258 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1259 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1260 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1261 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1262 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1263 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1264 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1265 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1266 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1267 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1268 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1273 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1277 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1283 speed = UHS_SDR12_BUS_SPEED;
1287 speed = UHS_SDR25_BUS_SPEED;
1290 speed = UHS_SDR50_BUS_SPEED;
1293 speed = UHS_DDR50_BUS_SPEED;
1296 speed = UHS_SDR104_BUS_SPEED;
1302 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1306 if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
1312 int sd_select_bus_width(struct mmc *mmc, int w)
1317 if ((w != 4) && (w != 1))
1320 cmd.cmdidx = MMC_CMD_APP_CMD;
1321 cmd.resp_type = MMC_RSP_R1;
1322 cmd.cmdarg = mmc->rca << 16;
1324 err = mmc_send_cmd(mmc, &cmd, NULL);
1328 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1329 cmd.resp_type = MMC_RSP_R1;
1334 err = mmc_send_cmd(mmc, &cmd, NULL);
1341 static int sd_read_ssr(struct mmc *mmc)
1345 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1346 struct mmc_data data;
1348 unsigned int au, eo, et, es;
1350 cmd.cmdidx = MMC_CMD_APP_CMD;
1351 cmd.resp_type = MMC_RSP_R1;
1352 cmd.cmdarg = mmc->rca << 16;
1354 err = mmc_send_cmd(mmc, &cmd, NULL);
1358 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1359 cmd.resp_type = MMC_RSP_R1;
1363 data.dest = (char *)ssr;
1364 data.blocksize = 64;
1366 data.flags = MMC_DATA_READ;
1368 err = mmc_send_cmd(mmc, &cmd, &data);
1376 for (i = 0; i < 16; i++)
1377 ssr[i] = be32_to_cpu(ssr[i]);
1379 au = (ssr[2] >> 12) & 0xF;
1380 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1381 mmc->ssr.au = sd_au_size[au];
1382 es = (ssr[3] >> 24) & 0xFF;
1383 es |= (ssr[2] & 0xFF) << 8;
1384 et = (ssr[3] >> 18) & 0x3F;
1386 eo = (ssr[3] >> 16) & 0x3;
1387 mmc->ssr.erase_timeout = (et * 1000) / es;
1388 mmc->ssr.erase_offset = eo * 1000;
1391 debug("Invalid Allocation Unit Size.\n");
1397 /* frequency bases */
1398 /* divided by 10 to be nice to platforms without floating point */
1399 static const int fbase[] = {
1406 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1407 * to platforms without floating point.
1409 static const u8 multipliers[] = {
1428 static inline int bus_width(uint cap)
1430 if (cap == MMC_MODE_8BIT)
1432 if (cap == MMC_MODE_4BIT)
1434 if (cap == MMC_MODE_1BIT)
1436 printf("invalid bus witdh capability 0x%x\n", cap);
1440 #if !CONFIG_IS_ENABLED(DM_MMC)
1441 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1446 static void mmc_send_init_stream(struct mmc *mmc)
1450 static int mmc_set_ios(struct mmc *mmc)
1454 if (mmc->cfg->ops->set_ios)
1455 ret = mmc->cfg->ops->set_ios(mmc);
1461 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1463 if (clock > mmc->cfg->f_max)
1464 clock = mmc->cfg->f_max;
1466 if (clock < mmc->cfg->f_min)
1467 clock = mmc->cfg->f_min;
1470 mmc->clk_disable = disable;
1472 return mmc_set_ios(mmc);
1475 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1477 mmc->bus_width = width;
1479 return mmc_set_ios(mmc);
1482 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1484 * helper function to display the capabilities in a human
1485 * friendly manner. The capabilities include bus width and
1488 void mmc_dump_capabilities(const char *text, uint caps)
1492 printf("%s: widths [", text);
1493 if (caps & MMC_MODE_8BIT)
1495 if (caps & MMC_MODE_4BIT)
1497 if (caps & MMC_MODE_1BIT)
1499 printf("\b\b] modes [");
1500 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1501 if (MMC_CAP(mode) & caps)
1502 printf("%s, ", mmc_mode_name(mode));
1507 struct mode_width_tuning {
1513 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1516 case MMC_SIGNAL_VOLTAGE_000: return 0;
1517 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1518 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1519 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1524 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1528 if (mmc->signal_voltage == signal_voltage)
1531 mmc->signal_voltage = signal_voltage;
1532 err = mmc_set_ios(mmc);
1534 debug("unable to set voltage (err %d)\n", err);
1539 static const struct mode_width_tuning sd_modes_by_pref[] = {
1542 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1543 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1547 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1551 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1555 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1559 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1563 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1567 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1571 #define for_each_sd_mode_by_pref(caps, mwt) \
1572 for (mwt = sd_modes_by_pref;\
1573 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1575 if (caps & MMC_CAP(mwt->mode))
1577 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1580 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1581 const struct mode_width_tuning *mwt;
1582 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1586 mmc_dump_capabilities("sd card", card_caps);
1587 mmc_dump_capabilities("host", mmc->host_caps);
1590 /* Restrict card's capabilities by what the host can do */
1591 caps = card_caps & mmc->host_caps;
1596 for_each_sd_mode_by_pref(caps, mwt) {
1599 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1600 if (*w & caps & mwt->widths) {
1601 debug("trying mode %s width %d (at %d MHz)\n",
1602 mmc_mode_name(mwt->mode),
1604 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1606 /* configure the bus width (card + host) */
1607 err = sd_select_bus_width(mmc, bus_width(*w));
1610 mmc_set_bus_width(mmc, bus_width(*w));
1612 /* configure the bus mode (card) */
1613 err = sd_set_card_speed(mmc, mwt->mode);
1617 /* configure the bus mode (host) */
1618 mmc_select_mode(mmc, mwt->mode);
1619 mmc_set_clock(mmc, mmc->tran_speed, false);
1621 /* execute tuning if needed */
1622 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1623 err = mmc_execute_tuning(mmc,
1626 debug("tuning failed\n");
1631 err = sd_read_ssr(mmc);
1635 printf("bad ssr\n");
1638 /* revert to a safer bus speed */
1639 mmc_select_mode(mmc, SD_LEGACY);
1640 mmc_set_clock(mmc, mmc->tran_speed, false);
1645 printf("unable to select a mode\n");
1650 * read the compare the part of ext csd that is constant.
1651 * This can be used to check that the transfer is working
1654 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1657 const u8 *ext_csd = mmc->ext_csd;
1658 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1660 if (mmc->version < MMC_VERSION_4)
1663 err = mmc_send_ext_csd(mmc, test_csd);
1667 /* Only compare read only fields */
1668 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1669 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1670 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1671 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1672 ext_csd[EXT_CSD_REV]
1673 == test_csd[EXT_CSD_REV] &&
1674 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1675 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1676 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1677 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1683 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1684 uint32_t allowed_mask)
1690 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
1691 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1692 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
1693 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1696 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1697 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1698 MMC_SIGNAL_VOLTAGE_180;
1699 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1700 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1703 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1707 while (card_mask & allowed_mask) {
1708 enum mmc_voltage best_match;
1710 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1711 if (!mmc_set_signal_voltage(mmc, best_match))
1714 allowed_mask &= ~best_match;
1720 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1723 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1724 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1728 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1732 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1736 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1740 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1744 #define for_each_mmc_mode_by_pref(caps, mwt) \
1745 for (mwt = mmc_modes_by_pref;\
1746 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1748 if (caps & MMC_CAP(mwt->mode))
1750 static const struct ext_csd_bus_width {
1754 } ext_csd_bus_width[] = {
1755 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1756 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1757 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1758 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1759 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1762 #define for_each_supported_width(caps, ddr, ecbv) \
1763 for (ecbv = ext_csd_bus_width;\
1764 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1766 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1768 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
1771 const struct mode_width_tuning *mwt;
1772 const struct ext_csd_bus_width *ecbw;
1775 mmc_dump_capabilities("mmc", card_caps);
1776 mmc_dump_capabilities("host", mmc->host_caps);
1779 /* Restrict card's capabilities by what the host can do */
1780 card_caps &= mmc->host_caps;
1782 /* Only version 4 of MMC supports wider bus widths */
1783 if (mmc->version < MMC_VERSION_4)
1786 if (!mmc->ext_csd) {
1787 debug("No ext_csd found!\n"); /* this should enver happen */
1791 mmc_set_clock(mmc, mmc->legacy_speed, false);
1793 for_each_mmc_mode_by_pref(card_caps, mwt) {
1794 for_each_supported_width(card_caps & mwt->widths,
1795 mmc_is_mode_ddr(mwt->mode), ecbw) {
1796 enum mmc_voltage old_voltage;
1797 debug("trying mode %s width %d (at %d MHz)\n",
1798 mmc_mode_name(mwt->mode),
1799 bus_width(ecbw->cap),
1800 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1801 old_voltage = mmc->signal_voltage;
1802 err = mmc_set_lowest_voltage(mmc, mwt->mode,
1803 MMC_ALL_SIGNAL_VOLTAGE);
1807 /* configure the bus width (card + host) */
1808 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1810 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1813 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
1815 /* configure the bus speed (card) */
1816 err = mmc_set_card_speed(mmc, mwt->mode);
1821 * configure the bus width AND the ddr mode (card)
1822 * The host side will be taken care of in the next step
1824 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1825 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1827 ecbw->ext_csd_bits);
1832 /* configure the bus mode (host) */
1833 mmc_select_mode(mmc, mwt->mode);
1834 mmc_set_clock(mmc, mmc->tran_speed, false);
1836 /* execute tuning if needed */
1838 err = mmc_execute_tuning(mmc, mwt->tuning);
1840 debug("tuning failed\n");
1845 /* do a transfer to check the configuration */
1846 err = mmc_read_and_compare_ext_csd(mmc);
1850 mmc_set_signal_voltage(mmc, old_voltage);
1851 /* if an error occured, revert to a safer bus mode */
1852 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1853 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1854 mmc_select_mode(mmc, MMC_LEGACY);
1855 mmc_set_bus_width(mmc, 1);
1859 printf("unable to select a mode\n");
1864 static int mmc_startup_v4(struct mmc *mmc)
1868 bool has_parts = false;
1869 bool part_completed;
1872 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1875 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1879 mmc->ext_csd = ext_csd;
1881 /* check ext_csd version and capacity */
1882 err = mmc_send_ext_csd(mmc, ext_csd);
1885 if (ext_csd[EXT_CSD_REV] >= 2) {
1887 * According to the JEDEC Standard, the value of
1888 * ext_csd's capacity is valid if the value is more
1891 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1892 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1893 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1894 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1895 capacity *= MMC_MAX_BLOCK_LEN;
1896 if ((capacity >> 20) > 2 * 1024)
1897 mmc->capacity_user = capacity;
1900 switch (ext_csd[EXT_CSD_REV]) {
1902 mmc->version = MMC_VERSION_4_1;
1905 mmc->version = MMC_VERSION_4_2;
1908 mmc->version = MMC_VERSION_4_3;
1911 mmc->version = MMC_VERSION_4_41;
1914 mmc->version = MMC_VERSION_4_5;
1917 mmc->version = MMC_VERSION_5_0;
1920 mmc->version = MMC_VERSION_5_1;
1924 /* The partition data may be non-zero but it is only
1925 * effective if PARTITION_SETTING_COMPLETED is set in
1926 * EXT_CSD, so ignore any data if this bit is not set,
1927 * except for enabling the high-capacity group size
1928 * definition (see below).
1930 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1931 EXT_CSD_PARTITION_SETTING_COMPLETED);
1933 /* store the partition info of emmc */
1934 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1935 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1936 ext_csd[EXT_CSD_BOOT_MULT])
1937 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1938 if (part_completed &&
1939 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1940 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1942 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1944 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1946 for (i = 0; i < 4; i++) {
1947 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1948 uint mult = (ext_csd[idx + 2] << 16) +
1949 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1952 if (!part_completed)
1954 mmc->capacity_gp[i] = mult;
1955 mmc->capacity_gp[i] *=
1956 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1957 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1958 mmc->capacity_gp[i] <<= 19;
1961 if (part_completed) {
1962 mmc->enh_user_size =
1963 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1964 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1965 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1966 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1967 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1968 mmc->enh_user_size <<= 19;
1969 mmc->enh_user_start =
1970 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1971 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1972 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1973 ext_csd[EXT_CSD_ENH_START_ADDR];
1974 if (mmc->high_capacity)
1975 mmc->enh_user_start <<= 9;
1979 * Host needs to enable ERASE_GRP_DEF bit if device is
1980 * partitioned. This bit will be lost every time after a reset
1981 * or power off. This will affect erase size.
1985 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1986 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1989 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1990 EXT_CSD_ERASE_GROUP_DEF, 1);
1995 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1998 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1999 /* Read out group size from ext_csd */
2000 mmc->erase_grp_size =
2001 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2003 * if high capacity and partition setting completed
2004 * SEC_COUNT is valid even if it is smaller than 2 GiB
2005 * JEDEC Standard JESD84-B45, 6.2.4
2007 if (mmc->high_capacity && part_completed) {
2008 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2009 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2010 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2011 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2012 capacity *= MMC_MAX_BLOCK_LEN;
2013 mmc->capacity_user = capacity;
2016 /* Calculate the group size from the csd value. */
2017 int erase_gsz, erase_gmul;
2019 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2020 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2021 mmc->erase_grp_size = (erase_gsz + 1)
2025 mmc->hc_wp_grp_size = 1024
2026 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2027 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2029 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2034 static int mmc_startup(struct mmc *mmc)
2040 struct blk_desc *bdesc;
2042 #ifdef CONFIG_MMC_SPI_CRC_ON
2043 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2044 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2045 cmd.resp_type = MMC_RSP_R1;
2047 err = mmc_send_cmd(mmc, &cmd, NULL);
2053 /* Put the Card in Identify Mode */
2054 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2055 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2056 cmd.resp_type = MMC_RSP_R2;
2059 err = mmc_send_cmd(mmc, &cmd, NULL);
2061 #ifdef CONFIG_MMC_QUIRKS
2062 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2065 * It has been seen that SEND_CID may fail on the first
2066 * attempt, let's try a few more time
2069 err = mmc_send_cmd(mmc, &cmd, NULL);
2072 } while (retries--);
2079 memcpy(mmc->cid, cmd.response, 16);
2082 * For MMC cards, set the Relative Address.
2083 * For SD cards, get the Relatvie Address.
2084 * This also puts the cards into Standby State
2086 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2087 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2088 cmd.cmdarg = mmc->rca << 16;
2089 cmd.resp_type = MMC_RSP_R6;
2091 err = mmc_send_cmd(mmc, &cmd, NULL);
2097 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2100 /* Get the Card-Specific Data */
2101 cmd.cmdidx = MMC_CMD_SEND_CSD;
2102 cmd.resp_type = MMC_RSP_R2;
2103 cmd.cmdarg = mmc->rca << 16;
2105 err = mmc_send_cmd(mmc, &cmd, NULL);
2110 mmc->csd[0] = cmd.response[0];
2111 mmc->csd[1] = cmd.response[1];
2112 mmc->csd[2] = cmd.response[2];
2113 mmc->csd[3] = cmd.response[3];
2115 if (mmc->version == MMC_VERSION_UNKNOWN) {
2116 int version = (cmd.response[0] >> 26) & 0xf;
2120 mmc->version = MMC_VERSION_1_2;
2123 mmc->version = MMC_VERSION_1_4;
2126 mmc->version = MMC_VERSION_2_2;
2129 mmc->version = MMC_VERSION_3;
2132 mmc->version = MMC_VERSION_4;
2135 mmc->version = MMC_VERSION_1_2;
2140 /* divide frequency by 10, since the mults are 10x bigger */
2141 freq = fbase[(cmd.response[0] & 0x7)];
2142 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2144 mmc->legacy_speed = freq * mult;
2145 mmc_select_mode(mmc, MMC_LEGACY);
2147 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2148 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2151 mmc->write_bl_len = mmc->read_bl_len;
2153 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2155 if (mmc->high_capacity) {
2156 csize = (mmc->csd[1] & 0x3f) << 16
2157 | (mmc->csd[2] & 0xffff0000) >> 16;
2160 csize = (mmc->csd[1] & 0x3ff) << 2
2161 | (mmc->csd[2] & 0xc0000000) >> 30;
2162 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2165 mmc->capacity_user = (csize + 1) << (cmult + 2);
2166 mmc->capacity_user *= mmc->read_bl_len;
2167 mmc->capacity_boot = 0;
2168 mmc->capacity_rpmb = 0;
2169 for (i = 0; i < 4; i++)
2170 mmc->capacity_gp[i] = 0;
2172 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2173 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2175 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2176 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2178 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2179 cmd.cmdidx = MMC_CMD_SET_DSR;
2180 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2181 cmd.resp_type = MMC_RSP_NONE;
2182 if (mmc_send_cmd(mmc, &cmd, NULL))
2183 printf("MMC: SET_DSR failed\n");
2186 /* Select the card, and put it into Transfer Mode */
2187 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2188 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2189 cmd.resp_type = MMC_RSP_R1;
2190 cmd.cmdarg = mmc->rca << 16;
2191 err = mmc_send_cmd(mmc, &cmd, NULL);
2198 * For SD, its erase group is always one sector
2200 mmc->erase_grp_size = 1;
2201 mmc->part_config = MMCPART_NOAVAILABLE;
2203 err = mmc_startup_v4(mmc);
2207 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2212 err = sd_get_capabilities(mmc);
2215 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2217 err = mmc_get_capabilities(mmc);
2220 mmc_select_mode_and_width(mmc, mmc->card_caps);
2226 mmc->best_mode = mmc->selected_mode;
2228 /* Fix the block length for DDR mode */
2229 if (mmc->ddr_mode) {
2230 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2231 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2234 /* fill in device description */
2235 bdesc = mmc_get_blk_desc(mmc);
2239 bdesc->blksz = mmc->read_bl_len;
2240 bdesc->log2blksz = LOG2(bdesc->blksz);
2241 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2242 #if !defined(CONFIG_SPL_BUILD) || \
2243 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2244 !defined(CONFIG_USE_TINY_PRINTF))
2245 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2246 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2247 (mmc->cid[3] >> 16) & 0xffff);
2248 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2249 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2250 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2251 (mmc->cid[2] >> 24) & 0xff);
2252 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2253 (mmc->cid[2] >> 16) & 0xf);
2255 bdesc->vendor[0] = 0;
2256 bdesc->product[0] = 0;
2257 bdesc->revision[0] = 0;
2259 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
2266 static int mmc_send_if_cond(struct mmc *mmc)
2271 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2272 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2273 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2274 cmd.resp_type = MMC_RSP_R7;
2276 err = mmc_send_cmd(mmc, &cmd, NULL);
2281 if ((cmd.response[0] & 0xff) != 0xaa)
2284 mmc->version = SD_VERSION_2;
2289 #if !CONFIG_IS_ENABLED(DM_MMC)
2290 /* board-specific MMC power initializations. */
2291 __weak void board_mmc_power_init(void)
2296 static int mmc_power_init(struct mmc *mmc)
2298 #if CONFIG_IS_ENABLED(DM_MMC)
2299 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2302 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2305 debug("%s: No vmmc supply\n", mmc->dev->name);
2307 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2308 &mmc->vqmmc_supply);
2310 debug("%s: No vqmmc supply\n", mmc->dev->name);
2312 #else /* !CONFIG_DM_MMC */
2314 * Driver model should use a regulator, as above, rather than calling
2315 * out to board code.
2317 board_mmc_power_init();
2323 * put the host in the initial state:
2324 * - turn on Vdd (card power supply)
2325 * - configure the bus width and clock to minimal values
2327 static void mmc_set_initial_state(struct mmc *mmc)
2331 /* First try to set 3.3V. If it fails set to 1.8V */
2332 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2334 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2336 printf("mmc: failed to set signal voltage\n");
2338 mmc_select_mode(mmc, MMC_LEGACY);
2339 mmc_set_bus_width(mmc, 1);
2340 mmc_set_clock(mmc, 0, false);
2343 static int mmc_power_on(struct mmc *mmc)
2345 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2346 if (mmc->vmmc_supply) {
2347 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2350 puts("Error enabling VMMC supply\n");
2358 static int mmc_power_off(struct mmc *mmc)
2360 mmc_set_clock(mmc, 1, true);
2361 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2362 if (mmc->vmmc_supply) {
2363 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2366 debug("Error disabling VMMC supply\n");
2374 static int mmc_power_cycle(struct mmc *mmc)
2378 ret = mmc_power_off(mmc);
2382 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2383 * to be on the safer side.
2386 return mmc_power_on(mmc);
2389 int mmc_start_init(struct mmc *mmc)
2392 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2396 * all hosts are capable of 1 bit bus-width and able to use the legacy
2399 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2400 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2402 /* we pretend there's no card when init is NULL */
2403 no_card = mmc_getcd(mmc) == 0;
2404 #if !CONFIG_IS_ENABLED(DM_MMC)
2405 no_card = no_card || (mmc->cfg->ops->init == NULL);
2409 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2410 printf("MMC: no card present\n");
2418 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2419 mmc_adapter_card_type_ident();
2421 err = mmc_power_init(mmc);
2425 #ifdef CONFIG_MMC_QUIRKS
2426 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2427 MMC_QUIRK_RETRY_SEND_CID;
2430 err = mmc_power_cycle(mmc);
2433 * if power cycling is not supported, we should not try
2434 * to use the UHS modes, because we wouldn't be able to
2435 * recover from an error during the UHS initialization.
2437 debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2439 mmc->host_caps &= ~UHS_CAPS;
2440 err = mmc_power_on(mmc);
2445 #if CONFIG_IS_ENABLED(DM_MMC)
2446 /* The device has already been probed ready for use */
2448 /* made sure it's not NULL earlier */
2449 err = mmc->cfg->ops->init(mmc);
2456 mmc_set_initial_state(mmc);
2457 mmc_send_init_stream(mmc);
2459 /* Reset the Card */
2460 err = mmc_go_idle(mmc);
2465 /* The internal partition reset to user partition(0) at every CMD0*/
2466 mmc_get_blk_desc(mmc)->hwpart = 0;
2468 /* Test for SD version 2 */
2469 err = mmc_send_if_cond(mmc);
2471 /* Now try to get the SD card's operating condition */
2472 err = sd_send_op_cond(mmc, uhs_en);
2473 if (err && uhs_en) {
2475 mmc_power_cycle(mmc);
2479 /* If the command timed out, we check for an MMC card */
2480 if (err == -ETIMEDOUT) {
2481 err = mmc_send_op_cond(mmc);
2484 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2485 printf("Card did not respond to voltage select!\n");
2492 mmc->init_in_progress = 1;
2497 static int mmc_complete_init(struct mmc *mmc)
2501 mmc->init_in_progress = 0;
2502 if (mmc->op_cond_pending)
2503 err = mmc_complete_op_cond(mmc);
2506 err = mmc_startup(mmc);
2514 int mmc_init(struct mmc *mmc)
2517 __maybe_unused unsigned start;
2518 #if CONFIG_IS_ENABLED(DM_MMC)
2519 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2526 start = get_timer(0);
2528 if (!mmc->init_in_progress)
2529 err = mmc_start_init(mmc);
2532 err = mmc_complete_init(mmc);
2534 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2539 int mmc_set_dsr(struct mmc *mmc, u16 val)
2545 /* CPU-specific MMC initializations */
2546 __weak int cpu_mmc_init(bd_t *bis)
2551 /* board-specific MMC initializations. */
2552 __weak int board_mmc_init(bd_t *bis)
2557 void mmc_set_preinit(struct mmc *mmc, int preinit)
2559 mmc->preinit = preinit;
2562 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2563 static int mmc_probe(bd_t *bis)
2567 #elif CONFIG_IS_ENABLED(DM_MMC)
2568 static int mmc_probe(bd_t *bis)
2572 struct udevice *dev;
2574 ret = uclass_get(UCLASS_MMC, &uc);
2579 * Try to add them in sequence order. Really with driver model we
2580 * should allow holes, but the current MMC list does not allow that.
2581 * So if we request 0, 1, 3 we will get 0, 1, 2.
2583 for (i = 0; ; i++) {
2584 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2588 uclass_foreach_dev(dev, uc) {
2589 ret = device_probe(dev);
2591 printf("%s - probe failed: %d\n", dev->name, ret);
2597 static int mmc_probe(bd_t *bis)
2599 if (board_mmc_init(bis) < 0)
2606 int mmc_initialize(bd_t *bis)
2608 static int initialized = 0;
2610 if (initialized) /* Avoid initializing mmc multiple times */
2614 #if !CONFIG_IS_ENABLED(BLK)
2615 #if !CONFIG_IS_ENABLED(MMC_TINY)
2619 ret = mmc_probe(bis);
2623 #ifndef CONFIG_SPL_BUILD
2624 print_mmc_devices(',');
2631 #ifdef CONFIG_CMD_BKOPS_ENABLE
2632 int mmc_set_bkops_enable(struct mmc *mmc)
2635 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2637 err = mmc_send_ext_csd(mmc, ext_csd);
2639 puts("Could not get ext_csd register values\n");
2643 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2644 puts("Background operations not supported on device\n");
2645 return -EMEDIUMTYPE;
2648 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2649 puts("Background operations already enabled\n");
2653 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2655 puts("Failed to enable manual background operations\n");
2659 puts("Enabled manual background operations\n");