drivers/mmc/mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008, Freescale Semiconductor, Inc
   4  * Andy Fleming
   5  *
   6  * Based vaguely on the Linux code
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <command.h>
  12 #include <dm.h>
  13 #include <dm/device-internal.h>
  14 #include <errno.h>
  15 #include <mmc.h>
  16 #include <part.h>
  17 #include <power/regulator.h>
  18 #include <malloc.h>
  19 #include <memalign.h>
  20 #include <linux/list.h>
  21 #include <div64.h>
  22 #include "mmc_private.h"
  23
  24 #define DEFAULT_CMD6_TIMEOUT_MS  500
  25
  26 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  27
  28 #if !CONFIG_IS_ENABLED(DM_MMC)
  29
  30 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
  31 {
  32         return -ENOSYS;
  33 }
  34
  35 __weak int board_mmc_getwp(struct mmc *mmc)
  36 {
  37         return -1;
  38 }
  39
  40 int mmc_getwp(struct mmc *mmc)
  41 {
  42         int wp;
  43
  44         wp = board_mmc_getwp(mmc);
  45
  46         if (wp < 0) {
  47                 if (mmc->cfg->ops->getwp)
  48                         wp = mmc->cfg->ops->getwp(mmc);
  49                 else
  50                         wp = 0;
  51         }
  52
  53         return wp;
  54 }
  55
  56 __weak int board_mmc_getcd(struct mmc *mmc)
  57 {
  58         return -1;
  59 }
  60 #endif
  61
  62 #ifdef CONFIG_MMC_TRACE
  63 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  64 {
  65         printf("CMD_SEND:%d\n", cmd->cmdidx);
  66         printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  67 }
  68
  69 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  70 {
  71         int i;
  72         u8 *ptr;
  73
  74         if (ret) {
  75                 printf("\t\tRET\t\t\t %d\n", ret);
  76         } else {
  77                 switch (cmd->resp_type) {
  78                 case MMC_RSP_NONE:
  79                         printf("\t\tMMC_RSP_NONE\n");
  80                         break;
  81                 case MMC_RSP_R1:
  82                         printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  83                                 cmd->response[0]);
  84                         break;
  85                 case MMC_RSP_R1b:
  86                         printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  87                                 cmd->response[0]);
  88                         break;
  89                 case MMC_RSP_R2:
  90                         printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  91                                 cmd->response[0]);
  92                         printf("\t\t          \t\t 0x%08x \n",
  93                                 cmd->response[1]);
  94                         printf("\t\t          \t\t 0x%08x \n",
  95                                 cmd->response[2]);
  96                         printf("\t\t          \t\t 0x%08x \n",
  97                                 cmd->response[3]);
  98                         printf("\n");
  99                         printf("\t\t\t\t\tDUMPING DATA\n");
 100                         for (i = 0; i < 4; i++) {
 101                                 int j;
 102                                 printf("\t\t\t\t\t%03d - ", i*4);
 103                                 ptr = (u8 *)&cmd->response[i];
 104                                 ptr += 3;
 105                                 for (j = 0; j < 4; j++)
 106                                         printf("%02x ", *ptr--);
 107                                 printf("\n");
 108                         }
 109                         break;
 110                 case MMC_RSP_R3:
 111                         printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
 112                                 cmd->response[0]);
 113                         break;
 114                 default:
 115                         printf("\t\tERROR MMC rsp not supported\n");
 116                         break;
 117                 }
 118         }
 119 }
 120
 121 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
 122 {
 123         int status;
 124
 125         status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
 126         printf("CURR STATE:%d\n", status);
 127 }
 128 #endif
 129
 130 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
 131 const char *mmc_mode_name(enum bus_mode mode)
 132 {
 133         static const char *const names[] = {
 134               [MMC_LEGACY]      = "MMC legacy",
 135               [MMC_HS]          = "MMC High Speed (26MHz)",
 136               [SD_HS]           = "SD High Speed (50MHz)",
 137               [UHS_SDR12]       = "UHS SDR12 (25MHz)",
 138               [UHS_SDR25]       = "UHS SDR25 (50MHz)",
 139               [UHS_SDR50]       = "UHS SDR50 (100MHz)",
 140               [UHS_SDR104]      = "UHS SDR104 (208MHz)",
 141               [UHS_DDR50]       = "UHS DDR50 (50MHz)",
 142               [MMC_HS_52]       = "MMC High Speed (52MHz)",
 143               [MMC_DDR_52]      = "MMC DDR52 (52MHz)",
 144               [MMC_HS_200]      = "HS200 (200MHz)",
 145               [MMC_HS_400]      = "HS400 (200MHz)",
 146               [MMC_HS_400_ES]   = "HS400ES (200MHz)",
 147         };
 148
 149         if (mode >= MMC_MODES_END)
 150                 return "Unknown mode";
 151         else
 152                 return names[mode];
 153 }
 154 #endif
 155
 156 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
 157 {
 158         static const int freqs[] = {
 159               [MMC_LEGACY]      = 25000000,
 160               [MMC_HS]          = 26000000,
 161               [SD_HS]           = 50000000,
 162               [MMC_HS_52]       = 52000000,
 163               [MMC_DDR_52]      = 52000000,
 164               [UHS_SDR12]       = 25000000,
 165               [UHS_SDR25]       = 50000000,
 166               [UHS_SDR50]       = 100000000,
 167               [UHS_DDR50]       = 50000000,
 168               [UHS_SDR104]      = 208000000,
 169               [MMC_HS_200]      = 200000000,
 170               [MMC_HS_400]      = 200000000,
 171               [MMC_HS_400_ES]   = 200000000,
 172         };
 173
 174         if (mode == MMC_LEGACY)
 175                 return mmc->legacy_speed;
 176         else if (mode >= MMC_MODES_END)
 177                 return 0;
 178         else
 179                 return freqs[mode];
 180 }
 181
 182 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
 183 {
 184         mmc->selected_mode = mode;
 185         mmc->tran_speed = mmc_mode2freq(mmc, mode);
 186         mmc->ddr_mode = mmc_is_mode_ddr(mode);
 187         pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
 188                  mmc->tran_speed / 1000000);
 189         return 0;
 190 }
 191
 192 #if !CONFIG_IS_ENABLED(DM_MMC)
 193 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 194 {
 195         int ret;
 196
 197         mmmc_trace_before_send(mmc, cmd);
 198         ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 199         mmmc_trace_after_send(mmc, cmd, ret);
 200
 201         return ret;
 202 }
 203 #endif
 204
 205 int mmc_send_status(struct mmc *mmc, unsigned int *status)
 206 {
 207         struct mmc_cmd cmd;
 208         int err, retries = 5;
 209
 210         cmd.cmdidx = MMC_CMD_SEND_STATUS;
 211         cmd.resp_type = MMC_RSP_R1;
 212         if (!mmc_host_is_spi(mmc))
 213                 cmd.cmdarg = mmc->rca << 16;
 214
 215         while (retries--) {
 216                 err = mmc_send_cmd(mmc, &cmd, NULL);
 217                 if (!err) {
 218                         mmc_trace_state(mmc, &cmd);
 219                         *status = cmd.response[0];
 220                         return 0;
 221                 }
 222         }
 223         mmc_trace_state(mmc, &cmd);
 224         return -ECOMM;
 225 }
 226
 227 int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
 228 {
 229         unsigned int status;
 230         int err;
 231
 232         err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 233         if (err != -ENOSYS)
 234                 return err;
 235
 236         while (1) {
 237                 err = mmc_send_status(mmc, &status);
 238                 if (err)
 239                         return err;
 240
 241                 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
 242                     (status & MMC_STATUS_CURR_STATE) !=
 243                      MMC_STATE_PRG)
 244                         break;
 245
 246                 if (status & MMC_STATUS_MASK) {
 247 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 248                         pr_err("Status Error: 0x%08x\n", status);
 249 #endif
 250                         return -ECOMM;
 251                 }
 252
 253                 if (timeout_ms-- <= 0)
 254                         break;
 255
 256                 udelay(1000);
 257         }
 258
 259         if (timeout_ms <= 0) {
 260 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 261                 pr_err("Timeout waiting card ready\n");
 262 #endif
 263                 return -ETIMEDOUT;
 264         }
 265
 266         return 0;
 267 }
 268
 269 int mmc_set_blocklen(struct mmc *mmc, int len)
 270 {
 271         struct mmc_cmd cmd;
 272         int err;
 273
 274         if (mmc->ddr_mode)
 275                 return 0;
 276
 277         cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
 278         cmd.resp_type = MMC_RSP_R1;
 279         cmd.cmdarg = len;
 280
 281         err = mmc_send_cmd(mmc, &cmd, NULL);
 282
 283 #ifdef CONFIG_MMC_QUIRKS
 284         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
 285                 int retries = 4;
 286                 /*
 287                  * It has been seen that SET_BLOCKLEN may fail on the first
 288                  * attempt, let's try a few more time
 289                  */
 290                 do {
 291                         err = mmc_send_cmd(mmc, &cmd, NULL);
 292                         if (!err)
 293                                 break;
 294                 } while (retries--);
 295         }
 296 #endif
 297
 298         return err;
 299 }
 300
 301 #ifdef MMC_SUPPORTS_TUNING
 302 static const u8 tuning_blk_pattern_4bit[] = {
 303         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 304         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 305         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 306         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 307         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 308         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 309         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 310         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 311 };
 312
 313 static const u8 tuning_blk_pattern_8bit[] = {
 314         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 315         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 316         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 317         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 318         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 319         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 320         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 321         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 322         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 323         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 324         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 325         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 326         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 327         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 328         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 329         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 330 };
 331
 332 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
 333 {
 334         struct mmc_cmd cmd;
 335         struct mmc_data data;
 336         const u8 *tuning_block_pattern;
 337         int size, err;
 338
 339         if (mmc->bus_width == 8) {
 340                 tuning_block_pattern = tuning_blk_pattern_8bit;
 341                 size = sizeof(tuning_blk_pattern_8bit);
 342         } else if (mmc->bus_width == 4) {
 343                 tuning_block_pattern = tuning_blk_pattern_4bit;
 344                 size = sizeof(tuning_blk_pattern_4bit);
 345         } else {
 346                 return -EINVAL;
 347         }
 348
 349         ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
 350
 351         cmd.cmdidx = opcode;
 352         cmd.cmdarg = 0;
 353         cmd.resp_type = MMC_RSP_R1;
 354
 355         data.dest = (void *)data_buf;
 356         data.blocks = 1;
 357         data.blocksize = size;
 358         data.flags = MMC_DATA_READ;
 359
 360         err = mmc_send_cmd(mmc, &cmd, &data);
 361         if (err)
 362                 return err;
 363
 364         if (memcmp(data_buf, tuning_block_pattern, size))
 365                 return -EIO;
 366
 367         return 0;
 368 }
 369 #endif
 370
 371 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 372                            lbaint_t blkcnt)
 373 {
 374         struct mmc_cmd cmd;
 375         struct mmc_data data;
 376
 377         if (blkcnt > 1)
 378                 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
 379         else
 380                 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
 381
 382         if (mmc->high_capacity)
 383                 cmd.cmdarg = start;
 384         else
 385                 cmd.cmdarg = start * mmc->read_bl_len;
 386
 387         cmd.resp_type = MMC_RSP_R1;
 388
 389         data.dest = dst;
 390         data.blocks = blkcnt;
 391         data.blocksize = mmc->read_bl_len;
 392         data.flags = MMC_DATA_READ;
 393
 394         if (mmc_send_cmd(mmc, &cmd, &data))
 395                 return 0;
 396
 397         if (blkcnt > 1) {
 398                 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 399                 cmd.cmdarg = 0;
 400                 cmd.resp_type = MMC_RSP_R1b;
 401                 if (mmc_send_cmd(mmc, &cmd, NULL)) {
 402 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 403                         pr_err("mmc fail to send stop cmd\n");
 404 #endif
 405                         return 0;
 406                 }
 407         }
 408
 409         return blkcnt;
 410 }
 411
 412 #if CONFIG_IS_ENABLED(BLK)
 413 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
 414 #else
 415 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 416                 void *dst)
 417 #endif
 418 {
 419 #if CONFIG_IS_ENABLED(BLK)
 420         struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 421 #endif
 422         int dev_num = block_dev->devnum;
 423         int err;
 424         lbaint_t cur, blocks_todo = blkcnt;
 425
 426         if (blkcnt == 0)
 427                 return 0;
 428
 429         struct mmc *mmc = find_mmc_device(dev_num);
 430         if (!mmc)
 431                 return 0;
 432
 433         if (CONFIG_IS_ENABLED(MMC_TINY))
 434                 err = mmc_switch_part(mmc, block_dev->hwpart);
 435         else
 436                 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
 437
 438         if (err < 0)
 439                 return 0;
 440
 441         if ((start + blkcnt) > block_dev->lba) {
 442 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 443                 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
 444                        start + blkcnt, block_dev->lba);
 445 #endif
 446                 return 0;
 447         }
 448
 449         if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
 450                 pr_debug("%s: Failed to set blocklen\n", __func__);
 451                 return 0;
 452         }
 453
 454         do {
 455                 cur = (blocks_todo > mmc->cfg->b_max) ?
 456                         mmc->cfg->b_max : blocks_todo;
 457                 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
 458                         pr_debug("%s: Failed to read blocks\n", __func__);
 459                         return 0;
 460                 }
 461                 blocks_todo -= cur;
 462                 start += cur;
 463                 dst += cur * mmc->read_bl_len;
 464         } while (blocks_todo > 0);
 465
 466         return blkcnt;
 467 }
 468
 469 static int mmc_go_idle(struct mmc *mmc)
 470 {
 471         struct mmc_cmd cmd;
 472         int err;
 473
 474         udelay(1000);
 475
 476         cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
 477         cmd.cmdarg = 0;
 478         cmd.resp_type = MMC_RSP_NONE;
 479
 480         err = mmc_send_cmd(mmc, &cmd, NULL);
 481
 482         if (err)
 483                 return err;
 484
 485         udelay(2000);
 486
 487         return 0;
 488 }
 489
 490 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 491 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
 492 {
 493         struct mmc_cmd cmd;
 494         int err = 0;
 495
 496         /*
 497          * Send CMD11 only if the request is to switch the card to
 498          * 1.8V signalling.
 499          */
 500         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 501                 return mmc_set_signal_voltage(mmc, signal_voltage);
 502
 503         cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
 504         cmd.cmdarg = 0;
 505         cmd.resp_type = MMC_RSP_R1;
 506
 507         err = mmc_send_cmd(mmc, &cmd, NULL);
 508         if (err)
 509                 return err;
 510
 511         if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
 512                 return -EIO;
 513
 514         /*
 515          * The card should drive cmd and dat[0:3] low immediately
 516          * after the response of cmd11, but wait 100 us to be sure
 517          */
 518         err = mmc_wait_dat0(mmc, 0, 100);
 519         if (err == -ENOSYS)
 520                 udelay(100);
 521         else if (err)
 522                 return -ETIMEDOUT;
 523
 524         /*
 525          * During a signal voltage level switch, the clock must be gated
 526          * for 5 ms according to the SD spec
 527          */
 528         mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
 529
 530         err = mmc_set_signal_voltage(mmc, signal_voltage);
 531         if (err)
 532                 return err;
 533
 534         /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
 535         mdelay(10);
 536         mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
 537
 538         /*
 539          * Failure to switch is indicated by the card holding
 540          * dat[0:3] low. Wait for at least 1 ms according to spec
 541          */
 542         err = mmc_wait_dat0(mmc, 1, 1000);
 543         if (err == -ENOSYS)
 544                 udelay(1000);
 545         else if (err)
 546                 return -ETIMEDOUT;
 547
 548         return 0;
 549 }
 550 #endif
 551
 552 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
 553 {
 554         int timeout = 1000;
 555         int err;
 556         struct mmc_cmd cmd;
 557
 558         while (1) {
 559                 cmd.cmdidx = MMC_CMD_APP_CMD;
 560                 cmd.resp_type = MMC_RSP_R1;
 561                 cmd.cmdarg = 0;
 562
 563                 err = mmc_send_cmd(mmc, &cmd, NULL);
 564
 565                 if (err)
 566                         return err;
 567
 568                 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
 569                 cmd.resp_type = MMC_RSP_R3;
 570
 571                 /*
 572                  * Most cards do not answer if some reserved bits
 573                  * in the ocr are set. However, Some controller
 574                  * can set bit 7 (reserved for low voltages), but
 575                  * how to manage low voltages SD card is not yet
 576                  * specified.
 577                  */
 578                 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
 579                         (mmc->cfg->voltages & 0xff8000);
 580
 581                 if (mmc->version == SD_VERSION_2)
 582                         cmd.cmdarg |= OCR_HCS;
 583
 584                 if (uhs_en)
 585                         cmd.cmdarg |= OCR_S18R;
 586
 587                 err = mmc_send_cmd(mmc, &cmd, NULL);
 588
 589                 if (err)
 590                         return err;
 591
 592                 if (cmd.response[0] & OCR_BUSY)
 593                         break;
 594
 595                 if (timeout-- <= 0)
 596                         return -EOPNOTSUPP;
 597
 598                 udelay(1000);
 599         }
 600
 601         if (mmc->version != SD_VERSION_2)
 602                 mmc->version = SD_VERSION_1_0;
 603
 604         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 605                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 606                 cmd.resp_type = MMC_RSP_R3;
 607                 cmd.cmdarg = 0;
 608
 609                 err = mmc_send_cmd(mmc, &cmd, NULL);
 610
 611                 if (err)
 612                         return err;
 613         }
 614
 615         mmc->ocr = cmd.response[0];
 616
 617 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 618         if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
 619             == 0x41000000) {
 620                 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
 621                 if (err)
 622                         return err;
 623         }
 624 #endif
 625
 626         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 627         mmc->rca = 0;
 628
 629         return 0;
 630 }
 631
 632 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
 633 {
 634         struct mmc_cmd cmd;
 635         int err;
 636
 637         cmd.cmdidx = MMC_CMD_SEND_OP_COND;
 638         cmd.resp_type = MMC_RSP_R3;
 639         cmd.cmdarg = 0;
 640         if (use_arg && !mmc_host_is_spi(mmc))
 641                 cmd.cmdarg = OCR_HCS |
 642                         (mmc->cfg->voltages &
 643                         (mmc->ocr & OCR_VOLTAGE_MASK)) |
 644                         (mmc->ocr & OCR_ACCESS_MODE);
 645
 646         err = mmc_send_cmd(mmc, &cmd, NULL);
 647         if (err)
 648                 return err;
 649         mmc->ocr = cmd.response[0];
 650         return 0;
 651 }
 652
 653 static int mmc_send_op_cond(struct mmc *mmc)
 654 {
 655         int err, i;
 656
 657         /* Some cards seem to need this */
 658         mmc_go_idle(mmc);
 659
 660         /* Asking to the card its capabilities */
 661         for (i = 0; i < 2; i++) {
 662                 err = mmc_send_op_cond_iter(mmc, i != 0);
 663                 if (err)
 664                         return err;
 665
 666                 /* exit if not busy (flag seems to be inverted) */
 667                 if (mmc->ocr & OCR_BUSY)
 668                         break;
 669         }
 670         mmc->op_cond_pending = 1;
 671         return 0;
 672 }
 673
 674 static int mmc_complete_op_cond(struct mmc *mmc)
 675 {
 676         struct mmc_cmd cmd;
 677         int timeout = 1000;
 678         ulong start;
 679         int err;
 680
 681         mmc->op_cond_pending = 0;
 682         if (!(mmc->ocr & OCR_BUSY)) {
 683                 /* Some cards seem to need this */
 684                 mmc_go_idle(mmc);
 685
 686                 start = get_timer(0);
 687                 while (1) {
 688                         err = mmc_send_op_cond_iter(mmc, 1);
 689                         if (err)
 690                                 return err;
 691                         if (mmc->ocr & OCR_BUSY)
 692                                 break;
 693                         if (get_timer(start) > timeout)
 694                                 return -EOPNOTSUPP;
 695                         udelay(100);
 696                 }
 697         }
 698
 699         if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 700                 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 701                 cmd.resp_type = MMC_RSP_R3;
 702                 cmd.cmdarg = 0;
 703
 704                 err = mmc_send_cmd(mmc, &cmd, NULL);
 705
 706                 if (err)
 707                         return err;
 708
 709                 mmc->ocr = cmd.response[0];
 710         }
 711
 712         mmc->version = MMC_VERSION_UNKNOWN;
 713
 714         mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 715         mmc->rca = 1;
 716
 717         return 0;
 718 }
 719
 720
 721 int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 722 {
 723         struct mmc_cmd cmd;
 724         struct mmc_data data;
 725         int err;
 726
 727         /* Get the Card Status Register */
 728         cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
 729         cmd.resp_type = MMC_RSP_R1;
 730         cmd.cmdarg = 0;
 731
 732         data.dest = (char *)ext_csd;
 733         data.blocks = 1;
 734         data.blocksize = MMC_MAX_BLOCK_LEN;
 735         data.flags = MMC_DATA_READ;
 736
 737         err = mmc_send_cmd(mmc, &cmd, &data);
 738
 739         return err;
 740 }
 741
 742 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 743                         bool send_status)
 744 {
 745         unsigned int status, start;
 746         struct mmc_cmd cmd;
 747         int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
 748         bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
 749                               (index == EXT_CSD_PART_CONF);
 750         int retries = 3;
 751         int ret;
 752
 753         if (mmc->gen_cmd6_time)
 754                 timeout_ms = mmc->gen_cmd6_time * 10;
 755
 756         if (is_part_switch  && mmc->part_switch_time)
 757                 timeout_ms = mmc->part_switch_time * 10;
 758
 759         cmd.cmdidx = MMC_CMD_SWITCH;
 760         cmd.resp_type = MMC_RSP_R1b;
 761         cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
 762                                  (index << 16) |
 763                                  (value << 8);
 764
 765         do {
 766                 ret = mmc_send_cmd(mmc, &cmd, NULL);
 767         } while (ret && retries-- > 0);
 768
 769         if (ret)
 770                 return ret;
 771
 772         start = get_timer(0);
 773
 774         /* poll dat0 for rdy/buys status */
 775         ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
 776         if (ret && ret != -ENOSYS)
 777                 return ret;
 778
 779         /*
 780          * In cases when not allowed to poll by using CMD13 or because we aren't
 781          * capable of polling by using mmc_wait_dat0, then rely on waiting the
 782          * stated timeout to be sufficient.
 783          */
 784         if (ret == -ENOSYS && !send_status)
 785                 mdelay(timeout_ms);
 786
 787         /* Finally wait until the card is ready or indicates a failure
 788          * to switch. It doesn't hurt to use CMD13 here even if send_status
 789          * is false, because by now (after 'timeout_ms' ms) the bus should be
 790          * reliable.
 791          */
 792         do {
 793                 ret = mmc_send_status(mmc, &status);
 794
 795                 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
 796                         pr_debug("switch failed %d/%d/0x%x !\n", set, index,
 797                                  value);
 798                         return -EIO;
 799                 }
 800                 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
 801                         return 0;
 802                 udelay(100);
 803         } while (get_timer(start) < timeout_ms);
 804
 805         return -ETIMEDOUT;
 806 }
 807
 808 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 809 {
 810         return __mmc_switch(mmc, set, index, value, true);
 811 }
 812
 813 int mmc_boot_wp(struct mmc *mmc)
 814 {
 815         return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
 816 }
 817
 818 #if !CONFIG_IS_ENABLED(MMC_TINY)
 819 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
 820                               bool hsdowngrade)
 821 {
 822         int err;
 823         int speed_bits;
 824
 825         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 826
 827         switch (mode) {
 828         case MMC_HS:
 829         case MMC_HS_52:
 830         case MMC_DDR_52:
 831                 speed_bits = EXT_CSD_TIMING_HS;
 832                 break;
 833 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 834         case MMC_HS_200:
 835                 speed_bits = EXT_CSD_TIMING_HS200;
 836                 break;
 837 #endif
 838 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 839         case MMC_HS_400:
 840                 speed_bits = EXT_CSD_TIMING_HS400;
 841                 break;
 842 #endif
 843 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 844         case MMC_HS_400_ES:
 845                 speed_bits = EXT_CSD_TIMING_HS400;
 846                 break;
 847 #endif
 848         case MMC_LEGACY:
 849                 speed_bits = EXT_CSD_TIMING_LEGACY;
 850                 break;
 851         default:
 852                 return -EINVAL;
 853         }
 854
 855         err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
 856                            speed_bits, !hsdowngrade);
 857         if (err)
 858                 return err;
 859
 860 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 861     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 862         /*
 863          * In case the eMMC is in HS200/HS400 mode and we are downgrading
 864          * to HS mode, the card clock are still running much faster than
 865          * the supported HS mode clock, so we can not reliably read out
 866          * Extended CSD. Reconfigure the controller to run at HS mode.
 867          */
 868         if (hsdowngrade) {
 869                 mmc_select_mode(mmc, MMC_HS);
 870                 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
 871         }
 872 #endif
 873
 874         if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
 875                 /* Now check to see that it worked */
 876                 err = mmc_send_ext_csd(mmc, test_csd);
 877                 if (err)
 878                         return err;
 879
 880                 /* No high-speed support */
 881                 if (!test_csd[EXT_CSD_HS_TIMING])
 882                         return -ENOTSUPP;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int mmc_get_capabilities(struct mmc *mmc)
 889 {
 890         u8 *ext_csd = mmc->ext_csd;
 891         char cardtype;
 892
 893         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
 894
 895         if (mmc_host_is_spi(mmc))
 896                 return 0;
 897
 898         /* Only version 4 supports high-speed */
 899         if (mmc->version < MMC_VERSION_4)
 900                 return 0;
 901
 902         if (!ext_csd) {
 903                 pr_err("No ext_csd found!\n"); /* this should enver happen */
 904                 return -ENOTSUPP;
 905         }
 906
 907         mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
 908
 909         cardtype = ext_csd[EXT_CSD_CARD_TYPE];
 910         mmc->cardtype = cardtype;
 911
 912 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 913         if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
 914                         EXT_CSD_CARD_TYPE_HS200_1_8V)) {
 915                 mmc->card_caps |= MMC_MODE_HS200;
 916         }
 917 #endif
 918 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
 919         CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 920         if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
 921                         EXT_CSD_CARD_TYPE_HS400_1_8V)) {
 922                 mmc->card_caps |= MMC_MODE_HS400;
 923         }
 924 #endif
 925         if (cardtype & EXT_CSD_CARD_TYPE_52) {
 926                 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
 927                         mmc->card_caps |= MMC_MODE_DDR_52MHz;
 928                 mmc->card_caps |= MMC_MODE_HS_52MHz;
 929         }
 930         if (cardtype & EXT_CSD_CARD_TYPE_26)
 931                 mmc->card_caps |= MMC_MODE_HS;
 932
 933 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
 934         if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
 935             (mmc->card_caps & MMC_MODE_HS400)) {
 936                 mmc->card_caps |= MMC_MODE_HS400_ES;
 937         }
 938 #endif
 939
 940         return 0;
 941 }
 942 #endif
 943
 944 static int mmc_set_capacity(struct mmc *mmc, int part_num)
 945 {
 946         switch (part_num) {
 947         case 0:
 948                 mmc->capacity = mmc->capacity_user;
 949                 break;
 950         case 1:
 951         case 2:
 952                 mmc->capacity = mmc->capacity_boot;
 953                 break;
 954         case 3:
 955                 mmc->capacity = mmc->capacity_rpmb;
 956                 break;
 957         case 4:
 958         case 5:
 959         case 6:
 960         case 7:
 961                 mmc->capacity = mmc->capacity_gp[part_num - 4];
 962                 break;
 963         default:
 964                 return -1;
 965         }
 966
 967         mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 968
 969         return 0;
 970 }
 971
 972 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 973 {
 974         int ret;
 975         int retry = 3;
 976
 977         do {
 978                 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 979                                  EXT_CSD_PART_CONF,
 980                                  (mmc->part_config & ~PART_ACCESS_MASK)
 981                                  | (part_num & PART_ACCESS_MASK));
 982         } while (ret && retry--);
 983
 984         /*
 985          * Set the capacity if the switch succeeded or was intended
 986          * to return to representing the raw device.
 987          */
 988         if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
 989                 ret = mmc_set_capacity(mmc, part_num);
 990                 mmc_get_blk_desc(mmc)->hwpart = part_num;
 991         }
 992
 993         return ret;
 994 }
 995
 996 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
 997 int mmc_hwpart_config(struct mmc *mmc,
 998                       const struct mmc_hwpart_conf *conf,
 999                       enum mmc_hwpart_conf_mode mode)
1000 {
1001         u8 part_attrs = 0;
1002         u32 enh_size_mult;
1003         u32 enh_start_addr;
1004         u32 gp_size_mult[4];
1005         u32 max_enh_size_mult;
1006         u32 tot_enh_size_mult = 0;
1007         u8 wr_rel_set;
1008         int i, pidx, err;
1009         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1010
1011         if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1012                 return -EINVAL;
1013
1014         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
1015                 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
1016                 return -EMEDIUMTYPE;
1017         }
1018
1019         if (!(mmc->part_support & PART_SUPPORT)) {
1020                 pr_err("Card does not support partitioning\n");
1021                 return -EMEDIUMTYPE;
1022         }
1023
1024         if (!mmc->hc_wp_grp_size) {
1025                 pr_err("Card does not define HC WP group size\n");
1026                 return -EMEDIUMTYPE;
1027         }
1028
1029         /* check partition alignment and total enhanced size */
1030         if (conf->user.enh_size) {
1031                 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1032                     conf->user.enh_start % mmc->hc_wp_grp_size) {
1033                         pr_err("User data enhanced area not HC WP group "
1034                                "size aligned\n");
1035                         return -EINVAL;
1036                 }
1037                 part_attrs |= EXT_CSD_ENH_USR;
1038                 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1039                 if (mmc->high_capacity) {
1040                         enh_start_addr = conf->user.enh_start;
1041                 } else {
1042                         enh_start_addr = (conf->user.enh_start << 9);
1043                 }
1044         } else {
1045                 enh_size_mult = 0;
1046                 enh_start_addr = 0;
1047         }
1048         tot_enh_size_mult += enh_size_mult;
1049
1050         for (pidx = 0; pidx < 4; pidx++) {
1051                 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1052                         pr_err("GP%i partition not HC WP group size "
1053                                "aligned\n", pidx+1);
1054                         return -EINVAL;
1055                 }
1056                 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1057                 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1058                         part_attrs |= EXT_CSD_ENH_GP(pidx);
1059                         tot_enh_size_mult += gp_size_mult[pidx];
1060                 }
1061         }
1062
1063         if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1064                 pr_err("Card does not support enhanced attribute\n");
1065                 return -EMEDIUMTYPE;
1066         }
1067
1068         err = mmc_send_ext_csd(mmc, ext_csd);
1069         if (err)
1070                 return err;
1071
1072         max_enh_size_mult =
1073                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1074                 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1075                 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1076         if (tot_enh_size_mult > max_enh_size_mult) {
1077                 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1078                        tot_enh_size_mult, max_enh_size_mult);
1079                 return -EMEDIUMTYPE;
1080         }
1081
1082         /* The default value of EXT_CSD_WR_REL_SET is device
1083          * dependent, the values can only be changed if the
1084          * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1085          * changed only once and before partitioning is completed. */
1086         wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1087         if (conf->user.wr_rel_change) {
1088                 if (conf->user.wr_rel_set)
1089                         wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1090                 else
1091                         wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1092         }
1093         for (pidx = 0; pidx < 4; pidx++) {
1094                 if (conf->gp_part[pidx].wr_rel_change) {
1095                         if (conf->gp_part[pidx].wr_rel_set)
1096                                 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1097                         else
1098                                 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1099                 }
1100         }
1101
1102         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1103             !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1104                 puts("Card does not support host controlled partition write "
1105                      "reliability settings\n");
1106                 return -EMEDIUMTYPE;
1107         }
1108
1109         if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1110             EXT_CSD_PARTITION_SETTING_COMPLETED) {
1111                 pr_err("Card already partitioned\n");
1112                 return -EPERM;
1113         }
1114
1115         if (mode == MMC_HWPART_CONF_CHECK)
1116                 return 0;
1117
1118         /* Partitioning requires high-capacity size definitions */
1119         if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1120                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1121                                  EXT_CSD_ERASE_GROUP_DEF, 1);
1122
1123                 if (err)
1124                         return err;
1125
1126                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1127
1128 #if CONFIG_IS_ENABLED(MMC_WRITE)
1129                 /* update erase group size to be high-capacity */
1130                 mmc->erase_grp_size =
1131                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1132 #endif
1133
1134         }
1135
1136         /* all OK, write the configuration */
1137         for (i = 0; i < 4; i++) {
1138                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1139                                  EXT_CSD_ENH_START_ADDR+i,
1140                                  (enh_start_addr >> (i*8)) & 0xFF);
1141                 if (err)
1142                         return err;
1143         }
1144         for (i = 0; i < 3; i++) {
1145                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1146                                  EXT_CSD_ENH_SIZE_MULT+i,
1147                                  (enh_size_mult >> (i*8)) & 0xFF);
1148                 if (err)
1149                         return err;
1150         }
1151         for (pidx = 0; pidx < 4; pidx++) {
1152                 for (i = 0; i < 3; i++) {
1153                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1154                                          EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1155                                          (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1156                         if (err)
1157                                 return err;
1158                 }
1159         }
1160         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1161                          EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1162         if (err)
1163                 return err;
1164
1165         if (mode == MMC_HWPART_CONF_SET)
1166                 return 0;
1167
1168         /* The WR_REL_SET is a write-once register but shall be
1169          * written before setting PART_SETTING_COMPLETED. As it is
1170          * write-once we can only write it when completing the
1171          * partitioning. */
1172         if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1173                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1174                                  EXT_CSD_WR_REL_SET, wr_rel_set);
1175                 if (err)
1176                         return err;
1177         }
1178
1179         /* Setting PART_SETTING_COMPLETED confirms the partition
1180          * configuration but it only becomes effective after power
1181          * cycle, so we do not adjust the partition related settings
1182          * in the mmc struct. */
1183
1184         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1185                          EXT_CSD_PARTITION_SETTING,
1186                          EXT_CSD_PARTITION_SETTING_COMPLETED);
1187         if (err)
1188                 return err;
1189
1190         return 0;
1191 }
1192 #endif
1193
1194 #if !CONFIG_IS_ENABLED(DM_MMC)
1195 int mmc_getcd(struct mmc *mmc)
1196 {
1197         int cd;
1198
1199         cd = board_mmc_getcd(mmc);
1200
1201         if (cd < 0) {
1202                 if (mmc->cfg->ops->getcd)
1203                         cd = mmc->cfg->ops->getcd(mmc);
1204                 else
1205                         cd = 1;
1206         }
1207
1208         return cd;
1209 }
1210 #endif
1211
1212 #if !CONFIG_IS_ENABLED(MMC_TINY)
1213 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1214 {
1215         struct mmc_cmd cmd;
1216         struct mmc_data data;
1217
1218         /* Switch the frequency */
1219         cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1220         cmd.resp_type = MMC_RSP_R1;
1221         cmd.cmdarg = (mode << 31) | 0xffffff;
1222         cmd.cmdarg &= ~(0xf << (group * 4));
1223         cmd.cmdarg |= value << (group * 4);
1224
1225         data.dest = (char *)resp;
1226         data.blocksize = 64;
1227         data.blocks = 1;
1228         data.flags = MMC_DATA_READ;
1229
1230         return mmc_send_cmd(mmc, &cmd, &data);
1231 }
1232
1233 static int sd_get_capabilities(struct mmc *mmc)
1234 {
1235         int err;
1236         struct mmc_cmd cmd;
1237         ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1238         ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1239         struct mmc_data data;
1240         int timeout;
1241 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1242         u32 sd3_bus_mode;
1243 #endif
1244
1245         mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
1246
1247         if (mmc_host_is_spi(mmc))
1248                 return 0;
1249
1250         /* Read the SCR to find out if this card supports higher speeds */
1251         cmd.cmdidx = MMC_CMD_APP_CMD;
1252         cmd.resp_type = MMC_RSP_R1;
1253         cmd.cmdarg = mmc->rca << 16;
1254
1255         err = mmc_send_cmd(mmc, &cmd, NULL);
1256
1257         if (err)
1258                 return err;
1259
1260         cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1261         cmd.resp_type = MMC_RSP_R1;
1262         cmd.cmdarg = 0;
1263
1264         timeout = 3;
1265
1266 retry_scr:
1267         data.dest = (char *)scr;
1268         data.blocksize = 8;
1269         data.blocks = 1;
1270         data.flags = MMC_DATA_READ;
1271
1272         err = mmc_send_cmd(mmc, &cmd, &data);
1273
1274         if (err) {
1275                 if (timeout--)
1276                         goto retry_scr;
1277
1278                 return err;
1279         }
1280
1281         mmc->scr[0] = __be32_to_cpu(scr[0]);
1282         mmc->scr[1] = __be32_to_cpu(scr[1]);
1283
1284         switch ((mmc->scr[0] >> 24) & 0xf) {
1285         case 0:
1286                 mmc->version = SD_VERSION_1_0;
1287                 break;
1288         case 1:
1289                 mmc->version = SD_VERSION_1_10;
1290                 break;
1291         case 2:
1292                 mmc->version = SD_VERSION_2;
1293                 if ((mmc->scr[0] >> 15) & 0x1)
1294                         mmc->version = SD_VERSION_3;
1295                 break;
1296         default:
1297                 mmc->version = SD_VERSION_1_0;
1298                 break;
1299         }
1300
1301         if (mmc->scr[0] & SD_DATA_4BIT)
1302                 mmc->card_caps |= MMC_MODE_4BIT;
1303
1304         /* Version 1.0 doesn't support switching */
1305         if (mmc->version == SD_VERSION_1_0)
1306                 return 0;
1307
1308         timeout = 4;
1309         while (timeout--) {
1310                 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1311                                 (u8 *)switch_status);
1312
1313                 if (err)
1314                         return err;
1315
1316                 /* The high-speed function is busy.  Try again */
1317                 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1318                         break;
1319         }
1320
1321         /* If high-speed isn't supported, we return */
1322         if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1323                 mmc->card_caps |= MMC_CAP(SD_HS);
1324
1325 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1326         /* Version before 3.0 don't support UHS modes */
1327         if (mmc->version < SD_VERSION_3)
1328                 return 0;
1329
1330         sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1331         if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1332                 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1333         if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1334                 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1335         if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1336                 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1337         if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1338                 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1339         if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1340                 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1341 #endif
1342
1343         return 0;
1344 }
1345
1346 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1347 {
1348         int err;
1349
1350         ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1351         int speed;
1352
1353         /* SD version 1.00 and 1.01 does not support CMD 6 */
1354         if (mmc->version == SD_VERSION_1_0)
1355                 return 0;
1356
1357         switch (mode) {
1358         case MMC_LEGACY:
1359                 speed = UHS_SDR12_BUS_SPEED;
1360                 break;
1361         case SD_HS:
1362                 speed = HIGH_SPEED_BUS_SPEED;
1363                 break;
1364 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1365         case UHS_SDR12:
1366                 speed = UHS_SDR12_BUS_SPEED;
1367                 break;
1368         case UHS_SDR25:
1369                 speed = UHS_SDR25_BUS_SPEED;
1370                 break;
1371         case UHS_SDR50:
1372                 speed = UHS_SDR50_BUS_SPEED;
1373                 break;
1374         case UHS_DDR50:
1375                 speed = UHS_DDR50_BUS_SPEED;
1376                 break;
1377         case UHS_SDR104:
1378                 speed = UHS_SDR104_BUS_SPEED;
1379                 break;
1380 #endif
1381         default:
1382                 return -EINVAL;
1383         }
1384
1385         err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1386         if (err)
1387                 return err;
1388
1389         if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1390                 return -ENOTSUPP;
1391
1392         return 0;
1393 }
1394
1395 static int sd_select_bus_width(struct mmc *mmc, int w)
1396 {
1397         int err;
1398         struct mmc_cmd cmd;
1399
1400         if ((w != 4) && (w != 1))
1401                 return -EINVAL;
1402
1403         cmd.cmdidx = MMC_CMD_APP_CMD;
1404         cmd.resp_type = MMC_RSP_R1;
1405         cmd.cmdarg = mmc->rca << 16;
1406
1407         err = mmc_send_cmd(mmc, &cmd, NULL);
1408         if (err)
1409                 return err;
1410
1411         cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1412         cmd.resp_type = MMC_RSP_R1;
1413         if (w == 4)
1414                 cmd.cmdarg = 2;
1415         else if (w == 1)
1416                 cmd.cmdarg = 0;
1417         err = mmc_send_cmd(mmc, &cmd, NULL);
1418         if (err)
1419                 return err;
1420
1421         return 0;
1422 }
1423 #endif
1424
1425 #if CONFIG_IS_ENABLED(MMC_WRITE)
1426 static int sd_read_ssr(struct mmc *mmc)
1427 {
1428         static const unsigned int sd_au_size[] = {
1429                 0,              SZ_16K / 512,           SZ_32K / 512,
1430                 SZ_64K / 512,   SZ_128K / 512,          SZ_256K / 512,
1431                 SZ_512K / 512,  SZ_1M / 512,            SZ_2M / 512,
1432                 SZ_4M / 512,    SZ_8M / 512,            (SZ_8M + SZ_4M) / 512,
1433                 SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1434                 SZ_64M / 512,
1435         };
1436         int err, i;
1437         struct mmc_cmd cmd;
1438         ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1439         struct mmc_data data;
1440         int timeout = 3;
1441         unsigned int au, eo, et, es;
1442
1443         cmd.cmdidx = MMC_CMD_APP_CMD;
1444         cmd.resp_type = MMC_RSP_R1;
1445         cmd.cmdarg = mmc->rca << 16;
1446
1447         err = mmc_send_cmd(mmc, &cmd, NULL);
1448 #ifdef CONFIG_MMC_QUIRKS
1449         if (err && (mmc->quirks & MMC_QUIRK_RETRY_APP_CMD)) {
1450                 int retries = 4;
1451                 /*
1452                  * It has been seen that APP_CMD may fail on the first
1453                  * attempt, let's try a few more times
1454                  */
1455                 do {
1456                         err = mmc_send_cmd(mmc, &cmd, NULL);
1457                         if (!err)
1458                                 break;
1459                 } while (retries--);
1460         }
1461 #endif
1462         if (err)
1463                 return err;
1464
1465         cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1466         cmd.resp_type = MMC_RSP_R1;
1467         cmd.cmdarg = 0;
1468
1469 retry_ssr:
1470         data.dest = (char *)ssr;
1471         data.blocksize = 64;
1472         data.blocks = 1;
1473         data.flags = MMC_DATA_READ;
1474
1475         err = mmc_send_cmd(mmc, &cmd, &data);
1476         if (err) {
1477                 if (timeout--)
1478                         goto retry_ssr;
1479
1480                 return err;
1481         }
1482
1483         for (i = 0; i < 16; i++)
1484                 ssr[i] = be32_to_cpu(ssr[i]);
1485
1486         au = (ssr[2] >> 12) & 0xF;
1487         if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1488                 mmc->ssr.au = sd_au_size[au];
1489                 es = (ssr[3] >> 24) & 0xFF;
1490                 es |= (ssr[2] & 0xFF) << 8;
1491                 et = (ssr[3] >> 18) & 0x3F;
1492                 if (es && et) {
1493                         eo = (ssr[3] >> 16) & 0x3;
1494                         mmc->ssr.erase_timeout = (et * 1000) / es;
1495                         mmc->ssr.erase_offset = eo * 1000;
1496                 }
1497         } else {
1498                 pr_debug("Invalid Allocation Unit Size.\n");
1499         }
1500
1501         return 0;
1502 }
1503 #endif
1504 /* frequency bases */
1505 /* divided by 10 to be nice to platforms without floating point */
1506 static const int fbase[] = {
1507         10000,
1508         100000,
1509         1000000,
1510         10000000,
1511 };
1512
1513 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
1514  * to platforms without floating point.
1515  */
1516 static const u8 multipliers[] = {
1517         0,      /* reserved */
1518         10,
1519         12,
1520         13,
1521         15,
1522         20,
1523         25,
1524         30,
1525         35,
1526         40,
1527         45,
1528         50,
1529         55,
1530         60,
1531         70,
1532         80,
1533 };
1534
1535 static inline int bus_width(uint cap)
1536 {
1537         if (cap == MMC_MODE_8BIT)
1538                 return 8;
1539         if (cap == MMC_MODE_4BIT)
1540                 return 4;
1541         if (cap == MMC_MODE_1BIT)
1542                 return 1;
1543         pr_warn("invalid bus witdh capability 0x%x\n", cap);
1544         return 0;
1545 }
1546
1547 #if !CONFIG_IS_ENABLED(DM_MMC)
1548 #ifdef MMC_SUPPORTS_TUNING
1549 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1550 {
1551         return -ENOTSUPP;
1552 }
1553 #endif
1554
1555 static int mmc_set_ios(struct mmc *mmc)
1556 {
1557         int ret = 0;
1558
1559         if (mmc->cfg->ops->set_ios)
1560                 ret = mmc->cfg->ops->set_ios(mmc);
1561
1562         return ret;
1563 }
1564
1565 static int mmc_host_power_cycle(struct mmc *mmc)
1566 {
1567         int ret = 0;
1568
1569         if (mmc->cfg->ops->host_power_cycle)
1570                 ret = mmc->cfg->ops->host_power_cycle(mmc);
1571
1572         return ret;
1573 }
1574 #endif
1575
1576 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1577 {
1578         if (!disable) {
1579                 if (clock > mmc->cfg->f_max)
1580                         clock = mmc->cfg->f_max;
1581
1582                 if (clock < mmc->cfg->f_min)
1583                         clock = mmc->cfg->f_min;
1584         }
1585
1586         mmc->clock = clock;
1587         mmc->clk_disable = disable;
1588
1589         debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1590
1591         return mmc_set_ios(mmc);
1592 }
1593
1594 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1595 {
1596         mmc->bus_width = width;
1597
1598         return mmc_set_ios(mmc);
1599 }
1600
1601 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1602 /*
1603  * helper function to display the capabilities in a human
1604  * friendly manner. The capabilities include bus width and
1605  * supported modes.
1606  */
1607 void mmc_dump_capabilities(const char *text, uint caps)
1608 {
1609         enum bus_mode mode;
1610
1611         pr_debug("%s: widths [", text);
1612         if (caps & MMC_MODE_8BIT)
1613                 pr_debug("8, ");
1614         if (caps & MMC_MODE_4BIT)
1615                 pr_debug("4, ");
1616         if (caps & MMC_MODE_1BIT)
1617                 pr_debug("1, ");
1618         pr_debug("\b\b] modes [");
1619         for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1620                 if (MMC_CAP(mode) & caps)
1621                         pr_debug("%s, ", mmc_mode_name(mode));
1622         pr_debug("\b\b]\n");
1623 }
1624 #endif
1625
1626 struct mode_width_tuning {
1627         enum bus_mode mode;
1628         uint widths;
1629 #ifdef MMC_SUPPORTS_TUNING
1630         uint tuning;
1631 #endif
1632 };
1633
1634 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1635 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1636 {
1637         switch (voltage) {
1638         case MMC_SIGNAL_VOLTAGE_000: return 0;
1639         case MMC_SIGNAL_VOLTAGE_330: return 3300;
1640         case MMC_SIGNAL_VOLTAGE_180: return 1800;
1641         case MMC_SIGNAL_VOLTAGE_120: return 1200;
1642         }
1643         return -EINVAL;
1644 }
1645
1646 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1647 {
1648         int err;
1649
1650         if (mmc->signal_voltage == signal_voltage)
1651                 return 0;
1652
1653         mmc->signal_voltage = signal_voltage;
1654         err = mmc_set_ios(mmc);
1655         if (err)
1656                 pr_debug("unable to set voltage (err %d)\n", err);
1657
1658         return err;
1659 }
1660 #else
1661 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1662 {
1663         return 0;
1664 }
1665 #endif
1666
1667 #if !CONFIG_IS_ENABLED(MMC_TINY)
1668 static const struct mode_width_tuning sd_modes_by_pref[] = {
1669 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1670 #ifdef MMC_SUPPORTS_TUNING
1671         {
1672                 .mode = UHS_SDR104,
1673                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1674                 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1675         },
1676 #endif
1677         {
1678                 .mode = UHS_SDR50,
1679                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1680         },
1681         {
1682                 .mode = UHS_DDR50,
1683                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1684         },
1685         {
1686                 .mode = UHS_SDR25,
1687                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1688         },
1689 #endif
1690         {
1691                 .mode = SD_HS,
1692                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1693         },
1694 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1695         {
1696                 .mode = UHS_SDR12,
1697                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1698         },
1699 #endif
1700         {
1701                 .mode = MMC_LEGACY,
1702                 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1703         }
1704 };
1705
1706 #define for_each_sd_mode_by_pref(caps, mwt) \
1707         for (mwt = sd_modes_by_pref;\
1708              mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1709              mwt++) \
1710                 if (caps & MMC_CAP(mwt->mode))
1711
1712 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1713 {
1714         int err;
1715         uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1716         const struct mode_width_tuning *mwt;
1717 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1718         bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1719 #else
1720         bool uhs_en = false;
1721 #endif
1722         uint caps;
1723
1724 #ifdef DEBUG
1725         mmc_dump_capabilities("sd card", card_caps);
1726         mmc_dump_capabilities("host", mmc->host_caps);
1727 #endif
1728
1729         if (mmc_host_is_spi(mmc)) {
1730                 mmc_set_bus_width(mmc, 1);
1731                 mmc_select_mode(mmc, MMC_LEGACY);
1732                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1733                 return 0;
1734         }
1735
1736         /* Restrict card's capabilities by what the host can do */
1737         caps = card_caps & mmc->host_caps;
1738
1739         if (!uhs_en)
1740                 caps &= ~UHS_CAPS;
1741
1742         for_each_sd_mode_by_pref(caps, mwt) {
1743                 uint *w;
1744
1745                 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1746                         if (*w & caps & mwt->widths) {
1747                                 pr_debug("trying mode %s width %d (at %d MHz)\n",
1748                                          mmc_mode_name(mwt->mode),
1749                                          bus_width(*w),
1750                                          mmc_mode2freq(mmc, mwt->mode) / 1000000);
1751
1752                                 /* configure the bus width (card + host) */
1753                                 err = sd_select_bus_width(mmc, bus_width(*w));
1754                                 if (err)
1755                                         goto error;
1756                                 mmc_set_bus_width(mmc, bus_width(*w));
1757
1758                                 /* configure the bus mode (card) */
1759                                 err = sd_set_card_speed(mmc, mwt->mode);
1760                                 if (err)
1761                                         goto error;
1762
1763                                 /* configure the bus mode (host) */
1764                                 mmc_select_mode(mmc, mwt->mode);
1765                                 mmc_set_clock(mmc, mmc->tran_speed,
1766                                                 MMC_CLK_ENABLE);
1767
1768 #ifdef MMC_SUPPORTS_TUNING
1769                                 /* execute tuning if needed */
1770                                 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1771                                         err = mmc_execute_tuning(mmc,
1772                                                                  mwt->tuning);
1773                                         if (err) {
1774                                                 pr_debug("tuning failed\n");
1775                                                 goto error;
1776                                         }
1777                                 }
1778 #endif
1779
1780 #if CONFIG_IS_ENABLED(MMC_WRITE)
1781                                 err = sd_read_ssr(mmc);
1782                                 if (err)
1783                                         pr_warn("unable to read ssr\n");
1784 #endif
1785                                 if (!err)
1786                                         return 0;
1787
1788 error:
1789                                 /* revert to a safer bus speed */
1790                                 mmc_select_mode(mmc, MMC_LEGACY);
1791                                 mmc_set_clock(mmc, mmc->tran_speed,
1792                                                 MMC_CLK_ENABLE);
1793                         }
1794                 }
1795         }
1796
1797         pr_err("unable to select a mode\n");
1798         return -ENOTSUPP;
1799 }
1800
1801 /*
1802  * read the compare the part of ext csd that is constant.
1803  * This can be used to check that the transfer is working
1804  * as expected.
1805  */
1806 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1807 {
1808         int err;
1809         const u8 *ext_csd = mmc->ext_csd;
1810         ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1811
1812         if (mmc->version < MMC_VERSION_4)
1813                 return 0;
1814
1815         err = mmc_send_ext_csd(mmc, test_csd);
1816         if (err)
1817                 return err;
1818
1819         /* Only compare read only fields */
1820         if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1821                 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1822             ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1823                 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1824             ext_csd[EXT_CSD_REV]
1825                 == test_csd[EXT_CSD_REV] &&
1826             ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1827                 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1828             memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1829                    &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1830                 return 0;
1831
1832         return -EBADMSG;
1833 }
1834
1835 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1836 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1837                                   uint32_t allowed_mask)
1838 {
1839         u32 card_mask = 0;
1840
1841         switch (mode) {
1842         case MMC_HS_400_ES:
1843         case MMC_HS_400:
1844         case MMC_HS_200:
1845                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1846                     EXT_CSD_CARD_TYPE_HS400_1_8V))
1847                         card_mask |= MMC_SIGNAL_VOLTAGE_180;
1848                 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1849                     EXT_CSD_CARD_TYPE_HS400_1_2V))
1850                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1851                 break;
1852         case MMC_DDR_52:
1853                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1854                         card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1855                                      MMC_SIGNAL_VOLTAGE_180;
1856                 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1857                         card_mask |= MMC_SIGNAL_VOLTAGE_120;
1858                 break;
1859         default:
1860                 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1861                 break;
1862         }
1863
1864         while (card_mask & allowed_mask) {
1865                 enum mmc_voltage best_match;
1866
1867                 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1868                 if (!mmc_set_signal_voltage(mmc,  best_match))
1869                         return 0;
1870
1871                 allowed_mask &= ~best_match;
1872         }
1873
1874         return -ENOTSUPP;
1875 }
1876 #else
1877 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1878                                          uint32_t allowed_mask)
1879 {
1880         return 0;
1881 }
1882 #endif
1883
1884 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1885 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1886         {
1887                 .mode = MMC_HS_400_ES,
1888                 .widths = MMC_MODE_8BIT,
1889         },
1890 #endif
1891 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1892         {
1893                 .mode = MMC_HS_400,
1894                 .widths = MMC_MODE_8BIT,
1895                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1896         },
1897 #endif
1898 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1899         {
1900                 .mode = MMC_HS_200,
1901                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1902                 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1903         },
1904 #endif
1905         {
1906                 .mode = MMC_DDR_52,
1907                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1908         },
1909         {
1910                 .mode = MMC_HS_52,
1911                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1912         },
1913         {
1914                 .mode = MMC_HS,
1915                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1916         },
1917         {
1918                 .mode = MMC_LEGACY,
1919                 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1920         }
1921 };
1922
1923 #define for_each_mmc_mode_by_pref(caps, mwt) \
1924         for (mwt = mmc_modes_by_pref;\
1925             mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1926             mwt++) \
1927                 if (caps & MMC_CAP(mwt->mode))
1928
1929 static const struct ext_csd_bus_width {
1930         uint cap;
1931         bool is_ddr;
1932         uint ext_csd_bits;
1933 } ext_csd_bus_width[] = {
1934         {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1935         {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1936         {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1937         {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1938         {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1939 };
1940
1941 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1942 static int mmc_select_hs400(struct mmc *mmc)
1943 {
1944         int err;
1945
1946         /* Set timing to HS200 for tuning */
1947         err = mmc_set_card_speed(mmc, MMC_HS_200, false);
1948         if (err)
1949                 return err;
1950
1951         /* configure the bus mode (host) */
1952         mmc_select_mode(mmc, MMC_HS_200);
1953         mmc_set_clock(mmc, mmc->tran_speed, false);
1954
1955         /* execute tuning if needed */
1956         err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1957         if (err) {
1958                 debug("tuning failed\n");
1959                 return err;
1960         }
1961
1962         /* Set back to HS */
1963         mmc_set_card_speed(mmc, MMC_HS, true);
1964
1965         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1966                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1967         if (err)
1968                 return err;
1969
1970         err = mmc_set_card_speed(mmc, MMC_HS_400, false);
1971         if (err)
1972                 return err;
1973
1974         mmc_select_mode(mmc, MMC_HS_400);
1975         err = mmc_set_clock(mmc, mmc->tran_speed, false);
1976         if (err)
1977                 return err;
1978
1979         return 0;
1980 }
1981 #else
1982 static int mmc_select_hs400(struct mmc *mmc)
1983 {
1984         return -ENOTSUPP;
1985 }
1986 #endif
1987
1988 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1989 #if !CONFIG_IS_ENABLED(DM_MMC)
1990 static int mmc_set_enhanced_strobe(struct mmc *mmc)
1991 {
1992         return -ENOTSUPP;
1993 }
1994 #endif
1995 static int mmc_select_hs400es(struct mmc *mmc)
1996 {
1997         int err;
1998
1999         err = mmc_set_card_speed(mmc, MMC_HS, true);
2000         if (err)
2001                 return err;
2002
2003         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2004                          EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2005                          EXT_CSD_BUS_WIDTH_STROBE);
2006         if (err) {
2007                 printf("switch to bus width for hs400 failed\n");
2008                 return err;
2009         }
2010         /* TODO: driver strength */
2011         err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2012         if (err)
2013                 return err;
2014
2015         mmc_select_mode(mmc, MMC_HS_400_ES);
2016         err = mmc_set_clock(mmc, mmc->tran_speed, false);
2017         if (err)
2018                 return err;
2019
2020         return mmc_set_enhanced_strobe(mmc);
2021 }
2022 #else
2023 static int mmc_select_hs400es(struct mmc *mmc)
2024 {
2025         return -ENOTSUPP;
2026 }
2027 #endif
2028
2029 #define for_each_supported_width(caps, ddr, ecbv) \
2030         for (ecbv = ext_csd_bus_width;\
2031             ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2032             ecbv++) \
2033                 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2034
2035 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
2036 {
2037         int err;
2038         const struct mode_width_tuning *mwt;
2039         const struct ext_csd_bus_width *ecbw;
2040
2041 #ifdef DEBUG
2042         mmc_dump_capabilities("mmc", card_caps);
2043         mmc_dump_capabilities("host", mmc->host_caps);
2044 #endif
2045
2046         if (mmc_host_is_spi(mmc)) {
2047                 mmc_set_bus_width(mmc, 1);
2048                 mmc_select_mode(mmc, MMC_LEGACY);
2049                 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2050                 return 0;
2051         }
2052
2053         /* Restrict card's capabilities by what the host can do */
2054         card_caps &= mmc->host_caps;
2055
2056         /* Only version 4 of MMC supports wider bus widths */
2057         if (mmc->version < MMC_VERSION_4)
2058                 return 0;
2059
2060         if (!mmc->ext_csd) {
2061                 pr_debug("No ext_csd found!\n"); /* this should enver happen */
2062                 return -ENOTSUPP;
2063         }
2064
2065 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2066     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2067         /*
2068          * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2069          * before doing anything else, since a transition from either of
2070          * the HS200/HS400 mode directly to legacy mode is not supported.
2071          */
2072         if (mmc->selected_mode == MMC_HS_200 ||
2073             mmc->selected_mode == MMC_HS_400)
2074                 mmc_set_card_speed(mmc, MMC_HS, true);
2075         else
2076 #endif
2077                 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
2078
2079         for_each_mmc_mode_by_pref(card_caps, mwt) {
2080                 for_each_supported_width(card_caps & mwt->widths,
2081                                          mmc_is_mode_ddr(mwt->mode), ecbw) {
2082                         enum mmc_voltage old_voltage;
2083                         pr_debug("trying mode %s width %d (at %d MHz)\n",
2084                                  mmc_mode_name(mwt->mode),
2085                                  bus_width(ecbw->cap),
2086                                  mmc_mode2freq(mmc, mwt->mode) / 1000000);
2087                         old_voltage = mmc->signal_voltage;
2088                         err = mmc_set_lowest_voltage(mmc, mwt->mode,
2089                                                      MMC_ALL_SIGNAL_VOLTAGE);
2090                         if (err)
2091                                 continue;
2092
2093                         /* configure the bus width (card + host) */
2094                         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2095                                     EXT_CSD_BUS_WIDTH,
2096                                     ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2097                         if (err)
2098                                 goto error;
2099                         mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2100
2101                         if (mwt->mode == MMC_HS_400) {
2102                                 err = mmc_select_hs400(mmc);
2103                                 if (err) {
2104                                         printf("Select HS400 failed %d\n", err);
2105                                         goto error;
2106                                 }
2107                         } else if (mwt->mode == MMC_HS_400_ES) {
2108                                 err = mmc_select_hs400es(mmc);
2109                                 if (err) {
2110                                         printf("Select HS400ES failed %d\n",
2111                                                err);
2112                                         goto error;
2113                                 }
2114                         } else {
2115                                 /* configure the bus speed (card) */
2116                                 err = mmc_set_card_speed(mmc, mwt->mode, false);
2117                                 if (err)
2118                                         goto error;
2119
2120                                 /*
2121                                  * configure the bus width AND the ddr mode
2122                                  * (card). The host side will be taken care
2123                                  * of in the next step
2124                                  */
2125                                 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2126                                         err = mmc_switch(mmc,
2127                                                          EXT_CSD_CMD_SET_NORMAL,
2128                                                          EXT_CSD_BUS_WIDTH,
2129                                                          ecbw->ext_csd_bits);
2130                                         if (err)
2131                                                 goto error;
2132                                 }
2133
2134                                 /* configure the bus mode (host) */
2135                                 mmc_select_mode(mmc, mwt->mode);
2136                                 mmc_set_clock(mmc, mmc->tran_speed,
2137                                               MMC_CLK_ENABLE);
2138 #ifdef MMC_SUPPORTS_TUNING
2139
2140                                 /* execute tuning if needed */
2141                                 if (mwt->tuning) {
2142                                         err = mmc_execute_tuning(mmc,
2143                                                                  mwt->tuning);
2144                                         if (err) {
2145                                                 pr_debug("tuning failed\n");
2146                                                 goto error;
2147                                         }
2148                                 }
2149 #endif
2150                         }
2151
2152                         /* do a transfer to check the configuration */
2153                         err = mmc_read_and_compare_ext_csd(mmc);
2154                         if (!err)
2155                                 return 0;
2156 error:
2157                         mmc_set_signal_voltage(mmc, old_voltage);
2158                         /* if an error occured, revert to a safer bus mode */
2159                         mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2160                                    EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2161                         mmc_select_mode(mmc, MMC_LEGACY);
2162                         mmc_set_bus_width(mmc, 1);
2163                 }
2164         }
2165
2166         pr_err("unable to select a mode\n");
2167
2168         return -ENOTSUPP;
2169 }
2170 #endif
2171
2172 #if CONFIG_IS_ENABLED(MMC_TINY)
2173 DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2174 #endif
2175
2176 static int mmc_startup_v4(struct mmc *mmc)
2177 {
2178         int err, i;
2179         u64 capacity;
2180         bool has_parts = false;
2181         bool part_completed;
2182         static const u32 mmc_versions[] = {
2183                 MMC_VERSION_4,
2184                 MMC_VERSION_4_1,
2185                 MMC_VERSION_4_2,
2186                 MMC_VERSION_4_3,
2187                 MMC_VERSION_4_4,
2188                 MMC_VERSION_4_41,
2189                 MMC_VERSION_4_5,
2190                 MMC_VERSION_5_0,
2191                 MMC_VERSION_5_1
2192         };
2193
2194 #if CONFIG_IS_ENABLED(MMC_TINY)
2195         u8 *ext_csd = ext_csd_bkup;
2196
2197         if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2198                 return 0;
2199
2200         if (!mmc->ext_csd)
2201                 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2202
2203         err = mmc_send_ext_csd(mmc, ext_csd);
2204         if (err)
2205                 goto error;
2206
2207         /* store the ext csd for future reference */
2208         if (!mmc->ext_csd)
2209                 mmc->ext_csd = ext_csd;
2210 #else
2211         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2212
2213         if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2214                 return 0;
2215
2216         /* check  ext_csd version and capacity */
2217         err = mmc_send_ext_csd(mmc, ext_csd);
2218         if (err)
2219                 goto error;
2220
2221         /* store the ext csd for future reference */
2222         if (!mmc->ext_csd)
2223                 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2224         if (!mmc->ext_csd)
2225                 return -ENOMEM;
2226         memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2227 #endif
2228         if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2229                 return -EINVAL;
2230
2231         mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2232
2233         if (mmc->version >= MMC_VERSION_4_2) {
2234                 /*
2235                  * According to the JEDEC Standard, the value of
2236                  * ext_csd's capacity is valid if the value is more
2237                  * than 2GB
2238                  */
2239                 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2240                                 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2241                                 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2242                                 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2243                 capacity *= MMC_MAX_BLOCK_LEN;
2244                 if ((capacity >> 20) > 2 * 1024)
2245                         mmc->capacity_user = capacity;
2246         }
2247
2248         if (mmc->version >= MMC_VERSION_4_5)
2249                 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2250
2251         /* The partition data may be non-zero but it is only
2252          * effective if PARTITION_SETTING_COMPLETED is set in
2253          * EXT_CSD, so ignore any data if this bit is not set,
2254          * except for enabling the high-capacity group size
2255          * definition (see below).
2256          */
2257         part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2258                             EXT_CSD_PARTITION_SETTING_COMPLETED);
2259
2260         mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2261         /* Some eMMC set the value too low so set a minimum */
2262         if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2263                 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2264
2265         /* store the partition info of emmc */
2266         mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2267         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2268             ext_csd[EXT_CSD_BOOT_MULT])
2269                 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2270         if (part_completed &&
2271             (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2272                 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2273
2274         mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2275
2276         mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2277
2278         for (i = 0; i < 4; i++) {
2279                 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2280                 uint mult = (ext_csd[idx + 2] << 16) +
2281                         (ext_csd[idx + 1] << 8) + ext_csd[idx];
2282                 if (mult)
2283                         has_parts = true;
2284                 if (!part_completed)
2285                         continue;
2286                 mmc->capacity_gp[i] = mult;
2287                 mmc->capacity_gp[i] *=
2288                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2289                 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2290                 mmc->capacity_gp[i] <<= 19;
2291         }
2292
2293 #ifndef CONFIG_SPL_BUILD
2294         if (part_completed) {
2295                 mmc->enh_user_size =
2296                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2297                         (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2298                         ext_csd[EXT_CSD_ENH_SIZE_MULT];
2299                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2300                 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2301                 mmc->enh_user_size <<= 19;
2302                 mmc->enh_user_start =
2303                         (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2304                         (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2305                         (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2306                         ext_csd[EXT_CSD_ENH_START_ADDR];
2307                 if (mmc->high_capacity)
2308                         mmc->enh_user_start <<= 9;
2309         }
2310 #endif
2311
2312         /*
2313          * Host needs to enable ERASE_GRP_DEF bit if device is
2314          * partitioned. This bit will be lost every time after a reset
2315          * or power off. This will affect erase size.
2316          */
2317         if (part_completed)
2318                 has_parts = true;
2319         if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2320             (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2321                 has_parts = true;
2322         if (has_parts) {
2323                 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2324                                  EXT_CSD_ERASE_GROUP_DEF, 1);
2325
2326                 if (err)
2327                         goto error;
2328
2329                 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2330         }
2331
2332         if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2333 #if CONFIG_IS_ENABLED(MMC_WRITE)
2334                 /* Read out group size from ext_csd */
2335                 mmc->erase_grp_size =
2336                         ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2337 #endif
2338                 /*
2339                  * if high capacity and partition setting completed
2340                  * SEC_COUNT is valid even if it is smaller than 2 GiB
2341                  * JEDEC Standard JESD84-B45, 6.2.4
2342                  */
2343                 if (mmc->high_capacity && part_completed) {
2344                         capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2345                                 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2346                                 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2347                                 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2348                         capacity *= MMC_MAX_BLOCK_LEN;
2349                         mmc->capacity_user = capacity;
2350                 }
2351         }
2352 #if CONFIG_IS_ENABLED(MMC_WRITE)
2353         else {
2354                 /* Calculate the group size from the csd value. */
2355                 int erase_gsz, erase_gmul;
2356
2357                 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2358                 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2359                 mmc->erase_grp_size = (erase_gsz + 1)
2360                         * (erase_gmul + 1);
2361         }
2362 #endif
2363 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2364         mmc->hc_wp_grp_size = 1024
2365                 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2366                 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2367 #endif
2368
2369         mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2370
2371         return 0;
2372 error:
2373         if (mmc->ext_csd) {
2374 #if !CONFIG_IS_ENABLED(MMC_TINY)
2375                 free(mmc->ext_csd);
2376 #endif
2377                 mmc->ext_csd = NULL;
2378         }
2379         return err;
2380 }
2381
2382 static int mmc_startup(struct mmc *mmc)
2383 {
2384         int err, i;
2385         uint mult, freq;
2386         u64 cmult, csize;
2387         struct mmc_cmd cmd;
2388         struct blk_desc *bdesc;
2389
2390 #ifdef CONFIG_MMC_SPI_CRC_ON
2391         if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2392                 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2393                 cmd.resp_type = MMC_RSP_R1;
2394                 cmd.cmdarg = 1;
2395                 err = mmc_send_cmd(mmc, &cmd, NULL);
2396                 if (err)
2397                         return err;
2398         }
2399 #endif
2400
2401         /* Put the Card in Identify Mode */
2402         cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2403                 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2404         cmd.resp_type = MMC_RSP_R2;
2405         cmd.cmdarg = 0;
2406
2407         err = mmc_send_cmd(mmc, &cmd, NULL);
2408
2409 #ifdef CONFIG_MMC_QUIRKS
2410         if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2411                 int retries = 4;
2412                 /*
2413                  * It has been seen that SEND_CID may fail on the first
2414                  * attempt, let's try a few more time
2415                  */
2416                 do {
2417                         err = mmc_send_cmd(mmc, &cmd, NULL);
2418                         if (!err)
2419                                 break;
2420                 } while (retries--);
2421         }
2422 #endif
2423
2424         if (err)
2425                 return err;
2426
2427         memcpy(mmc->cid, cmd.response, 16);
2428
2429         /*
2430          * For MMC cards, set the Relative Address.
2431          * For SD cards, get the Relatvie Address.
2432          * This also puts the cards into Standby State
2433          */
2434         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2435                 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2436                 cmd.cmdarg = mmc->rca << 16;
2437                 cmd.resp_type = MMC_RSP_R6;
2438
2439                 err = mmc_send_cmd(mmc, &cmd, NULL);
2440
2441                 if (err)
2442                         return err;
2443
2444                 if (IS_SD(mmc))
2445                         mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2446         }
2447
2448         /* Get the Card-Specific Data */
2449         cmd.cmdidx = MMC_CMD_SEND_CSD;
2450         cmd.resp_type = MMC_RSP_R2;
2451         cmd.cmdarg = mmc->rca << 16;
2452
2453         err = mmc_send_cmd(mmc, &cmd, NULL);
2454
2455         if (err)
2456                 return err;
2457
2458         mmc->csd[0] = cmd.response[0];
2459         mmc->csd[1] = cmd.response[1];
2460         mmc->csd[2] = cmd.response[2];
2461         mmc->csd[3] = cmd.response[3];
2462
2463         if (mmc->version == MMC_VERSION_UNKNOWN) {
2464                 int version = (cmd.response[0] >> 26) & 0xf;
2465
2466                 switch (version) {
2467                 case 0:
2468                         mmc->version = MMC_VERSION_1_2;
2469                         break;
2470                 case 1:
2471                         mmc->version = MMC_VERSION_1_4;
2472                         break;
2473                 case 2:
2474                         mmc->version = MMC_VERSION_2_2;
2475                         break;
2476                 case 3:
2477                         mmc->version = MMC_VERSION_3;
2478                         break;
2479                 case 4:
2480                         mmc->version = MMC_VERSION_4;
2481                         break;
2482                 default:
2483                         mmc->version = MMC_VERSION_1_2;
2484                         break;
2485                 }
2486         }
2487
2488         /* divide frequency by 10, since the mults are 10x bigger */
2489         freq = fbase[(cmd.response[0] & 0x7)];
2490         mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2491
2492         mmc->legacy_speed = freq * mult;
2493         mmc_select_mode(mmc, MMC_LEGACY);
2494
2495         mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2496         mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2497 #if CONFIG_IS_ENABLED(MMC_WRITE)
2498
2499         if (IS_SD(mmc))
2500                 mmc->write_bl_len = mmc->read_bl_len;
2501         else
2502                 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2503 #endif
2504
2505         if (mmc->high_capacity) {
2506                 csize = (mmc->csd[1] & 0x3f) << 16
2507                         | (mmc->csd[2] & 0xffff0000) >> 16;
2508                 cmult = 8;
2509         } else {
2510                 csize = (mmc->csd[1] & 0x3ff) << 2
2511                         | (mmc->csd[2] & 0xc0000000) >> 30;
2512                 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2513         }
2514
2515         mmc->capacity_user = (csize + 1) << (cmult + 2);
2516         mmc->capacity_user *= mmc->read_bl_len;
2517         mmc->capacity_boot = 0;
2518         mmc->capacity_rpmb = 0;
2519         for (i = 0; i < 4; i++)
2520                 mmc->capacity_gp[i] = 0;
2521
2522         if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2523                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2524
2525 #if CONFIG_IS_ENABLED(MMC_WRITE)
2526         if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2527                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2528 #endif
2529
2530         if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2531                 cmd.cmdidx = MMC_CMD_SET_DSR;
2532                 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2533                 cmd.resp_type = MMC_RSP_NONE;
2534                 if (mmc_send_cmd(mmc, &cmd, NULL))
2535                         pr_warn("MMC: SET_DSR failed\n");
2536         }
2537
2538         /* Select the card, and put it into Transfer Mode */
2539         if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2540                 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2541                 cmd.resp_type = MMC_RSP_R1;
2542                 cmd.cmdarg = mmc->rca << 16;
2543                 err = mmc_send_cmd(mmc, &cmd, NULL);
2544
2545                 if (err)
2546                         return err;
2547         }
2548
2549         /*
2550          * For SD, its erase group is always one sector
2551          */
2552 #if CONFIG_IS_ENABLED(MMC_WRITE)
2553         mmc->erase_grp_size = 1;
2554 #endif
2555         mmc->part_config = MMCPART_NOAVAILABLE;
2556
2557         err = mmc_startup_v4(mmc);
2558         if (err)
2559                 return err;
2560
2561         err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2562         if (err)
2563                 return err;
2564
2565 #if CONFIG_IS_ENABLED(MMC_TINY)
2566         mmc_set_clock(mmc, mmc->legacy_speed, false);
2567         mmc_select_mode(mmc, MMC_LEGACY);
2568         mmc_set_bus_width(mmc, 1);
2569 #else
2570         if (IS_SD(mmc)) {
2571                 err = sd_get_capabilities(mmc);
2572                 if (err)
2573                         return err;
2574                 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2575         } else {
2576                 err = mmc_get_capabilities(mmc);
2577                 if (err)
2578                         return err;
2579                 err = mmc_select_mode_and_width(mmc, mmc->card_caps);
2580         }
2581 #endif
2582         if (err)
2583                 return err;
2584
2585         mmc->best_mode = mmc->selected_mode;
2586
2587         /* Fix the block length for DDR mode */
2588         if (mmc->ddr_mode) {
2589                 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2590 #if CONFIG_IS_ENABLED(MMC_WRITE)
2591                 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2592 #endif
2593         }
2594
2595         /* fill in device description */
2596         bdesc = mmc_get_blk_desc(mmc);
2597         bdesc->lun = 0;
2598         bdesc->hwpart = 0;
2599         bdesc->type = 0;
2600         bdesc->blksz = mmc->read_bl_len;
2601         bdesc->log2blksz = LOG2(bdesc->blksz);
2602         bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2603 #if !defined(CONFIG_SPL_BUILD) || \
2604                 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2605                 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
2606         sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2607                 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2608                 (mmc->cid[3] >> 16) & 0xffff);
2609         sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2610                 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2611                 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2612                 (mmc->cid[2] >> 24) & 0xff);
2613         sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2614                 (mmc->cid[2] >> 16) & 0xf);
2615 #else
2616         bdesc->vendor[0] = 0;
2617         bdesc->product[0] = 0;
2618         bdesc->revision[0] = 0;
2619 #endif
2620
2621 #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2622         part_init(bdesc);
2623 #endif
2624
2625         return 0;
2626 }
2627
2628 static int mmc_send_if_cond(struct mmc *mmc)
2629 {
2630         struct mmc_cmd cmd;
2631         int err;
2632
2633         cmd.cmdidx = SD_CMD_SEND_IF_COND;
2634         /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2635         cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2636         cmd.resp_type = MMC_RSP_R7;
2637
2638         err = mmc_send_cmd(mmc, &cmd, NULL);
2639
2640         if (err)
2641                 return err;
2642
2643         if ((cmd.response[0] & 0xff) != 0xaa)
2644                 return -EOPNOTSUPP;
2645         else
2646                 mmc->version = SD_VERSION_2;
2647
2648         return 0;
2649 }
2650
2651 #if !CONFIG_IS_ENABLED(DM_MMC)
2652 /* board-specific MMC power initializations. */
2653 __weak void board_mmc_power_init(void)
2654 {
2655 }
2656 #endif
2657
2658 static int mmc_power_init(struct mmc *mmc)
2659 {
2660 #if CONFIG_IS_ENABLED(DM_MMC)
2661 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2662         int ret;
2663
2664         ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2665                                           &mmc->vmmc_supply);
2666         if (ret)
2667                 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2668
2669         ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2670                                           &mmc->vqmmc_supply);
2671         if (ret)
2672                 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2673 #endif
2674 #else /* !CONFIG_DM_MMC */
2675         /*
2676          * Driver model should use a regulator, as above, rather than calling
2677          * out to board code.
2678          */
2679         board_mmc_power_init();
2680 #endif
2681         return 0;
2682 }
2683
2684 /*
2685  * put the host in the initial state:
2686  * - turn on Vdd (card power supply)
2687  * - configure the bus width and clock to minimal values
2688  */
2689 static void mmc_set_initial_state(struct mmc *mmc)
2690 {
2691         int err;
2692
2693         /* First try to set 3.3V. If it fails set to 1.8V */
2694         err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2695         if (err != 0)
2696                 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2697         if (err != 0)
2698                 pr_warn("mmc: failed to set signal voltage\n");
2699
2700         mmc_select_mode(mmc, MMC_LEGACY);
2701         mmc_set_bus_width(mmc, 1);
2702         mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2703 }
2704
2705 static int mmc_power_on(struct mmc *mmc)
2706 {
2707 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2708         if (mmc->vmmc_supply) {
2709                 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2710
2711                 if (ret) {
2712                         puts("Error enabling VMMC supply\n");
2713                         return ret;
2714                 }
2715         }
2716 #endif
2717         return 0;
2718 }
2719
2720 static int mmc_power_off(struct mmc *mmc)
2721 {
2722         mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
2723 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2724         if (mmc->vmmc_supply) {
2725                 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2726
2727                 if (ret) {
2728                         pr_debug("Error disabling VMMC supply\n");
2729                         return ret;
2730                 }
2731         }
2732 #endif
2733         return 0;
2734 }
2735
2736 static int mmc_power_cycle(struct mmc *mmc)
2737 {
2738         int ret;
2739
2740         ret = mmc_power_off(mmc);
2741         if (ret)
2742                 return ret;
2743
2744         ret = mmc_host_power_cycle(mmc);
2745         if (ret)
2746                 return ret;
2747
2748         /*
2749          * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2750          * to be on the safer side.
2751          */
2752         udelay(2000);
2753         return mmc_power_on(mmc);
2754 }
2755
2756 int mmc_get_op_cond(struct mmc *mmc)
2757 {
2758         bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2759         int err;
2760
2761         if (mmc->has_init)
2762                 return 0;
2763
2764 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2765         mmc_adapter_card_type_ident();
2766 #endif
2767         err = mmc_power_init(mmc);
2768         if (err)
2769                 return err;
2770
2771 #ifdef CONFIG_MMC_QUIRKS
2772         mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2773                       MMC_QUIRK_RETRY_SEND_CID |
2774                       MMC_QUIRK_RETRY_APP_CMD;
2775 #endif
2776
2777         err = mmc_power_cycle(mmc);
2778         if (err) {
2779                 /*
2780                  * if power cycling is not supported, we should not try
2781                  * to use the UHS modes, because we wouldn't be able to
2782                  * recover from an error during the UHS initialization.
2783                  */
2784                 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2785                 uhs_en = false;
2786                 mmc->host_caps &= ~UHS_CAPS;
2787                 err = mmc_power_on(mmc);
2788         }
2789         if (err)
2790                 return err;
2791
2792 #if CONFIG_IS_ENABLED(DM_MMC)
2793         /* The device has already been probed ready for use */
2794 #else
2795         /* made sure it's not NULL earlier */
2796         err = mmc->cfg->ops->init(mmc);
2797         if (err)
2798                 return err;
2799 #endif
2800         mmc->ddr_mode = 0;
2801
2802 retry:
2803         mmc_set_initial_state(mmc);
2804
2805         /* Reset the Card */
2806         err = mmc_go_idle(mmc);
2807
2808         if (err)
2809                 return err;
2810
2811         /* The internal partition reset to user partition(0) at every CMD0*/
2812         mmc_get_blk_desc(mmc)->hwpart = 0;
2813
2814         /* Test for SD version 2 */
2815         err = mmc_send_if_cond(mmc);
2816
2817         /* Now try to get the SD card's operating condition */
2818         err = sd_send_op_cond(mmc, uhs_en);
2819         if (err && uhs_en) {
2820                 uhs_en = false;
2821                 mmc_power_cycle(mmc);
2822                 goto retry;
2823         }
2824
2825         /* If the command timed out, we check for an MMC card */
2826         if (err == -ETIMEDOUT) {
2827                 err = mmc_send_op_cond(mmc);
2828
2829                 if (err) {
2830 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2831                         pr_err("Card did not respond to voltage select!\n");
2832 #endif
2833                         return -EOPNOTSUPP;
2834                 }
2835         }
2836
2837         return err;
2838 }
2839
2840 int mmc_start_init(struct mmc *mmc)
2841 {
2842         bool no_card;
2843         int err = 0;
2844
2845         /*
2846          * all hosts are capable of 1 bit bus-width and able to use the legacy
2847          * timings.
2848          */
2849         mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
2850                          MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2851 #if CONFIG_IS_ENABLED(DM_MMC)
2852         mmc_deferred_probe(mmc);
2853 #endif
2854 #if !defined(CONFIG_MMC_BROKEN_CD)
2855         no_card = mmc_getcd(mmc) == 0;
2856 #else
2857         no_card = 0;
2858 #endif
2859 #if !CONFIG_IS_ENABLED(DM_MMC)
2860         /* we pretend there's no card when init is NULL */
2861         no_card = no_card || (mmc->cfg->ops->init == NULL);
2862 #endif
2863         if (no_card) {
2864                 mmc->has_init = 0;
2865 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2866                 pr_err("MMC: no card present\n");
2867 #endif
2868                 return -ENOMEDIUM;
2869         }
2870
2871         err = mmc_get_op_cond(mmc);
2872
2873         if (!err)
2874                 mmc->init_in_progress = 1;
2875
2876         return err;
2877 }
2878
2879 static int mmc_complete_init(struct mmc *mmc)
2880 {
2881         int err = 0;
2882
2883         mmc->init_in_progress = 0;
2884         if (mmc->op_cond_pending)
2885                 err = mmc_complete_op_cond(mmc);
2886
2887         if (!err)
2888                 err = mmc_startup(mmc);
2889         if (err)
2890                 mmc->has_init = 0;
2891         else
2892                 mmc->has_init = 1;
2893         return err;
2894 }
2895
2896 int mmc_init(struct mmc *mmc)
2897 {
2898         int err = 0;
2899         __maybe_unused ulong start;
2900 #if CONFIG_IS_ENABLED(DM_MMC)
2901         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2902
2903         upriv->mmc = mmc;
2904 #endif
2905         if (mmc->has_init)
2906                 return 0;
2907
2908         start = get_timer(0);
2909
2910         if (!mmc->init_in_progress)
2911                 err = mmc_start_init(mmc);
2912
2913         if (!err)
2914                 err = mmc_complete_init(mmc);
2915         if (err)
2916                 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2917
2918         return err;
2919 }
2920
2921 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2922     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2923     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2924 int mmc_deinit(struct mmc *mmc)
2925 {
2926         u32 caps_filtered;
2927
2928         if (!mmc->has_init)
2929                 return 0;
2930
2931         if (IS_SD(mmc)) {
2932                 caps_filtered = mmc->card_caps &
2933                         ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2934                           MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2935                           MMC_CAP(UHS_SDR104));
2936
2937                 return sd_select_mode_and_width(mmc, caps_filtered);
2938         } else {
2939                 caps_filtered = mmc->card_caps &
2940                         ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2941
2942                 return mmc_select_mode_and_width(mmc, caps_filtered);
2943         }
2944 }
2945 #endif
2946
2947 int mmc_set_dsr(struct mmc *mmc, u16 val)
2948 {
2949         mmc->dsr = val;
2950         return 0;
2951 }
2952
2953 /* CPU-specific MMC initializations */
2954 __weak int cpu_mmc_init(bd_t *bis)
2955 {
2956         return -1;
2957 }
2958
2959 /* board-specific MMC initializations. */
2960 __weak int board_mmc_init(bd_t *bis)
2961 {
2962         return -1;
2963 }
2964
2965 void mmc_set_preinit(struct mmc *mmc, int preinit)
2966 {
2967         mmc->preinit = preinit;
2968 }
2969
2970 #if CONFIG_IS_ENABLED(DM_MMC)
2971 static int mmc_probe(bd_t *bis)
2972 {
2973         int ret, i;
2974         struct uclass *uc;
2975         struct udevice *dev;
2976
2977         ret = uclass_get(UCLASS_MMC, &uc);
2978         if (ret)
2979                 return ret;
2980
2981         /*
2982          * Try to add them in sequence order. Really with driver model we
2983          * should allow holes, but the current MMC list does not allow that.
2984          * So if we request 0, 1, 3 we will get 0, 1, 2.
2985          */
2986         for (i = 0; ; i++) {
2987                 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2988                 if (ret == -ENODEV)
2989                         break;
2990         }
2991         uclass_foreach_dev(dev, uc) {
2992                 ret = device_probe(dev);
2993                 if (ret)
2994                         pr_err("%s - probe failed: %d\n", dev->name, ret);
2995         }
2996
2997         return 0;
2998 }
2999 #else
3000 static int mmc_probe(bd_t *bis)
3001 {
3002         if (board_mmc_init(bis) < 0)
3003                 cpu_mmc_init(bis);
3004
3005         return 0;
3006 }
3007 #endif
3008
3009 int mmc_initialize(bd_t *bis)
3010 {
3011         static int initialized = 0;
3012         int ret;
3013         if (initialized)        /* Avoid initializing mmc multiple times */
3014                 return 0;
3015         initialized = 1;
3016
3017 #if !CONFIG_IS_ENABLED(BLK)
3018 #if !CONFIG_IS_ENABLED(MMC_TINY)
3019         mmc_list_init();
3020 #endif
3021 #endif
3022         ret = mmc_probe(bis);
3023         if (ret)
3024                 return ret;
3025
3026 #ifndef CONFIG_SPL_BUILD
3027         print_mmc_devices(',');
3028 #endif
3029
3030         mmc_do_preinit();
3031         return 0;
3032 }
3033
3034 #if CONFIG_IS_ENABLED(DM_MMC)
3035 int mmc_init_device(int num)
3036 {
3037         struct udevice *dev;
3038         struct mmc *m;
3039         int ret;
3040
3041         ret = uclass_get_device(UCLASS_MMC, num, &dev);
3042         if (ret)
3043                 return ret;
3044
3045         m = mmc_get_mmc_dev(dev);
3046         if (!m)
3047                 return 0;
3048 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
3049         mmc_set_preinit(m, 1);
3050 #endif
3051         if (m->preinit)
3052                 mmc_start_init(m);
3053
3054         return 0;
3055 }
3056 #endif
3057
3058 #ifdef CONFIG_CMD_BKOPS_ENABLE
3059 int mmc_set_bkops_enable(struct mmc *mmc)
3060 {
3061         int err;
3062         ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3063
3064         err = mmc_send_ext_csd(mmc, ext_csd);
3065         if (err) {
3066                 puts("Could not get ext_csd register values\n");
3067                 return err;
3068         }
3069
3070         if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3071                 puts("Background operations not supported on device\n");
3072                 return -EMEDIUMTYPE;
3073         }
3074
3075         if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
3076                 puts("Background operations already enabled\n");
3077                 return 0;
3078         }
3079
3080         err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
3081         if (err) {
3082                 puts("Failed to enable manual background operations\n");
3083                 return err;
3084         }
3085
3086         puts("Enabled manual background operations\n");
3087
3088         return 0;
3089 }
3090 #endif