1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008, Freescale Semiconductor, Inc
6 * Based vaguely on the Linux code
13 #include <dm/device-internal.h>
17 #include <power/regulator.h>
20 #include <linux/list.h>
22 #include "mmc_private.h"
24 #define DEFAULT_CMD6_TIMEOUT_MS 500
26 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
27 static int mmc_power_cycle(struct mmc *mmc);
28 #if !CONFIG_IS_ENABLED(MMC_TINY)
29 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
32 #if !CONFIG_IS_ENABLED(DM_MMC)
34 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
39 __weak int board_mmc_getwp(struct mmc *mmc)
44 int mmc_getwp(struct mmc *mmc)
48 wp = board_mmc_getwp(mmc);
51 if (mmc->cfg->ops->getwp)
52 wp = mmc->cfg->ops->getwp(mmc);
60 __weak int board_mmc_getcd(struct mmc *mmc)
66 #ifdef CONFIG_MMC_TRACE
67 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
69 printf("CMD_SEND:%d\n", cmd->cmdidx);
70 printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
73 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
79 printf("\t\tRET\t\t\t %d\n", ret);
81 switch (cmd->resp_type) {
83 printf("\t\tMMC_RSP_NONE\n");
86 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
90 printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
94 printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
96 printf("\t\t \t\t 0x%08x \n",
98 printf("\t\t \t\t 0x%08x \n",
100 printf("\t\t \t\t 0x%08x \n",
103 printf("\t\t\t\t\tDUMPING DATA\n");
104 for (i = 0; i < 4; i++) {
106 printf("\t\t\t\t\t%03d - ", i*4);
107 ptr = (u8 *)&cmd->response[i];
109 for (j = 0; j < 4; j++)
110 printf("%02x ", *ptr--);
115 printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
119 printf("\t\tERROR MMC rsp not supported\n");
125 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
129 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
130 printf("CURR STATE:%d\n", status);
134 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
135 const char *mmc_mode_name(enum bus_mode mode)
137 static const char *const names[] = {
138 [MMC_LEGACY] = "MMC legacy",
139 [SD_LEGACY] = "SD Legacy",
140 [MMC_HS] = "MMC High Speed (26MHz)",
141 [SD_HS] = "SD High Speed (50MHz)",
142 [UHS_SDR12] = "UHS SDR12 (25MHz)",
143 [UHS_SDR25] = "UHS SDR25 (50MHz)",
144 [UHS_SDR50] = "UHS SDR50 (100MHz)",
145 [UHS_SDR104] = "UHS SDR104 (208MHz)",
146 [UHS_DDR50] = "UHS DDR50 (50MHz)",
147 [MMC_HS_52] = "MMC High Speed (52MHz)",
148 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
149 [MMC_HS_200] = "HS200 (200MHz)",
150 [MMC_HS_400] = "HS400 (200MHz)",
151 [MMC_HS_400_ES] = "HS400ES (200MHz)",
154 if (mode >= MMC_MODES_END)
155 return "Unknown mode";
161 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
163 static const int freqs[] = {
164 [MMC_LEGACY] = 25000000,
165 [SD_LEGACY] = 25000000,
168 [MMC_HS_52] = 52000000,
169 [MMC_DDR_52] = 52000000,
170 [UHS_SDR12] = 25000000,
171 [UHS_SDR25] = 50000000,
172 [UHS_SDR50] = 100000000,
173 [UHS_DDR50] = 50000000,
174 [UHS_SDR104] = 208000000,
175 [MMC_HS_200] = 200000000,
176 [MMC_HS_400] = 200000000,
177 [MMC_HS_400_ES] = 200000000,
180 if (mode == MMC_LEGACY)
181 return mmc->legacy_speed;
182 else if (mode >= MMC_MODES_END)
188 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
190 mmc->selected_mode = mode;
191 mmc->tran_speed = mmc_mode2freq(mmc, mode);
192 mmc->ddr_mode = mmc_is_mode_ddr(mode);
193 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
194 mmc->tran_speed / 1000000);
198 #if !CONFIG_IS_ENABLED(DM_MMC)
199 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
203 mmmc_trace_before_send(mmc, cmd);
204 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
205 mmmc_trace_after_send(mmc, cmd, ret);
211 int mmc_send_status(struct mmc *mmc, unsigned int *status)
214 int err, retries = 5;
216 cmd.cmdidx = MMC_CMD_SEND_STATUS;
217 cmd.resp_type = MMC_RSP_R1;
218 if (!mmc_host_is_spi(mmc))
219 cmd.cmdarg = mmc->rca << 16;
222 err = mmc_send_cmd(mmc, &cmd, NULL);
224 mmc_trace_state(mmc, &cmd);
225 *status = cmd.response[0];
229 mmc_trace_state(mmc, &cmd);
233 int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
238 err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
243 err = mmc_send_status(mmc, &status);
247 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
248 (status & MMC_STATUS_CURR_STATE) !=
252 if (status & MMC_STATUS_MASK) {
253 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
254 pr_err("Status Error: 0x%08x\n", status);
259 if (timeout_ms-- <= 0)
265 if (timeout_ms <= 0) {
266 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
267 pr_err("Timeout waiting card ready\n");
275 int mmc_set_blocklen(struct mmc *mmc, int len)
283 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
284 cmd.resp_type = MMC_RSP_R1;
287 err = mmc_send_cmd(mmc, &cmd, NULL);
289 #ifdef CONFIG_MMC_QUIRKS
290 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
293 * It has been seen that SET_BLOCKLEN may fail on the first
294 * attempt, let's try a few more time
297 err = mmc_send_cmd(mmc, &cmd, NULL);
307 #ifdef MMC_SUPPORTS_TUNING
308 static const u8 tuning_blk_pattern_4bit[] = {
309 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
310 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
311 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
312 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
313 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
314 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
315 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
316 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
319 static const u8 tuning_blk_pattern_8bit[] = {
320 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
321 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
322 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
323 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
324 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
325 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
326 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
327 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
328 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
329 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
330 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
331 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
332 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
333 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
334 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
335 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
338 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
341 struct mmc_data data;
342 const u8 *tuning_block_pattern;
345 if (mmc->bus_width == 8) {
346 tuning_block_pattern = tuning_blk_pattern_8bit;
347 size = sizeof(tuning_blk_pattern_8bit);
348 } else if (mmc->bus_width == 4) {
349 tuning_block_pattern = tuning_blk_pattern_4bit;
350 size = sizeof(tuning_blk_pattern_4bit);
355 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
359 cmd.resp_type = MMC_RSP_R1;
361 data.dest = (void *)data_buf;
363 data.blocksize = size;
364 data.flags = MMC_DATA_READ;
366 err = mmc_send_cmd(mmc, &cmd, &data);
370 if (memcmp(data_buf, tuning_block_pattern, size))
377 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
381 struct mmc_data data;
384 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
386 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
388 if (mmc->high_capacity)
391 cmd.cmdarg = start * mmc->read_bl_len;
393 cmd.resp_type = MMC_RSP_R1;
396 data.blocks = blkcnt;
397 data.blocksize = mmc->read_bl_len;
398 data.flags = MMC_DATA_READ;
400 if (mmc_send_cmd(mmc, &cmd, &data))
404 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
406 cmd.resp_type = MMC_RSP_R1b;
407 if (mmc_send_cmd(mmc, &cmd, NULL)) {
408 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
409 pr_err("mmc fail to send stop cmd\n");
418 #if CONFIG_IS_ENABLED(BLK)
419 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
421 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
425 #if CONFIG_IS_ENABLED(BLK)
426 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
428 int dev_num = block_dev->devnum;
430 lbaint_t cur, blocks_todo = blkcnt;
435 struct mmc *mmc = find_mmc_device(dev_num);
439 if (CONFIG_IS_ENABLED(MMC_TINY))
440 err = mmc_switch_part(mmc, block_dev->hwpart);
442 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
447 if ((start + blkcnt) > block_dev->lba) {
448 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
449 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
450 start + blkcnt, block_dev->lba);
455 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
456 pr_debug("%s: Failed to set blocklen\n", __func__);
461 cur = (blocks_todo > mmc->cfg->b_max) ?
462 mmc->cfg->b_max : blocks_todo;
463 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
464 pr_debug("%s: Failed to read blocks\n", __func__);
469 dst += cur * mmc->read_bl_len;
470 } while (blocks_todo > 0);
475 static int mmc_go_idle(struct mmc *mmc)
482 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
484 cmd.resp_type = MMC_RSP_NONE;
486 err = mmc_send_cmd(mmc, &cmd, NULL);
496 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
497 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
503 * Send CMD11 only if the request is to switch the card to
506 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
507 return mmc_set_signal_voltage(mmc, signal_voltage);
509 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
511 cmd.resp_type = MMC_RSP_R1;
513 err = mmc_send_cmd(mmc, &cmd, NULL);
517 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
521 * The card should drive cmd and dat[0:3] low immediately
522 * after the response of cmd11, but wait 100 us to be sure
524 err = mmc_wait_dat0(mmc, 0, 100);
531 * During a signal voltage level switch, the clock must be gated
532 * for 5 ms according to the SD spec
534 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
536 err = mmc_set_signal_voltage(mmc, signal_voltage);
540 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
542 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
545 * Failure to switch is indicated by the card holding
546 * dat[0:3] low. Wait for at least 1 ms according to spec
548 err = mmc_wait_dat0(mmc, 1, 1000);
558 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
565 cmd.cmdidx = MMC_CMD_APP_CMD;
566 cmd.resp_type = MMC_RSP_R1;
569 err = mmc_send_cmd(mmc, &cmd, NULL);
574 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
575 cmd.resp_type = MMC_RSP_R3;
578 * Most cards do not answer if some reserved bits
579 * in the ocr are set. However, Some controller
580 * can set bit 7 (reserved for low voltages), but
581 * how to manage low voltages SD card is not yet
584 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
585 (mmc->cfg->voltages & 0xff8000);
587 if (mmc->version == SD_VERSION_2)
588 cmd.cmdarg |= OCR_HCS;
591 cmd.cmdarg |= OCR_S18R;
593 err = mmc_send_cmd(mmc, &cmd, NULL);
598 if (cmd.response[0] & OCR_BUSY)
607 if (mmc->version != SD_VERSION_2)
608 mmc->version = SD_VERSION_1_0;
610 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
611 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
612 cmd.resp_type = MMC_RSP_R3;
615 err = mmc_send_cmd(mmc, &cmd, NULL);
621 mmc->ocr = cmd.response[0];
623 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
624 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
626 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
632 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
638 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
643 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
644 cmd.resp_type = MMC_RSP_R3;
646 if (use_arg && !mmc_host_is_spi(mmc))
647 cmd.cmdarg = OCR_HCS |
648 (mmc->cfg->voltages &
649 (mmc->ocr & OCR_VOLTAGE_MASK)) |
650 (mmc->ocr & OCR_ACCESS_MODE);
652 err = mmc_send_cmd(mmc, &cmd, NULL);
655 mmc->ocr = cmd.response[0];
659 static int mmc_send_op_cond(struct mmc *mmc)
663 /* Some cards seem to need this */
666 /* Asking to the card its capabilities */
667 for (i = 0; i < 2; i++) {
668 err = mmc_send_op_cond_iter(mmc, i != 0);
672 /* exit if not busy (flag seems to be inverted) */
673 if (mmc->ocr & OCR_BUSY)
676 mmc->op_cond_pending = 1;
680 static int mmc_complete_op_cond(struct mmc *mmc)
687 mmc->op_cond_pending = 0;
688 if (!(mmc->ocr & OCR_BUSY)) {
689 /* Some cards seem to need this */
692 start = get_timer(0);
694 err = mmc_send_op_cond_iter(mmc, 1);
697 if (mmc->ocr & OCR_BUSY)
699 if (get_timer(start) > timeout)
705 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
706 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
707 cmd.resp_type = MMC_RSP_R3;
710 err = mmc_send_cmd(mmc, &cmd, NULL);
715 mmc->ocr = cmd.response[0];
718 mmc->version = MMC_VERSION_UNKNOWN;
720 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
727 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
730 struct mmc_data data;
733 /* Get the Card Status Register */
734 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
735 cmd.resp_type = MMC_RSP_R1;
738 data.dest = (char *)ext_csd;
740 data.blocksize = MMC_MAX_BLOCK_LEN;
741 data.flags = MMC_DATA_READ;
743 err = mmc_send_cmd(mmc, &cmd, &data);
748 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
751 unsigned int status, start;
753 int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
754 bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
755 (index == EXT_CSD_PART_CONF);
759 if (mmc->gen_cmd6_time)
760 timeout_ms = mmc->gen_cmd6_time * 10;
762 if (is_part_switch && mmc->part_switch_time)
763 timeout_ms = mmc->part_switch_time * 10;
765 cmd.cmdidx = MMC_CMD_SWITCH;
766 cmd.resp_type = MMC_RSP_R1b;
767 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
772 ret = mmc_send_cmd(mmc, &cmd, NULL);
773 } while (ret && retries-- > 0);
778 start = get_timer(0);
780 /* poll dat0 for rdy/buys status */
781 ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
782 if (ret && ret != -ENOSYS)
786 * In cases when not allowed to poll by using CMD13 or because we aren't
787 * capable of polling by using mmc_wait_dat0, then rely on waiting the
788 * stated timeout to be sufficient.
790 if (ret == -ENOSYS && !send_status)
793 /* Finally wait until the card is ready or indicates a failure
794 * to switch. It doesn't hurt to use CMD13 here even if send_status
795 * is false, because by now (after 'timeout_ms' ms) the bus should be
799 ret = mmc_send_status(mmc, &status);
801 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
802 pr_debug("switch failed %d/%d/0x%x !\n", set, index,
806 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
809 } while (get_timer(start) < timeout_ms);
814 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
816 return __mmc_switch(mmc, set, index, value, true);
819 #if !CONFIG_IS_ENABLED(MMC_TINY)
820 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
826 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
832 speed_bits = EXT_CSD_TIMING_HS;
834 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
836 speed_bits = EXT_CSD_TIMING_HS200;
839 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
841 speed_bits = EXT_CSD_TIMING_HS400;
844 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
846 speed_bits = EXT_CSD_TIMING_HS400;
850 speed_bits = EXT_CSD_TIMING_LEGACY;
856 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
857 speed_bits, !hsdowngrade);
861 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
862 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
864 * In case the eMMC is in HS200/HS400 mode and we are downgrading
865 * to HS mode, the card clock are still running much faster than
866 * the supported HS mode clock, so we can not reliably read out
867 * Extended CSD. Reconfigure the controller to run at HS mode.
870 mmc_select_mode(mmc, MMC_HS);
871 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
875 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
876 /* Now check to see that it worked */
877 err = mmc_send_ext_csd(mmc, test_csd);
881 /* No high-speed support */
882 if (!test_csd[EXT_CSD_HS_TIMING])
889 static int mmc_get_capabilities(struct mmc *mmc)
891 u8 *ext_csd = mmc->ext_csd;
894 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
896 if (mmc_host_is_spi(mmc))
899 /* Only version 4 supports high-speed */
900 if (mmc->version < MMC_VERSION_4)
904 pr_err("No ext_csd found!\n"); /* this should enver happen */
908 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
910 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
911 mmc->cardtype = cardtype;
913 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
914 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
915 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
916 mmc->card_caps |= MMC_MODE_HS200;
919 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
920 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
921 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
922 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
923 mmc->card_caps |= MMC_MODE_HS400;
926 if (cardtype & EXT_CSD_CARD_TYPE_52) {
927 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
928 mmc->card_caps |= MMC_MODE_DDR_52MHz;
929 mmc->card_caps |= MMC_MODE_HS_52MHz;
931 if (cardtype & EXT_CSD_CARD_TYPE_26)
932 mmc->card_caps |= MMC_MODE_HS;
934 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
935 if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
936 (mmc->card_caps & MMC_MODE_HS400)) {
937 mmc->card_caps |= MMC_MODE_HS400_ES;
945 static int mmc_set_capacity(struct mmc *mmc, int part_num)
949 mmc->capacity = mmc->capacity_user;
953 mmc->capacity = mmc->capacity_boot;
956 mmc->capacity = mmc->capacity_rpmb;
962 mmc->capacity = mmc->capacity_gp[part_num - 4];
968 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
973 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
979 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
981 (mmc->part_config & ~PART_ACCESS_MASK)
982 | (part_num & PART_ACCESS_MASK));
983 } while (ret && retry--);
986 * Set the capacity if the switch succeeded or was intended
987 * to return to representing the raw device.
989 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
990 ret = mmc_set_capacity(mmc, part_num);
991 mmc_get_blk_desc(mmc)->hwpart = part_num;
997 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
998 int mmc_hwpart_config(struct mmc *mmc,
999 const struct mmc_hwpart_conf *conf,
1000 enum mmc_hwpart_conf_mode mode)
1005 u32 gp_size_mult[4];
1006 u32 max_enh_size_mult;
1007 u32 tot_enh_size_mult = 0;
1010 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1012 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1015 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
1016 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
1017 return -EMEDIUMTYPE;
1020 if (!(mmc->part_support & PART_SUPPORT)) {
1021 pr_err("Card does not support partitioning\n");
1022 return -EMEDIUMTYPE;
1025 if (!mmc->hc_wp_grp_size) {
1026 pr_err("Card does not define HC WP group size\n");
1027 return -EMEDIUMTYPE;
1030 /* check partition alignment and total enhanced size */
1031 if (conf->user.enh_size) {
1032 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1033 conf->user.enh_start % mmc->hc_wp_grp_size) {
1034 pr_err("User data enhanced area not HC WP group "
1038 part_attrs |= EXT_CSD_ENH_USR;
1039 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1040 if (mmc->high_capacity) {
1041 enh_start_addr = conf->user.enh_start;
1043 enh_start_addr = (conf->user.enh_start << 9);
1049 tot_enh_size_mult += enh_size_mult;
1051 for (pidx = 0; pidx < 4; pidx++) {
1052 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1053 pr_err("GP%i partition not HC WP group size "
1054 "aligned\n", pidx+1);
1057 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1058 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1059 part_attrs |= EXT_CSD_ENH_GP(pidx);
1060 tot_enh_size_mult += gp_size_mult[pidx];
1064 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1065 pr_err("Card does not support enhanced attribute\n");
1066 return -EMEDIUMTYPE;
1069 err = mmc_send_ext_csd(mmc, ext_csd);
1074 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1075 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1076 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1077 if (tot_enh_size_mult > max_enh_size_mult) {
1078 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1079 tot_enh_size_mult, max_enh_size_mult);
1080 return -EMEDIUMTYPE;
1083 /* The default value of EXT_CSD_WR_REL_SET is device
1084 * dependent, the values can only be changed if the
1085 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1086 * changed only once and before partitioning is completed. */
1087 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1088 if (conf->user.wr_rel_change) {
1089 if (conf->user.wr_rel_set)
1090 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1092 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1094 for (pidx = 0; pidx < 4; pidx++) {
1095 if (conf->gp_part[pidx].wr_rel_change) {
1096 if (conf->gp_part[pidx].wr_rel_set)
1097 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1099 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1103 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1104 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1105 puts("Card does not support host controlled partition write "
1106 "reliability settings\n");
1107 return -EMEDIUMTYPE;
1110 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1111 EXT_CSD_PARTITION_SETTING_COMPLETED) {
1112 pr_err("Card already partitioned\n");
1116 if (mode == MMC_HWPART_CONF_CHECK)
1119 /* Partitioning requires high-capacity size definitions */
1120 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1121 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1122 EXT_CSD_ERASE_GROUP_DEF, 1);
1127 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1129 /* update erase group size to be high-capacity */
1130 mmc->erase_grp_size =
1131 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1135 /* all OK, write the configuration */
1136 for (i = 0; i < 4; i++) {
1137 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1138 EXT_CSD_ENH_START_ADDR+i,
1139 (enh_start_addr >> (i*8)) & 0xFF);
1143 for (i = 0; i < 3; i++) {
1144 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1145 EXT_CSD_ENH_SIZE_MULT+i,
1146 (enh_size_mult >> (i*8)) & 0xFF);
1150 for (pidx = 0; pidx < 4; pidx++) {
1151 for (i = 0; i < 3; i++) {
1152 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1153 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1154 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1159 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1160 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1164 if (mode == MMC_HWPART_CONF_SET)
1167 /* The WR_REL_SET is a write-once register but shall be
1168 * written before setting PART_SETTING_COMPLETED. As it is
1169 * write-once we can only write it when completing the
1171 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1172 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1173 EXT_CSD_WR_REL_SET, wr_rel_set);
1178 /* Setting PART_SETTING_COMPLETED confirms the partition
1179 * configuration but it only becomes effective after power
1180 * cycle, so we do not adjust the partition related settings
1181 * in the mmc struct. */
1183 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1184 EXT_CSD_PARTITION_SETTING,
1185 EXT_CSD_PARTITION_SETTING_COMPLETED);
1193 #if !CONFIG_IS_ENABLED(DM_MMC)
1194 int mmc_getcd(struct mmc *mmc)
1198 cd = board_mmc_getcd(mmc);
1201 if (mmc->cfg->ops->getcd)
1202 cd = mmc->cfg->ops->getcd(mmc);
1211 #if !CONFIG_IS_ENABLED(MMC_TINY)
1212 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1215 struct mmc_data data;
1217 /* Switch the frequency */
1218 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1219 cmd.resp_type = MMC_RSP_R1;
1220 cmd.cmdarg = (mode << 31) | 0xffffff;
1221 cmd.cmdarg &= ~(0xf << (group * 4));
1222 cmd.cmdarg |= value << (group * 4);
1224 data.dest = (char *)resp;
1225 data.blocksize = 64;
1227 data.flags = MMC_DATA_READ;
1229 return mmc_send_cmd(mmc, &cmd, &data);
1232 static int sd_get_capabilities(struct mmc *mmc)
1236 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1237 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1238 struct mmc_data data;
1240 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1244 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1246 if (mmc_host_is_spi(mmc))
1249 /* Read the SCR to find out if this card supports higher speeds */
1250 cmd.cmdidx = MMC_CMD_APP_CMD;
1251 cmd.resp_type = MMC_RSP_R1;
1252 cmd.cmdarg = mmc->rca << 16;
1254 err = mmc_send_cmd(mmc, &cmd, NULL);
1259 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1260 cmd.resp_type = MMC_RSP_R1;
1266 data.dest = (char *)scr;
1269 data.flags = MMC_DATA_READ;
1271 err = mmc_send_cmd(mmc, &cmd, &data);
1280 mmc->scr[0] = __be32_to_cpu(scr[0]);
1281 mmc->scr[1] = __be32_to_cpu(scr[1]);
1283 switch ((mmc->scr[0] >> 24) & 0xf) {
1285 mmc->version = SD_VERSION_1_0;
1288 mmc->version = SD_VERSION_1_10;
1291 mmc->version = SD_VERSION_2;
1292 if ((mmc->scr[0] >> 15) & 0x1)
1293 mmc->version = SD_VERSION_3;
1296 mmc->version = SD_VERSION_1_0;
1300 if (mmc->scr[0] & SD_DATA_4BIT)
1301 mmc->card_caps |= MMC_MODE_4BIT;
1303 /* Version 1.0 doesn't support switching */
1304 if (mmc->version == SD_VERSION_1_0)
1309 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1310 (u8 *)switch_status);
1315 /* The high-speed function is busy. Try again */
1316 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1320 /* If high-speed isn't supported, we return */
1321 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1322 mmc->card_caps |= MMC_CAP(SD_HS);
1324 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1325 /* Version before 3.0 don't support UHS modes */
1326 if (mmc->version < SD_VERSION_3)
1329 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1330 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1331 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1332 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1333 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1334 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1335 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1336 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1337 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1338 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1339 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1345 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1349 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1352 /* SD version 1.00 and 1.01 does not support CMD 6 */
1353 if (mmc->version == SD_VERSION_1_0)
1358 speed = UHS_SDR12_BUS_SPEED;
1361 speed = HIGH_SPEED_BUS_SPEED;
1363 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1365 speed = UHS_SDR12_BUS_SPEED;
1368 speed = UHS_SDR25_BUS_SPEED;
1371 speed = UHS_SDR50_BUS_SPEED;
1374 speed = UHS_DDR50_BUS_SPEED;
1377 speed = UHS_SDR104_BUS_SPEED;
1384 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1388 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1394 static int sd_select_bus_width(struct mmc *mmc, int w)
1399 if ((w != 4) && (w != 1))
1402 cmd.cmdidx = MMC_CMD_APP_CMD;
1403 cmd.resp_type = MMC_RSP_R1;
1404 cmd.cmdarg = mmc->rca << 16;
1406 err = mmc_send_cmd(mmc, &cmd, NULL);
1410 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1411 cmd.resp_type = MMC_RSP_R1;
1416 err = mmc_send_cmd(mmc, &cmd, NULL);
1424 #if CONFIG_IS_ENABLED(MMC_WRITE)
1425 static int sd_read_ssr(struct mmc *mmc)
1427 static const unsigned int sd_au_size[] = {
1428 0, SZ_16K / 512, SZ_32K / 512,
1429 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1430 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1431 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1432 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1437 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1438 struct mmc_data data;
1440 unsigned int au, eo, et, es;
1442 cmd.cmdidx = MMC_CMD_APP_CMD;
1443 cmd.resp_type = MMC_RSP_R1;
1444 cmd.cmdarg = mmc->rca << 16;
1446 err = mmc_send_cmd(mmc, &cmd, NULL);
1450 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1451 cmd.resp_type = MMC_RSP_R1;
1455 data.dest = (char *)ssr;
1456 data.blocksize = 64;
1458 data.flags = MMC_DATA_READ;
1460 err = mmc_send_cmd(mmc, &cmd, &data);
1468 for (i = 0; i < 16; i++)
1469 ssr[i] = be32_to_cpu(ssr[i]);
1471 au = (ssr[2] >> 12) & 0xF;
1472 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1473 mmc->ssr.au = sd_au_size[au];
1474 es = (ssr[3] >> 24) & 0xFF;
1475 es |= (ssr[2] & 0xFF) << 8;
1476 et = (ssr[3] >> 18) & 0x3F;
1478 eo = (ssr[3] >> 16) & 0x3;
1479 mmc->ssr.erase_timeout = (et * 1000) / es;
1480 mmc->ssr.erase_offset = eo * 1000;
1483 pr_debug("Invalid Allocation Unit Size.\n");
1489 /* frequency bases */
1490 /* divided by 10 to be nice to platforms without floating point */
1491 static const int fbase[] = {
1498 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1499 * to platforms without floating point.
1501 static const u8 multipliers[] = {
1520 static inline int bus_width(uint cap)
1522 if (cap == MMC_MODE_8BIT)
1524 if (cap == MMC_MODE_4BIT)
1526 if (cap == MMC_MODE_1BIT)
1528 pr_warn("invalid bus witdh capability 0x%x\n", cap);
1532 #if !CONFIG_IS_ENABLED(DM_MMC)
1533 #ifdef MMC_SUPPORTS_TUNING
1534 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1540 static int mmc_set_ios(struct mmc *mmc)
1544 if (mmc->cfg->ops->set_ios)
1545 ret = mmc->cfg->ops->set_ios(mmc);
1550 static int mmc_host_power_cycle(struct mmc *mmc)
1554 if (mmc->cfg->ops->host_power_cycle)
1555 ret = mmc->cfg->ops->host_power_cycle(mmc);
1561 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1564 if (clock > mmc->cfg->f_max)
1565 clock = mmc->cfg->f_max;
1567 if (clock < mmc->cfg->f_min)
1568 clock = mmc->cfg->f_min;
1572 mmc->clk_disable = disable;
1574 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1576 return mmc_set_ios(mmc);
1579 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1581 mmc->bus_width = width;
1583 return mmc_set_ios(mmc);
1586 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1588 * helper function to display the capabilities in a human
1589 * friendly manner. The capabilities include bus width and
1592 void mmc_dump_capabilities(const char *text, uint caps)
1596 pr_debug("%s: widths [", text);
1597 if (caps & MMC_MODE_8BIT)
1599 if (caps & MMC_MODE_4BIT)
1601 if (caps & MMC_MODE_1BIT)
1603 pr_debug("\b\b] modes [");
1604 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1605 if (MMC_CAP(mode) & caps)
1606 pr_debug("%s, ", mmc_mode_name(mode));
1607 pr_debug("\b\b]\n");
1611 struct mode_width_tuning {
1614 #ifdef MMC_SUPPORTS_TUNING
1619 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1620 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1623 case MMC_SIGNAL_VOLTAGE_000: return 0;
1624 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1625 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1626 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1631 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1635 if (mmc->signal_voltage == signal_voltage)
1638 mmc->signal_voltage = signal_voltage;
1639 err = mmc_set_ios(mmc);
1641 pr_debug("unable to set voltage (err %d)\n", err);
1646 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1652 #if !CONFIG_IS_ENABLED(MMC_TINY)
1653 static const struct mode_width_tuning sd_modes_by_pref[] = {
1654 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1655 #ifdef MMC_SUPPORTS_TUNING
1658 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1659 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1664 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1668 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1672 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1677 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1679 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1682 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1687 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1691 #define for_each_sd_mode_by_pref(caps, mwt) \
1692 for (mwt = sd_modes_by_pref;\
1693 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1695 if (caps & MMC_CAP(mwt->mode))
1697 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1700 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1701 const struct mode_width_tuning *mwt;
1702 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1703 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1705 bool uhs_en = false;
1710 mmc_dump_capabilities("sd card", card_caps);
1711 mmc_dump_capabilities("host", mmc->host_caps);
1714 if (mmc_host_is_spi(mmc)) {
1715 mmc_set_bus_width(mmc, 1);
1716 mmc_select_mode(mmc, SD_LEGACY);
1717 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1721 /* Restrict card's capabilities by what the host can do */
1722 caps = card_caps & mmc->host_caps;
1727 for_each_sd_mode_by_pref(caps, mwt) {
1730 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1731 if (*w & caps & mwt->widths) {
1732 pr_debug("trying mode %s width %d (at %d MHz)\n",
1733 mmc_mode_name(mwt->mode),
1735 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1737 /* configure the bus width (card + host) */
1738 err = sd_select_bus_width(mmc, bus_width(*w));
1741 mmc_set_bus_width(mmc, bus_width(*w));
1743 /* configure the bus mode (card) */
1744 err = sd_set_card_speed(mmc, mwt->mode);
1748 /* configure the bus mode (host) */
1749 mmc_select_mode(mmc, mwt->mode);
1750 mmc_set_clock(mmc, mmc->tran_speed,
1753 #ifdef MMC_SUPPORTS_TUNING
1754 /* execute tuning if needed */
1755 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1756 err = mmc_execute_tuning(mmc,
1759 pr_debug("tuning failed\n");
1765 #if CONFIG_IS_ENABLED(MMC_WRITE)
1766 err = sd_read_ssr(mmc);
1768 pr_warn("unable to read ssr\n");
1774 /* revert to a safer bus speed */
1775 mmc_select_mode(mmc, SD_LEGACY);
1776 mmc_set_clock(mmc, mmc->tran_speed,
1782 pr_err("unable to select a mode\n");
1787 * read the compare the part of ext csd that is constant.
1788 * This can be used to check that the transfer is working
1791 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1794 const u8 *ext_csd = mmc->ext_csd;
1795 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1797 if (mmc->version < MMC_VERSION_4)
1800 err = mmc_send_ext_csd(mmc, test_csd);
1804 /* Only compare read only fields */
1805 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1806 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1807 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1808 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1809 ext_csd[EXT_CSD_REV]
1810 == test_csd[EXT_CSD_REV] &&
1811 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1812 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1813 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1814 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1820 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1821 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1822 uint32_t allowed_mask)
1830 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1831 EXT_CSD_CARD_TYPE_HS400_1_8V))
1832 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1833 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1834 EXT_CSD_CARD_TYPE_HS400_1_2V))
1835 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1838 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1839 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1840 MMC_SIGNAL_VOLTAGE_180;
1841 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1842 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1845 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1849 while (card_mask & allowed_mask) {
1850 enum mmc_voltage best_match;
1852 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1853 if (!mmc_set_signal_voltage(mmc, best_match))
1856 allowed_mask &= ~best_match;
1862 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1863 uint32_t allowed_mask)
1869 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1870 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1872 .mode = MMC_HS_400_ES,
1873 .widths = MMC_MODE_8BIT,
1876 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1879 .widths = MMC_MODE_8BIT,
1880 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1883 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1886 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1887 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1892 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1896 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1900 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1904 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1908 #define for_each_mmc_mode_by_pref(caps, mwt) \
1909 for (mwt = mmc_modes_by_pref;\
1910 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1912 if (caps & MMC_CAP(mwt->mode))
1914 static const struct ext_csd_bus_width {
1918 } ext_csd_bus_width[] = {
1919 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1920 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1921 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1922 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1923 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1926 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1927 static int mmc_select_hs400(struct mmc *mmc)
1931 /* Set timing to HS200 for tuning */
1932 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
1936 /* configure the bus mode (host) */
1937 mmc_select_mode(mmc, MMC_HS_200);
1938 mmc_set_clock(mmc, mmc->tran_speed, false);
1940 /* execute tuning if needed */
1941 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1943 debug("tuning failed\n");
1947 /* Set back to HS */
1948 mmc_set_card_speed(mmc, MMC_HS, true);
1950 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1951 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1955 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
1959 mmc_select_mode(mmc, MMC_HS_400);
1960 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1967 static int mmc_select_hs400(struct mmc *mmc)
1973 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1974 #if !CONFIG_IS_ENABLED(DM_MMC)
1975 static int mmc_set_enhanced_strobe(struct mmc *mmc)
1980 static int mmc_select_hs400es(struct mmc *mmc)
1984 err = mmc_set_card_speed(mmc, MMC_HS, true);
1988 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1989 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
1990 EXT_CSD_BUS_WIDTH_STROBE);
1992 printf("switch to bus width for hs400 failed\n");
1995 /* TODO: driver strength */
1996 err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2000 mmc_select_mode(mmc, MMC_HS_400_ES);
2001 err = mmc_set_clock(mmc, mmc->tran_speed, false);
2005 return mmc_set_enhanced_strobe(mmc);
2008 static int mmc_select_hs400es(struct mmc *mmc)
2014 #define for_each_supported_width(caps, ddr, ecbv) \
2015 for (ecbv = ext_csd_bus_width;\
2016 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2018 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2020 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
2023 const struct mode_width_tuning *mwt;
2024 const struct ext_csd_bus_width *ecbw;
2027 mmc_dump_capabilities("mmc", card_caps);
2028 mmc_dump_capabilities("host", mmc->host_caps);
2031 if (mmc_host_is_spi(mmc)) {
2032 mmc_set_bus_width(mmc, 1);
2033 mmc_select_mode(mmc, MMC_LEGACY);
2034 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2038 /* Restrict card's capabilities by what the host can do */
2039 card_caps &= mmc->host_caps;
2041 /* Only version 4 of MMC supports wider bus widths */
2042 if (mmc->version < MMC_VERSION_4)
2045 if (!mmc->ext_csd) {
2046 pr_debug("No ext_csd found!\n"); /* this should enver happen */
2050 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2051 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2053 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2054 * before doing anything else, since a transition from either of
2055 * the HS200/HS400 mode directly to legacy mode is not supported.
2057 if (mmc->selected_mode == MMC_HS_200 ||
2058 mmc->selected_mode == MMC_HS_400)
2059 mmc_set_card_speed(mmc, MMC_HS, true);
2062 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
2064 for_each_mmc_mode_by_pref(card_caps, mwt) {
2065 for_each_supported_width(card_caps & mwt->widths,
2066 mmc_is_mode_ddr(mwt->mode), ecbw) {
2067 enum mmc_voltage old_voltage;
2068 pr_debug("trying mode %s width %d (at %d MHz)\n",
2069 mmc_mode_name(mwt->mode),
2070 bus_width(ecbw->cap),
2071 mmc_mode2freq(mmc, mwt->mode) / 1000000);
2072 old_voltage = mmc->signal_voltage;
2073 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2074 MMC_ALL_SIGNAL_VOLTAGE);
2078 /* configure the bus width (card + host) */
2079 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2081 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2084 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2086 if (mwt->mode == MMC_HS_400) {
2087 err = mmc_select_hs400(mmc);
2089 printf("Select HS400 failed %d\n", err);
2092 } else if (mwt->mode == MMC_HS_400_ES) {
2093 err = mmc_select_hs400es(mmc);
2095 printf("Select HS400ES failed %d\n",
2100 /* configure the bus speed (card) */
2101 err = mmc_set_card_speed(mmc, mwt->mode, false);
2106 * configure the bus width AND the ddr mode
2107 * (card). The host side will be taken care
2108 * of in the next step
2110 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2111 err = mmc_switch(mmc,
2112 EXT_CSD_CMD_SET_NORMAL,
2114 ecbw->ext_csd_bits);
2119 /* configure the bus mode (host) */
2120 mmc_select_mode(mmc, mwt->mode);
2121 mmc_set_clock(mmc, mmc->tran_speed,
2123 #ifdef MMC_SUPPORTS_TUNING
2125 /* execute tuning if needed */
2127 err = mmc_execute_tuning(mmc,
2130 pr_debug("tuning failed\n");
2137 /* do a transfer to check the configuration */
2138 err = mmc_read_and_compare_ext_csd(mmc);
2142 mmc_set_signal_voltage(mmc, old_voltage);
2143 /* if an error occured, revert to a safer bus mode */
2144 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2145 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2146 mmc_select_mode(mmc, MMC_LEGACY);
2147 mmc_set_bus_width(mmc, 1);
2151 pr_err("unable to select a mode\n");
2157 #if CONFIG_IS_ENABLED(MMC_TINY)
2158 DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2161 static int mmc_startup_v4(struct mmc *mmc)
2165 bool has_parts = false;
2166 bool part_completed;
2167 static const u32 mmc_versions[] = {
2179 #if CONFIG_IS_ENABLED(MMC_TINY)
2180 u8 *ext_csd = ext_csd_bkup;
2182 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2186 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2188 err = mmc_send_ext_csd(mmc, ext_csd);
2192 /* store the ext csd for future reference */
2194 mmc->ext_csd = ext_csd;
2196 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2198 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2201 /* check ext_csd version and capacity */
2202 err = mmc_send_ext_csd(mmc, ext_csd);
2206 /* store the ext csd for future reference */
2208 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2211 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2213 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2216 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2218 if (mmc->version >= MMC_VERSION_4_2) {
2220 * According to the JEDEC Standard, the value of
2221 * ext_csd's capacity is valid if the value is more
2224 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2225 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2226 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2227 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2228 capacity *= MMC_MAX_BLOCK_LEN;
2229 if ((capacity >> 20) > 2 * 1024)
2230 mmc->capacity_user = capacity;
2233 if (mmc->version >= MMC_VERSION_4_5)
2234 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2236 /* The partition data may be non-zero but it is only
2237 * effective if PARTITION_SETTING_COMPLETED is set in
2238 * EXT_CSD, so ignore any data if this bit is not set,
2239 * except for enabling the high-capacity group size
2240 * definition (see below).
2242 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2243 EXT_CSD_PARTITION_SETTING_COMPLETED);
2245 mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2246 /* Some eMMC set the value too low so set a minimum */
2247 if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2248 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2250 /* store the partition info of emmc */
2251 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2252 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2253 ext_csd[EXT_CSD_BOOT_MULT])
2254 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2255 if (part_completed &&
2256 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2257 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2259 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2261 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2263 for (i = 0; i < 4; i++) {
2264 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2265 uint mult = (ext_csd[idx + 2] << 16) +
2266 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2269 if (!part_completed)
2271 mmc->capacity_gp[i] = mult;
2272 mmc->capacity_gp[i] *=
2273 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2274 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2275 mmc->capacity_gp[i] <<= 19;
2278 #ifndef CONFIG_SPL_BUILD
2279 if (part_completed) {
2280 mmc->enh_user_size =
2281 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2282 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2283 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2284 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2285 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2286 mmc->enh_user_size <<= 19;
2287 mmc->enh_user_start =
2288 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2289 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2290 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2291 ext_csd[EXT_CSD_ENH_START_ADDR];
2292 if (mmc->high_capacity)
2293 mmc->enh_user_start <<= 9;
2298 * Host needs to enable ERASE_GRP_DEF bit if device is
2299 * partitioned. This bit will be lost every time after a reset
2300 * or power off. This will affect erase size.
2304 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2305 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2308 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2309 EXT_CSD_ERASE_GROUP_DEF, 1);
2314 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2317 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2318 #if CONFIG_IS_ENABLED(MMC_WRITE)
2319 /* Read out group size from ext_csd */
2320 mmc->erase_grp_size =
2321 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2324 * if high capacity and partition setting completed
2325 * SEC_COUNT is valid even if it is smaller than 2 GiB
2326 * JEDEC Standard JESD84-B45, 6.2.4
2328 if (mmc->high_capacity && part_completed) {
2329 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2330 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2331 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2332 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2333 capacity *= MMC_MAX_BLOCK_LEN;
2334 mmc->capacity_user = capacity;
2337 #if CONFIG_IS_ENABLED(MMC_WRITE)
2339 /* Calculate the group size from the csd value. */
2340 int erase_gsz, erase_gmul;
2342 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2343 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2344 mmc->erase_grp_size = (erase_gsz + 1)
2348 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2349 mmc->hc_wp_grp_size = 1024
2350 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2351 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2354 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2359 #if !CONFIG_IS_ENABLED(MMC_TINY)
2362 mmc->ext_csd = NULL;
2367 static int mmc_startup(struct mmc *mmc)
2373 struct blk_desc *bdesc;
2375 #ifdef CONFIG_MMC_SPI_CRC_ON
2376 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2377 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2378 cmd.resp_type = MMC_RSP_R1;
2380 err = mmc_send_cmd(mmc, &cmd, NULL);
2386 /* Put the Card in Identify Mode */
2387 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2388 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2389 cmd.resp_type = MMC_RSP_R2;
2392 err = mmc_send_cmd(mmc, &cmd, NULL);
2394 #ifdef CONFIG_MMC_QUIRKS
2395 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2398 * It has been seen that SEND_CID may fail on the first
2399 * attempt, let's try a few more time
2402 err = mmc_send_cmd(mmc, &cmd, NULL);
2405 } while (retries--);
2412 memcpy(mmc->cid, cmd.response, 16);
2415 * For MMC cards, set the Relative Address.
2416 * For SD cards, get the Relatvie Address.
2417 * This also puts the cards into Standby State
2419 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2420 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2421 cmd.cmdarg = mmc->rca << 16;
2422 cmd.resp_type = MMC_RSP_R6;
2424 err = mmc_send_cmd(mmc, &cmd, NULL);
2430 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2433 /* Get the Card-Specific Data */
2434 cmd.cmdidx = MMC_CMD_SEND_CSD;
2435 cmd.resp_type = MMC_RSP_R2;
2436 cmd.cmdarg = mmc->rca << 16;
2438 err = mmc_send_cmd(mmc, &cmd, NULL);
2443 mmc->csd[0] = cmd.response[0];
2444 mmc->csd[1] = cmd.response[1];
2445 mmc->csd[2] = cmd.response[2];
2446 mmc->csd[3] = cmd.response[3];
2448 if (mmc->version == MMC_VERSION_UNKNOWN) {
2449 int version = (cmd.response[0] >> 26) & 0xf;
2453 mmc->version = MMC_VERSION_1_2;
2456 mmc->version = MMC_VERSION_1_4;
2459 mmc->version = MMC_VERSION_2_2;
2462 mmc->version = MMC_VERSION_3;
2465 mmc->version = MMC_VERSION_4;
2468 mmc->version = MMC_VERSION_1_2;
2473 /* divide frequency by 10, since the mults are 10x bigger */
2474 freq = fbase[(cmd.response[0] & 0x7)];
2475 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2477 mmc->legacy_speed = freq * mult;
2478 mmc_select_mode(mmc, MMC_LEGACY);
2480 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2481 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2482 #if CONFIG_IS_ENABLED(MMC_WRITE)
2485 mmc->write_bl_len = mmc->read_bl_len;
2487 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2490 if (mmc->high_capacity) {
2491 csize = (mmc->csd[1] & 0x3f) << 16
2492 | (mmc->csd[2] & 0xffff0000) >> 16;
2495 csize = (mmc->csd[1] & 0x3ff) << 2
2496 | (mmc->csd[2] & 0xc0000000) >> 30;
2497 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2500 mmc->capacity_user = (csize + 1) << (cmult + 2);
2501 mmc->capacity_user *= mmc->read_bl_len;
2502 mmc->capacity_boot = 0;
2503 mmc->capacity_rpmb = 0;
2504 for (i = 0; i < 4; i++)
2505 mmc->capacity_gp[i] = 0;
2507 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2508 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2510 #if CONFIG_IS_ENABLED(MMC_WRITE)
2511 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2512 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2515 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2516 cmd.cmdidx = MMC_CMD_SET_DSR;
2517 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2518 cmd.resp_type = MMC_RSP_NONE;
2519 if (mmc_send_cmd(mmc, &cmd, NULL))
2520 pr_warn("MMC: SET_DSR failed\n");
2523 /* Select the card, and put it into Transfer Mode */
2524 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2525 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2526 cmd.resp_type = MMC_RSP_R1;
2527 cmd.cmdarg = mmc->rca << 16;
2528 err = mmc_send_cmd(mmc, &cmd, NULL);
2535 * For SD, its erase group is always one sector
2537 #if CONFIG_IS_ENABLED(MMC_WRITE)
2538 mmc->erase_grp_size = 1;
2540 mmc->part_config = MMCPART_NOAVAILABLE;
2542 err = mmc_startup_v4(mmc);
2546 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2550 #if CONFIG_IS_ENABLED(MMC_TINY)
2551 mmc_set_clock(mmc, mmc->legacy_speed, false);
2552 mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2553 mmc_set_bus_width(mmc, 1);
2556 err = sd_get_capabilities(mmc);
2559 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2561 err = mmc_get_capabilities(mmc);
2564 mmc_select_mode_and_width(mmc, mmc->card_caps);
2570 mmc->best_mode = mmc->selected_mode;
2572 /* Fix the block length for DDR mode */
2573 if (mmc->ddr_mode) {
2574 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2575 #if CONFIG_IS_ENABLED(MMC_WRITE)
2576 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2580 /* fill in device description */
2581 bdesc = mmc_get_blk_desc(mmc);
2585 bdesc->blksz = mmc->read_bl_len;
2586 bdesc->log2blksz = LOG2(bdesc->blksz);
2587 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2588 #if !defined(CONFIG_SPL_BUILD) || \
2589 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2590 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
2591 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2592 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2593 (mmc->cid[3] >> 16) & 0xffff);
2594 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2595 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2596 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2597 (mmc->cid[2] >> 24) & 0xff);
2598 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2599 (mmc->cid[2] >> 16) & 0xf);
2601 bdesc->vendor[0] = 0;
2602 bdesc->product[0] = 0;
2603 bdesc->revision[0] = 0;
2606 #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2613 static int mmc_send_if_cond(struct mmc *mmc)
2618 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2619 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2620 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2621 cmd.resp_type = MMC_RSP_R7;
2623 err = mmc_send_cmd(mmc, &cmd, NULL);
2628 if ((cmd.response[0] & 0xff) != 0xaa)
2631 mmc->version = SD_VERSION_2;
2636 #if !CONFIG_IS_ENABLED(DM_MMC)
2637 /* board-specific MMC power initializations. */
2638 __weak void board_mmc_power_init(void)
2643 static int mmc_power_init(struct mmc *mmc)
2645 #if CONFIG_IS_ENABLED(DM_MMC)
2646 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2649 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2652 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2654 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2655 &mmc->vqmmc_supply);
2657 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2659 #else /* !CONFIG_DM_MMC */
2661 * Driver model should use a regulator, as above, rather than calling
2662 * out to board code.
2664 board_mmc_power_init();
2670 * put the host in the initial state:
2671 * - turn on Vdd (card power supply)
2672 * - configure the bus width and clock to minimal values
2674 static void mmc_set_initial_state(struct mmc *mmc)
2678 /* First try to set 3.3V. If it fails set to 1.8V */
2679 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2681 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2683 pr_warn("mmc: failed to set signal voltage\n");
2685 mmc_select_mode(mmc, MMC_LEGACY);
2686 mmc_set_bus_width(mmc, 1);
2687 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2690 static int mmc_power_on(struct mmc *mmc)
2692 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2693 if (mmc->vmmc_supply) {
2694 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2697 puts("Error enabling VMMC supply\n");
2705 static int mmc_power_off(struct mmc *mmc)
2707 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
2708 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2709 if (mmc->vmmc_supply) {
2710 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2713 pr_debug("Error disabling VMMC supply\n");
2721 static int mmc_power_cycle(struct mmc *mmc)
2725 ret = mmc_power_off(mmc);
2729 ret = mmc_host_power_cycle(mmc);
2734 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2735 * to be on the safer side.
2738 return mmc_power_on(mmc);
2741 int mmc_get_op_cond(struct mmc *mmc)
2743 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2749 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2750 mmc_adapter_card_type_ident();
2752 err = mmc_power_init(mmc);
2756 #ifdef CONFIG_MMC_QUIRKS
2757 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2758 MMC_QUIRK_RETRY_SEND_CID;
2761 err = mmc_power_cycle(mmc);
2764 * if power cycling is not supported, we should not try
2765 * to use the UHS modes, because we wouldn't be able to
2766 * recover from an error during the UHS initialization.
2768 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2770 mmc->host_caps &= ~UHS_CAPS;
2771 err = mmc_power_on(mmc);
2776 #if CONFIG_IS_ENABLED(DM_MMC)
2777 /* The device has already been probed ready for use */
2779 /* made sure it's not NULL earlier */
2780 err = mmc->cfg->ops->init(mmc);
2787 mmc_set_initial_state(mmc);
2789 /* Reset the Card */
2790 err = mmc_go_idle(mmc);
2795 /* The internal partition reset to user partition(0) at every CMD0*/
2796 mmc_get_blk_desc(mmc)->hwpart = 0;
2798 /* Test for SD version 2 */
2799 err = mmc_send_if_cond(mmc);
2801 /* Now try to get the SD card's operating condition */
2802 err = sd_send_op_cond(mmc, uhs_en);
2803 if (err && uhs_en) {
2805 mmc_power_cycle(mmc);
2809 /* If the command timed out, we check for an MMC card */
2810 if (err == -ETIMEDOUT) {
2811 err = mmc_send_op_cond(mmc);
2814 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2815 pr_err("Card did not respond to voltage select!\n");
2824 int mmc_start_init(struct mmc *mmc)
2830 * all hosts are capable of 1 bit bus-width and able to use the legacy
2833 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2834 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2836 #if !defined(CONFIG_MMC_BROKEN_CD)
2837 no_card = mmc_getcd(mmc) == 0;
2841 #if !CONFIG_IS_ENABLED(DM_MMC)
2842 /* we pretend there's no card when init is NULL */
2843 no_card = no_card || (mmc->cfg->ops->init == NULL);
2847 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2848 pr_err("MMC: no card present\n");
2853 err = mmc_get_op_cond(mmc);
2856 mmc->init_in_progress = 1;
2861 static int mmc_complete_init(struct mmc *mmc)
2865 mmc->init_in_progress = 0;
2866 if (mmc->op_cond_pending)
2867 err = mmc_complete_op_cond(mmc);
2870 err = mmc_startup(mmc);
2878 int mmc_init(struct mmc *mmc)
2881 __maybe_unused ulong start;
2882 #if CONFIG_IS_ENABLED(DM_MMC)
2883 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2890 start = get_timer(0);
2892 if (!mmc->init_in_progress)
2893 err = mmc_start_init(mmc);
2896 err = mmc_complete_init(mmc);
2898 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2903 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2904 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2905 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2906 int mmc_deinit(struct mmc *mmc)
2914 caps_filtered = mmc->card_caps &
2915 ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2916 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2917 MMC_CAP(UHS_SDR104));
2919 return sd_select_mode_and_width(mmc, caps_filtered);
2921 caps_filtered = mmc->card_caps &
2922 ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2924 return mmc_select_mode_and_width(mmc, caps_filtered);
2929 int mmc_set_dsr(struct mmc *mmc, u16 val)
2935 /* CPU-specific MMC initializations */
2936 __weak int cpu_mmc_init(bd_t *bis)
2941 /* board-specific MMC initializations. */
2942 __weak int board_mmc_init(bd_t *bis)
2947 void mmc_set_preinit(struct mmc *mmc, int preinit)
2949 mmc->preinit = preinit;
2952 #if CONFIG_IS_ENABLED(DM_MMC)
2953 static int mmc_probe(bd_t *bis)
2957 struct udevice *dev;
2959 ret = uclass_get(UCLASS_MMC, &uc);
2964 * Try to add them in sequence order. Really with driver model we
2965 * should allow holes, but the current MMC list does not allow that.
2966 * So if we request 0, 1, 3 we will get 0, 1, 2.
2968 for (i = 0; ; i++) {
2969 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2973 uclass_foreach_dev(dev, uc) {
2974 ret = device_probe(dev);
2976 pr_err("%s - probe failed: %d\n", dev->name, ret);
2982 static int mmc_probe(bd_t *bis)
2984 if (board_mmc_init(bis) < 0)
2991 int mmc_initialize(bd_t *bis)
2993 static int initialized = 0;
2995 if (initialized) /* Avoid initializing mmc multiple times */
2999 #if !CONFIG_IS_ENABLED(BLK)
3000 #if !CONFIG_IS_ENABLED(MMC_TINY)
3004 ret = mmc_probe(bis);
3008 #ifndef CONFIG_SPL_BUILD
3009 print_mmc_devices(',');
3016 #if CONFIG_IS_ENABLED(DM_MMC)
3017 int mmc_init_device(int num)
3019 struct udevice *dev;
3023 ret = uclass_get_device(UCLASS_MMC, num, &dev);
3027 m = mmc_get_mmc_dev(dev);
3030 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
3031 mmc_set_preinit(m, 1);
3040 #ifdef CONFIG_CMD_BKOPS_ENABLE
3041 int mmc_set_bkops_enable(struct mmc *mmc)
3044 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3046 err = mmc_send_ext_csd(mmc, ext_csd);
3048 puts("Could not get ext_csd register values\n");
3052 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3053 puts("Background operations not supported on device\n");
3054 return -EMEDIUMTYPE;
3057 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
3058 puts("Background operations already enabled\n");
3062 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
3064 puts("Failed to enable manual background operations\n");
3068 puts("Enabled manual background operations\n");