1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
16 #include <asm/arch/sd_emmc.h>
17 #include <linux/delay.h>
18 #include <linux/log2.h>
20 static inline void *get_regbase(const struct mmc *mmc)
22 struct meson_mmc_platdata *pdata = mmc->priv;
24 return pdata->regbase;
27 static inline uint32_t meson_read(struct mmc *mmc, int offset)
29 return readl(get_regbase(mmc) + offset);
32 static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
34 writel(val, get_regbase(mmc) + offset);
37 static void meson_mmc_config_clock(struct mmc *mmc)
39 uint32_t meson_mmc_clk = 0;
40 unsigned int clk, clk_src, clk_div;
45 /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
46 if (mmc->clock > 16000000) {
47 clk = SD_EMMC_CLKSRC_DIV2;
48 clk_src = CLK_SRC_DIV2;
50 clk = SD_EMMC_CLKSRC_24M;
51 clk_src = CLK_SRC_24M;
53 clk_div = DIV_ROUND_UP(clk, mmc->clock);
55 /* 180 phase core clock */
56 meson_mmc_clk |= CLK_CO_PHASE_180;
58 /* 180 phase tx clock */
59 meson_mmc_clk |= CLK_TX_PHASE_000;
62 meson_mmc_clk |= clk_src;
63 meson_mmc_clk |= clk_div;
65 meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
68 static int meson_dm_mmc_set_ios(struct udevice *dev)
70 struct mmc *mmc = mmc_get_mmc_dev(dev);
71 uint32_t meson_mmc_cfg;
73 meson_mmc_config_clock(mmc);
75 meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
77 meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
78 if (mmc->bus_width == 1)
79 meson_mmc_cfg |= CFG_BUS_WIDTH_1;
80 else if (mmc->bus_width == 4)
81 meson_mmc_cfg |= CFG_BUS_WIDTH_4;
82 else if (mmc->bus_width == 8)
83 meson_mmc_cfg |= CFG_BUS_WIDTH_8;
87 /* 512 bytes block length */
88 meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
89 meson_mmc_cfg |= CFG_BL_LEN_512;
91 /* Response timeout 256 clk */
92 meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
93 meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
95 /* Command-command gap 16 clk */
96 meson_mmc_cfg &= ~CFG_RC_CC_MASK;
97 meson_mmc_cfg |= CFG_RC_CC_16;
99 meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
104 static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
107 uint32_t meson_mmc_cmd = 0, cfg;
109 meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
111 if (cmd->resp_type & MMC_RSP_PRESENT) {
112 if (cmd->resp_type & MMC_RSP_136)
113 meson_mmc_cmd |= CMD_CFG_RESP_128;
115 if (cmd->resp_type & MMC_RSP_BUSY)
116 meson_mmc_cmd |= CMD_CFG_R1B;
118 if (!(cmd->resp_type & MMC_RSP_CRC))
119 meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
121 meson_mmc_cmd |= CMD_CFG_NO_RESP;
125 cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
126 cfg &= ~CFG_BL_LEN_MASK;
127 cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
128 meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
130 if (data->flags == MMC_DATA_WRITE)
131 meson_mmc_cmd |= CMD_CFG_DATA_WR;
133 meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
137 meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
138 CMD_CFG_END_OF_CHAIN;
140 meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
143 static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
145 struct meson_mmc_platdata *pdata = mmc->priv;
146 unsigned int data_size;
147 uint32_t data_addr = 0;
150 data_size = data->blocks * data->blocksize;
152 if (data->flags == MMC_DATA_READ) {
153 data_addr = (ulong) data->dest;
154 invalidate_dcache_range(data_addr,
155 data_addr + data_size);
157 pdata->w_buf = calloc(data_size, sizeof(char));
158 data_addr = (ulong) pdata->w_buf;
159 memcpy(pdata->w_buf, data->src, data_size);
160 flush_dcache_range(data_addr, data_addr + data_size);
164 meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
167 static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
169 if (cmd->resp_type & MMC_RSP_136) {
170 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
171 cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
172 cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
173 cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
175 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
179 static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
180 struct mmc_data *data)
182 struct mmc *mmc = mmc_get_mmc_dev(dev);
183 struct meson_mmc_platdata *pdata = mmc->priv;
188 /* max block size supported by chip is 512 byte */
189 if (data && data->blocksize > 512)
192 meson_mmc_setup_cmd(mmc, data, cmd);
193 meson_mmc_setup_addr(mmc, data);
195 meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
197 /* use 10s timeout */
198 start = get_timer(0);
200 status = meson_read(mmc, MESON_SD_EMMC_STATUS);
201 } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
203 if (!(status & STATUS_END_OF_CHAIN))
205 else if (status & STATUS_RESP_TIMEOUT)
207 else if (status & STATUS_ERR_MASK)
210 meson_mmc_read_response(mmc, cmd);
212 if (data && data->flags == MMC_DATA_WRITE)
215 /* reset status bits */
216 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
221 static const struct dm_mmc_ops meson_dm_mmc_ops = {
222 .send_cmd = meson_dm_mmc_send_cmd,
223 .set_ios = meson_dm_mmc_set_ios,
226 static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
228 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
231 addr = devfdt_get_addr(dev);
232 if (addr == FDT_ADDR_T_NONE)
235 pdata->regbase = (void *)addr;
240 static int meson_mmc_probe(struct udevice *dev)
242 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
243 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
244 struct mmc *mmc = &pdata->mmc;
245 struct mmc_config *cfg = &pdata->cfg;
246 struct clk_bulk clocks;
251 struct udevice *pwr_dev;
254 /* Enable the clocks feeding the MMC controller */
255 ret = clk_get_bulk(dev, &clocks);
259 ret = clk_enable_bulk(&clocks);
263 cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
264 MMC_VDD_31_32 | MMC_VDD_165_195;
265 cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
266 MMC_MODE_HS_52MHz | MMC_MODE_HS;
267 cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
268 cfg->f_max = 100000000; /* 100 MHz */
269 cfg->b_max = 511; /* max 512 - 1 blocks */
270 cfg->name = dev->name;
275 mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
278 /* Enable power if needed */
279 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
282 ret = pwrseq_set_power(pwr_dev, true);
288 /* reset all status bits */
289 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
291 /* disable interrupts */
292 meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
294 /* enable auto clock mode */
295 val = meson_read(mmc, MESON_SD_EMMC_CFG);
296 val &= ~CFG_SDCLK_ALWAYS_ON;
298 meson_write(mmc, val, MESON_SD_EMMC_CFG);
303 int meson_mmc_bind(struct udevice *dev)
305 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
307 return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
310 static const struct udevice_id meson_mmc_match[] = {
311 { .compatible = "amlogic,meson-gx-mmc" },
312 { .compatible = "amlogic,meson-axg-mmc" },
316 U_BOOT_DRIVER(meson_mmc) = {
317 .name = "meson_gx_mmc",
319 .of_match = meson_mmc_match,
320 .ops = &meson_dm_mmc_ops,
321 .probe = meson_mmc_probe,
322 .bind = meson_mmc_bind,
323 .ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
324 .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
328 static int meson_mmc_pwrseq_set_power(struct udevice *dev, bool enable)
330 struct gpio_desc reset;
333 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
336 dm_gpio_set_value(&reset, 1);
338 dm_gpio_set_value(&reset, 0);
344 static const struct pwrseq_ops meson_mmc_pwrseq_ops = {
345 .set_power = meson_mmc_pwrseq_set_power,
348 static const struct udevice_id meson_mmc_pwrseq_ids[] = {
349 { .compatible = "mmc-pwrseq-emmc" },
353 U_BOOT_DRIVER(meson_mmc_pwrseq_drv) = {
354 .name = "mmc_pwrseq_emmc",
356 .of_match = meson_mmc_pwrseq_ids,
357 .ops = &meson_mmc_pwrseq_ops,