1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
16 #include <linux/delay.h>
17 #include <linux/log2.h>
18 #include "meson_gx_mmc.h"
20 bool meson_gx_mmc_is_compatible(struct udevice *dev,
21 enum meson_gx_mmc_compatible family)
23 enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
25 return compat == family;
28 static inline void *get_regbase(const struct mmc *mmc)
30 struct meson_mmc_platdata *pdata = mmc->priv;
32 return pdata->regbase;
35 static inline uint32_t meson_read(struct mmc *mmc, int offset)
37 return readl(get_regbase(mmc) + offset);
40 static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
42 writel(val, get_regbase(mmc) + offset);
45 static void meson_mmc_config_clock(struct mmc *mmc)
47 uint32_t meson_mmc_clk = 0;
48 unsigned int clk, clk_src, clk_div;
53 /* TOFIX This should use the proper clock taken from DT */
55 /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
56 if (mmc->clock > 16000000) {
57 clk = SD_EMMC_CLKSRC_DIV2;
58 clk_src = CLK_SRC_DIV2;
60 clk = SD_EMMC_CLKSRC_24M;
61 clk_src = CLK_SRC_24M;
63 clk_div = DIV_ROUND_UP(clk, mmc->clock);
66 * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
67 * If CLK_CO_PHASE_270 is used, it's more stable than other.
68 * Other SoCs use CLK_CO_PHASE_180 by default.
69 * It needs to find what is a proper value about each SoCs.
71 if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
72 meson_mmc_clk |= CLK_CO_PHASE_270;
74 meson_mmc_clk |= CLK_CO_PHASE_180;
76 /* 180 phase tx clock */
77 meson_mmc_clk |= CLK_TX_PHASE_000;
80 meson_mmc_clk |= clk_src;
81 meson_mmc_clk |= clk_div;
83 meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
86 static int meson_dm_mmc_set_ios(struct udevice *dev)
88 struct mmc *mmc = mmc_get_mmc_dev(dev);
89 uint32_t meson_mmc_cfg;
91 meson_mmc_config_clock(mmc);
93 meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
95 meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
96 if (mmc->bus_width == 1)
97 meson_mmc_cfg |= CFG_BUS_WIDTH_1;
98 else if (mmc->bus_width == 4)
99 meson_mmc_cfg |= CFG_BUS_WIDTH_4;
100 else if (mmc->bus_width == 8)
101 meson_mmc_cfg |= CFG_BUS_WIDTH_8;
105 /* 512 bytes block length */
106 meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
107 meson_mmc_cfg |= CFG_BL_LEN_512;
109 /* Response timeout 256 clk */
110 meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
111 meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
113 /* Command-command gap 16 clk */
114 meson_mmc_cfg &= ~CFG_RC_CC_MASK;
115 meson_mmc_cfg |= CFG_RC_CC_16;
117 meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
122 static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
125 uint32_t meson_mmc_cmd = 0, cfg;
127 meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
129 if (cmd->resp_type & MMC_RSP_PRESENT) {
130 if (cmd->resp_type & MMC_RSP_136)
131 meson_mmc_cmd |= CMD_CFG_RESP_128;
133 if (cmd->resp_type & MMC_RSP_BUSY)
134 meson_mmc_cmd |= CMD_CFG_R1B;
136 if (!(cmd->resp_type & MMC_RSP_CRC))
137 meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
139 meson_mmc_cmd |= CMD_CFG_NO_RESP;
143 cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
144 cfg &= ~CFG_BL_LEN_MASK;
145 cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
146 meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
148 if (data->flags == MMC_DATA_WRITE)
149 meson_mmc_cmd |= CMD_CFG_DATA_WR;
151 meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
155 meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
156 CMD_CFG_END_OF_CHAIN;
158 meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
161 static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
163 struct meson_mmc_platdata *pdata = mmc->priv;
164 unsigned int data_size;
165 uint32_t data_addr = 0;
168 data_size = data->blocks * data->blocksize;
170 if (data->flags == MMC_DATA_READ) {
171 data_addr = (ulong) data->dest;
172 invalidate_dcache_range(data_addr,
173 data_addr + data_size);
175 pdata->w_buf = calloc(data_size, sizeof(char));
176 data_addr = (ulong) pdata->w_buf;
177 memcpy(pdata->w_buf, data->src, data_size);
178 flush_dcache_range(data_addr, data_addr + data_size);
182 meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
185 static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
187 if (cmd->resp_type & MMC_RSP_136) {
188 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
189 cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
190 cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
191 cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
193 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
197 static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
198 struct mmc_data *data)
200 struct mmc *mmc = mmc_get_mmc_dev(dev);
201 struct meson_mmc_platdata *pdata = mmc->priv;
206 /* max block size supported by chip is 512 byte */
207 if (data && data->blocksize > 512)
210 meson_mmc_setup_cmd(mmc, data, cmd);
211 meson_mmc_setup_addr(mmc, data);
213 meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
215 /* use 10s timeout */
216 start = get_timer(0);
218 status = meson_read(mmc, MESON_SD_EMMC_STATUS);
219 } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
221 if (!(status & STATUS_END_OF_CHAIN))
223 else if (status & STATUS_RESP_TIMEOUT)
225 else if (status & STATUS_ERR_MASK)
228 meson_mmc_read_response(mmc, cmd);
230 if (data && data->flags == MMC_DATA_WRITE)
233 /* reset status bits */
234 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
239 static const struct dm_mmc_ops meson_dm_mmc_ops = {
240 .send_cmd = meson_dm_mmc_send_cmd,
241 .set_ios = meson_dm_mmc_set_ios,
244 static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
246 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
249 addr = dev_read_addr(dev);
250 if (addr == FDT_ADDR_T_NONE)
253 pdata->regbase = (void *)addr;
258 static int meson_mmc_probe(struct udevice *dev)
260 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
261 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
262 struct mmc *mmc = &pdata->mmc;
263 struct mmc_config *cfg = &pdata->cfg;
264 struct clk_bulk clocks;
269 struct udevice *pwr_dev;
272 /* Enable the clocks feeding the MMC controller */
273 ret = clk_get_bulk(dev, &clocks);
277 ret = clk_enable_bulk(&clocks);
281 cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
282 MMC_VDD_31_32 | MMC_VDD_165_195;
283 cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
284 MMC_MODE_HS_52MHz | MMC_MODE_HS;
285 cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
286 cfg->f_max = 100000000; /* 100 MHz */
287 cfg->b_max = 511; /* max 512 - 1 blocks */
288 cfg->name = dev->name;
293 mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
296 /* Enable power if needed */
297 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
300 ret = pwrseq_set_power(pwr_dev, true);
306 /* reset all status bits */
307 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
309 /* disable interrupts */
310 meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
312 /* enable auto clock mode */
313 val = meson_read(mmc, MESON_SD_EMMC_CFG);
314 val &= ~CFG_SDCLK_ALWAYS_ON;
316 meson_write(mmc, val, MESON_SD_EMMC_CFG);
321 int meson_mmc_bind(struct udevice *dev)
323 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
325 return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
328 static const struct udevice_id meson_mmc_match[] = {
329 { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
330 { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
331 { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
335 U_BOOT_DRIVER(meson_mmc) = {
336 .name = "meson_gx_mmc",
338 .of_match = meson_mmc_match,
339 .ops = &meson_dm_mmc_ops,
340 .probe = meson_mmc_probe,
341 .bind = meson_mmc_bind,
342 .ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
343 .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
347 static int meson_mmc_pwrseq_set_power(struct udevice *dev, bool enable)
349 struct gpio_desc reset;
352 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
355 dm_gpio_set_value(&reset, 1);
357 dm_gpio_set_value(&reset, 0);
363 static const struct pwrseq_ops meson_mmc_pwrseq_ops = {
364 .set_power = meson_mmc_pwrseq_set_power,
367 static const struct udevice_id meson_mmc_pwrseq_ids[] = {
368 { .compatible = "mmc-pwrseq-emmc" },
372 U_BOOT_DRIVER(meson_mmc_pwrseq_drv) = {
373 .name = "mmc_pwrseq_emmc",
375 .of_match = meson_mmc_pwrseq_ids,
376 .ops = &meson_mmc_pwrseq_ops,