1 // SPDX-License-Identifier: GPL-2.0+
3 * Ingenic JZ MMC driver
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
13 #include <asm/unaligned.h>
15 #include <dm/device_compat.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <mach/jz4780.h>
22 #define MSC_STRPCL 0x000
23 #define MSC_STAT 0x004
24 #define MSC_CLKRT 0x008
25 #define MSC_CMDAT 0x00c
26 #define MSC_RESTO 0x010
27 #define MSC_RDTO 0x014
28 #define MSC_BLKLEN 0x018
30 #define MSC_SNOB 0x020
31 #define MSC_IMASK 0x024
32 #define MSC_IREG 0x028
36 #define MSC_RXFIFO 0x038
37 #define MSC_TXFIFO 0x03c
39 #define MSC_DMAC 0x044
40 #define MSC_DMANDA 0x048
41 #define MSC_DMADA 0x04c
42 #define MSC_DMALEN 0x050
43 #define MSC_DMACMD 0x054
44 #define MSC_CTRL2 0x058
45 #define MSC_RTCNT 0x05c
48 /* MSC Clock and Control Register (MSC_STRPCL) */
49 #define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
50 #define MSC_STRPCL_EXIT_TRANSFER BIT(6)
51 #define MSC_STRPCL_START_READWAIT BIT(5)
52 #define MSC_STRPCL_STOP_READWAIT BIT(4)
53 #define MSC_STRPCL_RESET BIT(3)
54 #define MSC_STRPCL_START_OP BIT(2)
55 #define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
56 #define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
58 /* MSC Status Register (MSC_STAT) */
59 #define MSC_STAT_AUTO_CMD_DONE BIT(31)
60 #define MSC_STAT_IS_RESETTING BIT(15)
61 #define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
62 #define MSC_STAT_PRG_DONE BIT(13)
63 #define MSC_STAT_DATA_TRAN_DONE BIT(12)
64 #define MSC_STAT_END_CMD_RES BIT(11)
65 #define MSC_STAT_DATA_FIFO_AFULL BIT(10)
66 #define MSC_STAT_IS_READWAIT BIT(9)
67 #define MSC_STAT_CLK_EN BIT(8)
68 #define MSC_STAT_DATA_FIFO_FULL BIT(7)
69 #define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
70 #define MSC_STAT_CRC_RES_ERR BIT(5)
71 #define MSC_STAT_CRC_READ_ERROR BIT(4)
72 #define MSC_STAT_CRC_WRITE_ERROR BIT(2)
73 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
74 #define MSC_STAT_TIME_OUT_RES BIT(1)
75 #define MSC_STAT_TIME_OUT_READ BIT(0)
77 /* MSC Bus Clock Control Register (MSC_CLKRT) */
78 #define MSC_CLKRT_CLK_RATE_MASK 0x7
80 /* MSC Command Sequence Control Register (MSC_CMDAT) */
81 #define MSC_CMDAT_IO_ABORT BIT(11)
82 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
83 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
84 #define MSC_CMDAT_DMA_EN BIT(8)
85 #define MSC_CMDAT_INIT BIT(7)
86 #define MSC_CMDAT_BUSY BIT(6)
87 #define MSC_CMDAT_STREAM_BLOCK BIT(5)
88 #define MSC_CMDAT_WRITE BIT(4)
89 #define MSC_CMDAT_DATA_EN BIT(3)
90 #define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
91 #define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
92 #define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
93 #define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
94 #define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
95 #define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
96 #define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
97 #define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
99 /* MSC Interrupts Mask Register (MSC_IMASK) */
100 #define MSC_IMASK_TIME_OUT_RES BIT(9)
101 #define MSC_IMASK_TIME_OUT_READ BIT(8)
102 #define MSC_IMASK_SDIO BIT(7)
103 #define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
104 #define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
105 #define MSC_IMASK_END_CMD_RES BIT(2)
106 #define MSC_IMASK_PRG_DONE BIT(1)
107 #define MSC_IMASK_DATA_TRAN_DONE BIT(0)
109 /* MSC Interrupts Status Register (MSC_IREG) */
110 #define MSC_IREG_TIME_OUT_RES BIT(9)
111 #define MSC_IREG_TIME_OUT_READ BIT(8)
112 #define MSC_IREG_SDIO BIT(7)
113 #define MSC_IREG_TXFIFO_WR_REQ BIT(6)
114 #define MSC_IREG_RXFIFO_RD_REQ BIT(5)
115 #define MSC_IREG_END_CMD_RES BIT(2)
116 #define MSC_IREG_PRG_DONE BIT(1)
117 #define MSC_IREG_DATA_TRAN_DONE BIT(0)
120 struct mmc_config cfg;
128 #define JZ_MMC_BUS_WIDTH_MASK 0x3
129 #define JZ_MMC_BUS_WIDTH_1 0x0
130 #define JZ_MMC_BUS_WIDTH_4 0x2
131 #define JZ_MMC_BUS_WIDTH_8 0x3
132 #define JZ_MMC_SENT_INIT BIT(2)
135 static int jz_mmc_clock_rate(void)
140 #if CONFIG_IS_ENABLED(MMC_WRITE)
141 static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
143 int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
144 const void *buf = data->src;
147 u32 val = get_unaligned_le32(buf);
149 wait_for_bit_le32(priv->regs + MSC_IREG,
150 MSC_IREG_TXFIFO_WR_REQ,
152 writel(val, priv->regs + MSC_TXFIFO);
157 static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
161 static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
163 int sz = data->blocks * data->blocksize;
164 void *buf = data->dest;
168 stat = readl(priv->regs + MSC_STAT);
170 if (stat & MSC_STAT_TIME_OUT_READ)
172 if (stat & MSC_STAT_CRC_READ_ERROR)
174 if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
179 val = readl(priv->regs + MSC_RXFIFO);
181 *(u8 *)buf = (u8)val;
183 put_unaligned_le16(val, buf);
185 put_unaligned_le32(val, buf);
188 stat = readl(priv->regs + MSC_STAT);
189 } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
190 } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
194 static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
195 struct mmc_cmd *cmd, struct mmc_data *data)
197 u32 stat, mask, cmdat = 0;
201 writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
202 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
203 MSC_STAT_CLK_EN, false, 10000, false);
207 writel(0, priv->regs + MSC_DMAC);
210 writel(cmd->cmdidx, priv->regs + MSC_CMD);
211 writel(cmd->cmdarg, priv->regs + MSC_ARG);
215 cmdat |= MSC_CMDAT_DATA_EN;
216 if (data->flags & MMC_DATA_WRITE)
217 cmdat |= MSC_CMDAT_WRITE;
219 writel(data->blocks, priv->regs + MSC_NOB);
220 writel(data->blocksize, priv->regs + MSC_BLKLEN);
222 writel(0, priv->regs + MSC_NOB);
223 writel(0, priv->regs + MSC_BLKLEN);
227 switch (cmd->resp_type) {
232 cmdat |= MSC_CMDAT_RESPONSE_R1;
235 cmdat |= MSC_CMDAT_RESPONSE_R2;
238 cmdat |= MSC_CMDAT_RESPONSE_R3;
244 if (cmd->resp_type & MMC_RSP_BUSY)
245 cmdat |= MSC_CMDAT_BUSY;
247 /* set init for the first command only */
248 if (!(priv->flags & JZ_MMC_SENT_INIT)) {
249 cmdat |= MSC_CMDAT_INIT;
250 priv->flags |= JZ_MMC_SENT_INIT;
253 cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
255 /* write the data setup */
256 writel(cmdat, priv->regs + MSC_CMDAT);
258 /* unmask interrupts */
259 mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
261 mask &= ~MSC_IMASK_DATA_TRAN_DONE;
262 if (data->flags & MMC_DATA_WRITE) {
263 mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
265 mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
266 MSC_IMASK_TIME_OUT_READ);
269 writel(mask, priv->regs + MSC_IMASK);
271 /* clear interrupts */
272 writel(0xffffffff, priv->regs + MSC_IREG);
274 /* start the command (& the clock) */
275 writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
276 priv->regs + MSC_STRPCL);
278 /* wait for completion */
279 for (i = 0; i < 100; i++) {
280 stat = readl(priv->regs + MSC_IREG);
281 stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
286 writel(stat, priv->regs + MSC_IREG);
287 if (stat & MSC_IREG_TIME_OUT_RES)
290 if (cmd->resp_type & MMC_RSP_PRESENT) {
291 /* read the response */
292 if (cmd->resp_type & MMC_RSP_136) {
295 a = readw(priv->regs + MSC_RES);
296 for (i = 0; i < 4; i++) {
297 b = readw(priv->regs + MSC_RES);
298 c = readw(priv->regs + MSC_RES);
300 (a << 24) | (b << 8) | (c >> 8);
304 cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
305 cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
306 cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
310 if (data->flags & MMC_DATA_WRITE)
311 jz_mmc_write_data(priv, data);
312 else if (data->flags & MMC_DATA_READ) {
313 ret = jz_mmc_read_data(priv, data);
322 static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
324 u32 real_rate = jz_mmc_clock_rate();
327 /* calculate clock divide */
328 while ((real_rate > mmc->clock) && (clk_div < 7)) {
332 writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
334 /* set the bus width for the next command */
335 priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
336 if (mmc->bus_width == 8)
337 priv->flags |= JZ_MMC_BUS_WIDTH_8;
338 else if (mmc->bus_width == 4)
339 priv->flags |= JZ_MMC_BUS_WIDTH_4;
341 priv->flags |= JZ_MMC_BUS_WIDTH_1;
346 static int jz_mmc_core_init(struct mmc *mmc)
348 struct jz_mmc_priv *priv = mmc->priv;
352 writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
353 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
354 MSC_STAT_IS_RESETTING, false, 10000, false);
358 /* Maximum timeouts */
359 writel(0xffff, priv->regs + MSC_RESTO);
360 writel(0xffffffff, priv->regs + MSC_RDTO);
362 /* Enable low power mode */
363 writel(0x1, priv->regs + MSC_LPM);
368 #if !CONFIG_IS_ENABLED(DM_MMC)
370 static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
371 struct mmc_data *data)
373 struct jz_mmc_priv *priv = mmc->priv;
375 return jz_mmc_send_cmd(mmc, priv, cmd, data);
378 static int jz_mmc_legacy_set_ios(struct mmc *mmc)
380 struct jz_mmc_priv *priv = mmc->priv;
382 return jz_mmc_set_ios(mmc, priv);
385 static const struct mmc_ops jz_msc_ops = {
386 .send_cmd = jz_mmc_legacy_send_cmd,
387 .set_ios = jz_mmc_legacy_set_ios,
388 .init = jz_mmc_core_init,
391 static struct jz_mmc_priv jz_mmc_priv_static;
392 static struct jz_mmc_plat jz_mmc_plat_static = {
397 .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
398 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
399 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
400 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
404 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
408 int jz_mmc_init(void __iomem *base)
412 jz_mmc_priv_static.regs = base;
414 mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
416 return mmc ? 0 : -ENODEV;
419 #else /* CONFIG_DM_MMC */
422 DECLARE_GLOBAL_DATA_PTR;
424 static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
425 struct mmc_data *data)
427 struct jz_mmc_priv *priv = dev_get_priv(dev);
428 struct mmc *mmc = mmc_get_mmc_dev(dev);
430 return jz_mmc_send_cmd(mmc, priv, cmd, data);
433 static int jz_mmc_dm_set_ios(struct udevice *dev)
435 struct jz_mmc_priv *priv = dev_get_priv(dev);
436 struct mmc *mmc = mmc_get_mmc_dev(dev);
438 return jz_mmc_set_ios(mmc, priv);
441 static const struct dm_mmc_ops jz_msc_ops = {
442 .send_cmd = jz_mmc_dm_send_cmd,
443 .set_ios = jz_mmc_dm_set_ios,
446 static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
448 struct jz_mmc_priv *priv = dev_get_priv(dev);
449 struct jz_mmc_plat *plat = dev_get_platdata(dev);
450 struct mmc_config *cfg;
453 priv->regs = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
457 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
459 ret = mmc_of_parse(dev, cfg);
461 dev_err(dev, "failed to parse host caps\n");
466 cfg->f_max = 52000000;
468 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
469 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
474 static int jz_mmc_bind(struct udevice *dev)
476 struct jz_mmc_plat *plat = dev_get_platdata(dev);
478 return mmc_bind(dev, &plat->mmc, &plat->cfg);
481 static int jz_mmc_probe(struct udevice *dev)
483 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
484 struct jz_mmc_priv *priv = dev_get_priv(dev);
485 struct jz_mmc_plat *plat = dev_get_platdata(dev);
487 plat->mmc.priv = priv;
488 upriv->mmc = &plat->mmc;
489 return jz_mmc_core_init(&plat->mmc);
492 static const struct udevice_id jz_mmc_ids[] = {
493 { .compatible = "ingenic,jz4780-mmc" },
497 U_BOOT_DRIVER(jz_mmc_drv) = {
500 .of_match = jz_mmc_ids,
501 .ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
503 .probe = jz_mmc_probe,
504 .priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
505 .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
508 #endif /* CONFIG_DM_MMC */