2 * linux/drivers/mmc/tmio_mmc.c
4 * Copyright (C) 2004 Ian Molton
5 * Copyright (C) 2007 Ian Molton
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Driver for the MMC / SD / SDIO cell found in:
13 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
15 * This driver draws mainly on scattered spec sheets, Reverse engineering
16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
17 * support). (Further 4 bit support from a later datasheet).
20 * Investigate using a workqueue for PIO transfers
23 * Better Power management
24 * Handle MMC errors better
25 * double buffer support
28 #include <linux/module.h>
29 #include <linux/irq.h>
30 #include <linux/device.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mfd/core.h>
35 #include <linux/mfd/tmio.h>
39 static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
44 for (clock = host->mmc->f_min, clk = 0x80000080;
45 new_clock >= (clock<<1); clk >>= 1)
50 if (host->set_clk_div)
51 host->set_clk_div(host->pdev, (clk>>22) & 1);
53 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
56 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
58 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
60 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
61 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
65 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
67 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
68 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
70 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
74 static void reset(struct tmio_mmc_host *host)
76 /* FIXME - should we set stop clock reg here */
77 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
78 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
80 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
81 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
86 tmio_mmc_finish_request(struct tmio_mmc_host *host)
88 struct mmc_request *mrq = host->mrq;
94 mmc_request_done(host->mmc, mrq);
97 /* These are the bitmasks the tmio chip requires to implement the MMC response
98 * types. Note that R1 and R6 are the same in this scheme. */
99 #define APP_CMD 0x0040
100 #define RESP_NONE 0x0300
101 #define RESP_R1 0x0400
102 #define RESP_R1B 0x0500
103 #define RESP_R2 0x0600
104 #define RESP_R3 0x0700
105 #define DATA_PRESENT 0x0800
106 #define TRANSFER_READ 0x1000
107 #define TRANSFER_MULTI 0x2000
108 #define SECURITY_CMD 0x4000
111 tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
113 struct mmc_data *data = host->data;
116 /* Command 12 is handled by hardware */
117 if (cmd->opcode == 12 && !cmd->arg) {
118 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
122 switch (mmc_resp_type(cmd)) {
123 case MMC_RSP_NONE: c |= RESP_NONE; break;
124 case MMC_RSP_R1: c |= RESP_R1; break;
125 case MMC_RSP_R1B: c |= RESP_R1B; break;
126 case MMC_RSP_R2: c |= RESP_R2; break;
127 case MMC_RSP_R3: c |= RESP_R3; break;
129 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
135 /* FIXME - this seems to be ok commented out but the spec suggest this bit
136 * should be set when issuing app commands.
137 * if(cmd->flags & MMC_FLAG_ACMD)
142 if (data->blocks > 1) {
143 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
146 if (data->flags & MMC_DATA_READ)
150 enable_mmc_irqs(host, TMIO_MASK_CMD);
152 /* Fire off the command */
153 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
154 sd_ctrl_write16(host, CTL_SD_CMD, c);
160 * This chip always returns (at least?) as much data as you ask for.
161 * I'm unsure what happens if you ask for less than a block. This should be
162 * looked into to ensure that a funny length read doesnt hose the controller.
164 static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
166 struct mmc_data *data = host->data;
173 pr_debug("Spurious PIO IRQ\n");
177 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
178 buf = (unsigned short *)(sg_virt + host->sg_off);
180 count = host->sg_ptr->length - host->sg_off;
181 if (count > data->blksz)
184 pr_debug("count: %08x offset: %08x flags %08x\n",
185 count, host->sg_off, data->flags);
187 /* Transfer the data */
188 if (data->flags & MMC_DATA_READ)
189 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
191 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
193 host->sg_off += count;
195 tmio_mmc_kunmap_atomic(sg_virt, &flags);
197 if (host->sg_off == host->sg_ptr->length)
198 tmio_mmc_next_sg(host);
203 static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
205 struct mmc_data *data = host->data;
206 struct mmc_command *stop;
211 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
216 /* FIXME - return correct transfer count on errors */
218 data->bytes_xfered = data->blocks * data->blksz;
220 data->bytes_xfered = 0;
222 pr_debug("Completed data request\n");
225 * FIXME: other drivers allow an optional stop command of any given type
226 * which we dont do, as the chip can auto generate them.
227 * Perhaps we can be smarter about when to use auto CMD12 and
228 * only issue the auto request when we know this is the desired
229 * stop command, allowing fallback to the stop command the
230 * upper layers expect. For now, we do what works.
233 if (data->flags & MMC_DATA_READ) {
235 disable_mmc_irqs(host, TMIO_MASK_READOP);
236 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
240 disable_mmc_irqs(host, TMIO_MASK_WRITEOP);
241 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
246 if (stop->opcode == 12 && !stop->arg)
247 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
252 tmio_mmc_finish_request(host);
255 static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
257 struct mmc_data *data = host->data;
262 if (host->chan_tx && (data->flags & MMC_DATA_WRITE)) {
264 * Has all data been written out yet? Testing on SuperH showed,
265 * that in most cases the first interrupt comes already with the
266 * BUSY status bit clear, but on some operations, like mount or
267 * in the beginning of a write / sync / umount, there is one
268 * DATAEND interrupt with the BUSY bit set, in this cases
269 * waiting for one more interrupt fixes the problem.
271 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
272 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
273 tasklet_schedule(&host->dma_complete);
275 } else if (host->chan_rx && (data->flags & MMC_DATA_READ)) {
276 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
277 tasklet_schedule(&host->dma_complete);
279 tmio_mmc_do_data_irq(host);
283 static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
286 struct mmc_command *cmd = host->cmd;
290 pr_debug("Spurious CMD irq\n");
296 /* This controller is sicker than the PXA one. Not only do we need to
297 * drop the top 8 bits of the first response word, we also need to
298 * modify the order of the response for short response command types.
301 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
302 cmd->resp[i] = sd_ctrl_read32(host, addr);
304 if (cmd->flags & MMC_RSP_136) {
305 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
306 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
307 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
309 } else if (cmd->flags & MMC_RSP_R3) {
310 cmd->resp[0] = cmd->resp[3];
313 if (stat & TMIO_STAT_CMDTIMEOUT)
314 cmd->error = -ETIMEDOUT;
315 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
316 cmd->error = -EILSEQ;
318 /* If there is data to handle we enable data IRQs here, and
319 * we will ultimatley finish the request in the data_end handler.
320 * If theres no data or we encountered an error, finish now.
322 if (host->data && !cmd->error) {
323 if (host->data->flags & MMC_DATA_READ) {
325 enable_mmc_irqs(host, TMIO_MASK_READOP);
327 struct dma_chan *chan = host->chan_tx;
329 enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
331 tasklet_schedule(&host->dma_issue);
334 tmio_mmc_finish_request(host);
340 static irqreturn_t tmio_mmc_irq(int irq, void *devid)
342 struct tmio_mmc_host *host = devid;
343 unsigned int ireg, irq_mask, status;
345 pr_debug("MMC IRQ begin\n");
347 status = sd_ctrl_read32(host, CTL_STATUS);
348 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
349 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
351 pr_debug_status(status);
352 pr_debug_status(ireg);
355 disable_mmc_irqs(host, status & ~irq_mask);
357 pr_warning("tmio_mmc: Spurious irq, disabling! "
358 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
359 pr_debug_status(status);
365 /* Card insert / remove attempts */
366 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
367 ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
368 TMIO_STAT_CARD_REMOVE);
369 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
372 /* CRC and other errors */
373 /* if (ireg & TMIO_STAT_ERR_IRQ)
374 * handled |= tmio_error_irq(host, irq, stat);
377 /* Command completion */
378 if (ireg & TMIO_MASK_CMD) {
379 ack_mmc_irqs(host, TMIO_MASK_CMD);
380 tmio_mmc_cmd_irq(host, status);
384 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
385 ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
386 tmio_mmc_pio_irq(host);
389 /* Data transfer completion */
390 if (ireg & TMIO_STAT_DATAEND) {
391 ack_mmc_irqs(host, TMIO_STAT_DATAEND);
392 tmio_mmc_data_irq(host);
395 /* Check status - keep going until we've handled it all */
396 status = sd_ctrl_read32(host, CTL_STATUS);
397 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
398 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
400 pr_debug("Status at end of loop: %08x\n", status);
401 pr_debug_status(status);
403 pr_debug("MMC IRQ end\n");
409 #ifdef CONFIG_TMIO_MMC_DMA
410 static void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
412 #if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE)
413 /* Switch DMA mode on or off - SuperH specific? */
414 sd_ctrl_write16(host, 0xd8, enable ? 2 : 0);
418 static void tmio_dma_complete(void *arg)
420 struct tmio_mmc_host *host = arg;
422 dev_dbg(&host->pdev->dev, "Command completed\n");
425 dev_warn(&host->pdev->dev, "NULL data in DMA completion!\n");
427 enable_mmc_irqs(host, TMIO_STAT_DATAEND);
430 static int tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
432 struct scatterlist *sg = host->sg_ptr;
433 struct dma_async_tx_descriptor *desc = NULL;
434 struct dma_chan *chan = host->chan_rx;
437 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, DMA_FROM_DEVICE);
439 host->dma_sglen = ret;
440 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
441 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
446 desc->callback = tmio_dma_complete;
447 desc->callback_param = host;
448 host->cookie = desc->tx_submit(desc);
449 if (host->cookie < 0) {
453 chan->device->device_issue_pending(chan);
456 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
457 __func__, host->sg_len, ret, host->cookie, host->mrq);
460 /* DMA failed, fall back to PIO */
463 host->chan_rx = NULL;
464 dma_release_channel(chan);
465 /* Free the Tx channel too */
466 chan = host->chan_tx;
468 host->chan_tx = NULL;
469 dma_release_channel(chan);
471 dev_warn(&host->pdev->dev,
472 "DMA failed: %d, falling back to PIO\n", ret);
473 tmio_mmc_enable_dma(host, false);
475 /* Fail this request, let above layers recover */
476 host->mrq->cmd->error = ret;
477 tmio_mmc_finish_request(host);
480 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
481 desc, host->cookie, host->sg_len);
483 return ret > 0 ? 0 : ret;
486 static int tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
488 struct scatterlist *sg = host->sg_ptr;
489 struct dma_async_tx_descriptor *desc = NULL;
490 struct dma_chan *chan = host->chan_tx;
493 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, DMA_TO_DEVICE);
495 host->dma_sglen = ret;
496 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
497 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
502 desc->callback = tmio_dma_complete;
503 desc->callback_param = host;
504 host->cookie = desc->tx_submit(desc);
505 if (host->cookie < 0) {
510 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
511 __func__, host->sg_len, ret, host->cookie, host->mrq);
514 /* DMA failed, fall back to PIO */
517 host->chan_tx = NULL;
518 dma_release_channel(chan);
519 /* Free the Rx channel too */
520 chan = host->chan_rx;
522 host->chan_rx = NULL;
523 dma_release_channel(chan);
525 dev_warn(&host->pdev->dev,
526 "DMA failed: %d, falling back to PIO\n", ret);
527 tmio_mmc_enable_dma(host, false);
529 /* Fail this request, let above layers recover */
530 host->mrq->cmd->error = ret;
531 tmio_mmc_finish_request(host);
534 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d\n", __func__,
537 return ret > 0 ? 0 : ret;
540 static int tmio_mmc_start_dma(struct tmio_mmc_host *host,
541 struct mmc_data *data)
543 if (data->flags & MMC_DATA_READ) {
545 return tmio_mmc_start_dma_rx(host);
548 return tmio_mmc_start_dma_tx(host);
554 static void tmio_issue_tasklet_fn(unsigned long priv)
556 struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
557 struct dma_chan *chan = host->chan_tx;
559 chan->device->device_issue_pending(chan);
562 static void tmio_tasklet_fn(unsigned long arg)
564 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
566 if (host->data->flags & MMC_DATA_READ)
567 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->dma_sglen,
570 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->dma_sglen,
573 tmio_mmc_do_data_irq(host);
576 /* It might be necessary to make filter MFD specific */
577 static bool tmio_mmc_filter(struct dma_chan *chan, void *arg)
579 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
584 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
585 struct tmio_mmc_data *pdata)
587 host->cookie = -EINVAL;
590 /* We can only either use DMA for both Tx and Rx or not use it at all */
595 dma_cap_set(DMA_SLAVE, mask);
597 host->chan_tx = dma_request_channel(mask, tmio_mmc_filter,
598 pdata->dma->chan_priv_tx);
599 dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
605 host->chan_rx = dma_request_channel(mask, tmio_mmc_filter,
606 pdata->dma->chan_priv_rx);
607 dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
610 if (!host->chan_rx) {
611 dma_release_channel(host->chan_tx);
612 host->chan_tx = NULL;
616 tasklet_init(&host->dma_complete, tmio_tasklet_fn, (unsigned long)host);
617 tasklet_init(&host->dma_issue, tmio_issue_tasklet_fn, (unsigned long)host);
619 tmio_mmc_enable_dma(host, true);
623 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
626 struct dma_chan *chan = host->chan_tx;
627 host->chan_tx = NULL;
628 dma_release_channel(chan);
631 struct dma_chan *chan = host->chan_rx;
632 host->chan_rx = NULL;
633 dma_release_channel(chan);
636 host->cookie = -EINVAL;
640 static int tmio_mmc_start_dma(struct tmio_mmc_host *host,
641 struct mmc_data *data)
646 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
647 struct tmio_mmc_data *pdata)
649 host->chan_tx = NULL;
650 host->chan_rx = NULL;
653 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
658 static int tmio_mmc_start_data(struct tmio_mmc_host *host,
659 struct mmc_data *data)
661 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
662 data->blksz, data->blocks);
664 /* Hardware cannot perform 1 and 2 byte requests in 4 bit mode */
665 if (data->blksz < 4 && host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
666 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
667 mmc_hostname(host->mmc), data->blksz);
671 tmio_mmc_init_sg(host, data);
674 /* Set transfer length / blocksize */
675 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
676 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
678 return tmio_mmc_start_dma(host, data);
681 /* Process requests from the MMC layer */
682 static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
684 struct tmio_mmc_host *host = mmc_priv(mmc);
688 pr_debug("request not null\n");
693 ret = tmio_mmc_start_data(host, mrq->data);
698 ret = tmio_mmc_start_command(host, mrq->cmd);
703 mrq->cmd->error = ret;
704 mmc_request_done(mmc, mrq);
707 /* Set MMC clock / power.
708 * Note: This controller uses a simple divider scheme therefore it cannot
709 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
710 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
713 static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
715 struct tmio_mmc_host *host = mmc_priv(mmc);
718 tmio_mmc_set_clock(host, ios->clock);
720 /* Power sequence - OFF -> ON -> UP */
721 switch (ios->power_mode) {
722 case MMC_POWER_OFF: /* power down SD bus */
724 host->set_pwr(host->pdev, 0);
725 tmio_mmc_clk_stop(host);
727 case MMC_POWER_ON: /* power up SD bus */
729 host->set_pwr(host->pdev, 1);
731 case MMC_POWER_UP: /* start bus clock */
732 tmio_mmc_clk_start(host);
736 switch (ios->bus_width) {
737 case MMC_BUS_WIDTH_1:
738 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
740 case MMC_BUS_WIDTH_4:
741 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
745 /* Let things settle. delay taken from winCE driver */
749 static int tmio_mmc_get_ro(struct mmc_host *mmc)
751 struct tmio_mmc_host *host = mmc_priv(mmc);
752 struct mfd_cell *cell = host->pdev->dev.platform_data;
753 struct tmio_mmc_data *pdata = cell->driver_data;
755 return ((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
756 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)) ? 0 : 1;
759 static const struct mmc_host_ops tmio_mmc_ops = {
760 .request = tmio_mmc_request,
761 .set_ios = tmio_mmc_set_ios,
762 .get_ro = tmio_mmc_get_ro,
766 static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state)
768 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
769 struct mmc_host *mmc = platform_get_drvdata(dev);
772 ret = mmc_suspend_host(mmc);
774 /* Tell MFD core it can disable us now.*/
775 if (!ret && cell->disable)
781 static int tmio_mmc_resume(struct platform_device *dev)
783 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
784 struct mmc_host *mmc = platform_get_drvdata(dev);
787 /* Tell the MFD core we are ready to be enabled */
789 ret = cell->resume(dev);
794 mmc_resume_host(mmc);
800 #define tmio_mmc_suspend NULL
801 #define tmio_mmc_resume NULL
804 static int __devinit tmio_mmc_probe(struct platform_device *dev)
806 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
807 struct tmio_mmc_data *pdata;
808 struct resource *res_ctl;
809 struct tmio_mmc_host *host;
810 struct mmc_host *mmc;
812 u32 irq_mask = TMIO_MASK_CMD;
814 if (dev->num_resources != 2)
817 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
821 pdata = cell->driver_data;
822 if (!pdata || !pdata->hclk)
827 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
831 host = mmc_priv(mmc);
834 platform_set_drvdata(dev, mmc);
836 host->set_pwr = pdata->set_pwr;
837 host->set_clk_div = pdata->set_clk_div;
839 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
840 host->bus_shift = resource_size(res_ctl) >> 10;
842 host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
846 mmc->ops = &tmio_mmc_ops;
847 mmc->caps = MMC_CAP_4_BIT_DATA;
848 mmc->caps |= pdata->capabilities;
849 mmc->f_max = pdata->hclk;
850 mmc->f_min = mmc->f_max / 512;
852 mmc->ocr_avail = pdata->ocr_mask;
854 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
856 /* Tell the MFD core we are ready to be enabled */
858 ret = cell->enable(dev);
863 tmio_mmc_clk_stop(host);
866 ret = platform_get_irq(dev, 0);
872 disable_mmc_irqs(host, TMIO_MASK_ALL);
874 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
875 IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host);
879 /* See if we also get DMA */
880 tmio_mmc_request_dma(host, pdata);
884 pr_info("%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
885 (unsigned long)host->ctl, host->irq);
887 /* Unmask the IRQs we want to know about */
889 irq_mask |= TMIO_MASK_READOP;
891 irq_mask |= TMIO_MASK_WRITEOP;
892 enable_mmc_irqs(host, irq_mask);
907 static int __devexit tmio_mmc_remove(struct platform_device *dev)
909 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
910 struct mmc_host *mmc = platform_get_drvdata(dev);
912 platform_set_drvdata(dev, NULL);
915 struct tmio_mmc_host *host = mmc_priv(mmc);
916 mmc_remove_host(mmc);
917 tmio_mmc_release_dma(host);
918 free_irq(host->irq, host);
928 /* ------------------- device registration ----------------------- */
930 static struct platform_driver tmio_mmc_driver = {
933 .owner = THIS_MODULE,
935 .probe = tmio_mmc_probe,
936 .remove = __devexit_p(tmio_mmc_remove),
937 .suspend = tmio_mmc_suspend,
938 .resume = tmio_mmc_resume,
942 static int __init tmio_mmc_init(void)
944 return platform_driver_register(&tmio_mmc_driver);
947 static void __exit tmio_mmc_exit(void)
949 platform_driver_unregister(&tmio_mmc_driver);
952 module_init(tmio_mmc_init);
953 module_exit(tmio_mmc_exit);
955 MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver");
956 MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
957 MODULE_LICENSE("GPL v2");
958 MODULE_ALIAS("platform:tmio-mmc");