drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 /*
  20  * The MMCIF driver is now processing MMC requests asynchronously, according
  21  * to the Linux MMC API requirement.
  22  *
  23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
  24  * data, and optional stop. To achieve asynchronous processing each of these
  25  * stages is split into two halves: a top and a bottom half. The top half
  26  * initialises the hardware, installs a timeout handler to handle completion
  27  * timeouts, and returns. In case of the command stage this immediately returns
  28  * control to the caller, leaving all further processing to run asynchronously.
  29  * All further request processing is performed by the bottom halves.
  30  *
  31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
  32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
  33  * request- and stage-specific handler methods.
  34  *
  35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
  36  * invocation, or a timeout work run. In case of an error or a successful
  37  * processing completion, the MMC core is informed and the request processing is
  38  * finished. In case processing has to continue, i.e., if data has to be read
  39  * from or written to the card, or if a stop command has to be sent, the next
  40  * top half is called, which performs the necessary hardware handling and
  41  * reschedules the timeout work. This returns the driver state machine into the
  42  * bottom half waiting state.
  43  */
  44
  45 #include <linux/bitops.h>
  46 #include <linux/clk.h>
  47 #include <linux/completion.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/mmc/card.h>
  52 #include <linux/mmc/core.h>
  53 #include <linux/mmc/host.h>
  54 #include <linux/mmc/mmc.h>
  55 #include <linux/mmc/sdio.h>
  56 #include <linux/mmc/sh_mmcif.h>
  57 #include <linux/mmc/slot-gpio.h>
  58 #include <linux/mod_devicetable.h>
  59 #include <linux/pagemap.h>
  60 #include <linux/platform_device.h>
  61 #include <linux/pm_qos.h>
  62 #include <linux/pm_runtime.h>
  63 #include <linux/spinlock.h>
  64 #include <linux/module.h>
  65
  66 #define DRIVER_NAME     "sh_mmcif"
  67 #define DRIVER_VERSION  "2010-04-28"
  68
  69 /* CE_CMD_SET */
  70 #define CMD_MASK                0x3f000000
  71 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  72 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  73 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  74 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  75 #define CMD_SET_CCSEN           (1 << 20)
  76 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  77 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  78 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  79 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  80 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  81 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  82 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  83 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  84 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  85 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  86 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  87 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  88 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  89 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  90 #define CMD_SET_CCSH            (1 << 5)
  91 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  92 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  93 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  94
  95 /* CE_CMD_CTRL */
  96 #define CMD_CTRL_BREAK          (1 << 0)
  97
  98 /* CE_BLOCK_SET */
  99 #define BLOCK_SIZE_MASK         0x0000ffff
 100
 101 /* CE_INT */
 102 #define INT_CCSDE               (1 << 29)
 103 #define INT_CMD12DRE            (1 << 26)
 104 #define INT_CMD12RBE            (1 << 25)
 105 #define INT_CMD12CRE            (1 << 24)
 106 #define INT_DTRANE              (1 << 23)
 107 #define INT_BUFRE               (1 << 22)
 108 #define INT_BUFWEN              (1 << 21)
 109 #define INT_BUFREN              (1 << 20)
 110 #define INT_CCSRCV              (1 << 19)
 111 #define INT_RBSYE               (1 << 17)
 112 #define INT_CRSPE               (1 << 16)
 113 #define INT_CMDVIO              (1 << 15)
 114 #define INT_BUFVIO              (1 << 14)
 115 #define INT_WDATERR             (1 << 11)
 116 #define INT_RDATERR             (1 << 10)
 117 #define INT_RIDXERR             (1 << 9)
 118 #define INT_RSPERR              (1 << 8)
 119 #define INT_CCSTO               (1 << 5)
 120 #define INT_CRCSTO              (1 << 4)
 121 #define INT_WDATTO              (1 << 3)
 122 #define INT_RDATTO              (1 << 2)
 123 #define INT_RBSYTO              (1 << 1)
 124 #define INT_RSPTO               (1 << 0)
 125 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 126                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 127                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 128                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 129
 130 /* CE_INT_MASK */
 131 #define MASK_ALL                0x00000000
 132 #define MASK_MCCSDE             (1 << 29)
 133 #define MASK_MCMD12DRE          (1 << 26)
 134 #define MASK_MCMD12RBE          (1 << 25)
 135 #define MASK_MCMD12CRE          (1 << 24)
 136 #define MASK_MDTRANE            (1 << 23)
 137 #define MASK_MBUFRE             (1 << 22)
 138 #define MASK_MBUFWEN            (1 << 21)
 139 #define MASK_MBUFREN            (1 << 20)
 140 #define MASK_MCCSRCV            (1 << 19)
 141 #define MASK_MRBSYE             (1 << 17)
 142 #define MASK_MCRSPE             (1 << 16)
 143 #define MASK_MCMDVIO            (1 << 15)
 144 #define MASK_MBUFVIO            (1 << 14)
 145 #define MASK_MWDATERR           (1 << 11)
 146 #define MASK_MRDATERR           (1 << 10)
 147 #define MASK_MRIDXERR           (1 << 9)
 148 #define MASK_MRSPERR            (1 << 8)
 149 #define MASK_MCCSTO             (1 << 5)
 150 #define MASK_MCRCSTO            (1 << 4)
 151 #define MASK_MWDATTO            (1 << 3)
 152 #define MASK_MRDATTO            (1 << 2)
 153 #define MASK_MRBSYTO            (1 << 1)
 154 #define MASK_MRSPTO             (1 << 0)
 155
 156 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 157                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 158                                  MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
 159                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 160
 161 /* CE_HOST_STS1 */
 162 #define STS1_CMDSEQ             (1 << 31)
 163
 164 /* CE_HOST_STS2 */
 165 #define STS2_CRCSTE             (1 << 31)
 166 #define STS2_CRC16E             (1 << 30)
 167 #define STS2_AC12CRCE           (1 << 29)
 168 #define STS2_RSPCRC7E           (1 << 28)
 169 #define STS2_CRCSTEBE           (1 << 27)
 170 #define STS2_RDATEBE            (1 << 26)
 171 #define STS2_AC12REBE           (1 << 25)
 172 #define STS2_RSPEBE             (1 << 24)
 173 #define STS2_AC12IDXE           (1 << 23)
 174 #define STS2_RSPIDXE            (1 << 22)
 175 #define STS2_CCSTO              (1 << 15)
 176 #define STS2_RDATTO             (1 << 14)
 177 #define STS2_DATBSYTO           (1 << 13)
 178 #define STS2_CRCSTTO            (1 << 12)
 179 #define STS2_AC12BSYTO          (1 << 11)
 180 #define STS2_RSPBSYTO           (1 << 10)
 181 #define STS2_AC12RSPTO          (1 << 9)
 182 #define STS2_RSPTO              (1 << 8)
 183 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 184                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 185 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 186                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 187                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 188                                  STS2_AC12RSPTO | STS2_RSPTO)
 189
 190 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 191 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 192 #define CLKDEV_INIT             400000   /* 400 KHz */
 193
 194 enum mmcif_state {
 195         STATE_IDLE,
 196         STATE_REQUEST,
 197         STATE_IOS,
 198 };
 199
 200 enum mmcif_wait_for {
 201         MMCIF_WAIT_FOR_REQUEST,
 202         MMCIF_WAIT_FOR_CMD,
 203         MMCIF_WAIT_FOR_MREAD,
 204         MMCIF_WAIT_FOR_MWRITE,
 205         MMCIF_WAIT_FOR_READ,
 206         MMCIF_WAIT_FOR_WRITE,
 207         MMCIF_WAIT_FOR_READ_END,
 208         MMCIF_WAIT_FOR_WRITE_END,
 209         MMCIF_WAIT_FOR_STOP,
 210 };
 211
 212 struct sh_mmcif_host {
 213         struct mmc_host *mmc;
 214         struct mmc_request *mrq;
 215         struct platform_device *pd;
 216         struct sh_dmae_slave dma_slave_tx;
 217         struct sh_dmae_slave dma_slave_rx;
 218         struct clk *hclk;
 219         unsigned int clk;
 220         int bus_width;
 221         bool sd_error;
 222         bool dying;
 223         long timeout;
 224         void __iomem *addr;
 225         u32 *pio_ptr;
 226         spinlock_t lock;                /* protect sh_mmcif_host::state */
 227         enum mmcif_state state;
 228         enum mmcif_wait_for wait_for;
 229         struct delayed_work timeout_work;
 230         size_t blocksize;
 231         int sg_idx;
 232         int sg_blkidx;
 233         bool power;
 234         bool card_present;
 235
 236         /* DMA support */
 237         struct dma_chan         *chan_rx;
 238         struct dma_chan         *chan_tx;
 239         struct completion       dma_complete;
 240         bool                    dma_active;
 241 };
 242
 243 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 244                                         unsigned int reg, u32 val)
 245 {
 246         writel(val | readl(host->addr + reg), host->addr + reg);
 247 }
 248
 249 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 250                                         unsigned int reg, u32 val)
 251 {
 252         writel(~val & readl(host->addr + reg), host->addr + reg);
 253 }
 254
 255 static void mmcif_dma_complete(void *arg)
 256 {
 257         struct sh_mmcif_host *host = arg;
 258         struct mmc_data *data = host->mrq->data;
 259
 260         dev_dbg(&host->pd->dev, "Command completed\n");
 261
 262         if (WARN(!data, "%s: NULL data in DMA completion!\n",
 263                  dev_name(&host->pd->dev)))
 264                 return;
 265
 266         if (data->flags & MMC_DATA_READ)
 267                 dma_unmap_sg(host->chan_rx->device->dev,
 268                              data->sg, data->sg_len,
 269                              DMA_FROM_DEVICE);
 270         else
 271                 dma_unmap_sg(host->chan_tx->device->dev,
 272                              data->sg, data->sg_len,
 273                              DMA_TO_DEVICE);
 274
 275         complete(&host->dma_complete);
 276 }
 277
 278 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 279 {
 280         struct mmc_data *data = host->mrq->data;
 281         struct scatterlist *sg = data->sg;
 282         struct dma_async_tx_descriptor *desc = NULL;
 283         struct dma_chan *chan = host->chan_rx;
 284         dma_cookie_t cookie = -EINVAL;
 285         int ret;
 286
 287         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 288                          DMA_FROM_DEVICE);
 289         if (ret > 0) {
 290                 host->dma_active = true;
 291                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 292                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 293         }
 294
 295         if (desc) {
 296                 desc->callback = mmcif_dma_complete;
 297                 desc->callback_param = host;
 298                 cookie = dmaengine_submit(desc);
 299                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 300                 dma_async_issue_pending(chan);
 301         }
 302         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 303                 __func__, data->sg_len, ret, cookie);
 304
 305         if (!desc) {
 306                 /* DMA failed, fall back to PIO */
 307                 if (ret >= 0)
 308                         ret = -EIO;
 309                 host->chan_rx = NULL;
 310                 host->dma_active = false;
 311                 dma_release_channel(chan);
 312                 /* Free the Tx channel too */
 313                 chan = host->chan_tx;
 314                 if (chan) {
 315                         host->chan_tx = NULL;
 316                         dma_release_channel(chan);
 317                 }
 318                 dev_warn(&host->pd->dev,
 319                          "DMA failed: %d, falling back to PIO\n", ret);
 320                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 321         }
 322
 323         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 324                 desc, cookie, data->sg_len);
 325 }
 326
 327 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 328 {
 329         struct mmc_data *data = host->mrq->data;
 330         struct scatterlist *sg = data->sg;
 331         struct dma_async_tx_descriptor *desc = NULL;
 332         struct dma_chan *chan = host->chan_tx;
 333         dma_cookie_t cookie = -EINVAL;
 334         int ret;
 335
 336         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 337                          DMA_TO_DEVICE);
 338         if (ret > 0) {
 339                 host->dma_active = true;
 340                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 341                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 342         }
 343
 344         if (desc) {
 345                 desc->callback = mmcif_dma_complete;
 346                 desc->callback_param = host;
 347                 cookie = dmaengine_submit(desc);
 348                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 349                 dma_async_issue_pending(chan);
 350         }
 351         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 352                 __func__, data->sg_len, ret, cookie);
 353
 354         if (!desc) {
 355                 /* DMA failed, fall back to PIO */
 356                 if (ret >= 0)
 357                         ret = -EIO;
 358                 host->chan_tx = NULL;
 359                 host->dma_active = false;
 360                 dma_release_channel(chan);
 361                 /* Free the Rx channel too */
 362                 chan = host->chan_rx;
 363                 if (chan) {
 364                         host->chan_rx = NULL;
 365                         dma_release_channel(chan);
 366                 }
 367                 dev_warn(&host->pd->dev,
 368                          "DMA failed: %d, falling back to PIO\n", ret);
 369                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 370         }
 371
 372         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 373                 desc, cookie);
 374 }
 375
 376 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
 377 {
 378         dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
 379         chan->private = arg;
 380         return true;
 381 }
 382
 383 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 384                                  struct sh_mmcif_plat_data *pdata)
 385 {
 386         struct sh_dmae_slave *tx, *rx;
 387         host->dma_active = false;
 388
 389         if (!pdata)
 390                 return;
 391
 392         /* We can only either use DMA for both Tx and Rx or not use it at all */
 393         if (pdata->dma) {
 394                 dev_warn(&host->pd->dev,
 395                          "Update your platform to use embedded DMA slave IDs\n");
 396                 tx = &pdata->dma->chan_priv_tx;
 397                 rx = &pdata->dma->chan_priv_rx;
 398         } else {
 399                 tx = &host->dma_slave_tx;
 400                 tx->slave_id = pdata->slave_id_tx;
 401                 rx = &host->dma_slave_rx;
 402                 rx->slave_id = pdata->slave_id_rx;
 403         }
 404         if (tx->slave_id > 0 && rx->slave_id > 0) {
 405                 dma_cap_mask_t mask;
 406
 407                 dma_cap_zero(mask);
 408                 dma_cap_set(DMA_SLAVE, mask);
 409
 410                 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx);
 411                 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
 412                         host->chan_tx);
 413
 414                 if (!host->chan_tx)
 415                         return;
 416
 417                 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx);
 418                 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
 419                         host->chan_rx);
 420
 421                 if (!host->chan_rx) {
 422                         dma_release_channel(host->chan_tx);
 423                         host->chan_tx = NULL;
 424                         return;
 425                 }
 426
 427                 init_completion(&host->dma_complete);
 428         }
 429 }
 430
 431 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 432 {
 433         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 434         /* Descriptors are freed automatically */
 435         if (host->chan_tx) {
 436                 struct dma_chan *chan = host->chan_tx;
 437                 host->chan_tx = NULL;
 438                 dma_release_channel(chan);
 439         }
 440         if (host->chan_rx) {
 441                 struct dma_chan *chan = host->chan_rx;
 442                 host->chan_rx = NULL;
 443                 dma_release_channel(chan);
 444         }
 445
 446         host->dma_active = false;
 447 }
 448
 449 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 450 {
 451         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 452         bool sup_pclk = p ? p->sup_pclk : false;
 453
 454         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 455         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 456
 457         if (!clk)
 458                 return;
 459         if (sup_pclk && clk == host->clk)
 460                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 461         else
 462                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 463                                 ((fls(DIV_ROUND_UP(host->clk,
 464                                                    clk) - 1) - 1) << 16));
 465
 466         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 467 }
 468
 469 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 470 {
 471         u32 tmp;
 472
 473         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 474
 475         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 476         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 477         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 478                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 479         /* byte swap on */
 480         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 481 }
 482
 483 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 484 {
 485         u32 state1, state2;
 486         int ret, timeout;
 487
 488         host->sd_error = false;
 489
 490         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 491         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 492         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 493         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 494
 495         if (state1 & STS1_CMDSEQ) {
 496                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 497                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 498                 for (timeout = 10000000; timeout; timeout--) {
 499                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 500                               & STS1_CMDSEQ))
 501                                 break;
 502                         mdelay(1);
 503                 }
 504                 if (!timeout) {
 505                         dev_err(&host->pd->dev,
 506                                 "Forced end of command sequence timeout err\n");
 507                         return -EIO;
 508                 }
 509                 sh_mmcif_sync_reset(host);
 510                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 511                 return -EIO;
 512         }
 513
 514         if (state2 & STS2_CRC_ERR) {
 515                 dev_dbg(&host->pd->dev, ": CRC error\n");
 516                 ret = -EIO;
 517         } else if (state2 & STS2_TIMEOUT_ERR) {
 518                 dev_dbg(&host->pd->dev, ": Timeout\n");
 519                 ret = -ETIMEDOUT;
 520         } else {
 521                 dev_dbg(&host->pd->dev, ": End/Index error\n");
 522                 ret = -EIO;
 523         }
 524         return ret;
 525 }
 526
 527 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
 528 {
 529         struct mmc_data *data = host->mrq->data;
 530
 531         host->sg_blkidx += host->blocksize;
 532
 533         /* data->sg->length must be a multiple of host->blocksize? */
 534         BUG_ON(host->sg_blkidx > data->sg->length);
 535
 536         if (host->sg_blkidx == data->sg->length) {
 537                 host->sg_blkidx = 0;
 538                 if (++host->sg_idx < data->sg_len)
 539                         host->pio_ptr = sg_virt(++data->sg);
 540         } else {
 541                 host->pio_ptr = p;
 542         }
 543
 544         if (host->sg_idx == data->sg_len)
 545                 return false;
 546
 547         return true;
 548 }
 549
 550 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
 551                                  struct mmc_request *mrq)
 552 {
 553         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 554                            BLOCK_SIZE_MASK) + 3;
 555
 556         host->wait_for = MMCIF_WAIT_FOR_READ;
 557         schedule_delayed_work(&host->timeout_work, host->timeout);
 558
 559         /* buf read enable */
 560         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 561 }
 562
 563 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
 564 {
 565         struct mmc_data *data = host->mrq->data;
 566         u32 *p = sg_virt(data->sg);
 567         int i;
 568
 569         if (host->sd_error) {
 570                 data->error = sh_mmcif_error_manage(host);
 571                 return false;
 572         }
 573
 574         for (i = 0; i < host->blocksize / 4; i++)
 575                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 576
 577         /* buffer read end */
 578         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 579         host->wait_for = MMCIF_WAIT_FOR_READ_END;
 580
 581         return true;
 582 }
 583
 584 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
 585                                 struct mmc_request *mrq)
 586 {
 587         struct mmc_data *data = mrq->data;
 588
 589         if (!data->sg_len || !data->sg->length)
 590                 return;
 591
 592         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 593                 BLOCK_SIZE_MASK;
 594
 595         host->wait_for = MMCIF_WAIT_FOR_MREAD;
 596         host->sg_idx = 0;
 597         host->sg_blkidx = 0;
 598         host->pio_ptr = sg_virt(data->sg);
 599         schedule_delayed_work(&host->timeout_work, host->timeout);
 600         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 601 }
 602
 603 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
 604 {
 605         struct mmc_data *data = host->mrq->data;
 606         u32 *p = host->pio_ptr;
 607         int i;
 608
 609         if (host->sd_error) {
 610                 data->error = sh_mmcif_error_manage(host);
 611                 return false;
 612         }
 613
 614         BUG_ON(!data->sg->length);
 615
 616         for (i = 0; i < host->blocksize / 4; i++)
 617                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 618
 619         if (!sh_mmcif_next_block(host, p))
 620                 return false;
 621
 622         schedule_delayed_work(&host->timeout_work, host->timeout);
 623         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 624
 625         return true;
 626 }
 627
 628 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
 629                                         struct mmc_request *mrq)
 630 {
 631         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 632                            BLOCK_SIZE_MASK) + 3;
 633
 634         host->wait_for = MMCIF_WAIT_FOR_WRITE;
 635         schedule_delayed_work(&host->timeout_work, host->timeout);
 636
 637         /* buf write enable */
 638         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 639 }
 640
 641 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
 642 {
 643         struct mmc_data *data = host->mrq->data;
 644         u32 *p = sg_virt(data->sg);
 645         int i;
 646
 647         if (host->sd_error) {
 648                 data->error = sh_mmcif_error_manage(host);
 649                 return false;
 650         }
 651
 652         for (i = 0; i < host->blocksize / 4; i++)
 653                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 654
 655         /* buffer write end */
 656         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 657         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
 658
 659         return true;
 660 }
 661
 662 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
 663                                 struct mmc_request *mrq)
 664 {
 665         struct mmc_data *data = mrq->data;
 666
 667         if (!data->sg_len || !data->sg->length)
 668                 return;
 669
 670         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 671                 BLOCK_SIZE_MASK;
 672
 673         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
 674         host->sg_idx = 0;
 675         host->sg_blkidx = 0;
 676         host->pio_ptr = sg_virt(data->sg);
 677         schedule_delayed_work(&host->timeout_work, host->timeout);
 678         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 679 }
 680
 681 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
 682 {
 683         struct mmc_data *data = host->mrq->data;
 684         u32 *p = host->pio_ptr;
 685         int i;
 686
 687         if (host->sd_error) {
 688                 data->error = sh_mmcif_error_manage(host);
 689                 return false;
 690         }
 691
 692         BUG_ON(!data->sg->length);
 693
 694         for (i = 0; i < host->blocksize / 4; i++)
 695                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 696
 697         if (!sh_mmcif_next_block(host, p))
 698                 return false;
 699
 700         schedule_delayed_work(&host->timeout_work, host->timeout);
 701         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 702
 703         return true;
 704 }
 705
 706 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 707                                                 struct mmc_command *cmd)
 708 {
 709         if (cmd->flags & MMC_RSP_136) {
 710                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 711                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 712                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 713                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 714         } else
 715                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 716 }
 717
 718 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 719                                                 struct mmc_command *cmd)
 720 {
 721         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 722 }
 723
 724 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 725                             struct mmc_request *mrq)
 726 {
 727         struct mmc_data *data = mrq->data;
 728         struct mmc_command *cmd = mrq->cmd;
 729         u32 opc = cmd->opcode;
 730         u32 tmp = 0;
 731
 732         /* Response Type check */
 733         switch (mmc_resp_type(cmd)) {
 734         case MMC_RSP_NONE:
 735                 tmp |= CMD_SET_RTYP_NO;
 736                 break;
 737         case MMC_RSP_R1:
 738         case MMC_RSP_R1B:
 739         case MMC_RSP_R3:
 740                 tmp |= CMD_SET_RTYP_6B;
 741                 break;
 742         case MMC_RSP_R2:
 743                 tmp |= CMD_SET_RTYP_17B;
 744                 break;
 745         default:
 746                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 747                 break;
 748         }
 749         switch (opc) {
 750         /* RBSY */
 751         case MMC_SWITCH:
 752         case MMC_STOP_TRANSMISSION:
 753         case MMC_SET_WRITE_PROT:
 754         case MMC_CLR_WRITE_PROT:
 755         case MMC_ERASE:
 756                 tmp |= CMD_SET_RBSY;
 757                 break;
 758         }
 759         /* WDAT / DATW */
 760         if (data) {
 761                 tmp |= CMD_SET_WDAT;
 762                 switch (host->bus_width) {
 763                 case MMC_BUS_WIDTH_1:
 764                         tmp |= CMD_SET_DATW_1;
 765                         break;
 766                 case MMC_BUS_WIDTH_4:
 767                         tmp |= CMD_SET_DATW_4;
 768                         break;
 769                 case MMC_BUS_WIDTH_8:
 770                         tmp |= CMD_SET_DATW_8;
 771                         break;
 772                 default:
 773                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 774                         break;
 775                 }
 776         }
 777         /* DWEN */
 778         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 779                 tmp |= CMD_SET_DWEN;
 780         /* CMLTE/CMD12EN */
 781         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 782                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 783                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 784                                 data->blocks << 16);
 785         }
 786         /* RIDXC[1:0] check bits */
 787         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 788             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 789                 tmp |= CMD_SET_RIDXC_BITS;
 790         /* RCRC7C[1:0] check bits */
 791         if (opc == MMC_SEND_OP_COND)
 792                 tmp |= CMD_SET_CRC7C_BITS;
 793         /* RCRC7C[1:0] internal CRC7 */
 794         if (opc == MMC_ALL_SEND_CID ||
 795                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 796                 tmp |= CMD_SET_CRC7C_INTERNAL;
 797
 798         return (opc << 24) | tmp;
 799 }
 800
 801 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 802                                struct mmc_request *mrq, u32 opc)
 803 {
 804         switch (opc) {
 805         case MMC_READ_MULTIPLE_BLOCK:
 806                 sh_mmcif_multi_read(host, mrq);
 807                 return 0;
 808         case MMC_WRITE_MULTIPLE_BLOCK:
 809                 sh_mmcif_multi_write(host, mrq);
 810                 return 0;
 811         case MMC_WRITE_BLOCK:
 812                 sh_mmcif_single_write(host, mrq);
 813                 return 0;
 814         case MMC_READ_SINGLE_BLOCK:
 815         case MMC_SEND_EXT_CSD:
 816                 sh_mmcif_single_read(host, mrq);
 817                 return 0;
 818         default:
 819                 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
 820                 return -EINVAL;
 821         }
 822 }
 823
 824 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 825                                struct mmc_request *mrq)
 826 {
 827         struct mmc_command *cmd = mrq->cmd;
 828         u32 opc = cmd->opcode;
 829         u32 mask;
 830
 831         switch (opc) {
 832         /* response busy check */
 833         case MMC_SWITCH:
 834         case MMC_STOP_TRANSMISSION:
 835         case MMC_SET_WRITE_PROT:
 836         case MMC_CLR_WRITE_PROT:
 837         case MMC_ERASE:
 838                 mask = MASK_START_CMD | MASK_MRBSYE;
 839                 break;
 840         default:
 841                 mask = MASK_START_CMD | MASK_MCRSPE;
 842                 break;
 843         }
 844
 845         if (mrq->data) {
 846                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 847                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 848                                 mrq->data->blksz);
 849         }
 850         opc = sh_mmcif_set_cmd(host, mrq);
 851
 852         sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 853         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 854         /* set arg */
 855         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 856         /* set cmd */
 857         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 858
 859         host->wait_for = MMCIF_WAIT_FOR_CMD;
 860         schedule_delayed_work(&host->timeout_work, host->timeout);
 861 }
 862
 863 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 864                               struct mmc_request *mrq)
 865 {
 866         switch (mrq->cmd->opcode) {
 867         case MMC_READ_MULTIPLE_BLOCK:
 868                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 869                 break;
 870         case MMC_WRITE_MULTIPLE_BLOCK:
 871                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 872                 break;
 873         default:
 874                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 875                 mrq->stop->error = sh_mmcif_error_manage(host);
 876                 return;
 877         }
 878
 879         host->wait_for = MMCIF_WAIT_FOR_STOP;
 880         schedule_delayed_work(&host->timeout_work, host->timeout);
 881 }
 882
 883 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 884 {
 885         struct sh_mmcif_host *host = mmc_priv(mmc);
 886         unsigned long flags;
 887
 888         spin_lock_irqsave(&host->lock, flags);
 889         if (host->state != STATE_IDLE) {
 890                 spin_unlock_irqrestore(&host->lock, flags);
 891                 mrq->cmd->error = -EAGAIN;
 892                 mmc_request_done(mmc, mrq);
 893                 return;
 894         }
 895
 896         host->state = STATE_REQUEST;
 897         spin_unlock_irqrestore(&host->lock, flags);
 898
 899         switch (mrq->cmd->opcode) {
 900         /* MMCIF does not support SD/SDIO command */
 901         case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
 902         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 903                 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
 904                         break;
 905         case MMC_APP_CMD:
 906                 host->state = STATE_IDLE;
 907                 mrq->cmd->error = -ETIMEDOUT;
 908                 mmc_request_done(mmc, mrq);
 909                 return;
 910         default:
 911                 break;
 912         }
 913
 914         host->mrq = mrq;
 915
 916         sh_mmcif_start_cmd(host, mrq);
 917 }
 918
 919 static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
 920 {
 921         int ret = clk_enable(host->hclk);
 922
 923         if (!ret) {
 924                 host->clk = clk_get_rate(host->hclk);
 925                 host->mmc->f_max = host->clk / 2;
 926                 host->mmc->f_min = host->clk / 512;
 927         }
 928
 929         return ret;
 930 }
 931
 932 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
 933 {
 934         struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
 935         struct mmc_host *mmc = host->mmc;
 936
 937         if (pd && pd->set_pwr)
 938                 pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF);
 939         if (!IS_ERR(mmc->supply.vmmc))
 940                 /* Errors ignored... */
 941                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
 942                                       ios->power_mode ? ios->vdd : 0);
 943 }
 944
 945 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 946 {
 947         struct sh_mmcif_host *host = mmc_priv(mmc);
 948         unsigned long flags;
 949
 950         spin_lock_irqsave(&host->lock, flags);
 951         if (host->state != STATE_IDLE) {
 952                 spin_unlock_irqrestore(&host->lock, flags);
 953                 return;
 954         }
 955
 956         host->state = STATE_IOS;
 957         spin_unlock_irqrestore(&host->lock, flags);
 958
 959         if (ios->power_mode == MMC_POWER_UP) {
 960                 if (!host->card_present) {
 961                         /* See if we also get DMA */
 962                         sh_mmcif_request_dma(host, host->pd->dev.platform_data);
 963                         host->card_present = true;
 964                 }
 965                 sh_mmcif_set_power(host, ios);
 966         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
 967                 /* clock stop */
 968                 sh_mmcif_clock_control(host, 0);
 969                 if (ios->power_mode == MMC_POWER_OFF) {
 970                         if (host->card_present) {
 971                                 sh_mmcif_release_dma(host);
 972                                 host->card_present = false;
 973                         }
 974                 }
 975                 if (host->power) {
 976                         pm_runtime_put(&host->pd->dev);
 977                         clk_disable(host->hclk);
 978                         host->power = false;
 979                         if (ios->power_mode == MMC_POWER_OFF)
 980                                 sh_mmcif_set_power(host, ios);
 981                 }
 982                 host->state = STATE_IDLE;
 983                 return;
 984         }
 985
 986         if (ios->clock) {
 987                 if (!host->power) {
 988                         sh_mmcif_clk_update(host);
 989                         pm_runtime_get_sync(&host->pd->dev);
 990                         host->power = true;
 991                         sh_mmcif_sync_reset(host);
 992                 }
 993                 sh_mmcif_clock_control(host, ios->clock);
 994         }
 995
 996         host->bus_width = ios->bus_width;
 997         host->state = STATE_IDLE;
 998 }
 999
1000 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1001 {
1002         struct sh_mmcif_host *host = mmc_priv(mmc);
1003         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
1004         int ret = mmc_gpio_get_cd(mmc);
1005
1006         if (ret >= 0)
1007                 return ret;
1008
1009         if (!p || !p->get_cd)
1010                 return -ENOSYS;
1011         else
1012                 return p->get_cd(host->pd);
1013 }
1014
1015 static struct mmc_host_ops sh_mmcif_ops = {
1016         .request        = sh_mmcif_request,
1017         .set_ios        = sh_mmcif_set_ios,
1018         .get_cd         = sh_mmcif_get_cd,
1019 };
1020
1021 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1022 {
1023         struct mmc_command *cmd = host->mrq->cmd;
1024         struct mmc_data *data = host->mrq->data;
1025         long time;
1026
1027         if (host->sd_error) {
1028                 switch (cmd->opcode) {
1029                 case MMC_ALL_SEND_CID:
1030                 case MMC_SELECT_CARD:
1031                 case MMC_APP_CMD:
1032                         cmd->error = -ETIMEDOUT;
1033                         host->sd_error = false;
1034                         break;
1035                 default:
1036                         cmd->error = sh_mmcif_error_manage(host);
1037                         dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1038                                 cmd->opcode, cmd->error);
1039                         break;
1040                 }
1041                 return false;
1042         }
1043         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1044                 cmd->error = 0;
1045                 return false;
1046         }
1047
1048         sh_mmcif_get_response(host, cmd);
1049
1050         if (!data)
1051                 return false;
1052
1053         if (data->flags & MMC_DATA_READ) {
1054                 if (host->chan_rx)
1055                         sh_mmcif_start_dma_rx(host);
1056         } else {
1057                 if (host->chan_tx)
1058                         sh_mmcif_start_dma_tx(host);
1059         }
1060
1061         if (!host->dma_active) {
1062                 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1063                 if (!data->error)
1064                         return true;
1065                 return false;
1066         }
1067
1068         /* Running in the IRQ thread, can sleep */
1069         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1070                                                          host->timeout);
1071         if (host->sd_error) {
1072                 dev_err(host->mmc->parent,
1073                         "Error IRQ while waiting for DMA completion!\n");
1074                 /* Woken up by an error IRQ: abort DMA */
1075                 if (data->flags & MMC_DATA_READ)
1076                         dmaengine_terminate_all(host->chan_rx);
1077                 else
1078                         dmaengine_terminate_all(host->chan_tx);
1079                 data->error = sh_mmcif_error_manage(host);
1080         } else if (!time) {
1081                 data->error = -ETIMEDOUT;
1082         } else if (time < 0) {
1083                 data->error = time;
1084         }
1085         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1086                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1087         host->dma_active = false;
1088
1089         if (data->error)
1090                 data->bytes_xfered = 0;
1091
1092         return false;
1093 }
1094
1095 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1096 {
1097         struct sh_mmcif_host *host = dev_id;
1098         struct mmc_request *mrq = host->mrq;
1099         struct mmc_data *data = mrq->data;
1100
1101         cancel_delayed_work_sync(&host->timeout_work);
1102
1103         /*
1104          * All handlers return true, if processing continues, and false, if the
1105          * request has to be completed - successfully or not
1106          */
1107         switch (host->wait_for) {
1108         case MMCIF_WAIT_FOR_REQUEST:
1109                 /* We're too late, the timeout has already kicked in */
1110                 return IRQ_HANDLED;
1111         case MMCIF_WAIT_FOR_CMD:
1112                 if (sh_mmcif_end_cmd(host))
1113                         /* Wait for data */
1114                         return IRQ_HANDLED;
1115                 break;
1116         case MMCIF_WAIT_FOR_MREAD:
1117                 if (sh_mmcif_mread_block(host))
1118                         /* Wait for more data */
1119                         return IRQ_HANDLED;
1120                 break;
1121         case MMCIF_WAIT_FOR_READ:
1122                 if (sh_mmcif_read_block(host))
1123                         /* Wait for data end */
1124                         return IRQ_HANDLED;
1125                 break;
1126         case MMCIF_WAIT_FOR_MWRITE:
1127                 if (sh_mmcif_mwrite_block(host))
1128                         /* Wait data to write */
1129                         return IRQ_HANDLED;
1130                 break;
1131         case MMCIF_WAIT_FOR_WRITE:
1132                 if (sh_mmcif_write_block(host))
1133                         /* Wait for data end */
1134                         return IRQ_HANDLED;
1135                 break;
1136         case MMCIF_WAIT_FOR_STOP:
1137                 if (host->sd_error) {
1138                         mrq->stop->error = sh_mmcif_error_manage(host);
1139                         break;
1140                 }
1141                 sh_mmcif_get_cmd12response(host, mrq->stop);
1142                 mrq->stop->error = 0;
1143                 break;
1144         case MMCIF_WAIT_FOR_READ_END:
1145         case MMCIF_WAIT_FOR_WRITE_END:
1146                 if (host->sd_error)
1147                         data->error = sh_mmcif_error_manage(host);
1148                 break;
1149         default:
1150                 BUG();
1151         }
1152
1153         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1154                 if (!mrq->cmd->error && data && !data->error)
1155                         data->bytes_xfered =
1156                                 data->blocks * data->blksz;
1157
1158                 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1159                         sh_mmcif_stop_cmd(host, mrq);
1160                         if (!mrq->stop->error)
1161                                 return IRQ_HANDLED;
1162                 }
1163         }
1164
1165         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1166         host->state = STATE_IDLE;
1167         host->mrq = NULL;
1168         mmc_request_done(host->mmc, mrq);
1169
1170         return IRQ_HANDLED;
1171 }
1172
1173 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1174 {
1175         struct sh_mmcif_host *host = dev_id;
1176         u32 state;
1177         int err = 0;
1178
1179         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1180
1181         if (state & INT_ERR_STS) {
1182                 /* error interrupts - process first */
1183                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1184                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1185                 err = 1;
1186         } else if (state & INT_RBSYE) {
1187                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1188                                 ~(INT_RBSYE | INT_CRSPE));
1189                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1190         } else if (state & INT_CRSPE) {
1191                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
1192                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1193         } else if (state & INT_BUFREN) {
1194                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
1195                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1196         } else if (state & INT_BUFWEN) {
1197                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
1198                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1199         } else if (state & INT_CMD12DRE) {
1200                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1201                         ~(INT_CMD12DRE | INT_CMD12RBE |
1202                           INT_CMD12CRE | INT_BUFRE));
1203                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1204         } else if (state & INT_BUFRE) {
1205                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
1206                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1207         } else if (state & INT_DTRANE) {
1208                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
1209                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1210         } else if (state & INT_CMD12RBE) {
1211                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1212                                 ~(INT_CMD12RBE | INT_CMD12CRE));
1213                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
1214         } else {
1215                 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
1216                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1217                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1218                 err = 1;
1219         }
1220         if (err) {
1221                 host->sd_error = true;
1222                 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
1223         }
1224         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1225                 if (!host->dma_active)
1226                         return IRQ_WAKE_THREAD;
1227                 else if (host->sd_error)
1228                         mmcif_dma_complete(host);
1229         } else {
1230                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1231         }
1232
1233         return IRQ_HANDLED;
1234 }
1235
1236 static void mmcif_timeout_work(struct work_struct *work)
1237 {
1238         struct delayed_work *d = container_of(work, struct delayed_work, work);
1239         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1240         struct mmc_request *mrq = host->mrq;
1241
1242         if (host->dying)
1243                 /* Don't run after mmc_remove_host() */
1244                 return;
1245
1246         /*
1247          * Handle races with cancel_delayed_work(), unless
1248          * cancel_delayed_work_sync() is used
1249          */
1250         switch (host->wait_for) {
1251         case MMCIF_WAIT_FOR_CMD:
1252                 mrq->cmd->error = sh_mmcif_error_manage(host);
1253                 break;
1254         case MMCIF_WAIT_FOR_STOP:
1255                 mrq->stop->error = sh_mmcif_error_manage(host);
1256                 break;
1257         case MMCIF_WAIT_FOR_MREAD:
1258         case MMCIF_WAIT_FOR_MWRITE:
1259         case MMCIF_WAIT_FOR_READ:
1260         case MMCIF_WAIT_FOR_WRITE:
1261         case MMCIF_WAIT_FOR_READ_END:
1262         case MMCIF_WAIT_FOR_WRITE_END:
1263                 mrq->data->error = sh_mmcif_error_manage(host);
1264                 break;
1265         default:
1266                 BUG();
1267         }
1268
1269         host->state = STATE_IDLE;
1270         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1271         host->mrq = NULL;
1272         mmc_request_done(host->mmc, mrq);
1273 }
1274
1275 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1276 {
1277         struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1278         struct mmc_host *mmc = host->mmc;
1279
1280         mmc_regulator_get_supply(mmc);
1281
1282         if (!pd)
1283                 return;
1284
1285         if (!mmc->ocr_avail)
1286                 mmc->ocr_avail = pd->ocr;
1287         else if (pd->ocr)
1288                 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1289 }
1290
1291 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1292 {
1293         int ret = 0, irq[2];
1294         struct mmc_host *mmc;
1295         struct sh_mmcif_host *host;
1296         struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
1297         struct resource *res;
1298         void __iomem *reg;
1299         char clk_name[8];
1300
1301         irq[0] = platform_get_irq(pdev, 0);
1302         irq[1] = platform_get_irq(pdev, 1);
1303         if (irq[0] < 0 || irq[1] < 0) {
1304                 dev_err(&pdev->dev, "Get irq error\n");
1305                 return -ENXIO;
1306         }
1307         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1308         if (!res) {
1309                 dev_err(&pdev->dev, "platform_get_resource error.\n");
1310                 return -ENXIO;
1311         }
1312         reg = ioremap(res->start, resource_size(res));
1313         if (!reg) {
1314                 dev_err(&pdev->dev, "ioremap error.\n");
1315                 return -ENOMEM;
1316         }
1317
1318         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1319         if (!mmc) {
1320                 ret = -ENOMEM;
1321                 goto ealloch;
1322         }
1323         host            = mmc_priv(mmc);
1324         host->mmc       = mmc;
1325         host->addr      = reg;
1326         host->timeout   = 1000;
1327
1328         host->pd = pdev;
1329
1330         spin_lock_init(&host->lock);
1331
1332         mmc->ops = &sh_mmcif_ops;
1333         sh_mmcif_init_ocr(host);
1334
1335         mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1336         if (pd && pd->caps)
1337                 mmc->caps |= pd->caps;
1338         mmc->max_segs = 32;
1339         mmc->max_blk_size = 512;
1340         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1341         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1342         mmc->max_seg_size = mmc->max_req_size;
1343
1344         platform_set_drvdata(pdev, host);
1345
1346         pm_runtime_enable(&pdev->dev);
1347         host->power = false;
1348
1349         snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1350         host->hclk = clk_get(&pdev->dev, clk_name);
1351         if (IS_ERR(host->hclk)) {
1352                 ret = PTR_ERR(host->hclk);
1353                 dev_err(&pdev->dev, "cannot get clock \"%s\": %d\n", clk_name, ret);
1354                 goto eclkget;
1355         }
1356         ret = sh_mmcif_clk_update(host);
1357         if (ret < 0)
1358                 goto eclkupdate;
1359
1360         ret = pm_runtime_resume(&pdev->dev);
1361         if (ret < 0)
1362                 goto eresume;
1363
1364         INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1365
1366         sh_mmcif_sync_reset(host);
1367         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1368
1369         ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
1370         if (ret) {
1371                 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1372                 goto ereqirq0;
1373         }
1374         ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
1375         if (ret) {
1376                 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1377                 goto ereqirq1;
1378         }
1379
1380         if (pd && pd->use_cd_gpio) {
1381                 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio);
1382                 if (ret < 0)
1383                         goto erqcd;
1384         }
1385
1386         clk_disable(host->hclk);
1387         ret = mmc_add_host(mmc);
1388         if (ret < 0)
1389                 goto emmcaddh;
1390
1391         dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1392
1393         dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1394         dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1395                 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1396         return ret;
1397
1398 emmcaddh:
1399         if (pd && pd->use_cd_gpio)
1400                 mmc_gpio_free_cd(mmc);
1401 erqcd:
1402         free_irq(irq[1], host);
1403 ereqirq1:
1404         free_irq(irq[0], host);
1405 ereqirq0:
1406         pm_runtime_suspend(&pdev->dev);
1407 eresume:
1408         clk_disable(host->hclk);
1409 eclkupdate:
1410         clk_put(host->hclk);
1411 eclkget:
1412         pm_runtime_disable(&pdev->dev);
1413         mmc_free_host(mmc);
1414 ealloch:
1415         iounmap(reg);
1416         return ret;
1417 }
1418
1419 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1420 {
1421         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1422         struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
1423         int irq[2];
1424
1425         host->dying = true;
1426         clk_enable(host->hclk);
1427         pm_runtime_get_sync(&pdev->dev);
1428
1429         dev_pm_qos_hide_latency_limit(&pdev->dev);
1430
1431         if (pd && pd->use_cd_gpio)
1432                 mmc_gpio_free_cd(host->mmc);
1433
1434         mmc_remove_host(host->mmc);
1435         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1436
1437         /*
1438          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1439          * mmc_remove_host() call above. But swapping order doesn't help either
1440          * (a query on the linux-mmc mailing list didn't bring any replies).
1441          */
1442         cancel_delayed_work_sync(&host->timeout_work);
1443
1444         if (host->addr)
1445                 iounmap(host->addr);
1446
1447         irq[0] = platform_get_irq(pdev, 0);
1448         irq[1] = platform_get_irq(pdev, 1);
1449
1450         free_irq(irq[0], host);
1451         free_irq(irq[1], host);
1452
1453         platform_set_drvdata(pdev, NULL);
1454
1455         mmc_free_host(host->mmc);
1456         pm_runtime_put_sync(&pdev->dev);
1457         clk_disable(host->hclk);
1458         pm_runtime_disable(&pdev->dev);
1459
1460         return 0;
1461 }
1462
1463 #ifdef CONFIG_PM
1464 static int sh_mmcif_suspend(struct device *dev)
1465 {
1466         struct sh_mmcif_host *host = dev_get_drvdata(dev);
1467         int ret = mmc_suspend_host(host->mmc);
1468
1469         if (!ret)
1470                 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1471
1472         return ret;
1473 }
1474
1475 static int sh_mmcif_resume(struct device *dev)
1476 {
1477         struct sh_mmcif_host *host = dev_get_drvdata(dev);
1478
1479         return mmc_resume_host(host->mmc);
1480 }
1481 #else
1482 #define sh_mmcif_suspend        NULL
1483 #define sh_mmcif_resume         NULL
1484 #endif  /* CONFIG_PM */
1485
1486 static const struct of_device_id mmcif_of_match[] = {
1487         { .compatible = "renesas,sh-mmcif" },
1488         { }
1489 };
1490 MODULE_DEVICE_TABLE(of, mmcif_of_match);
1491
1492 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1493         .suspend = sh_mmcif_suspend,
1494         .resume = sh_mmcif_resume,
1495 };
1496
1497 static struct platform_driver sh_mmcif_driver = {
1498         .probe          = sh_mmcif_probe,
1499         .remove         = sh_mmcif_remove,
1500         .driver         = {
1501                 .name   = DRIVER_NAME,
1502                 .pm     = &sh_mmcif_dev_pm_ops,
1503                 .owner  = THIS_MODULE,
1504                 .of_match_table = mmcif_of_match,
1505         },
1506 };
1507
1508 module_platform_driver(sh_mmcif_driver);
1509
1510 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1511 MODULE_LICENSE("GPL");
1512 MODULE_ALIAS("platform:" DRIVER_NAME);
1513 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");