drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 /*
  20  * The MMCIF driver is now processing MMC requests asynchronously, according
  21  * to the Linux MMC API requirement.
  22  *
  23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
  24  * data, and optional stop. To achieve asynchronous processing each of these
  25  * stages is split into two halves: a top and a bottom half. The top half
  26  * initialises the hardware, installs a timeout handler to handle completion
  27  * timeouts, and returns. In case of the command stage this immediately returns
  28  * control to the caller, leaving all further processing to run asynchronously.
  29  * All further request processing is performed by the bottom halves.
  30  *
  31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
  32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
  33  * request- and stage-specific handler methods.
  34  *
  35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
  36  * invocation, or a timeout work run. In case of an error or a successful
  37  * processing completion, the MMC core is informed and the request processing is
  38  * finished. In case processing has to continue, i.e., if data has to be read
  39  * from or written to the card, or if a stop command has to be sent, the next
  40  * top half is called, which performs the necessary hardware handling and
  41  * reschedules the timeout work. This returns the driver state machine into the
  42  * bottom half waiting state.
  43  */
  44
  45 #include <linux/bitops.h>
  46 #include <linux/clk.h>
  47 #include <linux/completion.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/mmc/card.h>
  52 #include <linux/mmc/core.h>
  53 #include <linux/mmc/host.h>
  54 #include <linux/mmc/mmc.h>
  55 #include <linux/mmc/sdio.h>
  56 #include <linux/mmc/sh_mmcif.h>
  57 #include <linux/mod_devicetable.h>
  58 #include <linux/pagemap.h>
  59 #include <linux/platform_device.h>
  60 #include <linux/pm_qos.h>
  61 #include <linux/pm_runtime.h>
  62 #include <linux/spinlock.h>
  63 #include <linux/module.h>
  64
  65 #define DRIVER_NAME     "sh_mmcif"
  66 #define DRIVER_VERSION  "2010-04-28"
  67
  68 /* CE_CMD_SET */
  69 #define CMD_MASK                0x3f000000
  70 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  71 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  72 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  73 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  74 #define CMD_SET_CCSEN           (1 << 20)
  75 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  76 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  77 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  78 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  79 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  80 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  81 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  82 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  83 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  84 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  85 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  86 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  87 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  88 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  89 #define CMD_SET_CCSH            (1 << 5)
  90 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  91 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  92 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  93
  94 /* CE_CMD_CTRL */
  95 #define CMD_CTRL_BREAK          (1 << 0)
  96
  97 /* CE_BLOCK_SET */
  98 #define BLOCK_SIZE_MASK         0x0000ffff
  99
 100 /* CE_INT */
 101 #define INT_CCSDE               (1 << 29)
 102 #define INT_CMD12DRE            (1 << 26)
 103 #define INT_CMD12RBE            (1 << 25)
 104 #define INT_CMD12CRE            (1 << 24)
 105 #define INT_DTRANE              (1 << 23)
 106 #define INT_BUFRE               (1 << 22)
 107 #define INT_BUFWEN              (1 << 21)
 108 #define INT_BUFREN              (1 << 20)
 109 #define INT_CCSRCV              (1 << 19)
 110 #define INT_RBSYE               (1 << 17)
 111 #define INT_CRSPE               (1 << 16)
 112 #define INT_CMDVIO              (1 << 15)
 113 #define INT_BUFVIO              (1 << 14)
 114 #define INT_WDATERR             (1 << 11)
 115 #define INT_RDATERR             (1 << 10)
 116 #define INT_RIDXERR             (1 << 9)
 117 #define INT_RSPERR              (1 << 8)
 118 #define INT_CCSTO               (1 << 5)
 119 #define INT_CRCSTO              (1 << 4)
 120 #define INT_WDATTO              (1 << 3)
 121 #define INT_RDATTO              (1 << 2)
 122 #define INT_RBSYTO              (1 << 1)
 123 #define INT_RSPTO               (1 << 0)
 124 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 125                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 126                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 127                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 128
 129 /* CE_INT_MASK */
 130 #define MASK_ALL                0x00000000
 131 #define MASK_MCCSDE             (1 << 29)
 132 #define MASK_MCMD12DRE          (1 << 26)
 133 #define MASK_MCMD12RBE          (1 << 25)
 134 #define MASK_MCMD12CRE          (1 << 24)
 135 #define MASK_MDTRANE            (1 << 23)
 136 #define MASK_MBUFRE             (1 << 22)
 137 #define MASK_MBUFWEN            (1 << 21)
 138 #define MASK_MBUFREN            (1 << 20)
 139 #define MASK_MCCSRCV            (1 << 19)
 140 #define MASK_MRBSYE             (1 << 17)
 141 #define MASK_MCRSPE             (1 << 16)
 142 #define MASK_MCMDVIO            (1 << 15)
 143 #define MASK_MBUFVIO            (1 << 14)
 144 #define MASK_MWDATERR           (1 << 11)
 145 #define MASK_MRDATERR           (1 << 10)
 146 #define MASK_MRIDXERR           (1 << 9)
 147 #define MASK_MRSPERR            (1 << 8)
 148 #define MASK_MCCSTO             (1 << 5)
 149 #define MASK_MCRCSTO            (1 << 4)
 150 #define MASK_MWDATTO            (1 << 3)
 151 #define MASK_MRDATTO            (1 << 2)
 152 #define MASK_MRBSYTO            (1 << 1)
 153 #define MASK_MRSPTO             (1 << 0)
 154
 155 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 156                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 157                                  MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
 158                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 159
 160 /* CE_HOST_STS1 */
 161 #define STS1_CMDSEQ             (1 << 31)
 162
 163 /* CE_HOST_STS2 */
 164 #define STS2_CRCSTE             (1 << 31)
 165 #define STS2_CRC16E             (1 << 30)
 166 #define STS2_AC12CRCE           (1 << 29)
 167 #define STS2_RSPCRC7E           (1 << 28)
 168 #define STS2_CRCSTEBE           (1 << 27)
 169 #define STS2_RDATEBE            (1 << 26)
 170 #define STS2_AC12REBE           (1 << 25)
 171 #define STS2_RSPEBE             (1 << 24)
 172 #define STS2_AC12IDXE           (1 << 23)
 173 #define STS2_RSPIDXE            (1 << 22)
 174 #define STS2_CCSTO              (1 << 15)
 175 #define STS2_RDATTO             (1 << 14)
 176 #define STS2_DATBSYTO           (1 << 13)
 177 #define STS2_CRCSTTO            (1 << 12)
 178 #define STS2_AC12BSYTO          (1 << 11)
 179 #define STS2_RSPBSYTO           (1 << 10)
 180 #define STS2_AC12RSPTO          (1 << 9)
 181 #define STS2_RSPTO              (1 << 8)
 182 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 183                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 184 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 185                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 186                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 187                                  STS2_AC12RSPTO | STS2_RSPTO)
 188
 189 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 190 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 191 #define CLKDEV_INIT             400000   /* 400 KHz */
 192
 193 enum mmcif_state {
 194         STATE_IDLE,
 195         STATE_REQUEST,
 196         STATE_IOS,
 197 };
 198
 199 enum mmcif_wait_for {
 200         MMCIF_WAIT_FOR_REQUEST,
 201         MMCIF_WAIT_FOR_CMD,
 202         MMCIF_WAIT_FOR_MREAD,
 203         MMCIF_WAIT_FOR_MWRITE,
 204         MMCIF_WAIT_FOR_READ,
 205         MMCIF_WAIT_FOR_WRITE,
 206         MMCIF_WAIT_FOR_READ_END,
 207         MMCIF_WAIT_FOR_WRITE_END,
 208         MMCIF_WAIT_FOR_STOP,
 209 };
 210
 211 struct sh_mmcif_host {
 212         struct mmc_host *mmc;
 213         struct mmc_request *mrq;
 214         struct platform_device *pd;
 215         struct sh_dmae_slave dma_slave_tx;
 216         struct sh_dmae_slave dma_slave_rx;
 217         struct clk *hclk;
 218         unsigned int clk;
 219         int bus_width;
 220         bool sd_error;
 221         bool dying;
 222         long timeout;
 223         void __iomem *addr;
 224         u32 *pio_ptr;
 225         spinlock_t lock;                /* protect sh_mmcif_host::state */
 226         enum mmcif_state state;
 227         enum mmcif_wait_for wait_for;
 228         struct delayed_work timeout_work;
 229         size_t blocksize;
 230         int sg_idx;
 231         int sg_blkidx;
 232         bool power;
 233         bool card_present;
 234
 235         /* DMA support */
 236         struct dma_chan         *chan_rx;
 237         struct dma_chan         *chan_tx;
 238         struct completion       dma_complete;
 239         bool                    dma_active;
 240 };
 241
 242 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 243                                         unsigned int reg, u32 val)
 244 {
 245         writel(val | readl(host->addr + reg), host->addr + reg);
 246 }
 247
 248 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 249                                         unsigned int reg, u32 val)
 250 {
 251         writel(~val & readl(host->addr + reg), host->addr + reg);
 252 }
 253
 254 static void mmcif_dma_complete(void *arg)
 255 {
 256         struct sh_mmcif_host *host = arg;
 257         struct mmc_data *data = host->mrq->data;
 258
 259         dev_dbg(&host->pd->dev, "Command completed\n");
 260
 261         if (WARN(!data, "%s: NULL data in DMA completion!\n",
 262                  dev_name(&host->pd->dev)))
 263                 return;
 264
 265         if (data->flags & MMC_DATA_READ)
 266                 dma_unmap_sg(host->chan_rx->device->dev,
 267                              data->sg, data->sg_len,
 268                              DMA_FROM_DEVICE);
 269         else
 270                 dma_unmap_sg(host->chan_tx->device->dev,
 271                              data->sg, data->sg_len,
 272                              DMA_TO_DEVICE);
 273
 274         complete(&host->dma_complete);
 275 }
 276
 277 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 278 {
 279         struct mmc_data *data = host->mrq->data;
 280         struct scatterlist *sg = data->sg;
 281         struct dma_async_tx_descriptor *desc = NULL;
 282         struct dma_chan *chan = host->chan_rx;
 283         dma_cookie_t cookie = -EINVAL;
 284         int ret;
 285
 286         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 287                          DMA_FROM_DEVICE);
 288         if (ret > 0) {
 289                 host->dma_active = true;
 290                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 291                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 292         }
 293
 294         if (desc) {
 295                 desc->callback = mmcif_dma_complete;
 296                 desc->callback_param = host;
 297                 cookie = dmaengine_submit(desc);
 298                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 299                 dma_async_issue_pending(chan);
 300         }
 301         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 302                 __func__, data->sg_len, ret, cookie);
 303
 304         if (!desc) {
 305                 /* DMA failed, fall back to PIO */
 306                 if (ret >= 0)
 307                         ret = -EIO;
 308                 host->chan_rx = NULL;
 309                 host->dma_active = false;
 310                 dma_release_channel(chan);
 311                 /* Free the Tx channel too */
 312                 chan = host->chan_tx;
 313                 if (chan) {
 314                         host->chan_tx = NULL;
 315                         dma_release_channel(chan);
 316                 }
 317                 dev_warn(&host->pd->dev,
 318                          "DMA failed: %d, falling back to PIO\n", ret);
 319                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 320         }
 321
 322         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 323                 desc, cookie, data->sg_len);
 324 }
 325
 326 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 327 {
 328         struct mmc_data *data = host->mrq->data;
 329         struct scatterlist *sg = data->sg;
 330         struct dma_async_tx_descriptor *desc = NULL;
 331         struct dma_chan *chan = host->chan_tx;
 332         dma_cookie_t cookie = -EINVAL;
 333         int ret;
 334
 335         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 336                          DMA_TO_DEVICE);
 337         if (ret > 0) {
 338                 host->dma_active = true;
 339                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 340                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 341         }
 342
 343         if (desc) {
 344                 desc->callback = mmcif_dma_complete;
 345                 desc->callback_param = host;
 346                 cookie = dmaengine_submit(desc);
 347                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 348                 dma_async_issue_pending(chan);
 349         }
 350         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 351                 __func__, data->sg_len, ret, cookie);
 352
 353         if (!desc) {
 354                 /* DMA failed, fall back to PIO */
 355                 if (ret >= 0)
 356                         ret = -EIO;
 357                 host->chan_tx = NULL;
 358                 host->dma_active = false;
 359                 dma_release_channel(chan);
 360                 /* Free the Rx channel too */
 361                 chan = host->chan_rx;
 362                 if (chan) {
 363                         host->chan_rx = NULL;
 364                         dma_release_channel(chan);
 365                 }
 366                 dev_warn(&host->pd->dev,
 367                          "DMA failed: %d, falling back to PIO\n", ret);
 368                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 369         }
 370
 371         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 372                 desc, cookie);
 373 }
 374
 375 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
 376 {
 377         dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
 378         chan->private = arg;
 379         return true;
 380 }
 381
 382 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 383                                  struct sh_mmcif_plat_data *pdata)
 384 {
 385         struct sh_dmae_slave *tx, *rx;
 386         host->dma_active = false;
 387
 388         if (!pdata)
 389                 return;
 390
 391         /* We can only either use DMA for both Tx and Rx or not use it at all */
 392         if (pdata->dma) {
 393                 dev_warn(&host->pd->dev,
 394                          "Update your platform to use embedded DMA slave IDs\n");
 395                 tx = &pdata->dma->chan_priv_tx;
 396                 rx = &pdata->dma->chan_priv_rx;
 397         } else {
 398                 tx = &host->dma_slave_tx;
 399                 tx->slave_id = pdata->slave_id_tx;
 400                 rx = &host->dma_slave_rx;
 401                 rx->slave_id = pdata->slave_id_rx;
 402         }
 403         if (tx->slave_id > 0 && rx->slave_id > 0) {
 404                 dma_cap_mask_t mask;
 405
 406                 dma_cap_zero(mask);
 407                 dma_cap_set(DMA_SLAVE, mask);
 408
 409                 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx);
 410                 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
 411                         host->chan_tx);
 412
 413                 if (!host->chan_tx)
 414                         return;
 415
 416                 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx);
 417                 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
 418                         host->chan_rx);
 419
 420                 if (!host->chan_rx) {
 421                         dma_release_channel(host->chan_tx);
 422                         host->chan_tx = NULL;
 423                         return;
 424                 }
 425
 426                 init_completion(&host->dma_complete);
 427         }
 428 }
 429
 430 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 431 {
 432         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 433         /* Descriptors are freed automatically */
 434         if (host->chan_tx) {
 435                 struct dma_chan *chan = host->chan_tx;
 436                 host->chan_tx = NULL;
 437                 dma_release_channel(chan);
 438         }
 439         if (host->chan_rx) {
 440                 struct dma_chan *chan = host->chan_rx;
 441                 host->chan_rx = NULL;
 442                 dma_release_channel(chan);
 443         }
 444
 445         host->dma_active = false;
 446 }
 447
 448 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 449 {
 450         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 451         bool sup_pclk = p ? p->sup_pclk : false;
 452
 453         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 454         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 455
 456         if (!clk)
 457                 return;
 458         if (sup_pclk && clk == host->clk)
 459                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 460         else
 461                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 462                                 ((fls(DIV_ROUND_UP(host->clk,
 463                                                    clk) - 1) - 1) << 16));
 464
 465         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 466 }
 467
 468 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 469 {
 470         u32 tmp;
 471
 472         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 473
 474         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 475         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 476         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 477                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 478         /* byte swap on */
 479         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 480 }
 481
 482 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 483 {
 484         u32 state1, state2;
 485         int ret, timeout;
 486
 487         host->sd_error = false;
 488
 489         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 490         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 491         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 492         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 493
 494         if (state1 & STS1_CMDSEQ) {
 495                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 496                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 497                 for (timeout = 10000000; timeout; timeout--) {
 498                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 499                               & STS1_CMDSEQ))
 500                                 break;
 501                         mdelay(1);
 502                 }
 503                 if (!timeout) {
 504                         dev_err(&host->pd->dev,
 505                                 "Forced end of command sequence timeout err\n");
 506                         return -EIO;
 507                 }
 508                 sh_mmcif_sync_reset(host);
 509                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 510                 return -EIO;
 511         }
 512
 513         if (state2 & STS2_CRC_ERR) {
 514                 dev_dbg(&host->pd->dev, ": CRC error\n");
 515                 ret = -EIO;
 516         } else if (state2 & STS2_TIMEOUT_ERR) {
 517                 dev_dbg(&host->pd->dev, ": Timeout\n");
 518                 ret = -ETIMEDOUT;
 519         } else {
 520                 dev_dbg(&host->pd->dev, ": End/Index error\n");
 521                 ret = -EIO;
 522         }
 523         return ret;
 524 }
 525
 526 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
 527 {
 528         struct mmc_data *data = host->mrq->data;
 529
 530         host->sg_blkidx += host->blocksize;
 531
 532         /* data->sg->length must be a multiple of host->blocksize? */
 533         BUG_ON(host->sg_blkidx > data->sg->length);
 534
 535         if (host->sg_blkidx == data->sg->length) {
 536                 host->sg_blkidx = 0;
 537                 if (++host->sg_idx < data->sg_len)
 538                         host->pio_ptr = sg_virt(++data->sg);
 539         } else {
 540                 host->pio_ptr = p;
 541         }
 542
 543         if (host->sg_idx == data->sg_len)
 544                 return false;
 545
 546         return true;
 547 }
 548
 549 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
 550                                  struct mmc_request *mrq)
 551 {
 552         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 553                            BLOCK_SIZE_MASK) + 3;
 554
 555         host->wait_for = MMCIF_WAIT_FOR_READ;
 556         schedule_delayed_work(&host->timeout_work, host->timeout);
 557
 558         /* buf read enable */
 559         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 560 }
 561
 562 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
 563 {
 564         struct mmc_data *data = host->mrq->data;
 565         u32 *p = sg_virt(data->sg);
 566         int i;
 567
 568         if (host->sd_error) {
 569                 data->error = sh_mmcif_error_manage(host);
 570                 return false;
 571         }
 572
 573         for (i = 0; i < host->blocksize / 4; i++)
 574                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 575
 576         /* buffer read end */
 577         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 578         host->wait_for = MMCIF_WAIT_FOR_READ_END;
 579
 580         return true;
 581 }
 582
 583 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
 584                                 struct mmc_request *mrq)
 585 {
 586         struct mmc_data *data = mrq->data;
 587
 588         if (!data->sg_len || !data->sg->length)
 589                 return;
 590
 591         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 592                 BLOCK_SIZE_MASK;
 593
 594         host->wait_for = MMCIF_WAIT_FOR_MREAD;
 595         host->sg_idx = 0;
 596         host->sg_blkidx = 0;
 597         host->pio_ptr = sg_virt(data->sg);
 598         schedule_delayed_work(&host->timeout_work, host->timeout);
 599         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 600 }
 601
 602 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
 603 {
 604         struct mmc_data *data = host->mrq->data;
 605         u32 *p = host->pio_ptr;
 606         int i;
 607
 608         if (host->sd_error) {
 609                 data->error = sh_mmcif_error_manage(host);
 610                 return false;
 611         }
 612
 613         BUG_ON(!data->sg->length);
 614
 615         for (i = 0; i < host->blocksize / 4; i++)
 616                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 617
 618         if (!sh_mmcif_next_block(host, p))
 619                 return false;
 620
 621         schedule_delayed_work(&host->timeout_work, host->timeout);
 622         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 623
 624         return true;
 625 }
 626
 627 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
 628                                         struct mmc_request *mrq)
 629 {
 630         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 631                            BLOCK_SIZE_MASK) + 3;
 632
 633         host->wait_for = MMCIF_WAIT_FOR_WRITE;
 634         schedule_delayed_work(&host->timeout_work, host->timeout);
 635
 636         /* buf write enable */
 637         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 638 }
 639
 640 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
 641 {
 642         struct mmc_data *data = host->mrq->data;
 643         u32 *p = sg_virt(data->sg);
 644         int i;
 645
 646         if (host->sd_error) {
 647                 data->error = sh_mmcif_error_manage(host);
 648                 return false;
 649         }
 650
 651         for (i = 0; i < host->blocksize / 4; i++)
 652                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 653
 654         /* buffer write end */
 655         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 656         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
 657
 658         return true;
 659 }
 660
 661 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
 662                                 struct mmc_request *mrq)
 663 {
 664         struct mmc_data *data = mrq->data;
 665
 666         if (!data->sg_len || !data->sg->length)
 667                 return;
 668
 669         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 670                 BLOCK_SIZE_MASK;
 671
 672         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
 673         host->sg_idx = 0;
 674         host->sg_blkidx = 0;
 675         host->pio_ptr = sg_virt(data->sg);
 676         schedule_delayed_work(&host->timeout_work, host->timeout);
 677         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 678 }
 679
 680 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
 681 {
 682         struct mmc_data *data = host->mrq->data;
 683         u32 *p = host->pio_ptr;
 684         int i;
 685
 686         if (host->sd_error) {
 687                 data->error = sh_mmcif_error_manage(host);
 688                 return false;
 689         }
 690
 691         BUG_ON(!data->sg->length);
 692
 693         for (i = 0; i < host->blocksize / 4; i++)
 694                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 695
 696         if (!sh_mmcif_next_block(host, p))
 697                 return false;
 698
 699         schedule_delayed_work(&host->timeout_work, host->timeout);
 700         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 701
 702         return true;
 703 }
 704
 705 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 706                                                 struct mmc_command *cmd)
 707 {
 708         if (cmd->flags & MMC_RSP_136) {
 709                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 710                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 711                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 712                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 713         } else
 714                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 715 }
 716
 717 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 718                                                 struct mmc_command *cmd)
 719 {
 720         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 721 }
 722
 723 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 724                             struct mmc_request *mrq)
 725 {
 726         struct mmc_data *data = mrq->data;
 727         struct mmc_command *cmd = mrq->cmd;
 728         u32 opc = cmd->opcode;
 729         u32 tmp = 0;
 730
 731         /* Response Type check */
 732         switch (mmc_resp_type(cmd)) {
 733         case MMC_RSP_NONE:
 734                 tmp |= CMD_SET_RTYP_NO;
 735                 break;
 736         case MMC_RSP_R1:
 737         case MMC_RSP_R1B:
 738         case MMC_RSP_R3:
 739                 tmp |= CMD_SET_RTYP_6B;
 740                 break;
 741         case MMC_RSP_R2:
 742                 tmp |= CMD_SET_RTYP_17B;
 743                 break;
 744         default:
 745                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 746                 break;
 747         }
 748         switch (opc) {
 749         /* RBSY */
 750         case MMC_SWITCH:
 751         case MMC_STOP_TRANSMISSION:
 752         case MMC_SET_WRITE_PROT:
 753         case MMC_CLR_WRITE_PROT:
 754         case MMC_ERASE:
 755                 tmp |= CMD_SET_RBSY;
 756                 break;
 757         }
 758         /* WDAT / DATW */
 759         if (data) {
 760                 tmp |= CMD_SET_WDAT;
 761                 switch (host->bus_width) {
 762                 case MMC_BUS_WIDTH_1:
 763                         tmp |= CMD_SET_DATW_1;
 764                         break;
 765                 case MMC_BUS_WIDTH_4:
 766                         tmp |= CMD_SET_DATW_4;
 767                         break;
 768                 case MMC_BUS_WIDTH_8:
 769                         tmp |= CMD_SET_DATW_8;
 770                         break;
 771                 default:
 772                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 773                         break;
 774                 }
 775         }
 776         /* DWEN */
 777         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 778                 tmp |= CMD_SET_DWEN;
 779         /* CMLTE/CMD12EN */
 780         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 781                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 782                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 783                                 data->blocks << 16);
 784         }
 785         /* RIDXC[1:0] check bits */
 786         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 787             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 788                 tmp |= CMD_SET_RIDXC_BITS;
 789         /* RCRC7C[1:0] check bits */
 790         if (opc == MMC_SEND_OP_COND)
 791                 tmp |= CMD_SET_CRC7C_BITS;
 792         /* RCRC7C[1:0] internal CRC7 */
 793         if (opc == MMC_ALL_SEND_CID ||
 794                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 795                 tmp |= CMD_SET_CRC7C_INTERNAL;
 796
 797         return (opc << 24) | tmp;
 798 }
 799
 800 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 801                                struct mmc_request *mrq, u32 opc)
 802 {
 803         switch (opc) {
 804         case MMC_READ_MULTIPLE_BLOCK:
 805                 sh_mmcif_multi_read(host, mrq);
 806                 return 0;
 807         case MMC_WRITE_MULTIPLE_BLOCK:
 808                 sh_mmcif_multi_write(host, mrq);
 809                 return 0;
 810         case MMC_WRITE_BLOCK:
 811                 sh_mmcif_single_write(host, mrq);
 812                 return 0;
 813         case MMC_READ_SINGLE_BLOCK:
 814         case MMC_SEND_EXT_CSD:
 815                 sh_mmcif_single_read(host, mrq);
 816                 return 0;
 817         default:
 818                 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
 819                 return -EINVAL;
 820         }
 821 }
 822
 823 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 824                                struct mmc_request *mrq)
 825 {
 826         struct mmc_command *cmd = mrq->cmd;
 827         u32 opc = cmd->opcode;
 828         u32 mask;
 829
 830         switch (opc) {
 831         /* response busy check */
 832         case MMC_SWITCH:
 833         case MMC_STOP_TRANSMISSION:
 834         case MMC_SET_WRITE_PROT:
 835         case MMC_CLR_WRITE_PROT:
 836         case MMC_ERASE:
 837                 mask = MASK_START_CMD | MASK_MRBSYE;
 838                 break;
 839         default:
 840                 mask = MASK_START_CMD | MASK_MCRSPE;
 841                 break;
 842         }
 843
 844         if (mrq->data) {
 845                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 846                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 847                                 mrq->data->blksz);
 848         }
 849         opc = sh_mmcif_set_cmd(host, mrq);
 850
 851         sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 852         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 853         /* set arg */
 854         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 855         /* set cmd */
 856         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 857
 858         host->wait_for = MMCIF_WAIT_FOR_CMD;
 859         schedule_delayed_work(&host->timeout_work, host->timeout);
 860 }
 861
 862 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 863                               struct mmc_request *mrq)
 864 {
 865         switch (mrq->cmd->opcode) {
 866         case MMC_READ_MULTIPLE_BLOCK:
 867                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 868                 break;
 869         case MMC_WRITE_MULTIPLE_BLOCK:
 870                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 871                 break;
 872         default:
 873                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 874                 mrq->stop->error = sh_mmcif_error_manage(host);
 875                 return;
 876         }
 877
 878         host->wait_for = MMCIF_WAIT_FOR_STOP;
 879         schedule_delayed_work(&host->timeout_work, host->timeout);
 880 }
 881
 882 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 883 {
 884         struct sh_mmcif_host *host = mmc_priv(mmc);
 885         unsigned long flags;
 886
 887         spin_lock_irqsave(&host->lock, flags);
 888         if (host->state != STATE_IDLE) {
 889                 spin_unlock_irqrestore(&host->lock, flags);
 890                 mrq->cmd->error = -EAGAIN;
 891                 mmc_request_done(mmc, mrq);
 892                 return;
 893         }
 894
 895         host->state = STATE_REQUEST;
 896         spin_unlock_irqrestore(&host->lock, flags);
 897
 898         switch (mrq->cmd->opcode) {
 899         /* MMCIF does not support SD/SDIO command */
 900         case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
 901         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 902                 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
 903                         break;
 904         case MMC_APP_CMD:
 905                 host->state = STATE_IDLE;
 906                 mrq->cmd->error = -ETIMEDOUT;
 907                 mmc_request_done(mmc, mrq);
 908                 return;
 909         default:
 910                 break;
 911         }
 912
 913         host->mrq = mrq;
 914
 915         sh_mmcif_start_cmd(host, mrq);
 916 }
 917
 918 static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
 919 {
 920         int ret = clk_enable(host->hclk);
 921
 922         if (!ret) {
 923                 host->clk = clk_get_rate(host->hclk);
 924                 host->mmc->f_max = host->clk / 2;
 925                 host->mmc->f_min = host->clk / 512;
 926         }
 927
 928         return ret;
 929 }
 930
 931 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
 932 {
 933         struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
 934         struct mmc_host *mmc = host->mmc;
 935
 936         if (pd && pd->set_pwr)
 937                 pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF);
 938         if (!IS_ERR(mmc->supply.vmmc))
 939                 /* Errors ignored... */
 940                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
 941                                       ios->power_mode ? ios->vdd : 0);
 942 }
 943
 944 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 945 {
 946         struct sh_mmcif_host *host = mmc_priv(mmc);
 947         unsigned long flags;
 948
 949         spin_lock_irqsave(&host->lock, flags);
 950         if (host->state != STATE_IDLE) {
 951                 spin_unlock_irqrestore(&host->lock, flags);
 952                 return;
 953         }
 954
 955         host->state = STATE_IOS;
 956         spin_unlock_irqrestore(&host->lock, flags);
 957
 958         if (ios->power_mode == MMC_POWER_UP) {
 959                 if (!host->card_present) {
 960                         /* See if we also get DMA */
 961                         sh_mmcif_request_dma(host, host->pd->dev.platform_data);
 962                         host->card_present = true;
 963                 }
 964                 sh_mmcif_set_power(host, ios);
 965         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
 966                 /* clock stop */
 967                 sh_mmcif_clock_control(host, 0);
 968                 if (ios->power_mode == MMC_POWER_OFF) {
 969                         if (host->card_present) {
 970                                 sh_mmcif_release_dma(host);
 971                                 host->card_present = false;
 972                         }
 973                 }
 974                 if (host->power) {
 975                         pm_runtime_put(&host->pd->dev);
 976                         clk_disable(host->hclk);
 977                         host->power = false;
 978                         if (ios->power_mode == MMC_POWER_OFF)
 979                                 sh_mmcif_set_power(host, ios);
 980                 }
 981                 host->state = STATE_IDLE;
 982                 return;
 983         }
 984
 985         if (ios->clock) {
 986                 if (!host->power) {
 987                         sh_mmcif_clk_update(host);
 988                         pm_runtime_get_sync(&host->pd->dev);
 989                         host->power = true;
 990                         sh_mmcif_sync_reset(host);
 991                 }
 992                 sh_mmcif_clock_control(host, ios->clock);
 993         }
 994
 995         host->bus_width = ios->bus_width;
 996         host->state = STATE_IDLE;
 997 }
 998
 999 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1000 {
1001         struct sh_mmcif_host *host = mmc_priv(mmc);
1002         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
1003
1004         if (!p || !p->get_cd)
1005                 return -ENOSYS;
1006         else
1007                 return p->get_cd(host->pd);
1008 }
1009
1010 static struct mmc_host_ops sh_mmcif_ops = {
1011         .request        = sh_mmcif_request,
1012         .set_ios        = sh_mmcif_set_ios,
1013         .get_cd         = sh_mmcif_get_cd,
1014 };
1015
1016 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1017 {
1018         struct mmc_command *cmd = host->mrq->cmd;
1019         struct mmc_data *data = host->mrq->data;
1020         long time;
1021
1022         if (host->sd_error) {
1023                 switch (cmd->opcode) {
1024                 case MMC_ALL_SEND_CID:
1025                 case MMC_SELECT_CARD:
1026                 case MMC_APP_CMD:
1027                         cmd->error = -ETIMEDOUT;
1028                         host->sd_error = false;
1029                         break;
1030                 default:
1031                         cmd->error = sh_mmcif_error_manage(host);
1032                         dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1033                                 cmd->opcode, cmd->error);
1034                         break;
1035                 }
1036                 return false;
1037         }
1038         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1039                 cmd->error = 0;
1040                 return false;
1041         }
1042
1043         sh_mmcif_get_response(host, cmd);
1044
1045         if (!data)
1046                 return false;
1047
1048         if (data->flags & MMC_DATA_READ) {
1049                 if (host->chan_rx)
1050                         sh_mmcif_start_dma_rx(host);
1051         } else {
1052                 if (host->chan_tx)
1053                         sh_mmcif_start_dma_tx(host);
1054         }
1055
1056         if (!host->dma_active) {
1057                 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1058                 if (!data->error)
1059                         return true;
1060                 return false;
1061         }
1062
1063         /* Running in the IRQ thread, can sleep */
1064         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1065                                                          host->timeout);
1066         if (host->sd_error) {
1067                 dev_err(host->mmc->parent,
1068                         "Error IRQ while waiting for DMA completion!\n");
1069                 /* Woken up by an error IRQ: abort DMA */
1070                 if (data->flags & MMC_DATA_READ)
1071                         dmaengine_terminate_all(host->chan_rx);
1072                 else
1073                         dmaengine_terminate_all(host->chan_tx);
1074                 data->error = sh_mmcif_error_manage(host);
1075         } else if (!time) {
1076                 data->error = -ETIMEDOUT;
1077         } else if (time < 0) {
1078                 data->error = time;
1079         }
1080         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1081                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1082         host->dma_active = false;
1083
1084         if (data->error)
1085                 data->bytes_xfered = 0;
1086
1087         return false;
1088 }
1089
1090 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1091 {
1092         struct sh_mmcif_host *host = dev_id;
1093         struct mmc_request *mrq = host->mrq;
1094         struct mmc_data *data = mrq->data;
1095
1096         cancel_delayed_work_sync(&host->timeout_work);
1097
1098         /*
1099          * All handlers return true, if processing continues, and false, if the
1100          * request has to be completed - successfully or not
1101          */
1102         switch (host->wait_for) {
1103         case MMCIF_WAIT_FOR_REQUEST:
1104                 /* We're too late, the timeout has already kicked in */
1105                 return IRQ_HANDLED;
1106         case MMCIF_WAIT_FOR_CMD:
1107                 if (sh_mmcif_end_cmd(host))
1108                         /* Wait for data */
1109                         return IRQ_HANDLED;
1110                 break;
1111         case MMCIF_WAIT_FOR_MREAD:
1112                 if (sh_mmcif_mread_block(host))
1113                         /* Wait for more data */
1114                         return IRQ_HANDLED;
1115                 break;
1116         case MMCIF_WAIT_FOR_READ:
1117                 if (sh_mmcif_read_block(host))
1118                         /* Wait for data end */
1119                         return IRQ_HANDLED;
1120                 break;
1121         case MMCIF_WAIT_FOR_MWRITE:
1122                 if (sh_mmcif_mwrite_block(host))
1123                         /* Wait data to write */
1124                         return IRQ_HANDLED;
1125                 break;
1126         case MMCIF_WAIT_FOR_WRITE:
1127                 if (sh_mmcif_write_block(host))
1128                         /* Wait for data end */
1129                         return IRQ_HANDLED;
1130                 break;
1131         case MMCIF_WAIT_FOR_STOP:
1132                 if (host->sd_error) {
1133                         mrq->stop->error = sh_mmcif_error_manage(host);
1134                         break;
1135                 }
1136                 sh_mmcif_get_cmd12response(host, mrq->stop);
1137                 mrq->stop->error = 0;
1138                 break;
1139         case MMCIF_WAIT_FOR_READ_END:
1140         case MMCIF_WAIT_FOR_WRITE_END:
1141                 if (host->sd_error)
1142                         data->error = sh_mmcif_error_manage(host);
1143                 break;
1144         default:
1145                 BUG();
1146         }
1147
1148         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1149                 if (!mrq->cmd->error && data && !data->error)
1150                         data->bytes_xfered =
1151                                 data->blocks * data->blksz;
1152
1153                 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1154                         sh_mmcif_stop_cmd(host, mrq);
1155                         if (!mrq->stop->error)
1156                                 return IRQ_HANDLED;
1157                 }
1158         }
1159
1160         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1161         host->state = STATE_IDLE;
1162         host->mrq = NULL;
1163         mmc_request_done(host->mmc, mrq);
1164
1165         return IRQ_HANDLED;
1166 }
1167
1168 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1169 {
1170         struct sh_mmcif_host *host = dev_id;
1171         u32 state;
1172         int err = 0;
1173
1174         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1175
1176         if (state & INT_ERR_STS) {
1177                 /* error interrupts - process first */
1178                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1179                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1180                 err = 1;
1181         } else if (state & INT_RBSYE) {
1182                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1183                                 ~(INT_RBSYE | INT_CRSPE));
1184                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1185         } else if (state & INT_CRSPE) {
1186                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
1187                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1188         } else if (state & INT_BUFREN) {
1189                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
1190                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1191         } else if (state & INT_BUFWEN) {
1192                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
1193                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1194         } else if (state & INT_CMD12DRE) {
1195                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1196                         ~(INT_CMD12DRE | INT_CMD12RBE |
1197                           INT_CMD12CRE | INT_BUFRE));
1198                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1199         } else if (state & INT_BUFRE) {
1200                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
1201                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1202         } else if (state & INT_DTRANE) {
1203                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
1204                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1205         } else if (state & INT_CMD12RBE) {
1206                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1207                                 ~(INT_CMD12RBE | INT_CMD12CRE));
1208                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
1209         } else {
1210                 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
1211                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1212                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1213                 err = 1;
1214         }
1215         if (err) {
1216                 host->sd_error = true;
1217                 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
1218         }
1219         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1220                 if (!host->dma_active)
1221                         return IRQ_WAKE_THREAD;
1222                 else if (host->sd_error)
1223                         mmcif_dma_complete(host);
1224         } else {
1225                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1226         }
1227
1228         return IRQ_HANDLED;
1229 }
1230
1231 static void mmcif_timeout_work(struct work_struct *work)
1232 {
1233         struct delayed_work *d = container_of(work, struct delayed_work, work);
1234         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1235         struct mmc_request *mrq = host->mrq;
1236
1237         if (host->dying)
1238                 /* Don't run after mmc_remove_host() */
1239                 return;
1240
1241         /*
1242          * Handle races with cancel_delayed_work(), unless
1243          * cancel_delayed_work_sync() is used
1244          */
1245         switch (host->wait_for) {
1246         case MMCIF_WAIT_FOR_CMD:
1247                 mrq->cmd->error = sh_mmcif_error_manage(host);
1248                 break;
1249         case MMCIF_WAIT_FOR_STOP:
1250                 mrq->stop->error = sh_mmcif_error_manage(host);
1251                 break;
1252         case MMCIF_WAIT_FOR_MREAD:
1253         case MMCIF_WAIT_FOR_MWRITE:
1254         case MMCIF_WAIT_FOR_READ:
1255         case MMCIF_WAIT_FOR_WRITE:
1256         case MMCIF_WAIT_FOR_READ_END:
1257         case MMCIF_WAIT_FOR_WRITE_END:
1258                 mrq->data->error = sh_mmcif_error_manage(host);
1259                 break;
1260         default:
1261                 BUG();
1262         }
1263
1264         host->state = STATE_IDLE;
1265         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1266         host->mrq = NULL;
1267         mmc_request_done(host->mmc, mrq);
1268 }
1269
1270 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1271 {
1272         struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1273         struct mmc_host *mmc = host->mmc;
1274
1275         mmc_regulator_get_supply(mmc);
1276
1277         if (!pd)
1278                 return;
1279
1280         if (!mmc->ocr_avail)
1281                 mmc->ocr_avail = pd->ocr;
1282         else if (pd->ocr)
1283                 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1284 }
1285
1286 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1287 {
1288         int ret = 0, irq[2];
1289         struct mmc_host *mmc;
1290         struct sh_mmcif_host *host;
1291         struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
1292         struct resource *res;
1293         void __iomem *reg;
1294         char clk_name[8];
1295
1296         irq[0] = platform_get_irq(pdev, 0);
1297         irq[1] = platform_get_irq(pdev, 1);
1298         if (irq[0] < 0 || irq[1] < 0) {
1299                 dev_err(&pdev->dev, "Get irq error\n");
1300                 return -ENXIO;
1301         }
1302         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1303         if (!res) {
1304                 dev_err(&pdev->dev, "platform_get_resource error.\n");
1305                 return -ENXIO;
1306         }
1307         reg = ioremap(res->start, resource_size(res));
1308         if (!reg) {
1309                 dev_err(&pdev->dev, "ioremap error.\n");
1310                 return -ENOMEM;
1311         }
1312
1313         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1314         if (!mmc) {
1315                 ret = -ENOMEM;
1316                 goto ealloch;
1317         }
1318         host            = mmc_priv(mmc);
1319         host->mmc       = mmc;
1320         host->addr      = reg;
1321         host->timeout   = 1000;
1322
1323         host->pd = pdev;
1324
1325         spin_lock_init(&host->lock);
1326
1327         mmc->ops = &sh_mmcif_ops;
1328         sh_mmcif_init_ocr(host);
1329
1330         mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1331         if (pd && pd->caps)
1332                 mmc->caps |= pd->caps;
1333         mmc->max_segs = 32;
1334         mmc->max_blk_size = 512;
1335         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1336         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1337         mmc->max_seg_size = mmc->max_req_size;
1338
1339         platform_set_drvdata(pdev, host);
1340
1341         pm_runtime_enable(&pdev->dev);
1342         host->power = false;
1343
1344         snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1345         host->hclk = clk_get(&pdev->dev, clk_name);
1346         if (IS_ERR(host->hclk)) {
1347                 ret = PTR_ERR(host->hclk);
1348                 dev_err(&pdev->dev, "cannot get clock \"%s\": %d\n", clk_name, ret);
1349                 goto eclkget;
1350         }
1351         ret = sh_mmcif_clk_update(host);
1352         if (ret < 0)
1353                 goto eclkupdate;
1354
1355         ret = pm_runtime_resume(&pdev->dev);
1356         if (ret < 0)
1357                 goto eresume;
1358
1359         INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1360
1361         sh_mmcif_sync_reset(host);
1362         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1363
1364         ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
1365         if (ret) {
1366                 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1367                 goto ereqirq0;
1368         }
1369         ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
1370         if (ret) {
1371                 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1372                 goto ereqirq1;
1373         }
1374
1375         clk_disable(host->hclk);
1376         ret = mmc_add_host(mmc);
1377         if (ret < 0)
1378                 goto emmcaddh;
1379
1380         dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1381
1382         dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1383         dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1384                 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1385         return ret;
1386
1387 emmcaddh:
1388         free_irq(irq[1], host);
1389 ereqirq1:
1390         free_irq(irq[0], host);
1391 ereqirq0:
1392         pm_runtime_suspend(&pdev->dev);
1393 eresume:
1394         clk_disable(host->hclk);
1395 eclkupdate:
1396         clk_put(host->hclk);
1397 eclkget:
1398         pm_runtime_disable(&pdev->dev);
1399         mmc_free_host(mmc);
1400 ealloch:
1401         iounmap(reg);
1402         return ret;
1403 }
1404
1405 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1406 {
1407         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1408         int irq[2];
1409
1410         host->dying = true;
1411         clk_enable(host->hclk);
1412         pm_runtime_get_sync(&pdev->dev);
1413
1414         dev_pm_qos_hide_latency_limit(&pdev->dev);
1415
1416         mmc_remove_host(host->mmc);
1417         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1418
1419         /*
1420          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1421          * mmc_remove_host() call above. But swapping order doesn't help either
1422          * (a query on the linux-mmc mailing list didn't bring any replies).
1423          */
1424         cancel_delayed_work_sync(&host->timeout_work);
1425
1426         if (host->addr)
1427                 iounmap(host->addr);
1428
1429         irq[0] = platform_get_irq(pdev, 0);
1430         irq[1] = platform_get_irq(pdev, 1);
1431
1432         free_irq(irq[0], host);
1433         free_irq(irq[1], host);
1434
1435         platform_set_drvdata(pdev, NULL);
1436
1437         mmc_free_host(host->mmc);
1438         pm_runtime_put_sync(&pdev->dev);
1439         clk_disable(host->hclk);
1440         pm_runtime_disable(&pdev->dev);
1441
1442         return 0;
1443 }
1444
1445 #ifdef CONFIG_PM
1446 static int sh_mmcif_suspend(struct device *dev)
1447 {
1448         struct sh_mmcif_host *host = dev_get_drvdata(dev);
1449         int ret = mmc_suspend_host(host->mmc);
1450
1451         if (!ret)
1452                 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1453
1454         return ret;
1455 }
1456
1457 static int sh_mmcif_resume(struct device *dev)
1458 {
1459         struct sh_mmcif_host *host = dev_get_drvdata(dev);
1460
1461         return mmc_resume_host(host->mmc);
1462 }
1463 #else
1464 #define sh_mmcif_suspend        NULL
1465 #define sh_mmcif_resume         NULL
1466 #endif  /* CONFIG_PM */
1467
1468 static const struct of_device_id mmcif_of_match[] = {
1469         { .compatible = "renesas,sh-mmcif" },
1470         { }
1471 };
1472 MODULE_DEVICE_TABLE(of, mmcif_of_match);
1473
1474 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1475         .suspend = sh_mmcif_suspend,
1476         .resume = sh_mmcif_resume,
1477 };
1478
1479 static struct platform_driver sh_mmcif_driver = {
1480         .probe          = sh_mmcif_probe,
1481         .remove         = sh_mmcif_remove,
1482         .driver         = {
1483                 .name   = DRIVER_NAME,
1484                 .pm     = &sh_mmcif_dev_pm_ops,
1485                 .owner  = THIS_MODULE,
1486                 .of_match_table = mmcif_of_match,
1487         },
1488 };
1489
1490 module_platform_driver(sh_mmcif_driver);
1491
1492 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1493 MODULE_LICENSE("GPL");
1494 MODULE_ALIAS("platform:" DRIVER_NAME);
1495 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");