drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 /*
  20  * The MMCIF driver is now processing MMC requests asynchronously, according
  21  * to the Linux MMC API requirement.
  22  *
  23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
  24  * data, and optional stop. To achieve asynchronous processing each of these
  25  * stages is split into two halves: a top and a bottom half. The top half
  26  * initialises the hardware, installs a timeout handler to handle completion
  27  * timeouts, and returns. In case of the command stage this immediately returns
  28  * control to the caller, leaving all further processing to run asynchronously.
  29  * All further request processing is performed by the bottom halves.
  30  *
  31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
  32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
  33  * request- and stage-specific handler methods.
  34  *
  35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
  36  * invocation, or a timeout work run. In case of an error or a successful
  37  * processing completion, the MMC core is informed and the request processing is
  38  * finished. In case processing has to continue, i.e., if data has to be read
  39  * from or written to the card, or if a stop command has to be sent, the next
  40  * top half is called, which performs the necessary hardware handling and
  41  * reschedules the timeout work. This returns the driver state machine into the
  42  * bottom half waiting state.
  43  */
  44
  45 #include <linux/bitops.h>
  46 #include <linux/clk.h>
  47 #include <linux/completion.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/mmc/card.h>
  52 #include <linux/mmc/core.h>
  53 #include <linux/mmc/host.h>
  54 #include <linux/mmc/mmc.h>
  55 #include <linux/mmc/sdio.h>
  56 #include <linux/mmc/sh_mmcif.h>
  57 #include <linux/pagemap.h>
  58 #include <linux/platform_device.h>
  59 #include <linux/pm_qos.h>
  60 #include <linux/pm_runtime.h>
  61 #include <linux/spinlock.h>
  62 #include <linux/module.h>
  63
  64 #define DRIVER_NAME     "sh_mmcif"
  65 #define DRIVER_VERSION  "2010-04-28"
  66
  67 /* CE_CMD_SET */
  68 #define CMD_MASK                0x3f000000
  69 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  70 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  71 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  72 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  73 #define CMD_SET_CCSEN           (1 << 20)
  74 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  75 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  76 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  77 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  78 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  79 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  80 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  81 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  82 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  83 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  84 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  85 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  86 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  87 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  88 #define CMD_SET_CCSH            (1 << 5)
  89 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  90 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  91 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  92
  93 /* CE_CMD_CTRL */
  94 #define CMD_CTRL_BREAK          (1 << 0)
  95
  96 /* CE_BLOCK_SET */
  97 #define BLOCK_SIZE_MASK         0x0000ffff
  98
  99 /* CE_INT */
 100 #define INT_CCSDE               (1 << 29)
 101 #define INT_CMD12DRE            (1 << 26)
 102 #define INT_CMD12RBE            (1 << 25)
 103 #define INT_CMD12CRE            (1 << 24)
 104 #define INT_DTRANE              (1 << 23)
 105 #define INT_BUFRE               (1 << 22)
 106 #define INT_BUFWEN              (1 << 21)
 107 #define INT_BUFREN              (1 << 20)
 108 #define INT_CCSRCV              (1 << 19)
 109 #define INT_RBSYE               (1 << 17)
 110 #define INT_CRSPE               (1 << 16)
 111 #define INT_CMDVIO              (1 << 15)
 112 #define INT_BUFVIO              (1 << 14)
 113 #define INT_WDATERR             (1 << 11)
 114 #define INT_RDATERR             (1 << 10)
 115 #define INT_RIDXERR             (1 << 9)
 116 #define INT_RSPERR              (1 << 8)
 117 #define INT_CCSTO               (1 << 5)
 118 #define INT_CRCSTO              (1 << 4)
 119 #define INT_WDATTO              (1 << 3)
 120 #define INT_RDATTO              (1 << 2)
 121 #define INT_RBSYTO              (1 << 1)
 122 #define INT_RSPTO               (1 << 0)
 123 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 124                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 125                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 126                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 127
 128 /* CE_INT_MASK */
 129 #define MASK_ALL                0x00000000
 130 #define MASK_MCCSDE             (1 << 29)
 131 #define MASK_MCMD12DRE          (1 << 26)
 132 #define MASK_MCMD12RBE          (1 << 25)
 133 #define MASK_MCMD12CRE          (1 << 24)
 134 #define MASK_MDTRANE            (1 << 23)
 135 #define MASK_MBUFRE             (1 << 22)
 136 #define MASK_MBUFWEN            (1 << 21)
 137 #define MASK_MBUFREN            (1 << 20)
 138 #define MASK_MCCSRCV            (1 << 19)
 139 #define MASK_MRBSYE             (1 << 17)
 140 #define MASK_MCRSPE             (1 << 16)
 141 #define MASK_MCMDVIO            (1 << 15)
 142 #define MASK_MBUFVIO            (1 << 14)
 143 #define MASK_MWDATERR           (1 << 11)
 144 #define MASK_MRDATERR           (1 << 10)
 145 #define MASK_MRIDXERR           (1 << 9)
 146 #define MASK_MRSPERR            (1 << 8)
 147 #define MASK_MCCSTO             (1 << 5)
 148 #define MASK_MCRCSTO            (1 << 4)
 149 #define MASK_MWDATTO            (1 << 3)
 150 #define MASK_MRDATTO            (1 << 2)
 151 #define MASK_MRBSYTO            (1 << 1)
 152 #define MASK_MRSPTO             (1 << 0)
 153
 154 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 155                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 156                                  MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
 157                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 158
 159 /* CE_HOST_STS1 */
 160 #define STS1_CMDSEQ             (1 << 31)
 161
 162 /* CE_HOST_STS2 */
 163 #define STS2_CRCSTE             (1 << 31)
 164 #define STS2_CRC16E             (1 << 30)
 165 #define STS2_AC12CRCE           (1 << 29)
 166 #define STS2_RSPCRC7E           (1 << 28)
 167 #define STS2_CRCSTEBE           (1 << 27)
 168 #define STS2_RDATEBE            (1 << 26)
 169 #define STS2_AC12REBE           (1 << 25)
 170 #define STS2_RSPEBE             (1 << 24)
 171 #define STS2_AC12IDXE           (1 << 23)
 172 #define STS2_RSPIDXE            (1 << 22)
 173 #define STS2_CCSTO              (1 << 15)
 174 #define STS2_RDATTO             (1 << 14)
 175 #define STS2_DATBSYTO           (1 << 13)
 176 #define STS2_CRCSTTO            (1 << 12)
 177 #define STS2_AC12BSYTO          (1 << 11)
 178 #define STS2_RSPBSYTO           (1 << 10)
 179 #define STS2_AC12RSPTO          (1 << 9)
 180 #define STS2_RSPTO              (1 << 8)
 181 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 182                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 183 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 184                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 185                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 186                                  STS2_AC12RSPTO | STS2_RSPTO)
 187
 188 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 189 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 190 #define CLKDEV_INIT             400000   /* 400 KHz */
 191
 192 enum mmcif_state {
 193         STATE_IDLE,
 194         STATE_REQUEST,
 195         STATE_IOS,
 196 };
 197
 198 enum mmcif_wait_for {
 199         MMCIF_WAIT_FOR_REQUEST,
 200         MMCIF_WAIT_FOR_CMD,
 201         MMCIF_WAIT_FOR_MREAD,
 202         MMCIF_WAIT_FOR_MWRITE,
 203         MMCIF_WAIT_FOR_READ,
 204         MMCIF_WAIT_FOR_WRITE,
 205         MMCIF_WAIT_FOR_READ_END,
 206         MMCIF_WAIT_FOR_WRITE_END,
 207         MMCIF_WAIT_FOR_STOP,
 208 };
 209
 210 struct sh_mmcif_host {
 211         struct mmc_host *mmc;
 212         struct mmc_request *mrq;
 213         struct platform_device *pd;
 214         struct sh_dmae_slave dma_slave_tx;
 215         struct sh_dmae_slave dma_slave_rx;
 216         struct clk *hclk;
 217         unsigned int clk;
 218         int bus_width;
 219         bool sd_error;
 220         bool dying;
 221         long timeout;
 222         void __iomem *addr;
 223         u32 *pio_ptr;
 224         spinlock_t lock;                /* protect sh_mmcif_host::state */
 225         enum mmcif_state state;
 226         enum mmcif_wait_for wait_for;
 227         struct delayed_work timeout_work;
 228         size_t blocksize;
 229         int sg_idx;
 230         int sg_blkidx;
 231         bool power;
 232         bool card_present;
 233
 234         /* DMA support */
 235         struct dma_chan         *chan_rx;
 236         struct dma_chan         *chan_tx;
 237         struct completion       dma_complete;
 238         bool                    dma_active;
 239 };
 240
 241 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 242                                         unsigned int reg, u32 val)
 243 {
 244         writel(val | readl(host->addr + reg), host->addr + reg);
 245 }
 246
 247 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 248                                         unsigned int reg, u32 val)
 249 {
 250         writel(~val & readl(host->addr + reg), host->addr + reg);
 251 }
 252
 253 static void mmcif_dma_complete(void *arg)
 254 {
 255         struct sh_mmcif_host *host = arg;
 256         struct mmc_data *data = host->mrq->data;
 257
 258         dev_dbg(&host->pd->dev, "Command completed\n");
 259
 260         if (WARN(!data, "%s: NULL data in DMA completion!\n",
 261                  dev_name(&host->pd->dev)))
 262                 return;
 263
 264         if (data->flags & MMC_DATA_READ)
 265                 dma_unmap_sg(host->chan_rx->device->dev,
 266                              data->sg, data->sg_len,
 267                              DMA_FROM_DEVICE);
 268         else
 269                 dma_unmap_sg(host->chan_tx->device->dev,
 270                              data->sg, data->sg_len,
 271                              DMA_TO_DEVICE);
 272
 273         complete(&host->dma_complete);
 274 }
 275
 276 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 277 {
 278         struct mmc_data *data = host->mrq->data;
 279         struct scatterlist *sg = data->sg;
 280         struct dma_async_tx_descriptor *desc = NULL;
 281         struct dma_chan *chan = host->chan_rx;
 282         dma_cookie_t cookie = -EINVAL;
 283         int ret;
 284
 285         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 286                          DMA_FROM_DEVICE);
 287         if (ret > 0) {
 288                 host->dma_active = true;
 289                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 290                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 291         }
 292
 293         if (desc) {
 294                 desc->callback = mmcif_dma_complete;
 295                 desc->callback_param = host;
 296                 cookie = dmaengine_submit(desc);
 297                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 298                 dma_async_issue_pending(chan);
 299         }
 300         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 301                 __func__, data->sg_len, ret, cookie);
 302
 303         if (!desc) {
 304                 /* DMA failed, fall back to PIO */
 305                 if (ret >= 0)
 306                         ret = -EIO;
 307                 host->chan_rx = NULL;
 308                 host->dma_active = false;
 309                 dma_release_channel(chan);
 310                 /* Free the Tx channel too */
 311                 chan = host->chan_tx;
 312                 if (chan) {
 313                         host->chan_tx = NULL;
 314                         dma_release_channel(chan);
 315                 }
 316                 dev_warn(&host->pd->dev,
 317                          "DMA failed: %d, falling back to PIO\n", ret);
 318                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 319         }
 320
 321         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 322                 desc, cookie, data->sg_len);
 323 }
 324
 325 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 326 {
 327         struct mmc_data *data = host->mrq->data;
 328         struct scatterlist *sg = data->sg;
 329         struct dma_async_tx_descriptor *desc = NULL;
 330         struct dma_chan *chan = host->chan_tx;
 331         dma_cookie_t cookie = -EINVAL;
 332         int ret;
 333
 334         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 335                          DMA_TO_DEVICE);
 336         if (ret > 0) {
 337                 host->dma_active = true;
 338                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 339                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 340         }
 341
 342         if (desc) {
 343                 desc->callback = mmcif_dma_complete;
 344                 desc->callback_param = host;
 345                 cookie = dmaengine_submit(desc);
 346                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 347                 dma_async_issue_pending(chan);
 348         }
 349         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 350                 __func__, data->sg_len, ret, cookie);
 351
 352         if (!desc) {
 353                 /* DMA failed, fall back to PIO */
 354                 if (ret >= 0)
 355                         ret = -EIO;
 356                 host->chan_tx = NULL;
 357                 host->dma_active = false;
 358                 dma_release_channel(chan);
 359                 /* Free the Rx channel too */
 360                 chan = host->chan_rx;
 361                 if (chan) {
 362                         host->chan_rx = NULL;
 363                         dma_release_channel(chan);
 364                 }
 365                 dev_warn(&host->pd->dev,
 366                          "DMA failed: %d, falling back to PIO\n", ret);
 367                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 368         }
 369
 370         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 371                 desc, cookie);
 372 }
 373
 374 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
 375 {
 376         dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
 377         chan->private = arg;
 378         return true;
 379 }
 380
 381 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 382                                  struct sh_mmcif_plat_data *pdata)
 383 {
 384         struct sh_dmae_slave *tx, *rx;
 385         host->dma_active = false;
 386
 387         /* We can only either use DMA for both Tx and Rx or not use it at all */
 388         tx = &host->dma_slave_tx;
 389         tx->shdma_slave.slave_id = pdata->slave_id_tx;
 390         rx = &host->dma_slave_rx;
 391         rx->shdma_slave.slave_id = pdata->slave_id_rx;
 392
 393         if (tx->shdma_slave.slave_id > 0 && rx->shdma_slave.slave_id > 0) {
 394                 dma_cap_mask_t mask;
 395
 396                 dma_cap_zero(mask);
 397                 dma_cap_set(DMA_SLAVE, mask);
 398
 399                 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter,
 400                                                     &tx->shdma_slave);
 401                 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
 402                         host->chan_tx);
 403
 404                 if (!host->chan_tx)
 405                         return;
 406
 407                 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter,
 408                                                     &rx->shdma_slave);
 409                 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
 410                         host->chan_rx);
 411
 412                 if (!host->chan_rx) {
 413                         dma_release_channel(host->chan_tx);
 414                         host->chan_tx = NULL;
 415                         return;
 416                 }
 417
 418                 init_completion(&host->dma_complete);
 419         }
 420 }
 421
 422 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 423 {
 424         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 425         /* Descriptors are freed automatically */
 426         if (host->chan_tx) {
 427                 struct dma_chan *chan = host->chan_tx;
 428                 host->chan_tx = NULL;
 429                 dma_release_channel(chan);
 430         }
 431         if (host->chan_rx) {
 432                 struct dma_chan *chan = host->chan_rx;
 433                 host->chan_rx = NULL;
 434                 dma_release_channel(chan);
 435         }
 436
 437         host->dma_active = false;
 438 }
 439
 440 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 441 {
 442         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 443
 444         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 445         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 446
 447         if (!clk)
 448                 return;
 449         if (p->sup_pclk && clk == host->clk)
 450                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 451         else
 452                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 453                                 ((fls(DIV_ROUND_UP(host->clk,
 454                                                    clk) - 1) - 1) << 16));
 455
 456         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 457 }
 458
 459 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 460 {
 461         u32 tmp;
 462
 463         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 464
 465         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 466         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 467         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 468                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 469         /* byte swap on */
 470         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 471 }
 472
 473 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 474 {
 475         u32 state1, state2;
 476         int ret, timeout;
 477
 478         host->sd_error = false;
 479
 480         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 481         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 482         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 483         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 484
 485         if (state1 & STS1_CMDSEQ) {
 486                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 487                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 488                 for (timeout = 10000000; timeout; timeout--) {
 489                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 490                               & STS1_CMDSEQ))
 491                                 break;
 492                         mdelay(1);
 493                 }
 494                 if (!timeout) {
 495                         dev_err(&host->pd->dev,
 496                                 "Forced end of command sequence timeout err\n");
 497                         return -EIO;
 498                 }
 499                 sh_mmcif_sync_reset(host);
 500                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 501                 return -EIO;
 502         }
 503
 504         if (state2 & STS2_CRC_ERR) {
 505                 dev_dbg(&host->pd->dev, ": CRC error\n");
 506                 ret = -EIO;
 507         } else if (state2 & STS2_TIMEOUT_ERR) {
 508                 dev_dbg(&host->pd->dev, ": Timeout\n");
 509                 ret = -ETIMEDOUT;
 510         } else {
 511                 dev_dbg(&host->pd->dev, ": End/Index error\n");
 512                 ret = -EIO;
 513         }
 514         return ret;
 515 }
 516
 517 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
 518 {
 519         struct mmc_data *data = host->mrq->data;
 520
 521         host->sg_blkidx += host->blocksize;
 522
 523         /* data->sg->length must be a multiple of host->blocksize? */
 524         BUG_ON(host->sg_blkidx > data->sg->length);
 525
 526         if (host->sg_blkidx == data->sg->length) {
 527                 host->sg_blkidx = 0;
 528                 if (++host->sg_idx < data->sg_len)
 529                         host->pio_ptr = sg_virt(++data->sg);
 530         } else {
 531                 host->pio_ptr = p;
 532         }
 533
 534         if (host->sg_idx == data->sg_len)
 535                 return false;
 536
 537         return true;
 538 }
 539
 540 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
 541                                  struct mmc_request *mrq)
 542 {
 543         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 544                            BLOCK_SIZE_MASK) + 3;
 545
 546         host->wait_for = MMCIF_WAIT_FOR_READ;
 547         schedule_delayed_work(&host->timeout_work, host->timeout);
 548
 549         /* buf read enable */
 550         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 551 }
 552
 553 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
 554 {
 555         struct mmc_data *data = host->mrq->data;
 556         u32 *p = sg_virt(data->sg);
 557         int i;
 558
 559         if (host->sd_error) {
 560                 data->error = sh_mmcif_error_manage(host);
 561                 return false;
 562         }
 563
 564         for (i = 0; i < host->blocksize / 4; i++)
 565                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 566
 567         /* buffer read end */
 568         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 569         host->wait_for = MMCIF_WAIT_FOR_READ_END;
 570
 571         return true;
 572 }
 573
 574 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
 575                                 struct mmc_request *mrq)
 576 {
 577         struct mmc_data *data = mrq->data;
 578
 579         if (!data->sg_len || !data->sg->length)
 580                 return;
 581
 582         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 583                 BLOCK_SIZE_MASK;
 584
 585         host->wait_for = MMCIF_WAIT_FOR_MREAD;
 586         host->sg_idx = 0;
 587         host->sg_blkidx = 0;
 588         host->pio_ptr = sg_virt(data->sg);
 589         schedule_delayed_work(&host->timeout_work, host->timeout);
 590         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 591 }
 592
 593 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
 594 {
 595         struct mmc_data *data = host->mrq->data;
 596         u32 *p = host->pio_ptr;
 597         int i;
 598
 599         if (host->sd_error) {
 600                 data->error = sh_mmcif_error_manage(host);
 601                 return false;
 602         }
 603
 604         BUG_ON(!data->sg->length);
 605
 606         for (i = 0; i < host->blocksize / 4; i++)
 607                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 608
 609         if (!sh_mmcif_next_block(host, p))
 610                 return false;
 611
 612         schedule_delayed_work(&host->timeout_work, host->timeout);
 613         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 614
 615         return true;
 616 }
 617
 618 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
 619                                         struct mmc_request *mrq)
 620 {
 621         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 622                            BLOCK_SIZE_MASK) + 3;
 623
 624         host->wait_for = MMCIF_WAIT_FOR_WRITE;
 625         schedule_delayed_work(&host->timeout_work, host->timeout);
 626
 627         /* buf write enable */
 628         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 629 }
 630
 631 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
 632 {
 633         struct mmc_data *data = host->mrq->data;
 634         u32 *p = sg_virt(data->sg);
 635         int i;
 636
 637         if (host->sd_error) {
 638                 data->error = sh_mmcif_error_manage(host);
 639                 return false;
 640         }
 641
 642         for (i = 0; i < host->blocksize / 4; i++)
 643                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 644
 645         /* buffer write end */
 646         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 647         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
 648
 649         return true;
 650 }
 651
 652 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
 653                                 struct mmc_request *mrq)
 654 {
 655         struct mmc_data *data = mrq->data;
 656
 657         if (!data->sg_len || !data->sg->length)
 658                 return;
 659
 660         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 661                 BLOCK_SIZE_MASK;
 662
 663         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
 664         host->sg_idx = 0;
 665         host->sg_blkidx = 0;
 666         host->pio_ptr = sg_virt(data->sg);
 667         schedule_delayed_work(&host->timeout_work, host->timeout);
 668         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 669 }
 670
 671 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
 672 {
 673         struct mmc_data *data = host->mrq->data;
 674         u32 *p = host->pio_ptr;
 675         int i;
 676
 677         if (host->sd_error) {
 678                 data->error = sh_mmcif_error_manage(host);
 679                 return false;
 680         }
 681
 682         BUG_ON(!data->sg->length);
 683
 684         for (i = 0; i < host->blocksize / 4; i++)
 685                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 686
 687         if (!sh_mmcif_next_block(host, p))
 688                 return false;
 689
 690         schedule_delayed_work(&host->timeout_work, host->timeout);
 691         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 692
 693         return true;
 694 }
 695
 696 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 697                                                 struct mmc_command *cmd)
 698 {
 699         if (cmd->flags & MMC_RSP_136) {
 700                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 701                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 702                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 703                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 704         } else
 705                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 706 }
 707
 708 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 709                                                 struct mmc_command *cmd)
 710 {
 711         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 712 }
 713
 714 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 715                             struct mmc_request *mrq)
 716 {
 717         struct mmc_data *data = mrq->data;
 718         struct mmc_command *cmd = mrq->cmd;
 719         u32 opc = cmd->opcode;
 720         u32 tmp = 0;
 721
 722         /* Response Type check */
 723         switch (mmc_resp_type(cmd)) {
 724         case MMC_RSP_NONE:
 725                 tmp |= CMD_SET_RTYP_NO;
 726                 break;
 727         case MMC_RSP_R1:
 728         case MMC_RSP_R1B:
 729         case MMC_RSP_R3:
 730                 tmp |= CMD_SET_RTYP_6B;
 731                 break;
 732         case MMC_RSP_R2:
 733                 tmp |= CMD_SET_RTYP_17B;
 734                 break;
 735         default:
 736                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 737                 break;
 738         }
 739         switch (opc) {
 740         /* RBSY */
 741         case MMC_SWITCH:
 742         case MMC_STOP_TRANSMISSION:
 743         case MMC_SET_WRITE_PROT:
 744         case MMC_CLR_WRITE_PROT:
 745         case MMC_ERASE:
 746                 tmp |= CMD_SET_RBSY;
 747                 break;
 748         }
 749         /* WDAT / DATW */
 750         if (data) {
 751                 tmp |= CMD_SET_WDAT;
 752                 switch (host->bus_width) {
 753                 case MMC_BUS_WIDTH_1:
 754                         tmp |= CMD_SET_DATW_1;
 755                         break;
 756                 case MMC_BUS_WIDTH_4:
 757                         tmp |= CMD_SET_DATW_4;
 758                         break;
 759                 case MMC_BUS_WIDTH_8:
 760                         tmp |= CMD_SET_DATW_8;
 761                         break;
 762                 default:
 763                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 764                         break;
 765                 }
 766         }
 767         /* DWEN */
 768         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 769                 tmp |= CMD_SET_DWEN;
 770         /* CMLTE/CMD12EN */
 771         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 772                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 773                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 774                                 data->blocks << 16);
 775         }
 776         /* RIDXC[1:0] check bits */
 777         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 778             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 779                 tmp |= CMD_SET_RIDXC_BITS;
 780         /* RCRC7C[1:0] check bits */
 781         if (opc == MMC_SEND_OP_COND)
 782                 tmp |= CMD_SET_CRC7C_BITS;
 783         /* RCRC7C[1:0] internal CRC7 */
 784         if (opc == MMC_ALL_SEND_CID ||
 785                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 786                 tmp |= CMD_SET_CRC7C_INTERNAL;
 787
 788         return (opc << 24) | tmp;
 789 }
 790
 791 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 792                                struct mmc_request *mrq, u32 opc)
 793 {
 794         switch (opc) {
 795         case MMC_READ_MULTIPLE_BLOCK:
 796                 sh_mmcif_multi_read(host, mrq);
 797                 return 0;
 798         case MMC_WRITE_MULTIPLE_BLOCK:
 799                 sh_mmcif_multi_write(host, mrq);
 800                 return 0;
 801         case MMC_WRITE_BLOCK:
 802                 sh_mmcif_single_write(host, mrq);
 803                 return 0;
 804         case MMC_READ_SINGLE_BLOCK:
 805         case MMC_SEND_EXT_CSD:
 806                 sh_mmcif_single_read(host, mrq);
 807                 return 0;
 808         default:
 809                 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
 810                 return -EINVAL;
 811         }
 812 }
 813
 814 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 815                                struct mmc_request *mrq)
 816 {
 817         struct mmc_command *cmd = mrq->cmd;
 818         u32 opc = cmd->opcode;
 819         u32 mask;
 820
 821         switch (opc) {
 822         /* response busy check */
 823         case MMC_SWITCH:
 824         case MMC_STOP_TRANSMISSION:
 825         case MMC_SET_WRITE_PROT:
 826         case MMC_CLR_WRITE_PROT:
 827         case MMC_ERASE:
 828                 mask = MASK_START_CMD | MASK_MRBSYE;
 829                 break;
 830         default:
 831                 mask = MASK_START_CMD | MASK_MCRSPE;
 832                 break;
 833         }
 834
 835         if (mrq->data) {
 836                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 837                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 838                                 mrq->data->blksz);
 839         }
 840         opc = sh_mmcif_set_cmd(host, mrq);
 841
 842         sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 843         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 844         /* set arg */
 845         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 846         /* set cmd */
 847         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 848
 849         host->wait_for = MMCIF_WAIT_FOR_CMD;
 850         schedule_delayed_work(&host->timeout_work, host->timeout);
 851 }
 852
 853 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 854                               struct mmc_request *mrq)
 855 {
 856         switch (mrq->cmd->opcode) {
 857         case MMC_READ_MULTIPLE_BLOCK:
 858                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 859                 break;
 860         case MMC_WRITE_MULTIPLE_BLOCK:
 861                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 862                 break;
 863         default:
 864                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 865                 mrq->stop->error = sh_mmcif_error_manage(host);
 866                 return;
 867         }
 868
 869         host->wait_for = MMCIF_WAIT_FOR_STOP;
 870         schedule_delayed_work(&host->timeout_work, host->timeout);
 871 }
 872
 873 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 874 {
 875         struct sh_mmcif_host *host = mmc_priv(mmc);
 876         unsigned long flags;
 877
 878         spin_lock_irqsave(&host->lock, flags);
 879         if (host->state != STATE_IDLE) {
 880                 spin_unlock_irqrestore(&host->lock, flags);
 881                 mrq->cmd->error = -EAGAIN;
 882                 mmc_request_done(mmc, mrq);
 883                 return;
 884         }
 885
 886         host->state = STATE_REQUEST;
 887         spin_unlock_irqrestore(&host->lock, flags);
 888
 889         switch (mrq->cmd->opcode) {
 890         /* MMCIF does not support SD/SDIO command */
 891         case SD_IO_SEND_OP_COND:
 892         case MMC_APP_CMD:
 893                 host->state = STATE_IDLE;
 894                 mrq->cmd->error = -ETIMEDOUT;
 895                 mmc_request_done(mmc, mrq);
 896                 return;
 897         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 898                 if (!mrq->data) {
 899                         /* send_if_cond cmd (not support) */
 900                         host->state = STATE_IDLE;
 901                         mrq->cmd->error = -ETIMEDOUT;
 902                         mmc_request_done(mmc, mrq);
 903                         return;
 904                 }
 905                 break;
 906         default:
 907                 break;
 908         }
 909
 910         host->mrq = mrq;
 911
 912         sh_mmcif_start_cmd(host, mrq);
 913 }
 914
 915 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 916 {
 917         struct sh_mmcif_host *host = mmc_priv(mmc);
 918         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 919         unsigned long flags;
 920
 921         spin_lock_irqsave(&host->lock, flags);
 922         if (host->state != STATE_IDLE) {
 923                 spin_unlock_irqrestore(&host->lock, flags);
 924                 return;
 925         }
 926
 927         host->state = STATE_IOS;
 928         spin_unlock_irqrestore(&host->lock, flags);
 929
 930         if (ios->power_mode == MMC_POWER_UP) {
 931                 if (!host->card_present) {
 932                         /* See if we also get DMA */
 933                         sh_mmcif_request_dma(host, host->pd->dev.platform_data);
 934                         host->card_present = true;
 935                 }
 936         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
 937                 /* clock stop */
 938                 sh_mmcif_clock_control(host, 0);
 939                 if (ios->power_mode == MMC_POWER_OFF) {
 940                         if (host->card_present) {
 941                                 sh_mmcif_release_dma(host);
 942                                 host->card_present = false;
 943                         }
 944                 }
 945                 if (host->power) {
 946                         pm_runtime_put(&host->pd->dev);
 947                         host->power = false;
 948                         if (p->down_pwr && ios->power_mode == MMC_POWER_OFF)
 949                                 p->down_pwr(host->pd);
 950                 }
 951                 host->state = STATE_IDLE;
 952                 return;
 953         }
 954
 955         if (ios->clock) {
 956                 if (!host->power) {
 957                         if (p->set_pwr)
 958                                 p->set_pwr(host->pd, ios->power_mode);
 959                         pm_runtime_get_sync(&host->pd->dev);
 960                         host->power = true;
 961                         sh_mmcif_sync_reset(host);
 962                 }
 963                 sh_mmcif_clock_control(host, ios->clock);
 964         }
 965
 966         host->bus_width = ios->bus_width;
 967         host->state = STATE_IDLE;
 968 }
 969
 970 static int sh_mmcif_get_cd(struct mmc_host *mmc)
 971 {
 972         struct sh_mmcif_host *host = mmc_priv(mmc);
 973         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 974
 975         if (!p->get_cd)
 976                 return -ENOSYS;
 977         else
 978                 return p->get_cd(host->pd);
 979 }
 980
 981 static struct mmc_host_ops sh_mmcif_ops = {
 982         .request        = sh_mmcif_request,
 983         .set_ios        = sh_mmcif_set_ios,
 984         .get_cd         = sh_mmcif_get_cd,
 985 };
 986
 987 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
 988 {
 989         struct mmc_command *cmd = host->mrq->cmd;
 990         struct mmc_data *data = host->mrq->data;
 991         long time;
 992
 993         if (host->sd_error) {
 994                 switch (cmd->opcode) {
 995                 case MMC_ALL_SEND_CID:
 996                 case MMC_SELECT_CARD:
 997                 case MMC_APP_CMD:
 998                         cmd->error = -ETIMEDOUT;
 999                         host->sd_error = false;
1000                         break;
1001                 default:
1002                         cmd->error = sh_mmcif_error_manage(host);
1003                         dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1004                                 cmd->opcode, cmd->error);
1005                         break;
1006                 }
1007                 return false;
1008         }
1009         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1010                 cmd->error = 0;
1011                 return false;
1012         }
1013
1014         sh_mmcif_get_response(host, cmd);
1015
1016         if (!data)
1017                 return false;
1018
1019         if (data->flags & MMC_DATA_READ) {
1020                 if (host->chan_rx)
1021                         sh_mmcif_start_dma_rx(host);
1022         } else {
1023                 if (host->chan_tx)
1024                         sh_mmcif_start_dma_tx(host);
1025         }
1026
1027         if (!host->dma_active) {
1028                 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1029                 if (!data->error)
1030                         return true;
1031                 return false;
1032         }
1033
1034         /* Running in the IRQ thread, can sleep */
1035         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1036                                                          host->timeout);
1037         if (host->sd_error) {
1038                 dev_err(host->mmc->parent,
1039                         "Error IRQ while waiting for DMA completion!\n");
1040                 /* Woken up by an error IRQ: abort DMA */
1041                 if (data->flags & MMC_DATA_READ)
1042                         dmaengine_terminate_all(host->chan_rx);
1043                 else
1044                         dmaengine_terminate_all(host->chan_tx);
1045                 data->error = sh_mmcif_error_manage(host);
1046         } else if (!time) {
1047                 data->error = -ETIMEDOUT;
1048         } else if (time < 0) {
1049                 data->error = time;
1050         }
1051         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1052                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1053         host->dma_active = false;
1054
1055         if (data->error)
1056                 data->bytes_xfered = 0;
1057
1058         return false;
1059 }
1060
1061 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1062 {
1063         struct sh_mmcif_host *host = dev_id;
1064         struct mmc_request *mrq = host->mrq;
1065         struct mmc_data *data = mrq->data;
1066
1067         cancel_delayed_work_sync(&host->timeout_work);
1068
1069         /*
1070          * All handlers return true, if processing continues, and false, if the
1071          * request has to be completed - successfully or not
1072          */
1073         switch (host->wait_for) {
1074         case MMCIF_WAIT_FOR_REQUEST:
1075                 /* We're too late, the timeout has already kicked in */
1076                 return IRQ_HANDLED;
1077         case MMCIF_WAIT_FOR_CMD:
1078                 if (sh_mmcif_end_cmd(host))
1079                         /* Wait for data */
1080                         return IRQ_HANDLED;
1081                 break;
1082         case MMCIF_WAIT_FOR_MREAD:
1083                 if (sh_mmcif_mread_block(host))
1084                         /* Wait for more data */
1085                         return IRQ_HANDLED;
1086                 break;
1087         case MMCIF_WAIT_FOR_READ:
1088                 if (sh_mmcif_read_block(host))
1089                         /* Wait for data end */
1090                         return IRQ_HANDLED;
1091                 break;
1092         case MMCIF_WAIT_FOR_MWRITE:
1093                 if (sh_mmcif_mwrite_block(host))
1094                         /* Wait data to write */
1095                         return IRQ_HANDLED;
1096                 break;
1097         case MMCIF_WAIT_FOR_WRITE:
1098                 if (sh_mmcif_write_block(host))
1099                         /* Wait for data end */
1100                         return IRQ_HANDLED;
1101                 break;
1102         case MMCIF_WAIT_FOR_STOP:
1103                 if (host->sd_error) {
1104                         mrq->stop->error = sh_mmcif_error_manage(host);
1105                         break;
1106                 }
1107                 sh_mmcif_get_cmd12response(host, mrq->stop);
1108                 mrq->stop->error = 0;
1109                 break;
1110         case MMCIF_WAIT_FOR_READ_END:
1111         case MMCIF_WAIT_FOR_WRITE_END:
1112                 if (host->sd_error)
1113                         data->error = sh_mmcif_error_manage(host);
1114                 break;
1115         default:
1116                 BUG();
1117         }
1118
1119         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1120                 if (!mrq->cmd->error && data && !data->error)
1121                         data->bytes_xfered =
1122                                 data->blocks * data->blksz;
1123
1124                 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1125                         sh_mmcif_stop_cmd(host, mrq);
1126                         if (!mrq->stop->error)
1127                                 return IRQ_HANDLED;
1128                 }
1129         }
1130
1131         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1132         host->state = STATE_IDLE;
1133         host->mrq = NULL;
1134         mmc_request_done(host->mmc, mrq);
1135
1136         return IRQ_HANDLED;
1137 }
1138
1139 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1140 {
1141         struct sh_mmcif_host *host = dev_id;
1142         u32 state;
1143         int err = 0;
1144
1145         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1146
1147         if (state & INT_ERR_STS) {
1148                 /* error interrupts - process first */
1149                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1150                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1151                 err = 1;
1152         } else if (state & INT_RBSYE) {
1153                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1154                                 ~(INT_RBSYE | INT_CRSPE));
1155                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1156         } else if (state & INT_CRSPE) {
1157                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
1158                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1159         } else if (state & INT_BUFREN) {
1160                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
1161                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1162         } else if (state & INT_BUFWEN) {
1163                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
1164                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1165         } else if (state & INT_CMD12DRE) {
1166                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1167                         ~(INT_CMD12DRE | INT_CMD12RBE |
1168                           INT_CMD12CRE | INT_BUFRE));
1169                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1170         } else if (state & INT_BUFRE) {
1171                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
1172                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1173         } else if (state & INT_DTRANE) {
1174                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
1175                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1176         } else if (state & INT_CMD12RBE) {
1177                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1178                                 ~(INT_CMD12RBE | INT_CMD12CRE));
1179                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
1180         } else {
1181                 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
1182                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1183                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1184                 err = 1;
1185         }
1186         if (err) {
1187                 host->sd_error = true;
1188                 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
1189         }
1190         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1191                 if (!host->dma_active)
1192                         return IRQ_WAKE_THREAD;
1193                 else if (host->sd_error)
1194                         mmcif_dma_complete(host);
1195         } else {
1196                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1197         }
1198
1199         return IRQ_HANDLED;
1200 }
1201
1202 static void mmcif_timeout_work(struct work_struct *work)
1203 {
1204         struct delayed_work *d = container_of(work, struct delayed_work, work);
1205         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1206         struct mmc_request *mrq = host->mrq;
1207
1208         if (host->dying)
1209                 /* Don't run after mmc_remove_host() */
1210                 return;
1211
1212         /*
1213          * Handle races with cancel_delayed_work(), unless
1214          * cancel_delayed_work_sync() is used
1215          */
1216         switch (host->wait_for) {
1217         case MMCIF_WAIT_FOR_CMD:
1218                 mrq->cmd->error = sh_mmcif_error_manage(host);
1219                 break;
1220         case MMCIF_WAIT_FOR_STOP:
1221                 mrq->stop->error = sh_mmcif_error_manage(host);
1222                 break;
1223         case MMCIF_WAIT_FOR_MREAD:
1224         case MMCIF_WAIT_FOR_MWRITE:
1225         case MMCIF_WAIT_FOR_READ:
1226         case MMCIF_WAIT_FOR_WRITE:
1227         case MMCIF_WAIT_FOR_READ_END:
1228         case MMCIF_WAIT_FOR_WRITE_END:
1229                 mrq->data->error = sh_mmcif_error_manage(host);
1230                 break;
1231         default:
1232                 BUG();
1233         }
1234
1235         host->state = STATE_IDLE;
1236         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1237         host->mrq = NULL;
1238         mmc_request_done(host->mmc, mrq);
1239 }
1240
1241 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1242 {
1243         int ret = 0, irq[2];
1244         struct mmc_host *mmc;
1245         struct sh_mmcif_host *host;
1246         struct sh_mmcif_plat_data *pd;
1247         struct resource *res;
1248         void __iomem *reg;
1249         char clk_name[8];
1250
1251         irq[0] = platform_get_irq(pdev, 0);
1252         irq[1] = platform_get_irq(pdev, 1);
1253         if (irq[0] < 0 || irq[1] < 0) {
1254                 dev_err(&pdev->dev, "Get irq error\n");
1255                 return -ENXIO;
1256         }
1257         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1258         if (!res) {
1259                 dev_err(&pdev->dev, "platform_get_resource error.\n");
1260                 return -ENXIO;
1261         }
1262         reg = ioremap(res->start, resource_size(res));
1263         if (!reg) {
1264                 dev_err(&pdev->dev, "ioremap error.\n");
1265                 return -ENOMEM;
1266         }
1267         pd = pdev->dev.platform_data;
1268         if (!pd) {
1269                 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
1270                 ret = -ENXIO;
1271                 goto clean_up;
1272         }
1273         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1274         if (!mmc) {
1275                 ret = -ENOMEM;
1276                 goto clean_up;
1277         }
1278         host            = mmc_priv(mmc);
1279         host->mmc       = mmc;
1280         host->addr      = reg;
1281         host->timeout   = 1000;
1282
1283         snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1284         host->hclk = clk_get(&pdev->dev, clk_name);
1285         if (IS_ERR(host->hclk)) {
1286                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1287                 ret = PTR_ERR(host->hclk);
1288                 goto clean_up1;
1289         }
1290         clk_enable(host->hclk);
1291         host->clk = clk_get_rate(host->hclk);
1292         host->pd = pdev;
1293
1294         spin_lock_init(&host->lock);
1295
1296         mmc->ops = &sh_mmcif_ops;
1297         mmc->f_max = host->clk / 2;
1298         mmc->f_min = host->clk / 512;
1299         if (pd->ocr)
1300                 mmc->ocr_avail = pd->ocr;
1301         mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1302         if (pd->caps)
1303                 mmc->caps |= pd->caps;
1304         mmc->max_segs = 32;
1305         mmc->max_blk_size = 512;
1306         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1307         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1308         mmc->max_seg_size = mmc->max_req_size;
1309
1310         sh_mmcif_sync_reset(host);
1311         platform_set_drvdata(pdev, host);
1312
1313         pm_runtime_enable(&pdev->dev);
1314         host->power = false;
1315
1316         ret = pm_runtime_resume(&pdev->dev);
1317         if (ret < 0)
1318                 goto clean_up2;
1319
1320         INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1321
1322         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1323
1324         ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
1325         if (ret) {
1326                 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1327                 goto clean_up3;
1328         }
1329         ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
1330         if (ret) {
1331                 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1332                 goto clean_up4;
1333         }
1334
1335         ret = mmc_add_host(mmc);
1336         if (ret < 0)
1337                 goto clean_up5;
1338
1339         dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1340
1341         dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1342         dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1343                 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1344         return ret;
1345
1346 clean_up5:
1347         free_irq(irq[1], host);
1348 clean_up4:
1349         free_irq(irq[0], host);
1350 clean_up3:
1351         pm_runtime_suspend(&pdev->dev);
1352 clean_up2:
1353         pm_runtime_disable(&pdev->dev);
1354         clk_disable(host->hclk);
1355 clean_up1:
1356         mmc_free_host(mmc);
1357 clean_up:
1358         if (reg)
1359                 iounmap(reg);
1360         return ret;
1361 }
1362
1363 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1364 {
1365         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1366         int irq[2];
1367
1368         host->dying = true;
1369         pm_runtime_get_sync(&pdev->dev);
1370
1371         dev_pm_qos_hide_latency_limit(&pdev->dev);
1372
1373         mmc_remove_host(host->mmc);
1374         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1375
1376         /*
1377          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1378          * mmc_remove_host() call above. But swapping order doesn't help either
1379          * (a query on the linux-mmc mailing list didn't bring any replies).
1380          */
1381         cancel_delayed_work_sync(&host->timeout_work);
1382
1383         if (host->addr)
1384                 iounmap(host->addr);
1385
1386         irq[0] = platform_get_irq(pdev, 0);
1387         irq[1] = platform_get_irq(pdev, 1);
1388
1389         free_irq(irq[0], host);
1390         free_irq(irq[1], host);
1391
1392         platform_set_drvdata(pdev, NULL);
1393
1394         clk_disable(host->hclk);
1395         mmc_free_host(host->mmc);
1396         pm_runtime_put_sync(&pdev->dev);
1397         pm_runtime_disable(&pdev->dev);
1398
1399         return 0;
1400 }
1401
1402 #ifdef CONFIG_PM
1403 static int sh_mmcif_suspend(struct device *dev)
1404 {
1405         struct platform_device *pdev = to_platform_device(dev);
1406         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1407         int ret = mmc_suspend_host(host->mmc);
1408
1409         if (!ret) {
1410                 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1411                 clk_disable(host->hclk);
1412         }
1413
1414         return ret;
1415 }
1416
1417 static int sh_mmcif_resume(struct device *dev)
1418 {
1419         struct platform_device *pdev = to_platform_device(dev);
1420         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1421
1422         clk_enable(host->hclk);
1423
1424         return mmc_resume_host(host->mmc);
1425 }
1426 #else
1427 #define sh_mmcif_suspend        NULL
1428 #define sh_mmcif_resume         NULL
1429 #endif  /* CONFIG_PM */
1430
1431 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1432         .suspend = sh_mmcif_suspend,
1433         .resume = sh_mmcif_resume,
1434 };
1435
1436 static struct platform_driver sh_mmcif_driver = {
1437         .probe          = sh_mmcif_probe,
1438         .remove         = sh_mmcif_remove,
1439         .driver         = {
1440                 .name   = DRIVER_NAME,
1441                 .pm     = &sh_mmcif_dev_pm_ops,
1442         },
1443 };
1444
1445 module_platform_driver(sh_mmcif_driver);
1446
1447 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1448 MODULE_LICENSE("GPL");
1449 MODULE_ALIAS("platform:" DRIVER_NAME);
1450 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");