drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 /*
  20  * The MMCIF driver is now processing MMC requests asynchronously, according
  21  * to the Linux MMC API requirement.
  22  *
  23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
  24  * data, and optional stop. To achieve asynchronous processing each of these
  25  * stages is split into two halves: a top and a bottom half. The top half
  26  * initialises the hardware, installs a timeout handler to handle completion
  27  * timeouts, and returns. In case of the command stage this immediately returns
  28  * control to the caller, leaving all further processing to run asynchronously.
  29  * All further request processing is performed by the bottom halves.
  30  *
  31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
  32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
  33  * request- and stage-specific handler methods.
  34  *
  35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
  36  * invocation, or a timeout work run. In case of an error or a successful
  37  * processing completion, the MMC core is informed and the request processing is
  38  * finished. In case processing has to continue, i.e., if data has to be read
  39  * from or written to the card, or if a stop command has to be sent, the next
  40  * top half is called, which performs the necessary hardware handling and
  41  * reschedules the timeout work. This returns the driver state machine into the
  42  * bottom half waiting state.
  43  */
  44
  45 #include <linux/bitops.h>
  46 #include <linux/clk.h>
  47 #include <linux/completion.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/mmc/card.h>
  52 #include <linux/mmc/core.h>
  53 #include <linux/mmc/host.h>
  54 #include <linux/mmc/mmc.h>
  55 #include <linux/mmc/sdio.h>
  56 #include <linux/mmc/sh_mmcif.h>
  57 #include <linux/mmc/slot-gpio.h>
  58 #include <linux/mod_devicetable.h>
  59 #include <linux/mutex.h>
  60 #include <linux/pagemap.h>
  61 #include <linux/platform_device.h>
  62 #include <linux/pm_qos.h>
  63 #include <linux/pm_runtime.h>
  64 #include <linux/sh_dma.h>
  65 #include <linux/spinlock.h>
  66 #include <linux/module.h>
  67
  68 #define DRIVER_NAME     "sh_mmcif"
  69 #define DRIVER_VERSION  "2010-04-28"
  70
  71 /* CE_CMD_SET */
  72 #define CMD_MASK                0x3f000000
  73 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  74 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  75 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  76 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  77 #define CMD_SET_CCSEN           (1 << 20)
  78 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  79 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  80 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  81 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  82 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  83 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  84 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  85 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  86 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  87 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  88 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  89 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  90 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  91 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  92 #define CMD_SET_CCSH            (1 << 5)
  93 #define CMD_SET_DARS            (1 << 2) /* Dual Data Rate */
  94 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  95 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  96 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  97
  98 /* CE_CMD_CTRL */
  99 #define CMD_CTRL_BREAK          (1 << 0)
 100
 101 /* CE_BLOCK_SET */
 102 #define BLOCK_SIZE_MASK         0x0000ffff
 103
 104 /* CE_INT */
 105 #define INT_CCSDE               (1 << 29)
 106 #define INT_CMD12DRE            (1 << 26)
 107 #define INT_CMD12RBE            (1 << 25)
 108 #define INT_CMD12CRE            (1 << 24)
 109 #define INT_DTRANE              (1 << 23)
 110 #define INT_BUFRE               (1 << 22)
 111 #define INT_BUFWEN              (1 << 21)
 112 #define INT_BUFREN              (1 << 20)
 113 #define INT_CCSRCV              (1 << 19)
 114 #define INT_RBSYE               (1 << 17)
 115 #define INT_CRSPE               (1 << 16)
 116 #define INT_CMDVIO              (1 << 15)
 117 #define INT_BUFVIO              (1 << 14)
 118 #define INT_WDATERR             (1 << 11)
 119 #define INT_RDATERR             (1 << 10)
 120 #define INT_RIDXERR             (1 << 9)
 121 #define INT_RSPERR              (1 << 8)
 122 #define INT_CCSTO               (1 << 5)
 123 #define INT_CRCSTO              (1 << 4)
 124 #define INT_WDATTO              (1 << 3)
 125 #define INT_RDATTO              (1 << 2)
 126 #define INT_RBSYTO              (1 << 1)
 127 #define INT_RSPTO               (1 << 0)
 128 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 129                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 130                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 131                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 132
 133 #define INT_ALL                 (INT_RBSYE | INT_CRSPE | INT_BUFREN |    \
 134                                  INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
 135                                  INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
 136
 137 #define INT_CCS                 (INT_CCSTO | INT_CCSRCV | INT_CCSDE)
 138
 139 /* CE_INT_MASK */
 140 #define MASK_ALL                0x00000000
 141 #define MASK_MCCSDE             (1 << 29)
 142 #define MASK_MCMD12DRE          (1 << 26)
 143 #define MASK_MCMD12RBE          (1 << 25)
 144 #define MASK_MCMD12CRE          (1 << 24)
 145 #define MASK_MDTRANE            (1 << 23)
 146 #define MASK_MBUFRE             (1 << 22)
 147 #define MASK_MBUFWEN            (1 << 21)
 148 #define MASK_MBUFREN            (1 << 20)
 149 #define MASK_MCCSRCV            (1 << 19)
 150 #define MASK_MRBSYE             (1 << 17)
 151 #define MASK_MCRSPE             (1 << 16)
 152 #define MASK_MCMDVIO            (1 << 15)
 153 #define MASK_MBUFVIO            (1 << 14)
 154 #define MASK_MWDATERR           (1 << 11)
 155 #define MASK_MRDATERR           (1 << 10)
 156 #define MASK_MRIDXERR           (1 << 9)
 157 #define MASK_MRSPERR            (1 << 8)
 158 #define MASK_MCCSTO             (1 << 5)
 159 #define MASK_MCRCSTO            (1 << 4)
 160 #define MASK_MWDATTO            (1 << 3)
 161 #define MASK_MRDATTO            (1 << 2)
 162 #define MASK_MRBSYTO            (1 << 1)
 163 #define MASK_MRSPTO             (1 << 0)
 164
 165 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 166                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 167                                  MASK_MCRCSTO | MASK_MWDATTO | \
 168                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 169
 170 #define MASK_CLEAN              (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE |      \
 171                                  MASK_MBUFREN | MASK_MBUFWEN |                  \
 172                                  MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE |  \
 173                                  MASK_MCMD12RBE | MASK_MCMD12CRE)
 174
 175 /* CE_HOST_STS1 */
 176 #define STS1_CMDSEQ             (1 << 31)
 177
 178 /* CE_HOST_STS2 */
 179 #define STS2_CRCSTE             (1 << 31)
 180 #define STS2_CRC16E             (1 << 30)
 181 #define STS2_AC12CRCE           (1 << 29)
 182 #define STS2_RSPCRC7E           (1 << 28)
 183 #define STS2_CRCSTEBE           (1 << 27)
 184 #define STS2_RDATEBE            (1 << 26)
 185 #define STS2_AC12REBE           (1 << 25)
 186 #define STS2_RSPEBE             (1 << 24)
 187 #define STS2_AC12IDXE           (1 << 23)
 188 #define STS2_RSPIDXE            (1 << 22)
 189 #define STS2_CCSTO              (1 << 15)
 190 #define STS2_RDATTO             (1 << 14)
 191 #define STS2_DATBSYTO           (1 << 13)
 192 #define STS2_CRCSTTO            (1 << 12)
 193 #define STS2_AC12BSYTO          (1 << 11)
 194 #define STS2_RSPBSYTO           (1 << 10)
 195 #define STS2_AC12RSPTO          (1 << 9)
 196 #define STS2_RSPTO              (1 << 8)
 197 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 198                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 199 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 200                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 201                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 202                                  STS2_AC12RSPTO | STS2_RSPTO)
 203
 204 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 205 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 206 #define CLKDEV_INIT             400000   /* 400 KHz */
 207
 208 enum mmcif_state {
 209         STATE_IDLE,
 210         STATE_REQUEST,
 211         STATE_IOS,
 212         STATE_TIMEOUT,
 213 };
 214
 215 enum mmcif_wait_for {
 216         MMCIF_WAIT_FOR_REQUEST,
 217         MMCIF_WAIT_FOR_CMD,
 218         MMCIF_WAIT_FOR_MREAD,
 219         MMCIF_WAIT_FOR_MWRITE,
 220         MMCIF_WAIT_FOR_READ,
 221         MMCIF_WAIT_FOR_WRITE,
 222         MMCIF_WAIT_FOR_READ_END,
 223         MMCIF_WAIT_FOR_WRITE_END,
 224         MMCIF_WAIT_FOR_STOP,
 225 };
 226
 227 struct sh_mmcif_host {
 228         struct mmc_host *mmc;
 229         struct mmc_request *mrq;
 230         struct platform_device *pd;
 231         struct clk *hclk;
 232         unsigned int clk;
 233         int bus_width;
 234         unsigned char timing;
 235         bool sd_error;
 236         bool dying;
 237         long timeout;
 238         void __iomem *addr;
 239         u32 *pio_ptr;
 240         spinlock_t lock;                /* protect sh_mmcif_host::state */
 241         enum mmcif_state state;
 242         enum mmcif_wait_for wait_for;
 243         struct delayed_work timeout_work;
 244         size_t blocksize;
 245         int sg_idx;
 246         int sg_blkidx;
 247         bool power;
 248         bool card_present;
 249         bool ccs_enable;                /* Command Completion Signal support */
 250         bool clk_ctrl2_enable;
 251         struct mutex thread_lock;
 252
 253         /* DMA support */
 254         struct dma_chan         *chan_rx;
 255         struct dma_chan         *chan_tx;
 256         struct completion       dma_complete;
 257         bool                    dma_active;
 258 };
 259
 260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 261                                         unsigned int reg, u32 val)
 262 {
 263         writel(val | readl(host->addr + reg), host->addr + reg);
 264 }
 265
 266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 267                                         unsigned int reg, u32 val)
 268 {
 269         writel(~val & readl(host->addr + reg), host->addr + reg);
 270 }
 271
 272 static void mmcif_dma_complete(void *arg)
 273 {
 274         struct sh_mmcif_host *host = arg;
 275         struct mmc_request *mrq = host->mrq;
 276
 277         dev_dbg(&host->pd->dev, "Command completed\n");
 278
 279         if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
 280                  dev_name(&host->pd->dev)))
 281                 return;
 282
 283         complete(&host->dma_complete);
 284 }
 285
 286 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 287 {
 288         struct mmc_data *data = host->mrq->data;
 289         struct scatterlist *sg = data->sg;
 290         struct dma_async_tx_descriptor *desc = NULL;
 291         struct dma_chan *chan = host->chan_rx;
 292         dma_cookie_t cookie = -EINVAL;
 293         int ret;
 294
 295         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 296                          DMA_FROM_DEVICE);
 297         if (ret > 0) {
 298                 host->dma_active = true;
 299                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 300                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 301         }
 302
 303         if (desc) {
 304                 desc->callback = mmcif_dma_complete;
 305                 desc->callback_param = host;
 306                 cookie = dmaengine_submit(desc);
 307                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 308                 dma_async_issue_pending(chan);
 309         }
 310         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 311                 __func__, data->sg_len, ret, cookie);
 312
 313         if (!desc) {
 314                 /* DMA failed, fall back to PIO */
 315                 if (ret >= 0)
 316                         ret = -EIO;
 317                 host->chan_rx = NULL;
 318                 host->dma_active = false;
 319                 dma_release_channel(chan);
 320                 /* Free the Tx channel too */
 321                 chan = host->chan_tx;
 322                 if (chan) {
 323                         host->chan_tx = NULL;
 324                         dma_release_channel(chan);
 325                 }
 326                 dev_warn(&host->pd->dev,
 327                          "DMA failed: %d, falling back to PIO\n", ret);
 328                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 329         }
 330
 331         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 332                 desc, cookie, data->sg_len);
 333 }
 334
 335 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 336 {
 337         struct mmc_data *data = host->mrq->data;
 338         struct scatterlist *sg = data->sg;
 339         struct dma_async_tx_descriptor *desc = NULL;
 340         struct dma_chan *chan = host->chan_tx;
 341         dma_cookie_t cookie = -EINVAL;
 342         int ret;
 343
 344         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 345                          DMA_TO_DEVICE);
 346         if (ret > 0) {
 347                 host->dma_active = true;
 348                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 349                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 350         }
 351
 352         if (desc) {
 353                 desc->callback = mmcif_dma_complete;
 354                 desc->callback_param = host;
 355                 cookie = dmaengine_submit(desc);
 356                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 357                 dma_async_issue_pending(chan);
 358         }
 359         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 360                 __func__, data->sg_len, ret, cookie);
 361
 362         if (!desc) {
 363                 /* DMA failed, fall back to PIO */
 364                 if (ret >= 0)
 365                         ret = -EIO;
 366                 host->chan_tx = NULL;
 367                 host->dma_active = false;
 368                 dma_release_channel(chan);
 369                 /* Free the Rx channel too */
 370                 chan = host->chan_rx;
 371                 if (chan) {
 372                         host->chan_rx = NULL;
 373                         dma_release_channel(chan);
 374                 }
 375                 dev_warn(&host->pd->dev,
 376                          "DMA failed: %d, falling back to PIO\n", ret);
 377                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 378         }
 379
 380         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 381                 desc, cookie);
 382 }
 383
 384 static struct dma_chan *
 385 sh_mmcif_request_dma_one(struct sh_mmcif_host *host,
 386                          struct sh_mmcif_plat_data *pdata,
 387                          enum dma_transfer_direction direction)
 388 {
 389         struct dma_slave_config cfg;
 390         struct dma_chan *chan;
 391         unsigned int slave_id;
 392         struct resource *res;
 393         dma_cap_mask_t mask;
 394         int ret;
 395
 396         dma_cap_zero(mask);
 397         dma_cap_set(DMA_SLAVE, mask);
 398
 399         if (pdata)
 400                 slave_id = direction == DMA_MEM_TO_DEV
 401                          ? pdata->slave_id_tx : pdata->slave_id_rx;
 402         else
 403                 slave_id = 0;
 404
 405         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
 406                                 (void *)(unsigned long)slave_id, &host->pd->dev,
 407                                 direction == DMA_MEM_TO_DEV ? "tx" : "rx");
 408
 409         dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__,
 410                 direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan);
 411
 412         if (!chan)
 413                 return NULL;
 414
 415         res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
 416
 417         /* In the OF case the driver will get the slave ID from the DT */
 418         cfg.slave_id = slave_id;
 419         cfg.direction = direction;
 420         cfg.dst_addr = res->start + MMCIF_CE_DATA;
 421         cfg.src_addr = 0;
 422         ret = dmaengine_slave_config(chan, &cfg);
 423         if (ret < 0) {
 424                 dma_release_channel(chan);
 425                 return NULL;
 426         }
 427
 428         return chan;
 429 }
 430
 431 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 432                                  struct sh_mmcif_plat_data *pdata)
 433 {
 434         host->dma_active = false;
 435
 436         if (pdata) {
 437                 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
 438                         return;
 439         } else if (!host->pd->dev.of_node) {
 440                 return;
 441         }
 442
 443         /* We can only either use DMA for both Tx and Rx or not use it at all */
 444         host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV);
 445         if (!host->chan_tx)
 446                 return;
 447
 448         host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM);
 449         if (!host->chan_rx) {
 450                 dma_release_channel(host->chan_tx);
 451                 host->chan_tx = NULL;
 452         }
 453 }
 454
 455 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 456 {
 457         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 458         /* Descriptors are freed automatically */
 459         if (host->chan_tx) {
 460                 struct dma_chan *chan = host->chan_tx;
 461                 host->chan_tx = NULL;
 462                 dma_release_channel(chan);
 463         }
 464         if (host->chan_rx) {
 465                 struct dma_chan *chan = host->chan_rx;
 466                 host->chan_rx = NULL;
 467                 dma_release_channel(chan);
 468         }
 469
 470         host->dma_active = false;
 471 }
 472
 473 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 474 {
 475         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 476         bool sup_pclk = p ? p->sup_pclk : false;
 477
 478         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 479         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 480
 481         if (!clk)
 482                 return;
 483         if (sup_pclk && clk == host->clk)
 484                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 485         else
 486                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 487                                 ((fls(DIV_ROUND_UP(host->clk,
 488                                                    clk) - 1) - 1) << 16));
 489
 490         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 491 }
 492
 493 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 494 {
 495         u32 tmp;
 496
 497         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 498
 499         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 500         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 501         if (host->ccs_enable)
 502                 tmp |= SCCSTO_29;
 503         if (host->clk_ctrl2_enable)
 504                 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
 505         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 506                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
 507         /* byte swap on */
 508         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 509 }
 510
 511 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 512 {
 513         u32 state1, state2;
 514         int ret, timeout;
 515
 516         host->sd_error = false;
 517
 518         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 519         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 520         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 521         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 522
 523         if (state1 & STS1_CMDSEQ) {
 524                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 525                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 526                 for (timeout = 10000000; timeout; timeout--) {
 527                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 528                               & STS1_CMDSEQ))
 529                                 break;
 530                         mdelay(1);
 531                 }
 532                 if (!timeout) {
 533                         dev_err(&host->pd->dev,
 534                                 "Forced end of command sequence timeout err\n");
 535                         return -EIO;
 536                 }
 537                 sh_mmcif_sync_reset(host);
 538                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 539                 return -EIO;
 540         }
 541
 542         if (state2 & STS2_CRC_ERR) {
 543                 dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n",
 544                         host->state, host->wait_for);
 545                 ret = -EIO;
 546         } else if (state2 & STS2_TIMEOUT_ERR) {
 547                 dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n",
 548                         host->state, host->wait_for);
 549                 ret = -ETIMEDOUT;
 550         } else {
 551                 dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n",
 552                         host->state, host->wait_for);
 553                 ret = -EIO;
 554         }
 555         return ret;
 556 }
 557
 558 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
 559 {
 560         struct mmc_data *data = host->mrq->data;
 561
 562         host->sg_blkidx += host->blocksize;
 563
 564         /* data->sg->length must be a multiple of host->blocksize? */
 565         BUG_ON(host->sg_blkidx > data->sg->length);
 566
 567         if (host->sg_blkidx == data->sg->length) {
 568                 host->sg_blkidx = 0;
 569                 if (++host->sg_idx < data->sg_len)
 570                         host->pio_ptr = sg_virt(++data->sg);
 571         } else {
 572                 host->pio_ptr = p;
 573         }
 574
 575         return host->sg_idx != data->sg_len;
 576 }
 577
 578 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
 579                                  struct mmc_request *mrq)
 580 {
 581         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 582                            BLOCK_SIZE_MASK) + 3;
 583
 584         host->wait_for = MMCIF_WAIT_FOR_READ;
 585
 586         /* buf read enable */
 587         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 588 }
 589
 590 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
 591 {
 592         struct mmc_data *data = host->mrq->data;
 593         u32 *p = sg_virt(data->sg);
 594         int i;
 595
 596         if (host->sd_error) {
 597                 data->error = sh_mmcif_error_manage(host);
 598                 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
 599                 return false;
 600         }
 601
 602         for (i = 0; i < host->blocksize / 4; i++)
 603                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 604
 605         /* buffer read end */
 606         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 607         host->wait_for = MMCIF_WAIT_FOR_READ_END;
 608
 609         return true;
 610 }
 611
 612 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
 613                                 struct mmc_request *mrq)
 614 {
 615         struct mmc_data *data = mrq->data;
 616
 617         if (!data->sg_len || !data->sg->length)
 618                 return;
 619
 620         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 621                 BLOCK_SIZE_MASK;
 622
 623         host->wait_for = MMCIF_WAIT_FOR_MREAD;
 624         host->sg_idx = 0;
 625         host->sg_blkidx = 0;
 626         host->pio_ptr = sg_virt(data->sg);
 627
 628         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 629 }
 630
 631 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
 632 {
 633         struct mmc_data *data = host->mrq->data;
 634         u32 *p = host->pio_ptr;
 635         int i;
 636
 637         if (host->sd_error) {
 638                 data->error = sh_mmcif_error_manage(host);
 639                 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
 640                 return false;
 641         }
 642
 643         BUG_ON(!data->sg->length);
 644
 645         for (i = 0; i < host->blocksize / 4; i++)
 646                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 647
 648         if (!sh_mmcif_next_block(host, p))
 649                 return false;
 650
 651         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 652
 653         return true;
 654 }
 655
 656 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
 657                                         struct mmc_request *mrq)
 658 {
 659         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 660                            BLOCK_SIZE_MASK) + 3;
 661
 662         host->wait_for = MMCIF_WAIT_FOR_WRITE;
 663
 664         /* buf write enable */
 665         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 666 }
 667
 668 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
 669 {
 670         struct mmc_data *data = host->mrq->data;
 671         u32 *p = sg_virt(data->sg);
 672         int i;
 673
 674         if (host->sd_error) {
 675                 data->error = sh_mmcif_error_manage(host);
 676                 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
 677                 return false;
 678         }
 679
 680         for (i = 0; i < host->blocksize / 4; i++)
 681                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 682
 683         /* buffer write end */
 684         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 685         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
 686
 687         return true;
 688 }
 689
 690 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
 691                                 struct mmc_request *mrq)
 692 {
 693         struct mmc_data *data = mrq->data;
 694
 695         if (!data->sg_len || !data->sg->length)
 696                 return;
 697
 698         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 699                 BLOCK_SIZE_MASK;
 700
 701         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
 702         host->sg_idx = 0;
 703         host->sg_blkidx = 0;
 704         host->pio_ptr = sg_virt(data->sg);
 705
 706         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 707 }
 708
 709 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
 710 {
 711         struct mmc_data *data = host->mrq->data;
 712         u32 *p = host->pio_ptr;
 713         int i;
 714
 715         if (host->sd_error) {
 716                 data->error = sh_mmcif_error_manage(host);
 717                 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
 718                 return false;
 719         }
 720
 721         BUG_ON(!data->sg->length);
 722
 723         for (i = 0; i < host->blocksize / 4; i++)
 724                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 725
 726         if (!sh_mmcif_next_block(host, p))
 727                 return false;
 728
 729         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 730
 731         return true;
 732 }
 733
 734 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 735                                                 struct mmc_command *cmd)
 736 {
 737         if (cmd->flags & MMC_RSP_136) {
 738                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 739                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 740                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 741                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 742         } else
 743                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 744 }
 745
 746 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 747                                                 struct mmc_command *cmd)
 748 {
 749         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 750 }
 751
 752 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 753                             struct mmc_request *mrq)
 754 {
 755         struct mmc_data *data = mrq->data;
 756         struct mmc_command *cmd = mrq->cmd;
 757         u32 opc = cmd->opcode;
 758         u32 tmp = 0;
 759
 760         /* Response Type check */
 761         switch (mmc_resp_type(cmd)) {
 762         case MMC_RSP_NONE:
 763                 tmp |= CMD_SET_RTYP_NO;
 764                 break;
 765         case MMC_RSP_R1:
 766         case MMC_RSP_R1B:
 767         case MMC_RSP_R3:
 768                 tmp |= CMD_SET_RTYP_6B;
 769                 break;
 770         case MMC_RSP_R2:
 771                 tmp |= CMD_SET_RTYP_17B;
 772                 break;
 773         default:
 774                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 775                 break;
 776         }
 777         switch (opc) {
 778         /* RBSY */
 779         case MMC_SLEEP_AWAKE:
 780         case MMC_SWITCH:
 781         case MMC_STOP_TRANSMISSION:
 782         case MMC_SET_WRITE_PROT:
 783         case MMC_CLR_WRITE_PROT:
 784         case MMC_ERASE:
 785                 tmp |= CMD_SET_RBSY;
 786                 break;
 787         }
 788         /* WDAT / DATW */
 789         if (data) {
 790                 tmp |= CMD_SET_WDAT;
 791                 switch (host->bus_width) {
 792                 case MMC_BUS_WIDTH_1:
 793                         tmp |= CMD_SET_DATW_1;
 794                         break;
 795                 case MMC_BUS_WIDTH_4:
 796                         tmp |= CMD_SET_DATW_4;
 797                         break;
 798                 case MMC_BUS_WIDTH_8:
 799                         tmp |= CMD_SET_DATW_8;
 800                         break;
 801                 default:
 802                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 803                         break;
 804                 }
 805                 switch (host->timing) {
 806                 case MMC_TIMING_UHS_DDR50:
 807                         /*
 808                          * MMC core will only set this timing, if the host
 809                          * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF
 810                          * implementations with this capability, e.g. sh73a0,
 811                          * will have to set it in their platform data.
 812                          */
 813                         tmp |= CMD_SET_DARS;
 814                         break;
 815                 }
 816         }
 817         /* DWEN */
 818         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 819                 tmp |= CMD_SET_DWEN;
 820         /* CMLTE/CMD12EN */
 821         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 822                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 823                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 824                                 data->blocks << 16);
 825         }
 826         /* RIDXC[1:0] check bits */
 827         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 828             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 829                 tmp |= CMD_SET_RIDXC_BITS;
 830         /* RCRC7C[1:0] check bits */
 831         if (opc == MMC_SEND_OP_COND)
 832                 tmp |= CMD_SET_CRC7C_BITS;
 833         /* RCRC7C[1:0] internal CRC7 */
 834         if (opc == MMC_ALL_SEND_CID ||
 835                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 836                 tmp |= CMD_SET_CRC7C_INTERNAL;
 837
 838         return (opc << 24) | tmp;
 839 }
 840
 841 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 842                                struct mmc_request *mrq, u32 opc)
 843 {
 844         switch (opc) {
 845         case MMC_READ_MULTIPLE_BLOCK:
 846                 sh_mmcif_multi_read(host, mrq);
 847                 return 0;
 848         case MMC_WRITE_MULTIPLE_BLOCK:
 849                 sh_mmcif_multi_write(host, mrq);
 850                 return 0;
 851         case MMC_WRITE_BLOCK:
 852                 sh_mmcif_single_write(host, mrq);
 853                 return 0;
 854         case MMC_READ_SINGLE_BLOCK:
 855         case MMC_SEND_EXT_CSD:
 856                 sh_mmcif_single_read(host, mrq);
 857                 return 0;
 858         default:
 859                 dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc);
 860                 return -EINVAL;
 861         }
 862 }
 863
 864 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 865                                struct mmc_request *mrq)
 866 {
 867         struct mmc_command *cmd = mrq->cmd;
 868         u32 opc = cmd->opcode;
 869         u32 mask;
 870
 871         switch (opc) {
 872         /* response busy check */
 873         case MMC_SLEEP_AWAKE:
 874         case MMC_SWITCH:
 875         case MMC_STOP_TRANSMISSION:
 876         case MMC_SET_WRITE_PROT:
 877         case MMC_CLR_WRITE_PROT:
 878         case MMC_ERASE:
 879                 mask = MASK_START_CMD | MASK_MRBSYE;
 880                 break;
 881         default:
 882                 mask = MASK_START_CMD | MASK_MCRSPE;
 883                 break;
 884         }
 885
 886         if (host->ccs_enable)
 887                 mask |= MASK_MCCSTO;
 888
 889         if (mrq->data) {
 890                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 891                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 892                                 mrq->data->blksz);
 893         }
 894         opc = sh_mmcif_set_cmd(host, mrq);
 895
 896         if (host->ccs_enable)
 897                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 898         else
 899                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
 900         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 901         /* set arg */
 902         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 903         /* set cmd */
 904         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 905
 906         host->wait_for = MMCIF_WAIT_FOR_CMD;
 907         schedule_delayed_work(&host->timeout_work, host->timeout);
 908 }
 909
 910 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 911                               struct mmc_request *mrq)
 912 {
 913         switch (mrq->cmd->opcode) {
 914         case MMC_READ_MULTIPLE_BLOCK:
 915                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 916                 break;
 917         case MMC_WRITE_MULTIPLE_BLOCK:
 918                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 919                 break;
 920         default:
 921                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 922                 mrq->stop->error = sh_mmcif_error_manage(host);
 923                 return;
 924         }
 925
 926         host->wait_for = MMCIF_WAIT_FOR_STOP;
 927 }
 928
 929 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 930 {
 931         struct sh_mmcif_host *host = mmc_priv(mmc);
 932         unsigned long flags;
 933
 934         spin_lock_irqsave(&host->lock, flags);
 935         if (host->state != STATE_IDLE) {
 936                 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state);
 937                 spin_unlock_irqrestore(&host->lock, flags);
 938                 mrq->cmd->error = -EAGAIN;
 939                 mmc_request_done(mmc, mrq);
 940                 return;
 941         }
 942
 943         host->state = STATE_REQUEST;
 944         spin_unlock_irqrestore(&host->lock, flags);
 945
 946         switch (mrq->cmd->opcode) {
 947         /* MMCIF does not support SD/SDIO command */
 948         case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
 949         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 950                 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
 951                         break;
 952         case MMC_APP_CMD:
 953         case SD_IO_RW_DIRECT:
 954                 host->state = STATE_IDLE;
 955                 mrq->cmd->error = -ETIMEDOUT;
 956                 mmc_request_done(mmc, mrq);
 957                 return;
 958         default:
 959                 break;
 960         }
 961
 962         host->mrq = mrq;
 963
 964         sh_mmcif_start_cmd(host, mrq);
 965 }
 966
 967 static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
 968 {
 969         int ret = clk_prepare_enable(host->hclk);
 970
 971         if (!ret) {
 972                 host->clk = clk_get_rate(host->hclk);
 973                 host->mmc->f_max = host->clk / 2;
 974                 host->mmc->f_min = host->clk / 512;
 975         }
 976
 977         return ret;
 978 }
 979
 980 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
 981 {
 982         struct mmc_host *mmc = host->mmc;
 983
 984         if (!IS_ERR(mmc->supply.vmmc))
 985                 /* Errors ignored... */
 986                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
 987                                       ios->power_mode ? ios->vdd : 0);
 988 }
 989
 990 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 991 {
 992         struct sh_mmcif_host *host = mmc_priv(mmc);
 993         unsigned long flags;
 994
 995         spin_lock_irqsave(&host->lock, flags);
 996         if (host->state != STATE_IDLE) {
 997                 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state);
 998                 spin_unlock_irqrestore(&host->lock, flags);
 999                 return;
1000         }
1001
1002         host->state = STATE_IOS;
1003         spin_unlock_irqrestore(&host->lock, flags);
1004
1005         if (ios->power_mode == MMC_POWER_UP) {
1006                 if (!host->card_present) {
1007                         /* See if we also get DMA */
1008                         sh_mmcif_request_dma(host, host->pd->dev.platform_data);
1009                         host->card_present = true;
1010                 }
1011                 sh_mmcif_set_power(host, ios);
1012         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
1013                 /* clock stop */
1014                 sh_mmcif_clock_control(host, 0);
1015                 if (ios->power_mode == MMC_POWER_OFF) {
1016                         if (host->card_present) {
1017                                 sh_mmcif_release_dma(host);
1018                                 host->card_present = false;
1019                         }
1020                 }
1021                 if (host->power) {
1022                         pm_runtime_put_sync(&host->pd->dev);
1023                         clk_disable_unprepare(host->hclk);
1024                         host->power = false;
1025                         if (ios->power_mode == MMC_POWER_OFF)
1026                                 sh_mmcif_set_power(host, ios);
1027                 }
1028                 host->state = STATE_IDLE;
1029                 return;
1030         }
1031
1032         if (ios->clock) {
1033                 if (!host->power) {
1034                         sh_mmcif_clk_update(host);
1035                         pm_runtime_get_sync(&host->pd->dev);
1036                         host->power = true;
1037                         sh_mmcif_sync_reset(host);
1038                 }
1039                 sh_mmcif_clock_control(host, ios->clock);
1040         }
1041
1042         host->timing = ios->timing;
1043         host->bus_width = ios->bus_width;
1044         host->state = STATE_IDLE;
1045 }
1046
1047 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1048 {
1049         struct sh_mmcif_host *host = mmc_priv(mmc);
1050         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
1051         int ret = mmc_gpio_get_cd(mmc);
1052
1053         if (ret >= 0)
1054                 return ret;
1055
1056         if (!p || !p->get_cd)
1057                 return -ENOSYS;
1058         else
1059                 return p->get_cd(host->pd);
1060 }
1061
1062 static struct mmc_host_ops sh_mmcif_ops = {
1063         .request        = sh_mmcif_request,
1064         .set_ios        = sh_mmcif_set_ios,
1065         .get_cd         = sh_mmcif_get_cd,
1066 };
1067
1068 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1069 {
1070         struct mmc_command *cmd = host->mrq->cmd;
1071         struct mmc_data *data = host->mrq->data;
1072         long time;
1073
1074         if (host->sd_error) {
1075                 switch (cmd->opcode) {
1076                 case MMC_ALL_SEND_CID:
1077                 case MMC_SELECT_CARD:
1078                 case MMC_APP_CMD:
1079                         cmd->error = -ETIMEDOUT;
1080                         break;
1081                 default:
1082                         cmd->error = sh_mmcif_error_manage(host);
1083                         break;
1084                 }
1085                 dev_dbg(&host->pd->dev, "CMD%d error %d\n",
1086                         cmd->opcode, cmd->error);
1087                 host->sd_error = false;
1088                 return false;
1089         }
1090         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1091                 cmd->error = 0;
1092                 return false;
1093         }
1094
1095         sh_mmcif_get_response(host, cmd);
1096
1097         if (!data)
1098                 return false;
1099
1100         /*
1101          * Completion can be signalled from DMA callback and error, so, have to
1102          * reset here, before setting .dma_active
1103          */
1104         init_completion(&host->dma_complete);
1105
1106         if (data->flags & MMC_DATA_READ) {
1107                 if (host->chan_rx)
1108                         sh_mmcif_start_dma_rx(host);
1109         } else {
1110                 if (host->chan_tx)
1111                         sh_mmcif_start_dma_tx(host);
1112         }
1113
1114         if (!host->dma_active) {
1115                 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1116                 return !data->error;
1117         }
1118
1119         /* Running in the IRQ thread, can sleep */
1120         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1121                                                          host->timeout);
1122
1123         if (data->flags & MMC_DATA_READ)
1124                 dma_unmap_sg(host->chan_rx->device->dev,
1125                              data->sg, data->sg_len,
1126                              DMA_FROM_DEVICE);
1127         else
1128                 dma_unmap_sg(host->chan_tx->device->dev,
1129                              data->sg, data->sg_len,
1130                              DMA_TO_DEVICE);
1131
1132         if (host->sd_error) {
1133                 dev_err(host->mmc->parent,
1134                         "Error IRQ while waiting for DMA completion!\n");
1135                 /* Woken up by an error IRQ: abort DMA */
1136                 data->error = sh_mmcif_error_manage(host);
1137         } else if (!time) {
1138                 dev_err(host->mmc->parent, "DMA timeout!\n");
1139                 data->error = -ETIMEDOUT;
1140         } else if (time < 0) {
1141                 dev_err(host->mmc->parent,
1142                         "wait_for_completion_...() error %ld!\n", time);
1143                 data->error = time;
1144         }
1145         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1146                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1147         host->dma_active = false;
1148
1149         if (data->error) {
1150                 data->bytes_xfered = 0;
1151                 /* Abort DMA */
1152                 if (data->flags & MMC_DATA_READ)
1153                         dmaengine_terminate_all(host->chan_rx);
1154                 else
1155                         dmaengine_terminate_all(host->chan_tx);
1156         }
1157
1158         return false;
1159 }
1160
1161 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1162 {
1163         struct sh_mmcif_host *host = dev_id;
1164         struct mmc_request *mrq;
1165         bool wait = false;
1166
1167         cancel_delayed_work_sync(&host->timeout_work);
1168
1169         mutex_lock(&host->thread_lock);
1170
1171         mrq = host->mrq;
1172         if (!mrq) {
1173                 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
1174                         host->state, host->wait_for);
1175                 mutex_unlock(&host->thread_lock);
1176                 return IRQ_HANDLED;
1177         }
1178
1179         /*
1180          * All handlers return true, if processing continues, and false, if the
1181          * request has to be completed - successfully or not
1182          */
1183         switch (host->wait_for) {
1184         case MMCIF_WAIT_FOR_REQUEST:
1185                 /* We're too late, the timeout has already kicked in */
1186                 mutex_unlock(&host->thread_lock);
1187                 return IRQ_HANDLED;
1188         case MMCIF_WAIT_FOR_CMD:
1189                 /* Wait for data? */
1190                 wait = sh_mmcif_end_cmd(host);
1191                 break;
1192         case MMCIF_WAIT_FOR_MREAD:
1193                 /* Wait for more data? */
1194                 wait = sh_mmcif_mread_block(host);
1195                 break;
1196         case MMCIF_WAIT_FOR_READ:
1197                 /* Wait for data end? */
1198                 wait = sh_mmcif_read_block(host);
1199                 break;
1200         case MMCIF_WAIT_FOR_MWRITE:
1201                 /* Wait data to write? */
1202                 wait = sh_mmcif_mwrite_block(host);
1203                 break;
1204         case MMCIF_WAIT_FOR_WRITE:
1205                 /* Wait for data end? */
1206                 wait = sh_mmcif_write_block(host);
1207                 break;
1208         case MMCIF_WAIT_FOR_STOP:
1209                 if (host->sd_error) {
1210                         mrq->stop->error = sh_mmcif_error_manage(host);
1211                         dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error);
1212                         break;
1213                 }
1214                 sh_mmcif_get_cmd12response(host, mrq->stop);
1215                 mrq->stop->error = 0;
1216                 break;
1217         case MMCIF_WAIT_FOR_READ_END:
1218         case MMCIF_WAIT_FOR_WRITE_END:
1219                 if (host->sd_error) {
1220                         mrq->data->error = sh_mmcif_error_manage(host);
1221                         dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error);
1222                 }
1223                 break;
1224         default:
1225                 BUG();
1226         }
1227
1228         if (wait) {
1229                 schedule_delayed_work(&host->timeout_work, host->timeout);
1230                 /* Wait for more data */
1231                 mutex_unlock(&host->thread_lock);
1232                 return IRQ_HANDLED;
1233         }
1234
1235         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1236                 struct mmc_data *data = mrq->data;
1237                 if (!mrq->cmd->error && data && !data->error)
1238                         data->bytes_xfered =
1239                                 data->blocks * data->blksz;
1240
1241                 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1242                         sh_mmcif_stop_cmd(host, mrq);
1243                         if (!mrq->stop->error) {
1244                                 schedule_delayed_work(&host->timeout_work, host->timeout);
1245                                 mutex_unlock(&host->thread_lock);
1246                                 return IRQ_HANDLED;
1247                         }
1248                 }
1249         }
1250
1251         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1252         host->state = STATE_IDLE;
1253         host->mrq = NULL;
1254         mmc_request_done(host->mmc, mrq);
1255
1256         mutex_unlock(&host->thread_lock);
1257
1258         return IRQ_HANDLED;
1259 }
1260
1261 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1262 {
1263         struct sh_mmcif_host *host = dev_id;
1264         u32 state, mask;
1265
1266         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1267         mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
1268         if (host->ccs_enable)
1269                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
1270         else
1271                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
1272         sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
1273
1274         if (state & ~MASK_CLEAN)
1275                 dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n",
1276                         state);
1277
1278         if (state & INT_ERR_STS || state & ~INT_ALL) {
1279                 host->sd_error = true;
1280                 dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state);
1281         }
1282         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1283                 if (!host->mrq)
1284                         dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state);
1285                 if (!host->dma_active)
1286                         return IRQ_WAKE_THREAD;
1287                 else if (host->sd_error)
1288                         mmcif_dma_complete(host);
1289         } else {
1290                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1291         }
1292
1293         return IRQ_HANDLED;
1294 }
1295
1296 static void mmcif_timeout_work(struct work_struct *work)
1297 {
1298         struct delayed_work *d = container_of(work, struct delayed_work, work);
1299         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1300         struct mmc_request *mrq = host->mrq;
1301         unsigned long flags;
1302
1303         if (host->dying)
1304                 /* Don't run after mmc_remove_host() */
1305                 return;
1306
1307         dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n",
1308                 host->wait_for, mrq->cmd->opcode);
1309
1310         spin_lock_irqsave(&host->lock, flags);
1311         if (host->state == STATE_IDLE) {
1312                 spin_unlock_irqrestore(&host->lock, flags);
1313                 return;
1314         }
1315
1316         host->state = STATE_TIMEOUT;
1317         spin_unlock_irqrestore(&host->lock, flags);
1318
1319         /*
1320          * Handle races with cancel_delayed_work(), unless
1321          * cancel_delayed_work_sync() is used
1322          */
1323         switch (host->wait_for) {
1324         case MMCIF_WAIT_FOR_CMD:
1325                 mrq->cmd->error = sh_mmcif_error_manage(host);
1326                 break;
1327         case MMCIF_WAIT_FOR_STOP:
1328                 mrq->stop->error = sh_mmcif_error_manage(host);
1329                 break;
1330         case MMCIF_WAIT_FOR_MREAD:
1331         case MMCIF_WAIT_FOR_MWRITE:
1332         case MMCIF_WAIT_FOR_READ:
1333         case MMCIF_WAIT_FOR_WRITE:
1334         case MMCIF_WAIT_FOR_READ_END:
1335         case MMCIF_WAIT_FOR_WRITE_END:
1336                 mrq->data->error = sh_mmcif_error_manage(host);
1337                 break;
1338         default:
1339                 BUG();
1340         }
1341
1342         host->state = STATE_IDLE;
1343         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1344         host->mrq = NULL;
1345         mmc_request_done(host->mmc, mrq);
1346 }
1347
1348 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1349 {
1350         struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1351         struct mmc_host *mmc = host->mmc;
1352
1353         mmc_regulator_get_supply(mmc);
1354
1355         if (!pd)
1356                 return;
1357
1358         if (!mmc->ocr_avail)
1359                 mmc->ocr_avail = pd->ocr;
1360         else if (pd->ocr)
1361                 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1362 }
1363
1364 static int sh_mmcif_probe(struct platform_device *pdev)
1365 {
1366         int ret = 0, irq[2];
1367         struct mmc_host *mmc;
1368         struct sh_mmcif_host *host;
1369         struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
1370         struct resource *res;
1371         void __iomem *reg;
1372         const char *name;
1373
1374         irq[0] = platform_get_irq(pdev, 0);
1375         irq[1] = platform_get_irq(pdev, 1);
1376         if (irq[0] < 0) {
1377                 dev_err(&pdev->dev, "Get irq error\n");
1378                 return -ENXIO;
1379         }
1380         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1381         if (!res) {
1382                 dev_err(&pdev->dev, "platform_get_resource error.\n");
1383                 return -ENXIO;
1384         }
1385         reg = ioremap(res->start, resource_size(res));
1386         if (!reg) {
1387                 dev_err(&pdev->dev, "ioremap error.\n");
1388                 return -ENOMEM;
1389         }
1390
1391         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1392         if (!mmc) {
1393                 ret = -ENOMEM;
1394                 goto ealloch;
1395         }
1396
1397         ret = mmc_of_parse(mmc);
1398         if (ret < 0)
1399                 goto eofparse;
1400
1401         host            = mmc_priv(mmc);
1402         host->mmc       = mmc;
1403         host->addr      = reg;
1404         host->timeout   = msecs_to_jiffies(1000);
1405         host->ccs_enable = !pd || !pd->ccs_unsupported;
1406         host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
1407
1408         host->pd = pdev;
1409
1410         spin_lock_init(&host->lock);
1411
1412         mmc->ops = &sh_mmcif_ops;
1413         sh_mmcif_init_ocr(host);
1414
1415         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1416         if (pd && pd->caps)
1417                 mmc->caps |= pd->caps;
1418         mmc->max_segs = 32;
1419         mmc->max_blk_size = 512;
1420         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1421         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1422         mmc->max_seg_size = mmc->max_req_size;
1423
1424         platform_set_drvdata(pdev, host);
1425
1426         pm_runtime_enable(&pdev->dev);
1427         host->power = false;
1428
1429         host->hclk = clk_get(&pdev->dev, NULL);
1430         if (IS_ERR(host->hclk)) {
1431                 ret = PTR_ERR(host->hclk);
1432                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
1433                 goto eclkget;
1434         }
1435         ret = sh_mmcif_clk_update(host);
1436         if (ret < 0)
1437                 goto eclkupdate;
1438
1439         ret = pm_runtime_resume(&pdev->dev);
1440         if (ret < 0)
1441                 goto eresume;
1442
1443         INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1444
1445         sh_mmcif_sync_reset(host);
1446         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1447
1448         name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error";
1449         ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host);
1450         if (ret) {
1451                 dev_err(&pdev->dev, "request_irq error (%s)\n", name);
1452                 goto ereqirq0;
1453         }
1454         if (irq[1] >= 0) {
1455                 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt,
1456                                            0, "sh_mmc:int", host);
1457                 if (ret) {
1458                         dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1459                         goto ereqirq1;
1460                 }
1461         }
1462
1463         if (pd && pd->use_cd_gpio) {
1464                 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0);
1465                 if (ret < 0)
1466                         goto erqcd;
1467         }
1468
1469         mutex_init(&host->thread_lock);
1470
1471         clk_disable_unprepare(host->hclk);
1472         ret = mmc_add_host(mmc);
1473         if (ret < 0)
1474                 goto emmcaddh;
1475
1476         dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1477
1478         dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1479         dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1480                 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1481         return ret;
1482
1483 emmcaddh:
1484 erqcd:
1485         if (irq[1] >= 0)
1486                 free_irq(irq[1], host);
1487 ereqirq1:
1488         free_irq(irq[0], host);
1489 ereqirq0:
1490         pm_runtime_suspend(&pdev->dev);
1491 eresume:
1492         clk_disable_unprepare(host->hclk);
1493 eclkupdate:
1494         clk_put(host->hclk);
1495 eclkget:
1496         pm_runtime_disable(&pdev->dev);
1497 eofparse:
1498         mmc_free_host(mmc);
1499 ealloch:
1500         iounmap(reg);
1501         return ret;
1502 }
1503
1504 static int sh_mmcif_remove(struct platform_device *pdev)
1505 {
1506         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1507         int irq[2];
1508
1509         host->dying = true;
1510         clk_prepare_enable(host->hclk);
1511         pm_runtime_get_sync(&pdev->dev);
1512
1513         dev_pm_qos_hide_latency_limit(&pdev->dev);
1514
1515         mmc_remove_host(host->mmc);
1516         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1517
1518         /*
1519          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1520          * mmc_remove_host() call above. But swapping order doesn't help either
1521          * (a query on the linux-mmc mailing list didn't bring any replies).
1522          */
1523         cancel_delayed_work_sync(&host->timeout_work);
1524
1525         if (host->addr)
1526                 iounmap(host->addr);
1527
1528         irq[0] = platform_get_irq(pdev, 0);
1529         irq[1] = platform_get_irq(pdev, 1);
1530
1531         free_irq(irq[0], host);
1532         if (irq[1] >= 0)
1533                 free_irq(irq[1], host);
1534
1535         clk_disable_unprepare(host->hclk);
1536         mmc_free_host(host->mmc);
1537         pm_runtime_put_sync(&pdev->dev);
1538         pm_runtime_disable(&pdev->dev);
1539
1540         return 0;
1541 }
1542
1543 #ifdef CONFIG_PM_SLEEP
1544 static int sh_mmcif_suspend(struct device *dev)
1545 {
1546         struct sh_mmcif_host *host = dev_get_drvdata(dev);
1547
1548         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1549
1550         return 0;
1551 }
1552
1553 static int sh_mmcif_resume(struct device *dev)
1554 {
1555         return 0;
1556 }
1557 #endif
1558
1559 static const struct of_device_id mmcif_of_match[] = {
1560         { .compatible = "renesas,sh-mmcif" },
1561         { }
1562 };
1563 MODULE_DEVICE_TABLE(of, mmcif_of_match);
1564
1565 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1566         SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume)
1567 };
1568
1569 static struct platform_driver sh_mmcif_driver = {
1570         .probe          = sh_mmcif_probe,
1571         .remove         = sh_mmcif_remove,
1572         .driver         = {
1573                 .name   = DRIVER_NAME,
1574                 .pm     = &sh_mmcif_dev_pm_ops,
1575                 .owner  = THIS_MODULE,
1576                 .of_match_table = mmcif_of_match,
1577         },
1578 };
1579
1580 module_platform_driver(sh_mmcif_driver);
1581
1582 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1583 MODULE_LICENSE("GPL");
1584 MODULE_ALIAS("platform:" DRIVER_NAME);
1585 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");