2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/ktime.h>
18 #include <linux/highmem.h>
20 #include <linux/module.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/scatterlist.h>
24 #include <linux/sizes.h>
25 #include <linux/swiotlb.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/pm_runtime.h>
30 #include <linux/leds.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/card.h>
35 #include <linux/mmc/sdio.h>
36 #include <linux/mmc/slot-gpio.h>
40 #define DRIVER_NAME "sdhci"
42 #define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
45 #define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
48 #define MAX_TUNING_LOOP 40
50 static unsigned int debug_quirks = 0;
51 static unsigned int debug_quirks2;
53 static void sdhci_finish_data(struct sdhci_host *);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57 void sdhci_dumpregs(struct sdhci_host *host)
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
116 SDHCI_DUMP("============================================\n");
118 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
120 /*****************************************************************************\
122 * Low level functions *
124 \*****************************************************************************/
126 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
128 return cmd->data || cmd->flags & MMC_RSP_BUSY;
131 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
135 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
136 !mmc_card_is_removable(host->mmc))
140 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
143 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
144 SDHCI_INT_CARD_INSERT;
146 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
149 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
150 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
153 static void sdhci_enable_card_detection(struct sdhci_host *host)
155 sdhci_set_card_detection(host, true);
158 static void sdhci_disable_card_detection(struct sdhci_host *host)
160 sdhci_set_card_detection(host, false);
163 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
168 pm_runtime_get_noresume(host->mmc->parent);
171 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
175 host->bus_on = false;
176 pm_runtime_put_noidle(host->mmc->parent);
179 void sdhci_reset(struct sdhci_host *host, u8 mask)
183 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
185 if (mask & SDHCI_RESET_ALL) {
187 /* Reset-all turns off SD Bus Power */
188 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
189 sdhci_runtime_pm_bus_off(host);
192 /* Wait max 100 ms */
193 timeout = ktime_add_ms(ktime_get(), 100);
195 /* hw clears the bit when it's done */
197 bool timedout = ktime_after(ktime_get(), timeout);
199 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
202 pr_err("%s: Reset 0x%x never completed.\n",
203 mmc_hostname(host->mmc), (int)mask);
204 sdhci_dumpregs(host);
210 EXPORT_SYMBOL_GPL(sdhci_reset);
212 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
214 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
215 struct mmc_host *mmc = host->mmc;
217 if (!mmc->ops->get_cd(mmc))
221 host->ops->reset(host, mask);
223 if (mask & SDHCI_RESET_ALL) {
224 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
225 if (host->ops->enable_dma)
226 host->ops->enable_dma(host);
229 /* Resetting the controller clears many */
230 host->preset_enabled = false;
234 static void sdhci_set_default_irqs(struct sdhci_host *host)
236 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
237 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
238 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
239 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
242 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
243 host->tuning_mode == SDHCI_TUNING_MODE_3)
244 host->ier |= SDHCI_INT_RETUNE;
246 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
247 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
250 static void sdhci_init(struct sdhci_host *host, int soft)
252 struct mmc_host *mmc = host->mmc;
255 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
257 sdhci_do_reset(host, SDHCI_RESET_ALL);
259 sdhci_set_default_irqs(host);
261 host->cqe_on = false;
264 /* force clock reconfiguration */
266 mmc->ops->set_ios(mmc, &mmc->ios);
270 static void sdhci_reinit(struct sdhci_host *host)
273 sdhci_enable_card_detection(host);
276 static void __sdhci_led_activate(struct sdhci_host *host)
280 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
281 ctrl |= SDHCI_CTRL_LED;
282 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
285 static void __sdhci_led_deactivate(struct sdhci_host *host)
289 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
290 ctrl &= ~SDHCI_CTRL_LED;
291 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
294 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
295 static void sdhci_led_control(struct led_classdev *led,
296 enum led_brightness brightness)
298 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
301 spin_lock_irqsave(&host->lock, flags);
303 if (host->runtime_suspended)
306 if (brightness == LED_OFF)
307 __sdhci_led_deactivate(host);
309 __sdhci_led_activate(host);
311 spin_unlock_irqrestore(&host->lock, flags);
314 static int sdhci_led_register(struct sdhci_host *host)
316 struct mmc_host *mmc = host->mmc;
318 snprintf(host->led_name, sizeof(host->led_name),
319 "%s::", mmc_hostname(mmc));
321 host->led.name = host->led_name;
322 host->led.brightness = LED_OFF;
323 host->led.default_trigger = mmc_hostname(mmc);
324 host->led.brightness_set = sdhci_led_control;
326 return led_classdev_register(mmc_dev(mmc), &host->led);
329 static void sdhci_led_unregister(struct sdhci_host *host)
331 led_classdev_unregister(&host->led);
334 static inline void sdhci_led_activate(struct sdhci_host *host)
338 static inline void sdhci_led_deactivate(struct sdhci_host *host)
344 static inline int sdhci_led_register(struct sdhci_host *host)
349 static inline void sdhci_led_unregister(struct sdhci_host *host)
353 static inline void sdhci_led_activate(struct sdhci_host *host)
355 __sdhci_led_activate(host);
358 static inline void sdhci_led_deactivate(struct sdhci_host *host)
360 __sdhci_led_deactivate(host);
365 /*****************************************************************************\
369 \*****************************************************************************/
371 static void sdhci_read_block_pio(struct sdhci_host *host)
374 size_t blksize, len, chunk;
375 u32 uninitialized_var(scratch);
378 DBG("PIO reading\n");
380 blksize = host->data->blksz;
383 local_irq_save(flags);
386 BUG_ON(!sg_miter_next(&host->sg_miter));
388 len = min(host->sg_miter.length, blksize);
391 host->sg_miter.consumed = len;
393 buf = host->sg_miter.addr;
397 scratch = sdhci_readl(host, SDHCI_BUFFER);
401 *buf = scratch & 0xFF;
410 sg_miter_stop(&host->sg_miter);
412 local_irq_restore(flags);
415 static void sdhci_write_block_pio(struct sdhci_host *host)
418 size_t blksize, len, chunk;
422 DBG("PIO writing\n");
424 blksize = host->data->blksz;
428 local_irq_save(flags);
431 BUG_ON(!sg_miter_next(&host->sg_miter));
433 len = min(host->sg_miter.length, blksize);
436 host->sg_miter.consumed = len;
438 buf = host->sg_miter.addr;
441 scratch |= (u32)*buf << (chunk * 8);
447 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
448 sdhci_writel(host, scratch, SDHCI_BUFFER);
455 sg_miter_stop(&host->sg_miter);
457 local_irq_restore(flags);
460 static void sdhci_transfer_pio(struct sdhci_host *host)
464 if (host->blocks == 0)
467 if (host->data->flags & MMC_DATA_READ)
468 mask = SDHCI_DATA_AVAILABLE;
470 mask = SDHCI_SPACE_AVAILABLE;
473 * Some controllers (JMicron JMB38x) mess up the buffer bits
474 * for transfers < 4 bytes. As long as it is just one block,
475 * we can ignore the bits.
477 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
478 (host->data->blocks == 1))
481 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
482 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
485 if (host->data->flags & MMC_DATA_READ)
486 sdhci_read_block_pio(host);
488 sdhci_write_block_pio(host);
491 if (host->blocks == 0)
495 DBG("PIO transfer complete.\n");
498 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
499 struct mmc_data *data, int cookie)
504 * If the data buffers are already mapped, return the previous
505 * dma_map_sg() result.
507 if (data->host_cookie == COOKIE_PRE_MAPPED)
508 return data->sg_count;
510 /* Bounce write requests to the bounce buffer */
511 if (host->bounce_buffer) {
512 unsigned int length = data->blksz * data->blocks;
514 if (length > host->bounce_buffer_size) {
515 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
516 mmc_hostname(host->mmc), length,
517 host->bounce_buffer_size);
520 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
521 /* Copy the data to the bounce buffer */
522 sg_copy_to_buffer(data->sg, data->sg_len,
526 /* Switch ownership to the DMA */
527 dma_sync_single_for_device(host->mmc->parent,
529 host->bounce_buffer_size,
530 mmc_get_dma_dir(data));
531 /* Just a dummy value */
534 /* Just access the data directly from memory */
535 sg_count = dma_map_sg(mmc_dev(host->mmc),
536 data->sg, data->sg_len,
537 mmc_get_dma_dir(data));
543 data->sg_count = sg_count;
544 data->host_cookie = cookie;
549 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
551 local_irq_save(*flags);
552 return kmap_atomic(sg_page(sg)) + sg->offset;
555 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
557 kunmap_atomic(buffer);
558 local_irq_restore(*flags);
561 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
562 dma_addr_t addr, int len, unsigned cmd)
564 struct sdhci_adma2_64_desc *dma_desc = desc;
566 /* 32-bit and 64-bit descriptors have these members in same position */
567 dma_desc->cmd = cpu_to_le16(cmd);
568 dma_desc->len = cpu_to_le16(len);
569 dma_desc->addr_lo = cpu_to_le32((u32)addr);
571 if (host->flags & SDHCI_USE_64_BIT_DMA)
572 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
575 static void sdhci_adma_mark_end(void *desc)
577 struct sdhci_adma2_64_desc *dma_desc = desc;
579 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
580 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
583 static void sdhci_adma_table_pre(struct sdhci_host *host,
584 struct mmc_data *data, int sg_count)
586 struct scatterlist *sg;
588 dma_addr_t addr, align_addr;
594 * The spec does not specify endianness of descriptor table.
595 * We currently guess that it is LE.
598 host->sg_count = sg_count;
600 desc = host->adma_table;
601 align = host->align_buffer;
603 align_addr = host->align_addr;
605 for_each_sg(data->sg, sg, host->sg_count, i) {
606 addr = sg_dma_address(sg);
607 len = sg_dma_len(sg);
610 * The SDHCI specification states that ADMA addresses must
611 * be 32-bit aligned. If they aren't, then we use a bounce
612 * buffer for the (up to three) bytes that screw up the
615 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
618 if (data->flags & MMC_DATA_WRITE) {
619 buffer = sdhci_kmap_atomic(sg, &flags);
620 memcpy(align, buffer, offset);
621 sdhci_kunmap_atomic(buffer, &flags);
625 sdhci_adma_write_desc(host, desc, align_addr, offset,
628 BUG_ON(offset > 65536);
630 align += SDHCI_ADMA2_ALIGN;
631 align_addr += SDHCI_ADMA2_ALIGN;
633 desc += host->desc_sz;
643 sdhci_adma_write_desc(host, desc, addr, len,
645 desc += host->desc_sz;
649 * If this triggers then we have a calculation bug
652 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
655 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
656 /* Mark the last descriptor as the terminating descriptor */
657 if (desc != host->adma_table) {
658 desc -= host->desc_sz;
659 sdhci_adma_mark_end(desc);
662 /* Add a terminating entry - nop, end, valid */
663 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
667 static void sdhci_adma_table_post(struct sdhci_host *host,
668 struct mmc_data *data)
670 struct scatterlist *sg;
676 if (data->flags & MMC_DATA_READ) {
677 bool has_unaligned = false;
679 /* Do a quick scan of the SG list for any unaligned mappings */
680 for_each_sg(data->sg, sg, host->sg_count, i)
681 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
682 has_unaligned = true;
687 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
688 data->sg_len, DMA_FROM_DEVICE);
690 align = host->align_buffer;
692 for_each_sg(data->sg, sg, host->sg_count, i) {
693 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
694 size = SDHCI_ADMA2_ALIGN -
695 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
697 buffer = sdhci_kmap_atomic(sg, &flags);
698 memcpy(buffer, align, size);
699 sdhci_kunmap_atomic(buffer, &flags);
701 align += SDHCI_ADMA2_ALIGN;
708 static u32 sdhci_sdma_address(struct sdhci_host *host)
710 if (host->bounce_buffer)
711 return host->bounce_addr;
713 return sg_dma_address(host->data->sg);
716 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
717 struct mmc_command *cmd,
718 struct mmc_data *data)
720 unsigned int target_timeout;
724 target_timeout = cmd->busy_timeout * 1000;
726 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
727 if (host->clock && data->timeout_clks) {
728 unsigned long long val;
731 * data->timeout_clks is in units of clock cycles.
732 * host->clock is in Hz. target_timeout is in us.
733 * Hence, us = 1000000 * cycles / Hz. Round up.
735 val = 1000000ULL * data->timeout_clks;
736 if (do_div(val, host->clock))
738 target_timeout += val;
742 return target_timeout;
745 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
746 struct mmc_command *cmd)
748 struct mmc_data *data = cmd->data;
749 struct mmc_host *mmc = host->mmc;
750 struct mmc_ios *ios = &mmc->ios;
751 unsigned char bus_width = 1 << ios->bus_width;
757 target_timeout = sdhci_target_timeout(host, cmd, data);
758 target_timeout *= NSEC_PER_USEC;
762 freq = host->mmc->actual_clock ? : host->clock;
763 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
764 do_div(transfer_time, freq);
765 /* multiply by '2' to account for any unknowns */
766 transfer_time = transfer_time * 2;
767 /* calculate timeout for the entire data */
768 host->data_timeout = data->blocks * target_timeout +
771 host->data_timeout = target_timeout;
774 if (host->data_timeout)
775 host->data_timeout += MMC_CMD_TRANSFER_TIME;
778 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
782 struct mmc_data *data = cmd->data;
783 unsigned target_timeout, current_timeout;
788 * If the host controller provides us with an incorrect timeout
789 * value, just skip the check and use 0xE. The hardware may take
790 * longer to time out, but that's much better than having a too-short
793 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
796 /* Unspecified timeout, assume max */
797 if (!data && !cmd->busy_timeout)
801 target_timeout = sdhci_target_timeout(host, cmd, data);
804 * Figure out needed cycles.
805 * We do this in steps in order to fit inside a 32 bit int.
806 * The first step is the minimum timeout, which will have a
807 * minimum resolution of 6 bits:
808 * (1) 2^13*1000 > 2^22,
809 * (2) host->timeout_clk < 2^16
814 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
815 while (current_timeout < target_timeout) {
817 current_timeout <<= 1;
823 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
824 DBG("Too large timeout 0x%x requested for CMD%d!\n",
834 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
836 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
837 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
839 if (host->flags & SDHCI_REQ_USE_DMA)
840 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
842 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
844 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
845 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
847 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
849 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
850 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
853 static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
856 host->ier |= SDHCI_INT_DATA_TIMEOUT;
858 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
859 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
860 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
863 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
867 if (host->ops->set_timeout) {
868 host->ops->set_timeout(host, cmd);
870 bool too_big = false;
872 count = sdhci_calc_timeout(host, cmd, &too_big);
875 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
876 sdhci_calc_sw_timeout(host, cmd);
877 sdhci_set_data_timeout_irq(host, false);
878 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
879 sdhci_set_data_timeout_irq(host, true);
882 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
886 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
889 struct mmc_data *data = cmd->data;
891 host->data_timeout = 0;
893 if (sdhci_data_line_cmd(cmd))
894 sdhci_set_timeout(host, cmd);
902 BUG_ON(data->blksz * data->blocks > 524288);
903 BUG_ON(data->blksz > host->mmc->max_blk_size);
904 BUG_ON(data->blocks > 65535);
907 host->data_early = 0;
908 host->data->bytes_xfered = 0;
910 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
911 struct scatterlist *sg;
912 unsigned int length_mask, offset_mask;
915 host->flags |= SDHCI_REQ_USE_DMA;
918 * FIXME: This doesn't account for merging when mapping the
921 * The assumption here being that alignment and lengths are
922 * the same after DMA mapping to device address space.
926 if (host->flags & SDHCI_USE_ADMA) {
927 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
930 * As we use up to 3 byte chunks to work
931 * around alignment problems, we need to
932 * check the offset as well.
937 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
939 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
943 if (unlikely(length_mask | offset_mask)) {
944 for_each_sg(data->sg, sg, data->sg_len, i) {
945 if (sg->length & length_mask) {
946 DBG("Reverting to PIO because of transfer size (%d)\n",
948 host->flags &= ~SDHCI_REQ_USE_DMA;
951 if (sg->offset & offset_mask) {
952 DBG("Reverting to PIO because of bad alignment\n");
953 host->flags &= ~SDHCI_REQ_USE_DMA;
960 if (host->flags & SDHCI_REQ_USE_DMA) {
961 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
965 * This only happens when someone fed
966 * us an invalid request.
969 host->flags &= ~SDHCI_REQ_USE_DMA;
970 } else if (host->flags & SDHCI_USE_ADMA) {
971 sdhci_adma_table_pre(host, data, sg_cnt);
973 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
974 if (host->flags & SDHCI_USE_64_BIT_DMA)
976 (u64)host->adma_addr >> 32,
977 SDHCI_ADMA_ADDRESS_HI);
979 WARN_ON(sg_cnt != 1);
980 sdhci_writel(host, sdhci_sdma_address(host),
986 * Always adjust the DMA selection as some controllers
987 * (e.g. JMicron) can't do PIO properly when the selection
990 if (host->version >= SDHCI_SPEC_200) {
991 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
992 ctrl &= ~SDHCI_CTRL_DMA_MASK;
993 if ((host->flags & SDHCI_REQ_USE_DMA) &&
994 (host->flags & SDHCI_USE_ADMA)) {
995 if (host->flags & SDHCI_USE_64_BIT_DMA)
996 ctrl |= SDHCI_CTRL_ADMA64;
998 ctrl |= SDHCI_CTRL_ADMA32;
1000 ctrl |= SDHCI_CTRL_SDMA;
1002 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1005 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1008 flags = SG_MITER_ATOMIC;
1009 if (host->data->flags & MMC_DATA_READ)
1010 flags |= SG_MITER_TO_SG;
1012 flags |= SG_MITER_FROM_SG;
1013 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1014 host->blocks = data->blocks;
1017 sdhci_set_transfer_irqs(host);
1019 /* Set the DMA boundary value and block size */
1020 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1022 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1025 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1026 struct mmc_request *mrq)
1028 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1029 !mrq->cap_cmd_during_tfr;
1032 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1033 struct mmc_command *cmd)
1036 struct mmc_data *data = cmd->data;
1040 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1041 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1042 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1043 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1045 /* clear Auto CMD settings for no data CMDs */
1046 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1047 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1048 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1053 WARN_ON(!host->data);
1055 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1056 mode = SDHCI_TRNS_BLK_CNT_EN;
1058 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1059 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1061 * If we are sending CMD23, CMD12 never gets sent
1062 * on successful completion (so no Auto-CMD12).
1064 if (sdhci_auto_cmd12(host, cmd->mrq) &&
1065 (cmd->opcode != SD_IO_RW_EXTENDED))
1066 mode |= SDHCI_TRNS_AUTO_CMD12;
1067 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
1068 mode |= SDHCI_TRNS_AUTO_CMD23;
1069 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1073 if (data->flags & MMC_DATA_READ)
1074 mode |= SDHCI_TRNS_READ;
1075 if (host->flags & SDHCI_REQ_USE_DMA)
1076 mode |= SDHCI_TRNS_DMA;
1078 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1081 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1083 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1084 ((mrq->cmd && mrq->cmd->error) ||
1085 (mrq->sbc && mrq->sbc->error) ||
1086 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1087 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1090 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1094 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1095 if (host->mrqs_done[i] == mrq) {
1101 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1102 if (!host->mrqs_done[i]) {
1103 host->mrqs_done[i] = mrq;
1108 WARN_ON(i >= SDHCI_MAX_MRQS);
1110 tasklet_schedule(&host->finish_tasklet);
1113 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1115 if (host->cmd && host->cmd->mrq == mrq)
1118 if (host->data_cmd && host->data_cmd->mrq == mrq)
1119 host->data_cmd = NULL;
1121 if (host->data && host->data->mrq == mrq)
1124 if (sdhci_needs_reset(host, mrq))
1125 host->pending_reset = true;
1127 __sdhci_finish_mrq(host, mrq);
1130 static void sdhci_finish_data(struct sdhci_host *host)
1132 struct mmc_command *data_cmd = host->data_cmd;
1133 struct mmc_data *data = host->data;
1136 host->data_cmd = NULL;
1139 * The controller needs a reset of internal state machines upon error
1143 if (!host->cmd || host->cmd == data_cmd)
1144 sdhci_do_reset(host, SDHCI_RESET_CMD);
1145 sdhci_do_reset(host, SDHCI_RESET_DATA);
1148 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1149 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1150 sdhci_adma_table_post(host, data);
1153 * The specification states that the block count register must
1154 * be updated, but it does not specify at what point in the
1155 * data flow. That makes the register entirely useless to read
1156 * back so we have to assume that nothing made it to the card
1157 * in the event of an error.
1160 data->bytes_xfered = 0;
1162 data->bytes_xfered = data->blksz * data->blocks;
1165 * Need to send CMD12 if -
1166 * a) open-ended multiblock transfer (no CMD23)
1167 * b) error in multiblock transfer
1173 * 'cap_cmd_during_tfr' request must not use the command line
1174 * after mmc_command_done() has been called. It is upper layer's
1175 * responsibility to send the stop command if required.
1177 if (data->mrq->cap_cmd_during_tfr) {
1178 sdhci_finish_mrq(host, data->mrq);
1180 /* Avoid triggering warning in sdhci_send_command() */
1182 sdhci_send_command(host, data->stop);
1185 sdhci_finish_mrq(host, data->mrq);
1189 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1190 unsigned long timeout)
1192 if (sdhci_data_line_cmd(mrq->cmd))
1193 mod_timer(&host->data_timer, timeout);
1195 mod_timer(&host->timer, timeout);
1198 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1200 if (sdhci_data_line_cmd(mrq->cmd))
1201 del_timer(&host->data_timer);
1203 del_timer(&host->timer);
1206 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1210 unsigned long timeout;
1214 /* Initially, a command has no error */
1217 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1218 cmd->opcode == MMC_STOP_TRANSMISSION)
1219 cmd->flags |= MMC_RSP_BUSY;
1221 /* Wait max 10 ms */
1224 mask = SDHCI_CMD_INHIBIT;
1225 if (sdhci_data_line_cmd(cmd))
1226 mask |= SDHCI_DATA_INHIBIT;
1228 /* We shouldn't wait for data inihibit for stop commands, even
1229 though they might use busy signaling */
1230 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1231 mask &= ~SDHCI_DATA_INHIBIT;
1233 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1235 pr_err("%s: Controller never released inhibit bit(s).\n",
1236 mmc_hostname(host->mmc));
1237 sdhci_dumpregs(host);
1239 sdhci_finish_mrq(host, cmd->mrq);
1247 if (sdhci_data_line_cmd(cmd)) {
1248 WARN_ON(host->data_cmd);
1249 host->data_cmd = cmd;
1252 sdhci_prepare_data(host, cmd);
1254 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1256 sdhci_set_transfer_mode(host, cmd);
1258 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1259 pr_err("%s: Unsupported response type!\n",
1260 mmc_hostname(host->mmc));
1261 cmd->error = -EINVAL;
1262 sdhci_finish_mrq(host, cmd->mrq);
1266 if (!(cmd->flags & MMC_RSP_PRESENT))
1267 flags = SDHCI_CMD_RESP_NONE;
1268 else if (cmd->flags & MMC_RSP_136)
1269 flags = SDHCI_CMD_RESP_LONG;
1270 else if (cmd->flags & MMC_RSP_BUSY)
1271 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1273 flags = SDHCI_CMD_RESP_SHORT;
1275 if (cmd->flags & MMC_RSP_CRC)
1276 flags |= SDHCI_CMD_CRC;
1277 if (cmd->flags & MMC_RSP_OPCODE)
1278 flags |= SDHCI_CMD_INDEX;
1280 /* CMD19 is special in that the Data Present Select should be set */
1281 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1282 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1283 flags |= SDHCI_CMD_DATA;
1286 if (host->data_timeout)
1287 timeout += nsecs_to_jiffies(host->data_timeout);
1288 else if (!cmd->data && cmd->busy_timeout > 9000)
1289 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1292 sdhci_mod_timer(host, cmd->mrq, timeout);
1294 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1296 EXPORT_SYMBOL_GPL(sdhci_send_command);
1298 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1302 for (i = 0; i < 4; i++) {
1303 reg = SDHCI_RESPONSE + (3 - i) * 4;
1304 cmd->resp[i] = sdhci_readl(host, reg);
1307 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1310 /* CRC is stripped so we need to do some shifting */
1311 for (i = 0; i < 4; i++) {
1314 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1318 static void sdhci_finish_command(struct sdhci_host *host)
1320 struct mmc_command *cmd = host->cmd;
1324 if (cmd->flags & MMC_RSP_PRESENT) {
1325 if (cmd->flags & MMC_RSP_136) {
1326 sdhci_read_rsp_136(host, cmd);
1328 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1332 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1333 mmc_command_done(host->mmc, cmd->mrq);
1336 * The host can send and interrupt when the busy state has
1337 * ended, allowing us to wait without wasting CPU cycles.
1338 * The busy signal uses DAT0 so this is similar to waiting
1339 * for data to complete.
1341 * Note: The 1.0 specification is a bit ambiguous about this
1342 * feature so there might be some problems with older
1345 if (cmd->flags & MMC_RSP_BUSY) {
1347 DBG("Cannot wait for busy signal when also doing a data transfer");
1348 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1349 cmd == host->data_cmd) {
1350 /* Command complete before busy is ended */
1355 /* Finished CMD23, now send actual command. */
1356 if (cmd == cmd->mrq->sbc) {
1357 sdhci_send_command(host, cmd->mrq->cmd);
1360 /* Processed actual command. */
1361 if (host->data && host->data_early)
1362 sdhci_finish_data(host);
1365 sdhci_finish_mrq(host, cmd->mrq);
1369 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1373 switch (host->timing) {
1374 case MMC_TIMING_UHS_SDR12:
1375 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1377 case MMC_TIMING_UHS_SDR25:
1378 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1380 case MMC_TIMING_UHS_SDR50:
1381 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1383 case MMC_TIMING_UHS_SDR104:
1384 case MMC_TIMING_MMC_HS200:
1385 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1387 case MMC_TIMING_UHS_DDR50:
1388 case MMC_TIMING_MMC_DDR52:
1389 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1391 case MMC_TIMING_MMC_HS400:
1392 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1395 pr_warn("%s: Invalid UHS-I mode selected\n",
1396 mmc_hostname(host->mmc));
1397 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1403 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1404 unsigned int *actual_clock)
1406 int div = 0; /* Initialized for compiler warning */
1407 int real_div = div, clk_mul = 1;
1409 bool switch_base_clk = false;
1411 if (host->version >= SDHCI_SPEC_300) {
1412 if (host->preset_enabled) {
1415 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1416 pre_val = sdhci_get_preset_value(host);
1417 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1418 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1419 if (host->clk_mul &&
1420 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1421 clk = SDHCI_PROG_CLOCK_MODE;
1423 clk_mul = host->clk_mul;
1425 real_div = max_t(int, 1, div << 1);
1431 * Check if the Host Controller supports Programmable Clock
1434 if (host->clk_mul) {
1435 for (div = 1; div <= 1024; div++) {
1436 if ((host->max_clk * host->clk_mul / div)
1440 if ((host->max_clk * host->clk_mul / div) <= clock) {
1442 * Set Programmable Clock Mode in the Clock
1445 clk = SDHCI_PROG_CLOCK_MODE;
1447 clk_mul = host->clk_mul;
1451 * Divisor can be too small to reach clock
1452 * speed requirement. Then use the base clock.
1454 switch_base_clk = true;
1458 if (!host->clk_mul || switch_base_clk) {
1459 /* Version 3.00 divisors must be a multiple of 2. */
1460 if (host->max_clk <= clock)
1463 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1465 if ((host->max_clk / div) <= clock)
1471 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1472 && !div && host->max_clk <= 25000000)
1476 /* Version 2.00 divisors must be a power of 2. */
1477 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1478 if ((host->max_clk / div) <= clock)
1487 *actual_clock = (host->max_clk * clk_mul) / real_div;
1488 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1489 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1490 << SDHCI_DIVIDER_HI_SHIFT;
1494 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1496 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1500 clk |= SDHCI_CLOCK_INT_EN;
1501 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1503 /* Wait max 20 ms */
1504 timeout = ktime_add_ms(ktime_get(), 20);
1506 bool timedout = ktime_after(ktime_get(), timeout);
1508 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1509 if (clk & SDHCI_CLOCK_INT_STABLE)
1512 pr_err("%s: Internal clock never stabilised.\n",
1513 mmc_hostname(host->mmc));
1514 sdhci_dumpregs(host);
1520 clk |= SDHCI_CLOCK_CARD_EN;
1521 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1523 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1525 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1529 host->mmc->actual_clock = 0;
1531 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1536 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1537 sdhci_enable_clk(host, clk);
1539 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1541 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1544 struct mmc_host *mmc = host->mmc;
1546 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1548 if (mode != MMC_POWER_OFF)
1549 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1551 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1554 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1559 if (mode != MMC_POWER_OFF) {
1561 case MMC_VDD_165_195:
1563 * Without a regulator, SDHCI does not support 2.0v
1564 * so we only get here if the driver deliberately
1565 * added the 2.0v range to ocr_avail. Map it to 1.8v
1566 * for the purpose of turning on the power.
1569 pwr = SDHCI_POWER_180;
1573 pwr = SDHCI_POWER_300;
1577 pwr = SDHCI_POWER_330;
1580 WARN(1, "%s: Invalid vdd %#x\n",
1581 mmc_hostname(host->mmc), vdd);
1586 if (host->pwr == pwr)
1592 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1593 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1594 sdhci_runtime_pm_bus_off(host);
1597 * Spec says that we should clear the power reg before setting
1598 * a new value. Some controllers don't seem to like this though.
1600 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1601 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1604 * At least the Marvell CaFe chip gets confused if we set the
1605 * voltage and set turn on power at the same time, so set the
1608 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1609 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1611 pwr |= SDHCI_POWER_ON;
1613 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1615 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1616 sdhci_runtime_pm_bus_on(host);
1619 * Some controllers need an extra 10ms delay of 10ms before
1620 * they can apply clock after applying power
1622 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1626 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1628 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1631 if (IS_ERR(host->mmc->supply.vmmc))
1632 sdhci_set_power_noreg(host, mode, vdd);
1634 sdhci_set_power_reg(host, mode, vdd);
1636 EXPORT_SYMBOL_GPL(sdhci_set_power);
1638 /*****************************************************************************\
1642 \*****************************************************************************/
1644 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1646 struct sdhci_host *host;
1648 unsigned long flags;
1650 host = mmc_priv(mmc);
1652 /* Firstly check card presence */
1653 present = mmc->ops->get_cd(mmc);
1655 spin_lock_irqsave(&host->lock, flags);
1657 sdhci_led_activate(host);
1660 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1661 * requests if Auto-CMD12 is enabled.
1663 if (sdhci_auto_cmd12(host, mrq)) {
1665 mrq->data->stop = NULL;
1670 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1671 mrq->cmd->error = -ENOMEDIUM;
1672 sdhci_finish_mrq(host, mrq);
1674 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1675 sdhci_send_command(host, mrq->sbc);
1677 sdhci_send_command(host, mrq->cmd);
1681 spin_unlock_irqrestore(&host->lock, flags);
1684 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1688 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1689 if (width == MMC_BUS_WIDTH_8) {
1690 ctrl &= ~SDHCI_CTRL_4BITBUS;
1691 ctrl |= SDHCI_CTRL_8BITBUS;
1693 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1694 ctrl &= ~SDHCI_CTRL_8BITBUS;
1695 if (width == MMC_BUS_WIDTH_4)
1696 ctrl |= SDHCI_CTRL_4BITBUS;
1698 ctrl &= ~SDHCI_CTRL_4BITBUS;
1700 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1702 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1704 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1708 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1709 /* Select Bus Speed Mode for host */
1710 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1711 if ((timing == MMC_TIMING_MMC_HS200) ||
1712 (timing == MMC_TIMING_UHS_SDR104))
1713 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1714 else if (timing == MMC_TIMING_UHS_SDR12)
1715 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1716 else if (timing == MMC_TIMING_UHS_SDR25)
1717 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1718 else if (timing == MMC_TIMING_UHS_SDR50)
1719 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1720 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1721 (timing == MMC_TIMING_MMC_DDR52))
1722 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1723 else if (timing == MMC_TIMING_MMC_HS400)
1724 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1725 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1727 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1729 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1731 struct sdhci_host *host = mmc_priv(mmc);
1734 if (ios->power_mode == MMC_POWER_UNDEFINED)
1737 if (host->flags & SDHCI_DEVICE_DEAD) {
1738 if (!IS_ERR(mmc->supply.vmmc) &&
1739 ios->power_mode == MMC_POWER_OFF)
1740 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1745 * Reset the chip on each power off.
1746 * Should clear out any weird states.
1748 if (ios->power_mode == MMC_POWER_OFF) {
1749 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1753 if (host->version >= SDHCI_SPEC_300 &&
1754 (ios->power_mode == MMC_POWER_UP) &&
1755 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1756 sdhci_enable_preset_value(host, false);
1758 if (!ios->clock || ios->clock != host->clock) {
1759 host->ops->set_clock(host, ios->clock);
1760 host->clock = ios->clock;
1762 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1764 host->timeout_clk = host->mmc->actual_clock ?
1765 host->mmc->actual_clock / 1000 :
1767 host->mmc->max_busy_timeout =
1768 host->ops->get_max_timeout_count ?
1769 host->ops->get_max_timeout_count(host) :
1771 host->mmc->max_busy_timeout /= host->timeout_clk;
1775 if (host->ops->set_power)
1776 host->ops->set_power(host, ios->power_mode, ios->vdd);
1778 sdhci_set_power(host, ios->power_mode, ios->vdd);
1780 if (host->ops->platform_send_init_74_clocks)
1781 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1783 host->ops->set_bus_width(host, ios->bus_width);
1785 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1787 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1788 if (ios->timing == MMC_TIMING_SD_HS ||
1789 ios->timing == MMC_TIMING_MMC_HS ||
1790 ios->timing == MMC_TIMING_MMC_HS400 ||
1791 ios->timing == MMC_TIMING_MMC_HS200 ||
1792 ios->timing == MMC_TIMING_MMC_DDR52 ||
1793 ios->timing == MMC_TIMING_UHS_SDR50 ||
1794 ios->timing == MMC_TIMING_UHS_SDR104 ||
1795 ios->timing == MMC_TIMING_UHS_DDR50 ||
1796 ios->timing == MMC_TIMING_UHS_SDR25)
1797 ctrl |= SDHCI_CTRL_HISPD;
1799 ctrl &= ~SDHCI_CTRL_HISPD;
1802 if (host->version >= SDHCI_SPEC_300) {
1805 if (!host->preset_enabled) {
1806 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1808 * We only need to set Driver Strength if the
1809 * preset value enable is not set.
1811 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1812 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1813 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1814 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1815 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1816 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1817 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1818 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1819 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1820 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1822 pr_warn("%s: invalid driver type, default to driver type B\n",
1824 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1827 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1830 * According to SDHC Spec v3.00, if the Preset Value
1831 * Enable in the Host Control 2 register is set, we
1832 * need to reset SD Clock Enable before changing High
1833 * Speed Enable to avoid generating clock gliches.
1836 /* Reset SD Clock Enable */
1837 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1838 clk &= ~SDHCI_CLOCK_CARD_EN;
1839 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1841 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1843 /* Re-enable SD Clock */
1844 host->ops->set_clock(host, host->clock);
1847 /* Reset SD Clock Enable */
1848 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1849 clk &= ~SDHCI_CLOCK_CARD_EN;
1850 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1852 host->ops->set_uhs_signaling(host, ios->timing);
1853 host->timing = ios->timing;
1855 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1856 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1857 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1858 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1859 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1860 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1861 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1864 sdhci_enable_preset_value(host, true);
1865 preset = sdhci_get_preset_value(host);
1866 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1867 >> SDHCI_PRESET_DRV_SHIFT;
1870 /* Re-enable SD Clock */
1871 host->ops->set_clock(host, host->clock);
1873 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1876 * Some (ENE) controllers go apeshit on some ios operation,
1877 * signalling timeout and CRC errors even on CMD0. Resetting
1878 * it on each ios seems to solve the problem.
1880 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1881 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1885 EXPORT_SYMBOL_GPL(sdhci_set_ios);
1887 static int sdhci_get_cd(struct mmc_host *mmc)
1889 struct sdhci_host *host = mmc_priv(mmc);
1890 int gpio_cd = mmc_gpio_get_cd(mmc);
1892 if (host->flags & SDHCI_DEVICE_DEAD)
1895 /* If nonremovable, assume that the card is always present. */
1896 if (!mmc_card_is_removable(host->mmc))
1900 * Try slot gpio detect, if defined it take precedence
1901 * over build in controller functionality
1906 /* If polling, assume that the card is always present. */
1907 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1910 /* Host native card detect */
1911 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1914 static int sdhci_check_ro(struct sdhci_host *host)
1916 unsigned long flags;
1919 spin_lock_irqsave(&host->lock, flags);
1921 if (host->flags & SDHCI_DEVICE_DEAD)
1923 else if (host->ops->get_ro)
1924 is_readonly = host->ops->get_ro(host);
1926 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1927 & SDHCI_WRITE_PROTECT);
1929 spin_unlock_irqrestore(&host->lock, flags);
1931 /* This quirk needs to be replaced by a callback-function later */
1932 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1933 !is_readonly : is_readonly;
1936 #define SAMPLE_COUNT 5
1938 static int sdhci_get_ro(struct mmc_host *mmc)
1940 struct sdhci_host *host = mmc_priv(mmc);
1943 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1944 return sdhci_check_ro(host);
1947 for (i = 0; i < SAMPLE_COUNT; i++) {
1948 if (sdhci_check_ro(host)) {
1949 if (++ro_count > SAMPLE_COUNT / 2)
1957 static void sdhci_hw_reset(struct mmc_host *mmc)
1959 struct sdhci_host *host = mmc_priv(mmc);
1961 if (host->ops && host->ops->hw_reset)
1962 host->ops->hw_reset(host);
1965 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1967 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1969 host->ier |= SDHCI_INT_CARD_INT;
1971 host->ier &= ~SDHCI_INT_CARD_INT;
1973 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1974 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1979 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1981 struct sdhci_host *host = mmc_priv(mmc);
1982 unsigned long flags;
1985 pm_runtime_get_noresume(host->mmc->parent);
1987 spin_lock_irqsave(&host->lock, flags);
1989 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1991 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1993 sdhci_enable_sdio_irq_nolock(host, enable);
1994 spin_unlock_irqrestore(&host->lock, flags);
1997 pm_runtime_put_noidle(host->mmc->parent);
1999 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2001 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2002 struct mmc_ios *ios)
2004 struct sdhci_host *host = mmc_priv(mmc);
2009 * Signal Voltage Switching is only applicable for Host Controllers
2012 if (host->version < SDHCI_SPEC_300)
2015 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2017 switch (ios->signal_voltage) {
2018 case MMC_SIGNAL_VOLTAGE_330:
2019 if (!(host->flags & SDHCI_SIGNALING_330))
2021 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2022 ctrl &= ~SDHCI_CTRL_VDD_180;
2023 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2025 if (!IS_ERR(mmc->supply.vqmmc)) {
2026 ret = mmc_regulator_set_vqmmc(mmc, ios);
2028 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2034 usleep_range(5000, 5500);
2036 /* 3.3V regulator output should be stable within 5 ms */
2037 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2038 if (!(ctrl & SDHCI_CTRL_VDD_180))
2041 pr_warn("%s: 3.3V regulator output did not became stable\n",
2045 case MMC_SIGNAL_VOLTAGE_180:
2046 if (!(host->flags & SDHCI_SIGNALING_180))
2048 if (!IS_ERR(mmc->supply.vqmmc)) {
2049 ret = mmc_regulator_set_vqmmc(mmc, ios);
2051 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2058 * Enable 1.8V Signal Enable in the Host Control2
2061 ctrl |= SDHCI_CTRL_VDD_180;
2062 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2064 /* Some controller need to do more when switching */
2065 if (host->ops->voltage_switch)
2066 host->ops->voltage_switch(host);
2068 /* 1.8V regulator output should be stable within 5 ms */
2069 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2070 if (ctrl & SDHCI_CTRL_VDD_180)
2073 pr_warn("%s: 1.8V regulator output did not became stable\n",
2077 case MMC_SIGNAL_VOLTAGE_120:
2078 if (!(host->flags & SDHCI_SIGNALING_120))
2080 if (!IS_ERR(mmc->supply.vqmmc)) {
2081 ret = mmc_regulator_set_vqmmc(mmc, ios);
2083 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2090 /* No signal voltage switch required */
2094 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2096 static int sdhci_card_busy(struct mmc_host *mmc)
2098 struct sdhci_host *host = mmc_priv(mmc);
2101 /* Check whether DAT[0] is 0 */
2102 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2104 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2107 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2109 struct sdhci_host *host = mmc_priv(mmc);
2110 unsigned long flags;
2112 spin_lock_irqsave(&host->lock, flags);
2113 host->flags |= SDHCI_HS400_TUNING;
2114 spin_unlock_irqrestore(&host->lock, flags);
2119 void sdhci_start_tuning(struct sdhci_host *host)
2123 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2124 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2125 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2126 ctrl |= SDHCI_CTRL_TUNED_CLK;
2127 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2130 * As per the Host Controller spec v3.00, tuning command
2131 * generates Buffer Read Ready interrupt, so enable that.
2133 * Note: The spec clearly says that when tuning sequence
2134 * is being performed, the controller does not generate
2135 * interrupts other than Buffer Read Ready interrupt. But
2136 * to make sure we don't hit a controller bug, we _only_
2137 * enable Buffer Read Ready interrupt here.
2139 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2140 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2142 EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2144 void sdhci_end_tuning(struct sdhci_host *host)
2146 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2147 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2149 EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2151 void sdhci_reset_tuning(struct sdhci_host *host)
2155 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2156 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2157 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2158 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2160 EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2162 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2164 sdhci_reset_tuning(host);
2166 sdhci_do_reset(host, SDHCI_RESET_CMD);
2167 sdhci_do_reset(host, SDHCI_RESET_DATA);
2169 sdhci_end_tuning(host);
2171 mmc_abort_tuning(host->mmc, opcode);
2175 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2176 * tuning command does not have a data payload (or rather the hardware does it
2177 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2178 * interrupt setup is different to other commands and there is no timeout
2179 * interrupt so special handling is needed.
2181 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2183 struct mmc_host *mmc = host->mmc;
2184 struct mmc_command cmd = {};
2185 struct mmc_request mrq = {};
2186 unsigned long flags;
2187 u32 b = host->sdma_boundary;
2189 spin_lock_irqsave(&host->lock, flags);
2191 cmd.opcode = opcode;
2192 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2197 * In response to CMD19, the card sends 64 bytes of tuning
2198 * block to the Host Controller. So we set the block size
2201 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2202 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2203 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2205 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2208 * The tuning block is sent by the card to the host controller.
2209 * So we set the TRNS_READ bit in the Transfer Mode register.
2210 * This also takes care of setting DMA Enable and Multi Block
2211 * Select in the same register to 0.
2213 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2215 sdhci_send_command(host, &cmd);
2219 sdhci_del_timer(host, &mrq);
2221 host->tuning_done = 0;
2224 spin_unlock_irqrestore(&host->lock, flags);
2226 /* Wait for Buffer Read Ready interrupt */
2227 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2228 msecs_to_jiffies(50));
2231 EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2233 static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2238 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2239 * of loops reaches 40 times.
2241 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2244 sdhci_send_tuning(host, opcode);
2246 if (!host->tuning_done) {
2247 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2248 mmc_hostname(host->mmc));
2249 sdhci_abort_tuning(host, opcode);
2253 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2254 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2255 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2256 return; /* Success! */
2260 /* Spec does not require a delay between tuning cycles */
2261 if (host->tuning_delay > 0)
2262 mdelay(host->tuning_delay);
2265 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2266 mmc_hostname(host->mmc));
2267 sdhci_reset_tuning(host);
2270 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2272 struct sdhci_host *host = mmc_priv(mmc);
2274 unsigned int tuning_count = 0;
2277 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2279 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2280 tuning_count = host->tuning_count;
2283 * The Host Controller needs tuning in case of SDR104 and DDR50
2284 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2285 * the Capabilities register.
2286 * If the Host Controller supports the HS200 mode then the
2287 * tuning function has to be executed.
2289 switch (host->timing) {
2290 /* HS400 tuning is done in HS200 mode */
2291 case MMC_TIMING_MMC_HS400:
2295 case MMC_TIMING_MMC_HS200:
2297 * Periodic re-tuning for HS400 is not expected to be needed, so
2304 case MMC_TIMING_UHS_SDR104:
2305 case MMC_TIMING_UHS_DDR50:
2308 case MMC_TIMING_UHS_SDR50:
2309 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2317 if (host->ops->platform_execute_tuning) {
2318 err = host->ops->platform_execute_tuning(host, opcode);
2322 host->mmc->retune_period = tuning_count;
2324 if (host->tuning_delay < 0)
2325 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2327 sdhci_start_tuning(host);
2329 __sdhci_execute_tuning(host, opcode);
2331 sdhci_end_tuning(host);
2333 host->flags &= ~SDHCI_HS400_TUNING;
2337 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2339 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2341 /* Host Controller v3.00 defines preset value registers */
2342 if (host->version < SDHCI_SPEC_300)
2346 * We only enable or disable Preset Value if they are not already
2347 * enabled or disabled respectively. Otherwise, we bail out.
2349 if (host->preset_enabled != enable) {
2350 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2353 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2355 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2357 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2360 host->flags |= SDHCI_PV_ENABLED;
2362 host->flags &= ~SDHCI_PV_ENABLED;
2364 host->preset_enabled = enable;
2368 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2371 struct sdhci_host *host = mmc_priv(mmc);
2372 struct mmc_data *data = mrq->data;
2374 if (data->host_cookie != COOKIE_UNMAPPED)
2375 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2376 mmc_get_dma_dir(data));
2378 data->host_cookie = COOKIE_UNMAPPED;
2381 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2383 struct sdhci_host *host = mmc_priv(mmc);
2385 mrq->data->host_cookie = COOKIE_UNMAPPED;
2388 * No pre-mapping in the pre hook if we're using the bounce buffer,
2389 * for that we would need two bounce buffers since one buffer is
2390 * in flight when this is getting called.
2392 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2393 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2396 static inline bool sdhci_has_requests(struct sdhci_host *host)
2398 return host->cmd || host->data_cmd;
2401 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2403 if (host->data_cmd) {
2404 host->data_cmd->error = err;
2405 sdhci_finish_mrq(host, host->data_cmd->mrq);
2409 host->cmd->error = err;
2410 sdhci_finish_mrq(host, host->cmd->mrq);
2414 static void sdhci_card_event(struct mmc_host *mmc)
2416 struct sdhci_host *host = mmc_priv(mmc);
2417 unsigned long flags;
2420 /* First check if client has provided their own card event */
2421 if (host->ops->card_event)
2422 host->ops->card_event(host);
2424 present = mmc->ops->get_cd(mmc);
2426 spin_lock_irqsave(&host->lock, flags);
2428 /* Check sdhci_has_requests() first in case we are runtime suspended */
2429 if (sdhci_has_requests(host) && !present) {
2430 pr_err("%s: Card removed during transfer!\n",
2431 mmc_hostname(host->mmc));
2432 pr_err("%s: Resetting controller.\n",
2433 mmc_hostname(host->mmc));
2435 sdhci_do_reset(host, SDHCI_RESET_CMD);
2436 sdhci_do_reset(host, SDHCI_RESET_DATA);
2438 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2441 spin_unlock_irqrestore(&host->lock, flags);
2444 static const struct mmc_host_ops sdhci_ops = {
2445 .request = sdhci_request,
2446 .post_req = sdhci_post_req,
2447 .pre_req = sdhci_pre_req,
2448 .set_ios = sdhci_set_ios,
2449 .get_cd = sdhci_get_cd,
2450 .get_ro = sdhci_get_ro,
2451 .hw_reset = sdhci_hw_reset,
2452 .enable_sdio_irq = sdhci_enable_sdio_irq,
2453 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2454 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2455 .execute_tuning = sdhci_execute_tuning,
2456 .card_event = sdhci_card_event,
2457 .card_busy = sdhci_card_busy,
2460 /*****************************************************************************\
2464 \*****************************************************************************/
2466 static bool sdhci_request_done(struct sdhci_host *host)
2468 unsigned long flags;
2469 struct mmc_request *mrq;
2472 spin_lock_irqsave(&host->lock, flags);
2474 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2475 mrq = host->mrqs_done[i];
2481 spin_unlock_irqrestore(&host->lock, flags);
2485 sdhci_del_timer(host, mrq);
2488 * Always unmap the data buffers if they were mapped by
2489 * sdhci_prepare_data() whenever we finish with a request.
2490 * This avoids leaking DMA mappings on error.
2492 if (host->flags & SDHCI_REQ_USE_DMA) {
2493 struct mmc_data *data = mrq->data;
2495 if (data && data->host_cookie == COOKIE_MAPPED) {
2496 if (host->bounce_buffer) {
2498 * On reads, copy the bounced data into the
2501 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2502 unsigned int length = data->bytes_xfered;
2504 if (length > host->bounce_buffer_size) {
2505 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2506 mmc_hostname(host->mmc),
2507 host->bounce_buffer_size,
2508 data->bytes_xfered);
2509 /* Cap it down and continue */
2510 length = host->bounce_buffer_size;
2512 dma_sync_single_for_cpu(
2515 host->bounce_buffer_size,
2517 sg_copy_from_buffer(data->sg,
2519 host->bounce_buffer,
2522 /* No copying, just switch ownership */
2523 dma_sync_single_for_cpu(
2526 host->bounce_buffer_size,
2527 mmc_get_dma_dir(data));
2530 /* Unmap the raw data */
2531 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2533 mmc_get_dma_dir(data));
2535 data->host_cookie = COOKIE_UNMAPPED;
2540 * The controller needs a reset of internal state machines
2541 * upon error conditions.
2543 if (sdhci_needs_reset(host, mrq)) {
2545 * Do not finish until command and data lines are available for
2546 * reset. Note there can only be one other mrq, so it cannot
2547 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2548 * would both be null.
2550 if (host->cmd || host->data_cmd) {
2551 spin_unlock_irqrestore(&host->lock, flags);
2555 /* Some controllers need this kick or reset won't work here */
2556 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2557 /* This is to force an update */
2558 host->ops->set_clock(host, host->clock);
2560 /* Spec says we should do both at the same time, but Ricoh
2561 controllers do not like that. */
2562 sdhci_do_reset(host, SDHCI_RESET_CMD);
2563 sdhci_do_reset(host, SDHCI_RESET_DATA);
2565 host->pending_reset = false;
2568 if (!sdhci_has_requests(host))
2569 sdhci_led_deactivate(host);
2571 host->mrqs_done[i] = NULL;
2574 spin_unlock_irqrestore(&host->lock, flags);
2576 mmc_request_done(host->mmc, mrq);
2581 static void sdhci_tasklet_finish(unsigned long param)
2583 struct sdhci_host *host = (struct sdhci_host *)param;
2585 while (!sdhci_request_done(host))
2589 static void sdhci_timeout_timer(struct timer_list *t)
2591 struct sdhci_host *host;
2592 unsigned long flags;
2594 host = from_timer(host, t, timer);
2596 spin_lock_irqsave(&host->lock, flags);
2598 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2599 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2600 mmc_hostname(host->mmc));
2601 sdhci_dumpregs(host);
2603 host->cmd->error = -ETIMEDOUT;
2604 sdhci_finish_mrq(host, host->cmd->mrq);
2608 spin_unlock_irqrestore(&host->lock, flags);
2611 static void sdhci_timeout_data_timer(struct timer_list *t)
2613 struct sdhci_host *host;
2614 unsigned long flags;
2616 host = from_timer(host, t, data_timer);
2618 spin_lock_irqsave(&host->lock, flags);
2620 if (host->data || host->data_cmd ||
2621 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2622 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2623 mmc_hostname(host->mmc));
2624 sdhci_dumpregs(host);
2627 host->data->error = -ETIMEDOUT;
2628 sdhci_finish_data(host);
2629 } else if (host->data_cmd) {
2630 host->data_cmd->error = -ETIMEDOUT;
2631 sdhci_finish_mrq(host, host->data_cmd->mrq);
2633 host->cmd->error = -ETIMEDOUT;
2634 sdhci_finish_mrq(host, host->cmd->mrq);
2639 spin_unlock_irqrestore(&host->lock, flags);
2642 /*****************************************************************************\
2644 * Interrupt handling *
2646 \*****************************************************************************/
2648 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
2650 /* Handle auto-CMD12 error */
2651 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
2652 struct mmc_request *mrq = host->data_cmd->mrq;
2653 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2654 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2655 SDHCI_INT_DATA_TIMEOUT :
2658 /* Treat auto-CMD12 error the same as data error */
2659 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
2660 *intmask_p |= data_err_bit;
2667 * SDHCI recovers from errors by resetting the cmd and data
2668 * circuits. Until that is done, there very well might be more
2669 * interrupts, so ignore them in that case.
2671 if (host->pending_reset)
2673 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2674 mmc_hostname(host->mmc), (unsigned)intmask);
2675 sdhci_dumpregs(host);
2679 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2680 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2681 if (intmask & SDHCI_INT_TIMEOUT)
2682 host->cmd->error = -ETIMEDOUT;
2684 host->cmd->error = -EILSEQ;
2686 /* Treat data command CRC error the same as data CRC error */
2687 if (host->cmd->data &&
2688 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2691 *intmask_p |= SDHCI_INT_DATA_CRC;
2695 sdhci_finish_mrq(host, host->cmd->mrq);
2699 /* Handle auto-CMD23 error */
2700 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
2701 struct mmc_request *mrq = host->cmd->mrq;
2702 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2703 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2707 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
2708 mrq->sbc->error = err;
2709 sdhci_finish_mrq(host, mrq);
2714 if (intmask & SDHCI_INT_RESPONSE)
2715 sdhci_finish_command(host);
2718 static void sdhci_adma_show_error(struct sdhci_host *host)
2720 void *desc = host->adma_table;
2721 dma_addr_t dma = host->adma_addr;
2723 sdhci_dumpregs(host);
2726 struct sdhci_adma2_64_desc *dma_desc = desc;
2728 if (host->flags & SDHCI_USE_64_BIT_DMA)
2729 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2730 (unsigned long long)dma,
2731 le32_to_cpu(dma_desc->addr_hi),
2732 le32_to_cpu(dma_desc->addr_lo),
2733 le16_to_cpu(dma_desc->len),
2734 le16_to_cpu(dma_desc->cmd));
2736 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2737 (unsigned long long)dma,
2738 le32_to_cpu(dma_desc->addr_lo),
2739 le16_to_cpu(dma_desc->len),
2740 le16_to_cpu(dma_desc->cmd));
2742 desc += host->desc_sz;
2743 dma += host->desc_sz;
2745 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2750 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2754 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2755 if (intmask & SDHCI_INT_DATA_AVAIL) {
2756 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2757 if (command == MMC_SEND_TUNING_BLOCK ||
2758 command == MMC_SEND_TUNING_BLOCK_HS200) {
2759 host->tuning_done = 1;
2760 wake_up(&host->buf_ready_int);
2766 struct mmc_command *data_cmd = host->data_cmd;
2769 * The "data complete" interrupt is also used to
2770 * indicate that a busy state has ended. See comment
2771 * above in sdhci_cmd_irq().
2773 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2774 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2775 host->data_cmd = NULL;
2776 data_cmd->error = -ETIMEDOUT;
2777 sdhci_finish_mrq(host, data_cmd->mrq);
2780 if (intmask & SDHCI_INT_DATA_END) {
2781 host->data_cmd = NULL;
2783 * Some cards handle busy-end interrupt
2784 * before the command completed, so make
2785 * sure we do things in the proper order.
2787 if (host->cmd == data_cmd)
2790 sdhci_finish_mrq(host, data_cmd->mrq);
2796 * SDHCI recovers from errors by resetting the cmd and data
2797 * circuits. Until that is done, there very well might be more
2798 * interrupts, so ignore them in that case.
2800 if (host->pending_reset)
2803 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2804 mmc_hostname(host->mmc), (unsigned)intmask);
2805 sdhci_dumpregs(host);
2810 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2811 host->data->error = -ETIMEDOUT;
2812 else if (intmask & SDHCI_INT_DATA_END_BIT)
2813 host->data->error = -EILSEQ;
2814 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2815 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2817 host->data->error = -EILSEQ;
2818 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2819 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
2821 sdhci_adma_show_error(host);
2822 host->data->error = -EIO;
2823 if (host->ops->adma_workaround)
2824 host->ops->adma_workaround(host, intmask);
2827 if (host->data->error)
2828 sdhci_finish_data(host);
2830 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2831 sdhci_transfer_pio(host);
2834 * We currently don't do anything fancy with DMA
2835 * boundaries, but as we can't disable the feature
2836 * we need to at least restart the transfer.
2838 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2839 * should return a valid address to continue from, but as
2840 * some controllers are faulty, don't trust them.
2842 if (intmask & SDHCI_INT_DMA_END) {
2843 u32 dmastart, dmanow;
2845 dmastart = sdhci_sdma_address(host);
2846 dmanow = dmastart + host->data->bytes_xfered;
2848 * Force update to the next DMA block boundary.
2851 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2852 SDHCI_DEFAULT_BOUNDARY_SIZE;
2853 host->data->bytes_xfered = dmanow - dmastart;
2854 DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2855 dmastart, host->data->bytes_xfered, dmanow);
2856 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2859 if (intmask & SDHCI_INT_DATA_END) {
2860 if (host->cmd == host->data_cmd) {
2862 * Data managed to finish before the
2863 * command completed. Make sure we do
2864 * things in the proper order.
2866 host->data_early = 1;
2868 sdhci_finish_data(host);
2874 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2876 irqreturn_t result = IRQ_NONE;
2877 struct sdhci_host *host = dev_id;
2878 u32 intmask, mask, unexpected = 0;
2881 spin_lock(&host->lock);
2883 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2884 spin_unlock(&host->lock);
2888 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2889 if (!intmask || intmask == 0xffffffff) {
2895 DBG("IRQ status 0x%08x\n", intmask);
2897 if (host->ops->irq) {
2898 intmask = host->ops->irq(host, intmask);
2903 /* Clear selected interrupts. */
2904 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2905 SDHCI_INT_BUS_POWER);
2906 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2908 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2909 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2913 * There is a observation on i.mx esdhc. INSERT
2914 * bit will be immediately set again when it gets
2915 * cleared, if a card is inserted. We have to mask
2916 * the irq to prevent interrupt storm which will
2917 * freeze the system. And the REMOVE gets the
2920 * More testing are needed here to ensure it works
2921 * for other platforms though.
2923 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2924 SDHCI_INT_CARD_REMOVE);
2925 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2926 SDHCI_INT_CARD_INSERT;
2927 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2928 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2930 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2931 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2933 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2934 SDHCI_INT_CARD_REMOVE);
2935 result = IRQ_WAKE_THREAD;
2938 if ((intmask & SDHCI_INT_DATA_END) && !host->data &&
2939 host->cmd && (host->cmd == host->cmd->mrq->stop))
2940 intmask &= ~SDHCI_INT_DATA_END;
2942 if (intmask & SDHCI_INT_CMD_MASK)
2943 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
2945 if (intmask & SDHCI_INT_DATA_MASK)
2946 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2948 if (intmask & SDHCI_INT_BUS_POWER)
2949 pr_err("%s: Card is consuming too much power!\n",
2950 mmc_hostname(host->mmc));
2952 if (intmask & SDHCI_INT_RETUNE)
2953 mmc_retune_needed(host->mmc);
2955 if ((intmask & SDHCI_INT_CARD_INT) &&
2956 (host->ier & SDHCI_INT_CARD_INT)) {
2957 sdhci_enable_sdio_irq_nolock(host, false);
2958 host->thread_isr |= SDHCI_INT_CARD_INT;
2959 result = IRQ_WAKE_THREAD;
2962 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2963 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2964 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2965 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2968 unexpected |= intmask;
2969 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2972 if (result == IRQ_NONE)
2973 result = IRQ_HANDLED;
2975 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2976 } while (intmask && --max_loops);
2978 spin_unlock(&host->lock);
2981 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2982 mmc_hostname(host->mmc), unexpected);
2983 sdhci_dumpregs(host);
2989 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2991 struct sdhci_host *host = dev_id;
2992 unsigned long flags;
2995 spin_lock_irqsave(&host->lock, flags);
2996 isr = host->thread_isr;
2997 host->thread_isr = 0;
2998 spin_unlock_irqrestore(&host->lock, flags);
3000 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3001 struct mmc_host *mmc = host->mmc;
3003 mmc->ops->card_event(mmc);
3004 mmc_detect_change(mmc, msecs_to_jiffies(200));
3007 if (isr & SDHCI_INT_CARD_INT) {
3008 sdio_run_irqs(host->mmc);
3010 spin_lock_irqsave(&host->lock, flags);
3011 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3012 sdhci_enable_sdio_irq_nolock(host, true);
3013 spin_unlock_irqrestore(&host->lock, flags);
3016 return isr ? IRQ_HANDLED : IRQ_NONE;
3019 /*****************************************************************************\
3023 \*****************************************************************************/
3027 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3029 return mmc_card_is_removable(host->mmc) &&
3030 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3031 !mmc_can_gpio_cd(host->mmc);
3035 * To enable wakeup events, the corresponding events have to be enabled in
3036 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3037 * Table' in the SD Host Controller Standard Specification.
3038 * It is useless to restore SDHCI_INT_ENABLE state in
3039 * sdhci_disable_irq_wakeups() since it will be set by
3040 * sdhci_enable_card_detection() or sdhci_init().
3042 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3044 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3050 if (sdhci_cd_irq_can_wakeup(host)) {
3051 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3052 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3055 if (mmc_card_wake_sdio_irq(host->mmc)) {
3056 wake_val |= SDHCI_WAKE_ON_INT;
3057 irq_val |= SDHCI_INT_CARD_INT;
3063 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3066 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3068 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3070 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3072 return host->irq_wake_enabled;
3075 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3078 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3079 | SDHCI_WAKE_ON_INT;
3081 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3083 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3085 disable_irq_wake(host->irq);
3087 host->irq_wake_enabled = false;
3090 int sdhci_suspend_host(struct sdhci_host *host)
3092 sdhci_disable_card_detection(host);
3094 mmc_retune_timer_stop(host->mmc);
3096 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3097 !sdhci_enable_irq_wakeups(host)) {
3099 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3100 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3101 free_irq(host->irq, host);
3107 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3109 int sdhci_resume_host(struct sdhci_host *host)
3111 struct mmc_host *mmc = host->mmc;
3114 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3115 if (host->ops->enable_dma)
3116 host->ops->enable_dma(host);
3119 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3120 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3121 /* Card keeps power but host controller does not */
3122 sdhci_init(host, 0);
3125 mmc->ops->set_ios(mmc, &mmc->ios);
3127 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3131 if (host->irq_wake_enabled) {
3132 sdhci_disable_irq_wakeups(host);
3134 ret = request_threaded_irq(host->irq, sdhci_irq,
3135 sdhci_thread_irq, IRQF_SHARED,
3136 mmc_hostname(host->mmc), host);
3141 sdhci_enable_card_detection(host);
3146 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3148 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3150 unsigned long flags;
3152 mmc_retune_timer_stop(host->mmc);
3154 spin_lock_irqsave(&host->lock, flags);
3155 host->ier &= SDHCI_INT_CARD_INT;
3156 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3157 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3158 spin_unlock_irqrestore(&host->lock, flags);
3160 synchronize_hardirq(host->irq);
3162 spin_lock_irqsave(&host->lock, flags);
3163 host->runtime_suspended = true;
3164 spin_unlock_irqrestore(&host->lock, flags);
3168 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3170 int sdhci_runtime_resume_host(struct sdhci_host *host)
3172 struct mmc_host *mmc = host->mmc;
3173 unsigned long flags;
3174 int host_flags = host->flags;
3176 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3177 if (host->ops->enable_dma)
3178 host->ops->enable_dma(host);
3181 sdhci_init(host, 0);
3183 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3184 mmc->ios.power_mode != MMC_POWER_OFF) {
3185 /* Force clock and power re-program */
3188 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3189 mmc->ops->set_ios(mmc, &mmc->ios);
3191 if ((host_flags & SDHCI_PV_ENABLED) &&
3192 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3193 spin_lock_irqsave(&host->lock, flags);
3194 sdhci_enable_preset_value(host, true);
3195 spin_unlock_irqrestore(&host->lock, flags);
3198 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3199 mmc->ops->hs400_enhanced_strobe)
3200 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3203 spin_lock_irqsave(&host->lock, flags);
3205 host->runtime_suspended = false;
3207 /* Enable SDIO IRQ */
3208 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3209 sdhci_enable_sdio_irq_nolock(host, true);
3211 /* Enable Card Detection */
3212 sdhci_enable_card_detection(host);
3214 spin_unlock_irqrestore(&host->lock, flags);
3218 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3220 #endif /* CONFIG_PM */
3222 /*****************************************************************************\
3224 * Command Queue Engine (CQE) helpers *
3226 \*****************************************************************************/
3228 void sdhci_cqe_enable(struct mmc_host *mmc)
3230 struct sdhci_host *host = mmc_priv(mmc);
3231 unsigned long flags;
3234 spin_lock_irqsave(&host->lock, flags);
3236 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3237 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3238 if (host->flags & SDHCI_USE_64_BIT_DMA)
3239 ctrl |= SDHCI_CTRL_ADMA64;
3241 ctrl |= SDHCI_CTRL_ADMA32;
3242 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3244 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3247 /* Set maximum timeout */
3248 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
3250 host->ier = host->cqe_ier;
3252 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3253 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3255 host->cqe_on = true;
3257 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3258 mmc_hostname(mmc), host->ier,
3259 sdhci_readl(host, SDHCI_INT_STATUS));
3262 spin_unlock_irqrestore(&host->lock, flags);
3264 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3266 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3268 struct sdhci_host *host = mmc_priv(mmc);
3269 unsigned long flags;
3271 spin_lock_irqsave(&host->lock, flags);
3273 sdhci_set_default_irqs(host);
3275 host->cqe_on = false;
3278 sdhci_do_reset(host, SDHCI_RESET_CMD);
3279 sdhci_do_reset(host, SDHCI_RESET_DATA);
3282 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3283 mmc_hostname(mmc), host->ier,
3284 sdhci_readl(host, SDHCI_INT_STATUS));
3287 spin_unlock_irqrestore(&host->lock, flags);
3289 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3291 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3299 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3300 *cmd_error = -EILSEQ;
3301 else if (intmask & SDHCI_INT_TIMEOUT)
3302 *cmd_error = -ETIMEDOUT;
3306 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3307 *data_error = -EILSEQ;
3308 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3309 *data_error = -ETIMEDOUT;
3310 else if (intmask & SDHCI_INT_ADMA_ERROR)
3315 /* Clear selected interrupts. */
3316 mask = intmask & host->cqe_ier;
3317 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3319 if (intmask & SDHCI_INT_BUS_POWER)
3320 pr_err("%s: Card is consuming too much power!\n",
3321 mmc_hostname(host->mmc));
3323 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3325 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3326 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3327 mmc_hostname(host->mmc), intmask);
3328 sdhci_dumpregs(host);
3333 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3335 /*****************************************************************************\
3337 * Device allocation/registration *
3339 \*****************************************************************************/
3341 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3344 struct mmc_host *mmc;
3345 struct sdhci_host *host;
3347 WARN_ON(dev == NULL);
3349 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3351 return ERR_PTR(-ENOMEM);
3353 host = mmc_priv(mmc);
3355 host->mmc_host_ops = sdhci_ops;
3356 mmc->ops = &host->mmc_host_ops;
3358 host->flags = SDHCI_SIGNALING_330;
3360 host->cqe_ier = SDHCI_CQE_INT_MASK;
3361 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3363 host->tuning_delay = -1;
3365 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3370 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3372 static int sdhci_set_dma_mask(struct sdhci_host *host)
3374 struct mmc_host *mmc = host->mmc;
3375 struct device *dev = mmc_dev(mmc);
3378 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3379 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3381 /* Try 64-bit mask if hardware is capable of it */
3382 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3383 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3385 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3387 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3391 /* 32-bit mask as default & fallback */
3393 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3395 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3402 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3405 u64 dt_caps_mask = 0;
3408 if (host->read_caps)
3411 host->read_caps = true;
3414 host->quirks = debug_quirks;
3417 host->quirks2 = debug_quirks2;
3419 sdhci_do_reset(host, SDHCI_RESET_ALL);
3421 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3422 "sdhci-caps-mask", &dt_caps_mask);
3423 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3424 "sdhci-caps", &dt_caps);
3426 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3427 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3429 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3435 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3436 host->caps &= ~lower_32_bits(dt_caps_mask);
3437 host->caps |= lower_32_bits(dt_caps);
3440 if (host->version < SDHCI_SPEC_300)
3444 host->caps1 = *caps1;
3446 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3447 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3448 host->caps1 |= upper_32_bits(dt_caps);
3451 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3453 static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3455 struct mmc_host *mmc = host->mmc;
3456 unsigned int max_blocks;
3457 unsigned int bounce_size;
3461 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3462 * has diminishing returns, this is probably because SD/MMC
3463 * cards are usually optimized to handle this size of requests.
3465 bounce_size = SZ_64K;
3467 * Adjust downwards to maximum request size if this is less
3468 * than our segment size, else hammer down the maximum
3469 * request size to the maximum buffer size.
3471 if (mmc->max_req_size < bounce_size)
3472 bounce_size = mmc->max_req_size;
3473 max_blocks = bounce_size / 512;
3476 * When we just support one segment, we can get significant
3477 * speedups by the help of a bounce buffer to group scattered
3478 * reads/writes together.
3480 host->bounce_buffer = devm_kmalloc(mmc->parent,
3483 if (!host->bounce_buffer) {
3484 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3488 * Exiting with zero here makes sure we proceed with
3489 * mmc->max_segs == 1.
3494 host->bounce_addr = dma_map_single(mmc->parent,
3495 host->bounce_buffer,
3498 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3500 /* Again fall back to max_segs == 1 */
3502 host->bounce_buffer_size = bounce_size;
3504 /* Lie about this since we're bouncing */
3505 mmc->max_segs = max_blocks;
3506 mmc->max_seg_size = bounce_size;
3507 mmc->max_req_size = bounce_size;
3509 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3510 mmc_hostname(mmc), max_blocks, bounce_size);
3515 int sdhci_setup_host(struct sdhci_host *host)
3517 struct mmc_host *mmc;
3518 u32 max_current_caps;
3519 unsigned int ocr_avail;
3520 unsigned int override_timeout_clk;
3524 WARN_ON(host == NULL);
3531 * If there are external regulators, get them. Note this must be done
3532 * early before resetting the host and reading the capabilities so that
3533 * the host can take the appropriate action if regulators are not
3536 ret = mmc_regulator_get_supply(mmc);
3540 DBG("Version: 0x%08x | Present: 0x%08x\n",
3541 sdhci_readw(host, SDHCI_HOST_VERSION),
3542 sdhci_readl(host, SDHCI_PRESENT_STATE));
3543 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3544 sdhci_readl(host, SDHCI_CAPABILITIES),
3545 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3547 sdhci_read_caps(host);
3549 override_timeout_clk = host->timeout_clk;
3551 if (host->version > SDHCI_SPEC_300) {
3552 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3553 mmc_hostname(mmc), host->version);
3556 if (host->quirks & SDHCI_QUIRK_BROKEN_CQE)
3557 mmc->caps2 &= ~MMC_CAP2_CQE;
3559 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3560 host->flags |= SDHCI_USE_SDMA;
3561 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3562 DBG("Controller doesn't have SDMA capability\n");
3564 host->flags |= SDHCI_USE_SDMA;
3566 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3567 (host->flags & SDHCI_USE_SDMA)) {
3568 DBG("Disabling DMA as it is marked broken\n");
3569 host->flags &= ~SDHCI_USE_SDMA;
3572 if ((host->version >= SDHCI_SPEC_200) &&
3573 (host->caps & SDHCI_CAN_DO_ADMA2))
3574 host->flags |= SDHCI_USE_ADMA;
3576 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3577 (host->flags & SDHCI_USE_ADMA)) {
3578 DBG("Disabling ADMA as it is marked broken\n");
3579 host->flags &= ~SDHCI_USE_ADMA;
3583 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3584 * and *must* do 64-bit DMA. A driver has the opportunity to change
3585 * that during the first call to ->enable_dma(). Similarly
3586 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3589 if (host->caps & SDHCI_CAN_64BIT)
3590 host->flags |= SDHCI_USE_64_BIT_DMA;
3592 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3593 ret = sdhci_set_dma_mask(host);
3595 if (!ret && host->ops->enable_dma)
3596 ret = host->ops->enable_dma(host);
3599 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3601 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3607 /* SDMA does not support 64-bit DMA */
3608 if (host->flags & SDHCI_USE_64_BIT_DMA)
3609 host->flags &= ~SDHCI_USE_SDMA;
3611 if (host->flags & SDHCI_USE_ADMA) {
3616 * The DMA descriptor table size is calculated as the maximum
3617 * number of segments times 2, to allow for an alignment
3618 * descriptor for each segment, plus 1 for a nop end descriptor,
3619 * all multipled by the descriptor size.
3621 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3622 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3623 SDHCI_ADMA2_64_DESC_SZ;
3624 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3626 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3627 SDHCI_ADMA2_32_DESC_SZ;
3628 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3631 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3632 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3633 host->adma_table_sz, &dma, GFP_KERNEL);
3635 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3637 host->flags &= ~SDHCI_USE_ADMA;
3638 } else if ((dma + host->align_buffer_sz) &
3639 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3640 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3642 host->flags &= ~SDHCI_USE_ADMA;
3643 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3644 host->adma_table_sz, buf, dma);
3646 host->align_buffer = buf;
3647 host->align_addr = dma;
3649 host->adma_table = buf + host->align_buffer_sz;
3650 host->adma_addr = dma + host->align_buffer_sz;
3655 * If we use DMA, then it's up to the caller to set the DMA
3656 * mask, but PIO does not need the hw shim so we set a new
3657 * mask here in that case.
3659 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3660 host->dma_mask = DMA_BIT_MASK(64);
3661 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3664 if (host->version >= SDHCI_SPEC_300)
3665 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3666 >> SDHCI_CLOCK_BASE_SHIFT;
3668 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3669 >> SDHCI_CLOCK_BASE_SHIFT;
3671 host->max_clk *= 1000000;
3672 if (host->max_clk == 0 || host->quirks &
3673 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3674 if (!host->ops->get_max_clock) {
3675 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3680 host->max_clk = host->ops->get_max_clock(host);
3684 * In case of Host Controller v3.00, find out whether clock
3685 * multiplier is supported.
3687 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3688 SDHCI_CLOCK_MUL_SHIFT;
3691 * In case the value in Clock Multiplier is 0, then programmable
3692 * clock mode is not supported, otherwise the actual clock
3693 * multiplier is one more than the value of Clock Multiplier
3694 * in the Capabilities Register.
3700 * Set host parameters.
3702 max_clk = host->max_clk;
3704 if (host->ops->get_min_clock)
3705 mmc->f_min = host->ops->get_min_clock(host);
3706 else if (host->version >= SDHCI_SPEC_300) {
3707 if (host->clk_mul) {
3708 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3709 max_clk = host->max_clk * host->clk_mul;
3711 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3713 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3715 if (!mmc->f_max || mmc->f_max > max_clk)
3716 mmc->f_max = max_clk;
3718 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3719 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3720 SDHCI_TIMEOUT_CLK_SHIFT;
3722 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3723 host->timeout_clk *= 1000;
3725 if (host->timeout_clk == 0) {
3726 if (!host->ops->get_timeout_clock) {
3727 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3734 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3738 if (override_timeout_clk)
3739 host->timeout_clk = override_timeout_clk;
3741 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3742 host->ops->get_max_timeout_count(host) : 1 << 27;
3743 mmc->max_busy_timeout /= host->timeout_clk;
3746 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
3747 !host->ops->get_max_timeout_count)
3748 mmc->max_busy_timeout = 0;
3750 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3751 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3753 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3754 host->flags |= SDHCI_AUTO_CMD12;
3756 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3757 if ((host->version >= SDHCI_SPEC_300) &&
3758 ((host->flags & SDHCI_USE_ADMA) ||
3759 !(host->flags & SDHCI_USE_SDMA)) &&
3760 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3761 host->flags |= SDHCI_AUTO_CMD23;
3762 DBG("Auto-CMD23 available\n");
3764 DBG("Auto-CMD23 unavailable\n");
3768 * A controller may support 8-bit width, but the board itself
3769 * might not have the pins brought out. Boards that support
3770 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3771 * their platform code before calling sdhci_add_host(), and we
3772 * won't assume 8-bit width for hosts without that CAP.
3774 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3775 mmc->caps |= MMC_CAP_4_BIT_DATA;
3777 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3778 mmc->caps &= ~MMC_CAP_CMD23;
3780 if (host->caps & SDHCI_CAN_DO_HISPD)
3781 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3783 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3784 mmc_card_is_removable(mmc) &&
3785 mmc_gpio_get_cd(host->mmc) < 0)
3786 mmc->caps |= MMC_CAP_NEEDS_POLL;
3788 if (!IS_ERR(mmc->supply.vqmmc)) {
3789 ret = regulator_enable(mmc->supply.vqmmc);
3791 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3792 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3794 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3795 SDHCI_SUPPORT_SDR50 |
3796 SDHCI_SUPPORT_DDR50);
3798 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
3799 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
3801 host->flags &= ~SDHCI_SIGNALING_330;
3804 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3805 mmc_hostname(mmc), ret);
3806 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3810 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3811 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3812 SDHCI_SUPPORT_DDR50);
3814 * The SDHCI controller in a SoC might support HS200/HS400
3815 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
3816 * but if the board is modeled such that the IO lines are not
3817 * connected to 1.8v then HS200/HS400 cannot be supported.
3818 * Disable HS200/HS400 if the board does not have 1.8v connected
3819 * to the IO lines. (Applicable for other modes in 1.8v)
3821 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
3822 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
3825 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3826 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3827 SDHCI_SUPPORT_DDR50))
3828 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3830 /* SDR104 supports also implies SDR50 support */
3831 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3832 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3833 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3834 * field can be promoted to support HS200.
3836 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3837 mmc->caps2 |= MMC_CAP2_HS200;
3838 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3839 mmc->caps |= MMC_CAP_UHS_SDR50;
3842 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3843 (host->caps1 & SDHCI_SUPPORT_HS400))
3844 mmc->caps2 |= MMC_CAP2_HS400;
3846 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3847 (IS_ERR(mmc->supply.vqmmc) ||
3848 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3850 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3852 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3853 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3854 mmc->caps |= MMC_CAP_UHS_DDR50;
3856 /* Does the host need tuning for SDR50? */
3857 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3858 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3860 /* Driver Type(s) (A, C, D) supported by the host */
3861 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3862 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3863 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3864 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3865 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3866 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3868 /* Initial value for re-tuning timer count */
3869 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3870 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3873 * In case Re-tuning Timer is not disabled, the actual value of
3874 * re-tuning timer will be 2 ^ (n - 1).
3876 if (host->tuning_count)
3877 host->tuning_count = 1 << (host->tuning_count - 1);
3879 /* Re-tuning mode supported by the Host Controller */
3880 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3881 SDHCI_RETUNING_MODE_SHIFT;
3886 * According to SD Host Controller spec v3.00, if the Host System
3887 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3888 * the value is meaningful only if Voltage Support in the Capabilities
3889 * register is set. The actual current value is 4 times the register
3892 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3893 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3894 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3897 /* convert to SDHCI_MAX_CURRENT format */
3898 curr = curr/1000; /* convert to mA */
3899 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3901 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3903 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3904 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3905 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3909 if (host->caps & SDHCI_CAN_VDD_330) {
3910 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3912 mmc->max_current_330 = ((max_current_caps &
3913 SDHCI_MAX_CURRENT_330_MASK) >>
3914 SDHCI_MAX_CURRENT_330_SHIFT) *
3915 SDHCI_MAX_CURRENT_MULTIPLIER;
3917 if (host->caps & SDHCI_CAN_VDD_300) {
3918 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3920 mmc->max_current_300 = ((max_current_caps &
3921 SDHCI_MAX_CURRENT_300_MASK) >>
3922 SDHCI_MAX_CURRENT_300_SHIFT) *
3923 SDHCI_MAX_CURRENT_MULTIPLIER;
3925 if (host->caps & SDHCI_CAN_VDD_180) {
3926 ocr_avail |= MMC_VDD_165_195;
3928 mmc->max_current_180 = ((max_current_caps &
3929 SDHCI_MAX_CURRENT_180_MASK) >>
3930 SDHCI_MAX_CURRENT_180_SHIFT) *
3931 SDHCI_MAX_CURRENT_MULTIPLIER;
3934 /* If OCR set by host, use it instead. */
3936 ocr_avail = host->ocr_mask;
3938 /* If OCR set by external regulators, give it highest prio. */
3940 ocr_avail = mmc->ocr_avail;
3942 mmc->ocr_avail = ocr_avail;
3943 mmc->ocr_avail_sdio = ocr_avail;
3944 if (host->ocr_avail_sdio)
3945 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3946 mmc->ocr_avail_sd = ocr_avail;
3947 if (host->ocr_avail_sd)
3948 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3949 else /* normal SD controllers don't support 1.8V */
3950 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3951 mmc->ocr_avail_mmc = ocr_avail;
3952 if (host->ocr_avail_mmc)
3953 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3955 if (mmc->ocr_avail == 0) {
3956 pr_err("%s: Hardware doesn't report any support voltages.\n",
3962 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3963 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3964 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3965 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3966 host->flags |= SDHCI_SIGNALING_180;
3968 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3969 host->flags |= SDHCI_SIGNALING_120;
3971 spin_lock_init(&host->lock);
3974 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3975 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3978 mmc->max_req_size = 524288;
3981 * Maximum number of segments. Depends on if the hardware
3982 * can do scatter/gather or not.
3984 if (host->flags & SDHCI_USE_ADMA) {
3985 mmc->max_segs = SDHCI_MAX_SEGS;
3986 } else if (host->flags & SDHCI_USE_SDMA) {
3988 if (swiotlb_max_segment()) {
3989 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
3991 mmc->max_req_size = min(mmc->max_req_size,
3995 mmc->max_segs = SDHCI_MAX_SEGS;
3999 * Maximum segment size. Could be one segment with the maximum number
4000 * of bytes. When doing hardware scatter/gather, each entry cannot
4001 * be larger than 64 KiB though.
4003 if (host->flags & SDHCI_USE_ADMA) {
4004 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4005 mmc->max_seg_size = 65535;
4007 mmc->max_seg_size = 65536;
4009 mmc->max_seg_size = mmc->max_req_size;
4013 * Maximum block size. This varies from controller to controller and
4014 * is specified in the capabilities register.
4016 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4017 mmc->max_blk_size = 2;
4019 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4020 SDHCI_MAX_BLOCK_SHIFT;
4021 if (mmc->max_blk_size >= 3) {
4022 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4024 mmc->max_blk_size = 0;
4028 mmc->max_blk_size = 512 << mmc->max_blk_size;
4031 * Maximum block count.
4033 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4035 if (mmc->max_segs == 1) {
4036 /* This may alter mmc->*_blk_* parameters */
4037 ret = sdhci_allocate_bounce_buffer(host);
4045 if (!IS_ERR(mmc->supply.vqmmc))
4046 regulator_disable(mmc->supply.vqmmc);
4048 if (host->align_buffer)
4049 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4050 host->adma_table_sz, host->align_buffer,
4052 host->adma_table = NULL;
4053 host->align_buffer = NULL;
4057 EXPORT_SYMBOL_GPL(sdhci_setup_host);
4059 void sdhci_cleanup_host(struct sdhci_host *host)
4061 struct mmc_host *mmc = host->mmc;
4063 if (!IS_ERR(mmc->supply.vqmmc))
4064 regulator_disable(mmc->supply.vqmmc);
4066 if (host->align_buffer)
4067 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4068 host->adma_table_sz, host->align_buffer,
4070 host->adma_table = NULL;
4071 host->align_buffer = NULL;
4073 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4075 int __sdhci_add_host(struct sdhci_host *host)
4077 struct mmc_host *mmc = host->mmc;
4083 tasklet_init(&host->finish_tasklet,
4084 sdhci_tasklet_finish, (unsigned long)host);
4086 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4087 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4089 init_waitqueue_head(&host->buf_ready_int);
4091 sdhci_init(host, 0);
4093 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4094 IRQF_SHARED, mmc_hostname(mmc), host);
4096 pr_err("%s: Failed to request IRQ %d: %d\n",
4097 mmc_hostname(mmc), host->irq, ret);
4101 ret = sdhci_led_register(host);
4103 pr_err("%s: Failed to register LED device: %d\n",
4104 mmc_hostname(mmc), ret);
4110 ret = mmc_add_host(mmc);
4114 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4115 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4116 (host->flags & SDHCI_USE_ADMA) ?
4117 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4118 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4120 sdhci_enable_card_detection(host);
4125 sdhci_led_unregister(host);
4127 sdhci_do_reset(host, SDHCI_RESET_ALL);
4128 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4129 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4130 free_irq(host->irq, host);
4132 tasklet_kill(&host->finish_tasklet);
4136 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4138 int sdhci_add_host(struct sdhci_host *host)
4142 ret = sdhci_setup_host(host);
4146 ret = __sdhci_add_host(host);
4153 sdhci_cleanup_host(host);
4157 EXPORT_SYMBOL_GPL(sdhci_add_host);
4159 void sdhci_remove_host(struct sdhci_host *host, int dead)
4161 struct mmc_host *mmc = host->mmc;
4162 unsigned long flags;
4165 spin_lock_irqsave(&host->lock, flags);
4167 host->flags |= SDHCI_DEVICE_DEAD;
4169 if (sdhci_has_requests(host)) {
4170 pr_err("%s: Controller removed during "
4171 " transfer!\n", mmc_hostname(mmc));
4172 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4175 spin_unlock_irqrestore(&host->lock, flags);
4178 sdhci_disable_card_detection(host);
4180 mmc_remove_host(mmc);
4182 sdhci_led_unregister(host);
4185 sdhci_do_reset(host, SDHCI_RESET_ALL);
4187 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4188 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4189 free_irq(host->irq, host);
4191 del_timer_sync(&host->timer);
4192 del_timer_sync(&host->data_timer);
4194 tasklet_kill(&host->finish_tasklet);
4196 if (!IS_ERR(mmc->supply.vqmmc))
4197 regulator_disable(mmc->supply.vqmmc);
4199 if (host->align_buffer)
4200 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4201 host->adma_table_sz, host->align_buffer,
4204 host->adma_table = NULL;
4205 host->align_buffer = NULL;
4208 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4210 void sdhci_free_host(struct sdhci_host *host)
4212 mmc_free_host(host->mmc);
4215 EXPORT_SYMBOL_GPL(sdhci_free_host);
4217 /*****************************************************************************\
4219 * Driver init/exit *
4221 \*****************************************************************************/
4223 static int __init sdhci_drv_init(void)
4226 ": Secure Digital Host Controller Interface driver\n");
4227 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4232 static void __exit sdhci_drv_exit(void)
4236 module_init(sdhci_drv_init);
4237 module_exit(sdhci_drv_exit);
4239 module_param(debug_quirks, uint, 0444);
4240 module_param(debug_quirks2, uint, 0444);
4242 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4243 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4244 MODULE_LICENSE("GPL");
4246 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4247 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");