drivers/mmc/host/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   4  *
   5  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   6  *
   7  * Thanks to the following companies for their support:
   8  *
   9  *     - JMicron (hardware and technical support)
  10  */
  11
  12 #include <linux/bitfield.h>
  13 #include <linux/delay.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/ktime.h>
  16 #include <linux/highmem.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/sizes.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/of.h>
  26
  27 #include <linux/leds.h>
  28
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/card.h>
  32 #include <linux/mmc/sdio.h>
  33 #include <linux/mmc/slot-gpio.h>
  34
  35 #include "sdhci.h"
  36
  37 #define DRIVER_NAME "sdhci"
  38
  39 #define DBG(f, x...) \
  40         pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  41
  42 #define SDHCI_DUMP(f, x...) \
  43         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 static unsigned int debug_quirks = 0;
  48 static unsigned int debug_quirks2;
  49
  50 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  51
  52 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
  53
  54 void sdhci_dumpregs(struct sdhci_host *host)
  55 {
  56         SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
  57
  58         SDHCI_DUMP("Sys addr:  0x%08x | Version:  0x%08x\n",
  59                    sdhci_readl(host, SDHCI_DMA_ADDRESS),
  60                    sdhci_readw(host, SDHCI_HOST_VERSION));
  61         SDHCI_DUMP("Blk size:  0x%08x | Blk cnt:  0x%08x\n",
  62                    sdhci_readw(host, SDHCI_BLOCK_SIZE),
  63                    sdhci_readw(host, SDHCI_BLOCK_COUNT));
  64         SDHCI_DUMP("Argument:  0x%08x | Trn mode: 0x%08x\n",
  65                    sdhci_readl(host, SDHCI_ARGUMENT),
  66                    sdhci_readw(host, SDHCI_TRANSFER_MODE));
  67         SDHCI_DUMP("Present:   0x%08x | Host ctl: 0x%08x\n",
  68                    sdhci_readl(host, SDHCI_PRESENT_STATE),
  69                    sdhci_readb(host, SDHCI_HOST_CONTROL));
  70         SDHCI_DUMP("Power:     0x%08x | Blk gap:  0x%08x\n",
  71                    sdhci_readb(host, SDHCI_POWER_CONTROL),
  72                    sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  73         SDHCI_DUMP("Wake-up:   0x%08x | Clock:    0x%08x\n",
  74                    sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  75                    sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  76         SDHCI_DUMP("Timeout:   0x%08x | Int stat: 0x%08x\n",
  77                    sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  78                    sdhci_readl(host, SDHCI_INT_STATUS));
  79         SDHCI_DUMP("Int enab:  0x%08x | Sig enab: 0x%08x\n",
  80                    sdhci_readl(host, SDHCI_INT_ENABLE),
  81                    sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  82         SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
  83                    sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
  84                    sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  85         SDHCI_DUMP("Caps:      0x%08x | Caps_1:   0x%08x\n",
  86                    sdhci_readl(host, SDHCI_CAPABILITIES),
  87                    sdhci_readl(host, SDHCI_CAPABILITIES_1));
  88         SDHCI_DUMP("Cmd:       0x%08x | Max curr: 0x%08x\n",
  89                    sdhci_readw(host, SDHCI_COMMAND),
  90                    sdhci_readl(host, SDHCI_MAX_CURRENT));
  91         SDHCI_DUMP("Resp[0]:   0x%08x | Resp[1]:  0x%08x\n",
  92                    sdhci_readl(host, SDHCI_RESPONSE),
  93                    sdhci_readl(host, SDHCI_RESPONSE + 4));
  94         SDHCI_DUMP("Resp[2]:   0x%08x | Resp[3]:  0x%08x\n",
  95                    sdhci_readl(host, SDHCI_RESPONSE + 8),
  96                    sdhci_readl(host, SDHCI_RESPONSE + 12));
  97         SDHCI_DUMP("Host ctl2: 0x%08x\n",
  98                    sdhci_readw(host, SDHCI_HOST_CONTROL2));
  99
 100         if (host->flags & SDHCI_USE_ADMA) {
 101                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
 102                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x%08x\n",
 103                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 104                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
 105                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 106                 } else {
 107                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x\n",
 108                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 109                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 110                 }
 111         }
 112
 113         if (host->ops->dump_vendor_regs)
 114                 host->ops->dump_vendor_regs(host);
 115
 116         SDHCI_DUMP("============================================\n");
 117 }
 118 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
 119
 120 /*****************************************************************************\
 121  *                                                                           *
 122  * Low level functions                                                       *
 123  *                                                                           *
 124 \*****************************************************************************/
 125
 126 static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
 127 {
 128         u16 ctrl2;
 129
 130         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 131         if (ctrl2 & SDHCI_CTRL_V4_MODE)
 132                 return;
 133
 134         ctrl2 |= SDHCI_CTRL_V4_MODE;
 135         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 136 }
 137
 138 /*
 139  * This can be called before sdhci_add_host() by Vendor's host controller
 140  * driver to enable v4 mode if supported.
 141  */
 142 void sdhci_enable_v4_mode(struct sdhci_host *host)
 143 {
 144         host->v4_mode = true;
 145         sdhci_do_enable_v4_mode(host);
 146 }
 147 EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
 148
 149 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
 150 {
 151         return cmd->data || cmd->flags & MMC_RSP_BUSY;
 152 }
 153
 154 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 155 {
 156         u32 present;
 157
 158         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 159             !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
 160                 return;
 161
 162         if (enable) {
 163                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 164                                       SDHCI_CARD_PRESENT;
 165
 166                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 167                                        SDHCI_INT_CARD_INSERT;
 168         } else {
 169                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 170         }
 171
 172         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 173         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 174 }
 175
 176 static void sdhci_enable_card_detection(struct sdhci_host *host)
 177 {
 178         sdhci_set_card_detection(host, true);
 179 }
 180
 181 static void sdhci_disable_card_detection(struct sdhci_host *host)
 182 {
 183         sdhci_set_card_detection(host, false);
 184 }
 185
 186 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
 187 {
 188         if (host->bus_on)
 189                 return;
 190         host->bus_on = true;
 191         pm_runtime_get_noresume(mmc_dev(host->mmc));
 192 }
 193
 194 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
 195 {
 196         if (!host->bus_on)
 197                 return;
 198         host->bus_on = false;
 199         pm_runtime_put_noidle(mmc_dev(host->mmc));
 200 }
 201
 202 void sdhci_reset(struct sdhci_host *host, u8 mask)
 203 {
 204         ktime_t timeout;
 205
 206         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 207
 208         if (mask & SDHCI_RESET_ALL) {
 209                 host->clock = 0;
 210                 /* Reset-all turns off SD Bus Power */
 211                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 212                         sdhci_runtime_pm_bus_off(host);
 213         }
 214
 215         /* Wait max 100 ms */
 216         timeout = ktime_add_ms(ktime_get(), 100);
 217
 218         /* hw clears the bit when it's done */
 219         while (1) {
 220                 bool timedout = ktime_after(ktime_get(), timeout);
 221
 222                 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
 223                         break;
 224                 if (timedout) {
 225                         pr_err("%s: Reset 0x%x never completed.\n",
 226                                 mmc_hostname(host->mmc), (int)mask);
 227                         sdhci_dumpregs(host);
 228                         return;
 229                 }
 230                 udelay(10);
 231         }
 232 }
 233 EXPORT_SYMBOL_GPL(sdhci_reset);
 234
 235 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 236 {
 237         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 238                 struct mmc_host *mmc = host->mmc;
 239
 240                 if (!mmc->ops->get_cd(mmc))
 241                         return;
 242         }
 243
 244         host->ops->reset(host, mask);
 245
 246         if (mask & SDHCI_RESET_ALL) {
 247                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 248                         if (host->ops->enable_dma)
 249                                 host->ops->enable_dma(host);
 250                 }
 251
 252                 /* Resetting the controller clears many */
 253                 host->preset_enabled = false;
 254         }
 255 }
 256
 257 static void sdhci_set_default_irqs(struct sdhci_host *host)
 258 {
 259         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 260                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 261                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 262                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 263                     SDHCI_INT_RESPONSE;
 264
 265         if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
 266             host->tuning_mode == SDHCI_TUNING_MODE_3)
 267                 host->ier |= SDHCI_INT_RETUNE;
 268
 269         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 270         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 271 }
 272
 273 static void sdhci_config_dma(struct sdhci_host *host)
 274 {
 275         u8 ctrl;
 276         u16 ctrl2;
 277
 278         if (host->version < SDHCI_SPEC_200)
 279                 return;
 280
 281         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 282
 283         /*
 284          * Always adjust the DMA selection as some controllers
 285          * (e.g. JMicron) can't do PIO properly when the selection
 286          * is ADMA.
 287          */
 288         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 289         if (!(host->flags & SDHCI_REQ_USE_DMA))
 290                 goto out;
 291
 292         /* Note if DMA Select is zero then SDMA is selected */
 293         if (host->flags & SDHCI_USE_ADMA)
 294                 ctrl |= SDHCI_CTRL_ADMA32;
 295
 296         if (host->flags & SDHCI_USE_64_BIT_DMA) {
 297                 /*
 298                  * If v4 mode, all supported DMA can be 64-bit addressing if
 299                  * controller supports 64-bit system address, otherwise only
 300                  * ADMA can support 64-bit addressing.
 301                  */
 302                 if (host->v4_mode) {
 303                         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 304                         ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
 305                         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 306                 } else if (host->flags & SDHCI_USE_ADMA) {
 307                         /*
 308                          * Don't need to undo SDHCI_CTRL_ADMA32 in order to
 309                          * set SDHCI_CTRL_ADMA64.
 310                          */
 311                         ctrl |= SDHCI_CTRL_ADMA64;
 312                 }
 313         }
 314
 315 out:
 316         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 317 }
 318
 319 static void sdhci_init(struct sdhci_host *host, int soft)
 320 {
 321         struct mmc_host *mmc = host->mmc;
 322         unsigned long flags;
 323
 324         if (soft)
 325                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 326         else
 327                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 328
 329         if (host->v4_mode)
 330                 sdhci_do_enable_v4_mode(host);
 331
 332         spin_lock_irqsave(&host->lock, flags);
 333         sdhci_set_default_irqs(host);
 334         spin_unlock_irqrestore(&host->lock, flags);
 335
 336         host->cqe_on = false;
 337
 338         if (soft) {
 339                 /* force clock reconfiguration */
 340                 host->clock = 0;
 341                 mmc->ops->set_ios(mmc, &mmc->ios);
 342         }
 343 }
 344
 345 static void sdhci_reinit(struct sdhci_host *host)
 346 {
 347         u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 348
 349         sdhci_init(host, 0);
 350         sdhci_enable_card_detection(host);
 351
 352         /*
 353          * A change to the card detect bits indicates a change in present state,
 354          * refer sdhci_set_card_detection(). A card detect interrupt might have
 355          * been missed while the host controller was being reset, so trigger a
 356          * rescan to check.
 357          */
 358         if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
 359                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
 360 }
 361
 362 static void __sdhci_led_activate(struct sdhci_host *host)
 363 {
 364         u8 ctrl;
 365
 366         if (host->quirks & SDHCI_QUIRK_NO_LED)
 367                 return;
 368
 369         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 370         ctrl |= SDHCI_CTRL_LED;
 371         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 372 }
 373
 374 static void __sdhci_led_deactivate(struct sdhci_host *host)
 375 {
 376         u8 ctrl;
 377
 378         if (host->quirks & SDHCI_QUIRK_NO_LED)
 379                 return;
 380
 381         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 382         ctrl &= ~SDHCI_CTRL_LED;
 383         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 384 }
 385
 386 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
 387 static void sdhci_led_control(struct led_classdev *led,
 388                               enum led_brightness brightness)
 389 {
 390         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 391         unsigned long flags;
 392
 393         spin_lock_irqsave(&host->lock, flags);
 394
 395         if (host->runtime_suspended)
 396                 goto out;
 397
 398         if (brightness == LED_OFF)
 399                 __sdhci_led_deactivate(host);
 400         else
 401                 __sdhci_led_activate(host);
 402 out:
 403         spin_unlock_irqrestore(&host->lock, flags);
 404 }
 405
 406 static int sdhci_led_register(struct sdhci_host *host)
 407 {
 408         struct mmc_host *mmc = host->mmc;
 409
 410         if (host->quirks & SDHCI_QUIRK_NO_LED)
 411                 return 0;
 412
 413         snprintf(host->led_name, sizeof(host->led_name),
 414                  "%s::", mmc_hostname(mmc));
 415
 416         host->led.name = host->led_name;
 417         host->led.brightness = LED_OFF;
 418         host->led.default_trigger = mmc_hostname(mmc);
 419         host->led.brightness_set = sdhci_led_control;
 420
 421         return led_classdev_register(mmc_dev(mmc), &host->led);
 422 }
 423
 424 static void sdhci_led_unregister(struct sdhci_host *host)
 425 {
 426         if (host->quirks & SDHCI_QUIRK_NO_LED)
 427                 return;
 428
 429         led_classdev_unregister(&host->led);
 430 }
 431
 432 static inline void sdhci_led_activate(struct sdhci_host *host)
 433 {
 434 }
 435
 436 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 437 {
 438 }
 439
 440 #else
 441
 442 static inline int sdhci_led_register(struct sdhci_host *host)
 443 {
 444         return 0;
 445 }
 446
 447 static inline void sdhci_led_unregister(struct sdhci_host *host)
 448 {
 449 }
 450
 451 static inline void sdhci_led_activate(struct sdhci_host *host)
 452 {
 453         __sdhci_led_activate(host);
 454 }
 455
 456 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 457 {
 458         __sdhci_led_deactivate(host);
 459 }
 460
 461 #endif
 462
 463 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
 464                             unsigned long timeout)
 465 {
 466         if (sdhci_data_line_cmd(mrq->cmd))
 467                 mod_timer(&host->data_timer, timeout);
 468         else
 469                 mod_timer(&host->timer, timeout);
 470 }
 471
 472 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
 473 {
 474         if (sdhci_data_line_cmd(mrq->cmd))
 475                 del_timer(&host->data_timer);
 476         else
 477                 del_timer(&host->timer);
 478 }
 479
 480 static inline bool sdhci_has_requests(struct sdhci_host *host)
 481 {
 482         return host->cmd || host->data_cmd;
 483 }
 484
 485 /*****************************************************************************\
 486  *                                                                           *
 487  * Core functions                                                            *
 488  *                                                                           *
 489 \*****************************************************************************/
 490
 491 static void sdhci_read_block_pio(struct sdhci_host *host)
 492 {
 493         unsigned long flags;
 494         size_t blksize, len, chunk;
 495         u32 scratch;
 496         u8 *buf;
 497
 498         DBG("PIO reading\n");
 499
 500         blksize = host->data->blksz;
 501         chunk = 0;
 502
 503         local_irq_save(flags);
 504
 505         while (blksize) {
 506                 BUG_ON(!sg_miter_next(&host->sg_miter));
 507
 508                 len = min(host->sg_miter.length, blksize);
 509
 510                 blksize -= len;
 511                 host->sg_miter.consumed = len;
 512
 513                 buf = host->sg_miter.addr;
 514
 515                 while (len) {
 516                         if (chunk == 0) {
 517                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 518                                 chunk = 4;
 519                         }
 520
 521                         *buf = scratch & 0xFF;
 522
 523                         buf++;
 524                         scratch >>= 8;
 525                         chunk--;
 526                         len--;
 527                 }
 528         }
 529
 530         sg_miter_stop(&host->sg_miter);
 531
 532         local_irq_restore(flags);
 533 }
 534
 535 static void sdhci_write_block_pio(struct sdhci_host *host)
 536 {
 537         unsigned long flags;
 538         size_t blksize, len, chunk;
 539         u32 scratch;
 540         u8 *buf;
 541
 542         DBG("PIO writing\n");
 543
 544         blksize = host->data->blksz;
 545         chunk = 0;
 546         scratch = 0;
 547
 548         local_irq_save(flags);
 549
 550         while (blksize) {
 551                 BUG_ON(!sg_miter_next(&host->sg_miter));
 552
 553                 len = min(host->sg_miter.length, blksize);
 554
 555                 blksize -= len;
 556                 host->sg_miter.consumed = len;
 557
 558                 buf = host->sg_miter.addr;
 559
 560                 while (len) {
 561                         scratch |= (u32)*buf << (chunk * 8);
 562
 563                         buf++;
 564                         chunk++;
 565                         len--;
 566
 567                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 568                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 569                                 chunk = 0;
 570                                 scratch = 0;
 571                         }
 572                 }
 573         }
 574
 575         sg_miter_stop(&host->sg_miter);
 576
 577         local_irq_restore(flags);
 578 }
 579
 580 static void sdhci_transfer_pio(struct sdhci_host *host)
 581 {
 582         u32 mask;
 583
 584         if (host->blocks == 0)
 585                 return;
 586
 587         if (host->data->flags & MMC_DATA_READ)
 588                 mask = SDHCI_DATA_AVAILABLE;
 589         else
 590                 mask = SDHCI_SPACE_AVAILABLE;
 591
 592         /*
 593          * Some controllers (JMicron JMB38x) mess up the buffer bits
 594          * for transfers < 4 bytes. As long as it is just one block,
 595          * we can ignore the bits.
 596          */
 597         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 598                 (host->data->blocks == 1))
 599                 mask = ~0;
 600
 601         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 602                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 603                         udelay(100);
 604
 605                 if (host->data->flags & MMC_DATA_READ)
 606                         sdhci_read_block_pio(host);
 607                 else
 608                         sdhci_write_block_pio(host);
 609
 610                 host->blocks--;
 611                 if (host->blocks == 0)
 612                         break;
 613         }
 614
 615         DBG("PIO transfer complete.\n");
 616 }
 617
 618 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
 619                                   struct mmc_data *data, int cookie)
 620 {
 621         int sg_count;
 622
 623         /*
 624          * If the data buffers are already mapped, return the previous
 625          * dma_map_sg() result.
 626          */
 627         if (data->host_cookie == COOKIE_PRE_MAPPED)
 628                 return data->sg_count;
 629
 630         /* Bounce write requests to the bounce buffer */
 631         if (host->bounce_buffer) {
 632                 unsigned int length = data->blksz * data->blocks;
 633
 634                 if (length > host->bounce_buffer_size) {
 635                         pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
 636                                mmc_hostname(host->mmc), length,
 637                                host->bounce_buffer_size);
 638                         return -EIO;
 639                 }
 640                 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
 641                         /* Copy the data to the bounce buffer */
 642                         if (host->ops->copy_to_bounce_buffer) {
 643                                 host->ops->copy_to_bounce_buffer(host,
 644                                                                  data, length);
 645                         } else {
 646                                 sg_copy_to_buffer(data->sg, data->sg_len,
 647                                                   host->bounce_buffer, length);
 648                         }
 649                 }
 650                 /* Switch ownership to the DMA */
 651                 dma_sync_single_for_device(mmc_dev(host->mmc),
 652                                            host->bounce_addr,
 653                                            host->bounce_buffer_size,
 654                                            mmc_get_dma_dir(data));
 655                 /* Just a dummy value */
 656                 sg_count = 1;
 657         } else {
 658                 /* Just access the data directly from memory */
 659                 sg_count = dma_map_sg(mmc_dev(host->mmc),
 660                                       data->sg, data->sg_len,
 661                                       mmc_get_dma_dir(data));
 662         }
 663
 664         if (sg_count == 0)
 665                 return -ENOSPC;
 666
 667         data->sg_count = sg_count;
 668         data->host_cookie = cookie;
 669
 670         return sg_count;
 671 }
 672
 673 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 674 {
 675         local_irq_save(*flags);
 676         return kmap_atomic(sg_page(sg)) + sg->offset;
 677 }
 678
 679 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 680 {
 681         kunmap_atomic(buffer);
 682         local_irq_restore(*flags);
 683 }
 684
 685 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
 686                            dma_addr_t addr, int len, unsigned int cmd)
 687 {
 688         struct sdhci_adma2_64_desc *dma_desc = *desc;
 689
 690         /* 32-bit and 64-bit descriptors have these members in same position */
 691         dma_desc->cmd = cpu_to_le16(cmd);
 692         dma_desc->len = cpu_to_le16(len);
 693         dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
 694
 695         if (host->flags & SDHCI_USE_64_BIT_DMA)
 696                 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
 697
 698         *desc += host->desc_sz;
 699 }
 700 EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
 701
 702 static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
 703                                            void **desc, dma_addr_t addr,
 704                                            int len, unsigned int cmd)
 705 {
 706         if (host->ops->adma_write_desc)
 707                 host->ops->adma_write_desc(host, desc, addr, len, cmd);
 708         else
 709                 sdhci_adma_write_desc(host, desc, addr, len, cmd);
 710 }
 711
 712 static void sdhci_adma_mark_end(void *desc)
 713 {
 714         struct sdhci_adma2_64_desc *dma_desc = desc;
 715
 716         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 717         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 718 }
 719
 720 static void sdhci_adma_table_pre(struct sdhci_host *host,
 721         struct mmc_data *data, int sg_count)
 722 {
 723         struct scatterlist *sg;
 724         unsigned long flags;
 725         dma_addr_t addr, align_addr;
 726         void *desc, *align;
 727         char *buffer;
 728         int len, offset, i;
 729
 730         /*
 731          * The spec does not specify endianness of descriptor table.
 732          * We currently guess that it is LE.
 733          */
 734
 735         host->sg_count = sg_count;
 736
 737         desc = host->adma_table;
 738         align = host->align_buffer;
 739
 740         align_addr = host->align_addr;
 741
 742         for_each_sg(data->sg, sg, host->sg_count, i) {
 743                 addr = sg_dma_address(sg);
 744                 len = sg_dma_len(sg);
 745
 746                 /*
 747                  * The SDHCI specification states that ADMA addresses must
 748                  * be 32-bit aligned. If they aren't, then we use a bounce
 749                  * buffer for the (up to three) bytes that screw up the
 750                  * alignment.
 751                  */
 752                 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
 753                          SDHCI_ADMA2_MASK;
 754                 if (offset) {
 755                         if (data->flags & MMC_DATA_WRITE) {
 756                                 buffer = sdhci_kmap_atomic(sg, &flags);
 757                                 memcpy(align, buffer, offset);
 758                                 sdhci_kunmap_atomic(buffer, &flags);
 759                         }
 760
 761                         /* tran, valid */
 762                         __sdhci_adma_write_desc(host, &desc, align_addr,
 763                                                 offset, ADMA2_TRAN_VALID);
 764
 765                         BUG_ON(offset > 65536);
 766
 767                         align += SDHCI_ADMA2_ALIGN;
 768                         align_addr += SDHCI_ADMA2_ALIGN;
 769
 770                         addr += offset;
 771                         len -= offset;
 772                 }
 773
 774                 /*
 775                  * The block layer forces a minimum segment size of PAGE_SIZE,
 776                  * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
 777                  * multiple descriptors, noting that the ADMA table is sized
 778                  * for 4KiB chunks anyway, so it will be big enough.
 779                  */
 780                 while (len > host->max_adma) {
 781                         int n = 32 * 1024; /* 32KiB*/
 782
 783                         __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
 784                         addr += n;
 785                         len -= n;
 786                 }
 787
 788                 /* tran, valid */
 789                 if (len)
 790                         __sdhci_adma_write_desc(host, &desc, addr, len,
 791                                                 ADMA2_TRAN_VALID);
 792
 793                 /*
 794                  * If this triggers then we have a calculation bug
 795                  * somewhere. :/
 796                  */
 797                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 798         }
 799
 800         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 801                 /* Mark the last descriptor as the terminating descriptor */
 802                 if (desc != host->adma_table) {
 803                         desc -= host->desc_sz;
 804                         sdhci_adma_mark_end(desc);
 805                 }
 806         } else {
 807                 /* Add a terminating entry - nop, end, valid */
 808                 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
 809         }
 810 }
 811
 812 static void sdhci_adma_table_post(struct sdhci_host *host,
 813         struct mmc_data *data)
 814 {
 815         struct scatterlist *sg;
 816         int i, size;
 817         void *align;
 818         char *buffer;
 819         unsigned long flags;
 820
 821         if (data->flags & MMC_DATA_READ) {
 822                 bool has_unaligned = false;
 823
 824                 /* Do a quick scan of the SG list for any unaligned mappings */
 825                 for_each_sg(data->sg, sg, host->sg_count, i)
 826                         if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 827                                 has_unaligned = true;
 828                                 break;
 829                         }
 830
 831                 if (has_unaligned) {
 832                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 833                                             data->sg_len, DMA_FROM_DEVICE);
 834
 835                         align = host->align_buffer;
 836
 837                         for_each_sg(data->sg, sg, host->sg_count, i) {
 838                                 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 839                                         size = SDHCI_ADMA2_ALIGN -
 840                                                (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
 841
 842                                         buffer = sdhci_kmap_atomic(sg, &flags);
 843                                         memcpy(buffer, align, size);
 844                                         sdhci_kunmap_atomic(buffer, &flags);
 845
 846                                         align += SDHCI_ADMA2_ALIGN;
 847                                 }
 848                         }
 849                 }
 850         }
 851 }
 852
 853 static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
 854 {
 855         sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
 856         if (host->flags & SDHCI_USE_64_BIT_DMA)
 857                 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
 858 }
 859
 860 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
 861 {
 862         if (host->bounce_buffer)
 863                 return host->bounce_addr;
 864         else
 865                 return sg_dma_address(host->data->sg);
 866 }
 867
 868 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
 869 {
 870         if (host->v4_mode)
 871                 sdhci_set_adma_addr(host, addr);
 872         else
 873                 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
 874 }
 875
 876 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
 877                                          struct mmc_command *cmd,
 878                                          struct mmc_data *data)
 879 {
 880         unsigned int target_timeout;
 881
 882         /* timeout in us */
 883         if (!data) {
 884                 target_timeout = cmd->busy_timeout * 1000;
 885         } else {
 886                 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
 887                 if (host->clock && data->timeout_clks) {
 888                         unsigned long long val;
 889
 890                         /*
 891                          * data->timeout_clks is in units of clock cycles.
 892                          * host->clock is in Hz.  target_timeout is in us.
 893                          * Hence, us = 1000000 * cycles / Hz.  Round up.
 894                          */
 895                         val = 1000000ULL * data->timeout_clks;
 896                         if (do_div(val, host->clock))
 897                                 target_timeout++;
 898                         target_timeout += val;
 899                 }
 900         }
 901
 902         return target_timeout;
 903 }
 904
 905 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
 906                                   struct mmc_command *cmd)
 907 {
 908         struct mmc_data *data = cmd->data;
 909         struct mmc_host *mmc = host->mmc;
 910         struct mmc_ios *ios = &mmc->ios;
 911         unsigned char bus_width = 1 << ios->bus_width;
 912         unsigned int blksz;
 913         unsigned int freq;
 914         u64 target_timeout;
 915         u64 transfer_time;
 916
 917         target_timeout = sdhci_target_timeout(host, cmd, data);
 918         target_timeout *= NSEC_PER_USEC;
 919
 920         if (data) {
 921                 blksz = data->blksz;
 922                 freq = mmc->actual_clock ? : host->clock;
 923                 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
 924                 do_div(transfer_time, freq);
 925                 /* multiply by '2' to account for any unknowns */
 926                 transfer_time = transfer_time * 2;
 927                 /* calculate timeout for the entire data */
 928                 host->data_timeout = data->blocks * target_timeout +
 929                                      transfer_time;
 930         } else {
 931                 host->data_timeout = target_timeout;
 932         }
 933
 934         if (host->data_timeout)
 935                 host->data_timeout += MMC_CMD_TRANSFER_TIME;
 936 }
 937
 938 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
 939                              bool *too_big)
 940 {
 941         u8 count;
 942         struct mmc_data *data;
 943         unsigned target_timeout, current_timeout;
 944
 945         *too_big = true;
 946
 947         /*
 948          * If the host controller provides us with an incorrect timeout
 949          * value, just skip the check and use the maximum. The hardware may take
 950          * longer to time out, but that's much better than having a too-short
 951          * timeout value.
 952          */
 953         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 954                 return host->max_timeout_count;
 955
 956         /* Unspecified command, asume max */
 957         if (cmd == NULL)
 958                 return host->max_timeout_count;
 959
 960         data = cmd->data;
 961         /* Unspecified timeout, assume max */
 962         if (!data && !cmd->busy_timeout)
 963                 return host->max_timeout_count;
 964
 965         /* timeout in us */
 966         target_timeout = sdhci_target_timeout(host, cmd, data);
 967
 968         /*
 969          * Figure out needed cycles.
 970          * We do this in steps in order to fit inside a 32 bit int.
 971          * The first step is the minimum timeout, which will have a
 972          * minimum resolution of 6 bits:
 973          * (1) 2^13*1000 > 2^22,
 974          * (2) host->timeout_clk < 2^16
 975          *     =>
 976          *     (1) / (2) > 2^6
 977          */
 978         count = 0;
 979         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 980         while (current_timeout < target_timeout) {
 981                 count++;
 982                 current_timeout <<= 1;
 983                 if (count > host->max_timeout_count)
 984                         break;
 985         }
 986
 987         if (count > host->max_timeout_count) {
 988                 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
 989                         DBG("Too large timeout 0x%x requested for CMD%d!\n",
 990                             count, cmd->opcode);
 991                 count = host->max_timeout_count;
 992         } else {
 993                 *too_big = false;
 994         }
 995
 996         return count;
 997 }
 998
 999 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1000 {
1001         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
1002         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
1003
1004         if (host->flags & SDHCI_REQ_USE_DMA)
1005                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
1006         else
1007                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1008
1009         if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1010                 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1011         else
1012                 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1013
1014         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1015         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1016 }
1017
1018 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1019 {
1020         if (enable)
1021                 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1022         else
1023                 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1024         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1025         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1026 }
1027 EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1028
1029 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1030 {
1031         bool too_big = false;
1032         u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1033
1034         if (too_big &&
1035             host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1036                 sdhci_calc_sw_timeout(host, cmd);
1037                 sdhci_set_data_timeout_irq(host, false);
1038         } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1039                 sdhci_set_data_timeout_irq(host, true);
1040         }
1041
1042         sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1043 }
1044 EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1045
1046 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1047 {
1048         if (host->ops->set_timeout)
1049                 host->ops->set_timeout(host, cmd);
1050         else
1051                 __sdhci_set_timeout(host, cmd);
1052 }
1053
1054 static void sdhci_initialize_data(struct sdhci_host *host,
1055                                   struct mmc_data *data)
1056 {
1057         WARN_ON(host->data);
1058
1059         /* Sanity checks */
1060         BUG_ON(data->blksz * data->blocks > 524288);
1061         BUG_ON(data->blksz > host->mmc->max_blk_size);
1062         BUG_ON(data->blocks > 65535);
1063
1064         host->data = data;
1065         host->data_early = 0;
1066         host->data->bytes_xfered = 0;
1067 }
1068
1069 static inline void sdhci_set_block_info(struct sdhci_host *host,
1070                                         struct mmc_data *data)
1071 {
1072         /* Set the DMA boundary value and block size */
1073         sdhci_writew(host,
1074                      SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1075                      SDHCI_BLOCK_SIZE);
1076         /*
1077          * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1078          * can be supported, in that case 16-bit block count register must be 0.
1079          */
1080         if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1081             (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1082                 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1083                         sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1084                 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1085         } else {
1086                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1087         }
1088 }
1089
1090 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1091 {
1092         struct mmc_data *data = cmd->data;
1093
1094         sdhci_initialize_data(host, data);
1095
1096         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1097                 struct scatterlist *sg;
1098                 unsigned int length_mask, offset_mask;
1099                 int i;
1100
1101                 host->flags |= SDHCI_REQ_USE_DMA;
1102
1103                 /*
1104                  * FIXME: This doesn't account for merging when mapping the
1105                  * scatterlist.
1106                  *
1107                  * The assumption here being that alignment and lengths are
1108                  * the same after DMA mapping to device address space.
1109                  */
1110                 length_mask = 0;
1111                 offset_mask = 0;
1112                 if (host->flags & SDHCI_USE_ADMA) {
1113                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1114                                 length_mask = 3;
1115                                 /*
1116                                  * As we use up to 3 byte chunks to work
1117                                  * around alignment problems, we need to
1118                                  * check the offset as well.
1119                                  */
1120                                 offset_mask = 3;
1121                         }
1122                 } else {
1123                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1124                                 length_mask = 3;
1125                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1126                                 offset_mask = 3;
1127                 }
1128
1129                 if (unlikely(length_mask | offset_mask)) {
1130                         for_each_sg(data->sg, sg, data->sg_len, i) {
1131                                 if (sg->length & length_mask) {
1132                                         DBG("Reverting to PIO because of transfer size (%d)\n",
1133                                             sg->length);
1134                                         host->flags &= ~SDHCI_REQ_USE_DMA;
1135                                         break;
1136                                 }
1137                                 if (sg->offset & offset_mask) {
1138                                         DBG("Reverting to PIO because of bad alignment\n");
1139                                         host->flags &= ~SDHCI_REQ_USE_DMA;
1140                                         break;
1141                                 }
1142                         }
1143                 }
1144         }
1145
1146         if (host->flags & SDHCI_REQ_USE_DMA) {
1147                 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1148
1149                 if (sg_cnt <= 0) {
1150                         /*
1151                          * This only happens when someone fed
1152                          * us an invalid request.
1153                          */
1154                         WARN_ON(1);
1155                         host->flags &= ~SDHCI_REQ_USE_DMA;
1156                 } else if (host->flags & SDHCI_USE_ADMA) {
1157                         sdhci_adma_table_pre(host, data, sg_cnt);
1158                         sdhci_set_adma_addr(host, host->adma_addr);
1159                 } else {
1160                         WARN_ON(sg_cnt != 1);
1161                         sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1162                 }
1163         }
1164
1165         sdhci_config_dma(host);
1166
1167         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1168                 int flags;
1169
1170                 flags = SG_MITER_ATOMIC;
1171                 if (host->data->flags & MMC_DATA_READ)
1172                         flags |= SG_MITER_TO_SG;
1173                 else
1174                         flags |= SG_MITER_FROM_SG;
1175                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1176                 host->blocks = data->blocks;
1177         }
1178
1179         sdhci_set_transfer_irqs(host);
1180
1181         sdhci_set_block_info(host, data);
1182 }
1183
1184 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1185
1186 static int sdhci_external_dma_init(struct sdhci_host *host)
1187 {
1188         int ret = 0;
1189         struct mmc_host *mmc = host->mmc;
1190
1191         host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1192         if (IS_ERR(host->tx_chan)) {
1193                 ret = PTR_ERR(host->tx_chan);
1194                 if (ret != -EPROBE_DEFER)
1195                         pr_warn("Failed to request TX DMA channel.\n");
1196                 host->tx_chan = NULL;
1197                 return ret;
1198         }
1199
1200         host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1201         if (IS_ERR(host->rx_chan)) {
1202                 if (host->tx_chan) {
1203                         dma_release_channel(host->tx_chan);
1204                         host->tx_chan = NULL;
1205                 }
1206
1207                 ret = PTR_ERR(host->rx_chan);
1208                 if (ret != -EPROBE_DEFER)
1209                         pr_warn("Failed to request RX DMA channel.\n");
1210                 host->rx_chan = NULL;
1211         }
1212
1213         return ret;
1214 }
1215
1216 static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1217                                                    struct mmc_data *data)
1218 {
1219         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1220 }
1221
1222 static int sdhci_external_dma_setup(struct sdhci_host *host,
1223                                     struct mmc_command *cmd)
1224 {
1225         int ret, i;
1226         enum dma_transfer_direction dir;
1227         struct dma_async_tx_descriptor *desc;
1228         struct mmc_data *data = cmd->data;
1229         struct dma_chan *chan;
1230         struct dma_slave_config cfg;
1231         dma_cookie_t cookie;
1232         int sg_cnt;
1233
1234         if (!host->mapbase)
1235                 return -EINVAL;
1236
1237         memset(&cfg, 0, sizeof(cfg));
1238         cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1239         cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1240         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1241         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1242         cfg.src_maxburst = data->blksz / 4;
1243         cfg.dst_maxburst = data->blksz / 4;
1244
1245         /* Sanity check: all the SG entries must be aligned by block size. */
1246         for (i = 0; i < data->sg_len; i++) {
1247                 if ((data->sg + i)->length % data->blksz)
1248                         return -EINVAL;
1249         }
1250
1251         chan = sdhci_external_dma_channel(host, data);
1252
1253         ret = dmaengine_slave_config(chan, &cfg);
1254         if (ret)
1255                 return ret;
1256
1257         sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1258         if (sg_cnt <= 0)
1259                 return -EINVAL;
1260
1261         dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1262         desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1263                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1264         if (!desc)
1265                 return -EINVAL;
1266
1267         desc->callback = NULL;
1268         desc->callback_param = NULL;
1269
1270         cookie = dmaengine_submit(desc);
1271         if (dma_submit_error(cookie))
1272                 ret = cookie;
1273
1274         return ret;
1275 }
1276
1277 static void sdhci_external_dma_release(struct sdhci_host *host)
1278 {
1279         if (host->tx_chan) {
1280                 dma_release_channel(host->tx_chan);
1281                 host->tx_chan = NULL;
1282         }
1283
1284         if (host->rx_chan) {
1285                 dma_release_channel(host->rx_chan);
1286                 host->rx_chan = NULL;
1287         }
1288
1289         sdhci_switch_external_dma(host, false);
1290 }
1291
1292 static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1293                                               struct mmc_command *cmd)
1294 {
1295         struct mmc_data *data = cmd->data;
1296
1297         sdhci_initialize_data(host, data);
1298
1299         host->flags |= SDHCI_REQ_USE_DMA;
1300         sdhci_set_transfer_irqs(host);
1301
1302         sdhci_set_block_info(host, data);
1303 }
1304
1305 static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1306                                             struct mmc_command *cmd)
1307 {
1308         if (!sdhci_external_dma_setup(host, cmd)) {
1309                 __sdhci_external_dma_prepare_data(host, cmd);
1310         } else {
1311                 sdhci_external_dma_release(host);
1312                 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1313                        mmc_hostname(host->mmc));
1314                 sdhci_prepare_data(host, cmd);
1315         }
1316 }
1317
1318 static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1319                                             struct mmc_command *cmd)
1320 {
1321         struct dma_chan *chan;
1322
1323         if (!cmd->data)
1324                 return;
1325
1326         chan = sdhci_external_dma_channel(host, cmd->data);
1327         if (chan)
1328                 dma_async_issue_pending(chan);
1329 }
1330
1331 #else
1332
1333 static inline int sdhci_external_dma_init(struct sdhci_host *host)
1334 {
1335         return -EOPNOTSUPP;
1336 }
1337
1338 static inline void sdhci_external_dma_release(struct sdhci_host *host)
1339 {
1340 }
1341
1342 static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1343                                                    struct mmc_command *cmd)
1344 {
1345         /* This should never happen */
1346         WARN_ON_ONCE(1);
1347 }
1348
1349 static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1350                                                    struct mmc_command *cmd)
1351 {
1352 }
1353
1354 static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1355                                                           struct mmc_data *data)
1356 {
1357         return NULL;
1358 }
1359
1360 #endif
1361
1362 void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1363 {
1364         host->use_external_dma = en;
1365 }
1366 EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1367
1368 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1369                                     struct mmc_request *mrq)
1370 {
1371         return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1372                !mrq->cap_cmd_during_tfr;
1373 }
1374
1375 static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1376                                     struct mmc_request *mrq)
1377 {
1378         return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1379 }
1380
1381 static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1382                                       struct mmc_request *mrq)
1383 {
1384         return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1385 }
1386
1387 static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1388                                          struct mmc_command *cmd,
1389                                          u16 *mode)
1390 {
1391         bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1392                          (cmd->opcode != SD_IO_RW_EXTENDED);
1393         bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1394         u16 ctrl2;
1395
1396         /*
1397          * In case of Version 4.10 or later, use of 'Auto CMD Auto
1398          * Select' is recommended rather than use of 'Auto CMD12
1399          * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1400          * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1401          */
1402         if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1403             (use_cmd12 || use_cmd23)) {
1404                 *mode |= SDHCI_TRNS_AUTO_SEL;
1405
1406                 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1407                 if (use_cmd23)
1408                         ctrl2 |= SDHCI_CMD23_ENABLE;
1409                 else
1410                         ctrl2 &= ~SDHCI_CMD23_ENABLE;
1411                 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1412
1413                 return;
1414         }
1415
1416         /*
1417          * If we are sending CMD23, CMD12 never gets sent
1418          * on successful completion (so no Auto-CMD12).
1419          */
1420         if (use_cmd12)
1421                 *mode |= SDHCI_TRNS_AUTO_CMD12;
1422         else if (use_cmd23)
1423                 *mode |= SDHCI_TRNS_AUTO_CMD23;
1424 }
1425
1426 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1427         struct mmc_command *cmd)
1428 {
1429         u16 mode = 0;
1430         struct mmc_data *data = cmd->data;
1431
1432         if (data == NULL) {
1433                 if (host->quirks2 &
1434                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1435                         /* must not clear SDHCI_TRANSFER_MODE when tuning */
1436                         if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1437                                 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1438                 } else {
1439                 /* clear Auto CMD settings for no data CMDs */
1440                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1441                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1442                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1443                 }
1444                 return;
1445         }
1446
1447         WARN_ON(!host->data);
1448
1449         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1450                 mode = SDHCI_TRNS_BLK_CNT_EN;
1451
1452         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1453                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1454                 sdhci_auto_cmd_select(host, cmd, &mode);
1455                 if (sdhci_auto_cmd23(host, cmd->mrq))
1456                         sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1457         }
1458
1459         if (data->flags & MMC_DATA_READ)
1460                 mode |= SDHCI_TRNS_READ;
1461         if (host->flags & SDHCI_REQ_USE_DMA)
1462                 mode |= SDHCI_TRNS_DMA;
1463
1464         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1465 }
1466
1467 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1468 {
1469         return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1470                 ((mrq->cmd && mrq->cmd->error) ||
1471                  (mrq->sbc && mrq->sbc->error) ||
1472                  (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1473                  (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1474 }
1475
1476 static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1477 {
1478         int i;
1479
1480         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1481                 if (host->mrqs_done[i] == mrq) {
1482                         WARN_ON(1);
1483                         return;
1484                 }
1485         }
1486
1487         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1488                 if (!host->mrqs_done[i]) {
1489                         host->mrqs_done[i] = mrq;
1490                         break;
1491                 }
1492         }
1493
1494         WARN_ON(i >= SDHCI_MAX_MRQS);
1495 }
1496
1497 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1498 {
1499         if (host->cmd && host->cmd->mrq == mrq)
1500                 host->cmd = NULL;
1501
1502         if (host->data_cmd && host->data_cmd->mrq == mrq)
1503                 host->data_cmd = NULL;
1504
1505         if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1506                 host->deferred_cmd = NULL;
1507
1508         if (host->data && host->data->mrq == mrq)
1509                 host->data = NULL;
1510
1511         if (sdhci_needs_reset(host, mrq))
1512                 host->pending_reset = true;
1513
1514         sdhci_set_mrq_done(host, mrq);
1515
1516         sdhci_del_timer(host, mrq);
1517
1518         if (!sdhci_has_requests(host))
1519                 sdhci_led_deactivate(host);
1520 }
1521
1522 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1523 {
1524         __sdhci_finish_mrq(host, mrq);
1525
1526         queue_work(host->complete_wq, &host->complete_work);
1527 }
1528
1529 static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1530 {
1531         struct mmc_command *data_cmd = host->data_cmd;
1532         struct mmc_data *data = host->data;
1533
1534         host->data = NULL;
1535         host->data_cmd = NULL;
1536
1537         /*
1538          * The controller needs a reset of internal state machines upon error
1539          * conditions.
1540          */
1541         if (data->error) {
1542                 if (!host->cmd || host->cmd == data_cmd)
1543                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1544                 sdhci_do_reset(host, SDHCI_RESET_DATA);
1545         }
1546
1547         if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1548             (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1549                 sdhci_adma_table_post(host, data);
1550
1551         /*
1552          * The specification states that the block count register must
1553          * be updated, but it does not specify at what point in the
1554          * data flow. That makes the register entirely useless to read
1555          * back so we have to assume that nothing made it to the card
1556          * in the event of an error.
1557          */
1558         if (data->error)
1559                 data->bytes_xfered = 0;
1560         else
1561                 data->bytes_xfered = data->blksz * data->blocks;
1562
1563         /*
1564          * Need to send CMD12 if -
1565          * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1566          * b) error in multiblock transfer
1567          */
1568         if (data->stop &&
1569             ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1570              data->error)) {
1571                 /*
1572                  * 'cap_cmd_during_tfr' request must not use the command line
1573                  * after mmc_command_done() has been called. It is upper layer's
1574                  * responsibility to send the stop command if required.
1575                  */
1576                 if (data->mrq->cap_cmd_during_tfr) {
1577                         __sdhci_finish_mrq(host, data->mrq);
1578                 } else {
1579                         /* Avoid triggering warning in sdhci_send_command() */
1580                         host->cmd = NULL;
1581                         if (!sdhci_send_command(host, data->stop)) {
1582                                 if (sw_data_timeout) {
1583                                         /*
1584                                          * This is anyway a sw data timeout, so
1585                                          * give up now.
1586                                          */
1587                                         data->stop->error = -EIO;
1588                                         __sdhci_finish_mrq(host, data->mrq);
1589                                 } else {
1590                                         WARN_ON(host->deferred_cmd);
1591                                         host->deferred_cmd = data->stop;
1592                                 }
1593                         }
1594                 }
1595         } else {
1596                 __sdhci_finish_mrq(host, data->mrq);
1597         }
1598 }
1599
1600 static void sdhci_finish_data(struct sdhci_host *host)
1601 {
1602         __sdhci_finish_data(host, false);
1603 }
1604
1605 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1606 {
1607         int flags;
1608         u32 mask;
1609         unsigned long timeout;
1610
1611         WARN_ON(host->cmd);
1612
1613         /* Initially, a command has no error */
1614         cmd->error = 0;
1615
1616         if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1617             cmd->opcode == MMC_STOP_TRANSMISSION)
1618                 cmd->flags |= MMC_RSP_BUSY;
1619
1620         mask = SDHCI_CMD_INHIBIT;
1621         if (sdhci_data_line_cmd(cmd))
1622                 mask |= SDHCI_DATA_INHIBIT;
1623
1624         /* We shouldn't wait for data inihibit for stop commands, even
1625            though they might use busy signaling */
1626         if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1627                 mask &= ~SDHCI_DATA_INHIBIT;
1628
1629         if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1630                 return false;
1631
1632         host->cmd = cmd;
1633         host->data_timeout = 0;
1634         if (sdhci_data_line_cmd(cmd)) {
1635                 WARN_ON(host->data_cmd);
1636                 host->data_cmd = cmd;
1637                 sdhci_set_timeout(host, cmd);
1638         }
1639
1640         if (cmd->data) {
1641                 if (host->use_external_dma)
1642                         sdhci_external_dma_prepare_data(host, cmd);
1643                 else
1644                         sdhci_prepare_data(host, cmd);
1645         }
1646
1647         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1648
1649         sdhci_set_transfer_mode(host, cmd);
1650
1651         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1652                 WARN_ONCE(1, "Unsupported response type!\n");
1653                 /*
1654                  * This does not happen in practice because 136-bit response
1655                  * commands never have busy waiting, so rather than complicate
1656                  * the error path, just remove busy waiting and continue.
1657                  */
1658                 cmd->flags &= ~MMC_RSP_BUSY;
1659         }
1660
1661         if (!(cmd->flags & MMC_RSP_PRESENT))
1662                 flags = SDHCI_CMD_RESP_NONE;
1663         else if (cmd->flags & MMC_RSP_136)
1664                 flags = SDHCI_CMD_RESP_LONG;
1665         else if (cmd->flags & MMC_RSP_BUSY)
1666                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1667         else
1668                 flags = SDHCI_CMD_RESP_SHORT;
1669
1670         if (cmd->flags & MMC_RSP_CRC)
1671                 flags |= SDHCI_CMD_CRC;
1672         if (cmd->flags & MMC_RSP_OPCODE)
1673                 flags |= SDHCI_CMD_INDEX;
1674
1675         /* CMD19 is special in that the Data Present Select should be set */
1676         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1677             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1678                 flags |= SDHCI_CMD_DATA;
1679
1680         timeout = jiffies;
1681         if (host->data_timeout)
1682                 timeout += nsecs_to_jiffies(host->data_timeout);
1683         else if (!cmd->data && cmd->busy_timeout > 9000)
1684                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1685         else
1686                 timeout += 10 * HZ;
1687         sdhci_mod_timer(host, cmd->mrq, timeout);
1688
1689         if (host->use_external_dma)
1690                 sdhci_external_dma_pre_transfer(host, cmd);
1691
1692         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1693
1694         return true;
1695 }
1696
1697 static bool sdhci_present_error(struct sdhci_host *host,
1698                                 struct mmc_command *cmd, bool present)
1699 {
1700         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1701                 cmd->error = -ENOMEDIUM;
1702                 return true;
1703         }
1704
1705         return false;
1706 }
1707
1708 static bool sdhci_send_command_retry(struct sdhci_host *host,
1709                                      struct mmc_command *cmd,
1710                                      unsigned long flags)
1711         __releases(host->lock)
1712         __acquires(host->lock)
1713 {
1714         struct mmc_command *deferred_cmd = host->deferred_cmd;
1715         int timeout = 10; /* Approx. 10 ms */
1716         bool present;
1717
1718         while (!sdhci_send_command(host, cmd)) {
1719                 if (!timeout--) {
1720                         pr_err("%s: Controller never released inhibit bit(s).\n",
1721                                mmc_hostname(host->mmc));
1722                         sdhci_dumpregs(host);
1723                         cmd->error = -EIO;
1724                         return false;
1725                 }
1726
1727                 spin_unlock_irqrestore(&host->lock, flags);
1728
1729                 usleep_range(1000, 1250);
1730
1731                 present = host->mmc->ops->get_cd(host->mmc);
1732
1733                 spin_lock_irqsave(&host->lock, flags);
1734
1735                 /* A deferred command might disappear, handle that */
1736                 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1737                         return true;
1738
1739                 if (sdhci_present_error(host, cmd, present))
1740                         return false;
1741         }
1742
1743         if (cmd == host->deferred_cmd)
1744                 host->deferred_cmd = NULL;
1745
1746         return true;
1747 }
1748
1749 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1750 {
1751         int i, reg;
1752
1753         for (i = 0; i < 4; i++) {
1754                 reg = SDHCI_RESPONSE + (3 - i) * 4;
1755                 cmd->resp[i] = sdhci_readl(host, reg);
1756         }
1757
1758         if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1759                 return;
1760
1761         /* CRC is stripped so we need to do some shifting */
1762         for (i = 0; i < 4; i++) {
1763                 cmd->resp[i] <<= 8;
1764                 if (i != 3)
1765                         cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1766         }
1767 }
1768
1769 static void sdhci_finish_command(struct sdhci_host *host)
1770 {
1771         struct mmc_command *cmd = host->cmd;
1772
1773         host->cmd = NULL;
1774
1775         if (cmd->flags & MMC_RSP_PRESENT) {
1776                 if (cmd->flags & MMC_RSP_136) {
1777                         sdhci_read_rsp_136(host, cmd);
1778                 } else {
1779                         cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1780                 }
1781         }
1782
1783         if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1784                 mmc_command_done(host->mmc, cmd->mrq);
1785
1786         /*
1787          * The host can send and interrupt when the busy state has
1788          * ended, allowing us to wait without wasting CPU cycles.
1789          * The busy signal uses DAT0 so this is similar to waiting
1790          * for data to complete.
1791          *
1792          * Note: The 1.0 specification is a bit ambiguous about this
1793          *       feature so there might be some problems with older
1794          *       controllers.
1795          */
1796         if (cmd->flags & MMC_RSP_BUSY) {
1797                 if (cmd->data) {
1798                         DBG("Cannot wait for busy signal when also doing a data transfer");
1799                 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1800                            cmd == host->data_cmd) {
1801                         /* Command complete before busy is ended */
1802                         return;
1803                 }
1804         }
1805
1806         /* Finished CMD23, now send actual command. */
1807         if (cmd == cmd->mrq->sbc) {
1808                 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1809                         WARN_ON(host->deferred_cmd);
1810                         host->deferred_cmd = cmd->mrq->cmd;
1811                 }
1812         } else {
1813
1814                 /* Processed actual command. */
1815                 if (host->data && host->data_early)
1816                         sdhci_finish_data(host);
1817
1818                 if (!cmd->data)
1819                         __sdhci_finish_mrq(host, cmd->mrq);
1820         }
1821 }
1822
1823 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1824 {
1825         u16 preset = 0;
1826
1827         switch (host->timing) {
1828         case MMC_TIMING_MMC_HS:
1829         case MMC_TIMING_SD_HS:
1830                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1831                 break;
1832         case MMC_TIMING_UHS_SDR12:
1833                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1834                 break;
1835         case MMC_TIMING_UHS_SDR25:
1836                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1837                 break;
1838         case MMC_TIMING_UHS_SDR50:
1839                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1840                 break;
1841         case MMC_TIMING_UHS_SDR104:
1842         case MMC_TIMING_MMC_HS200:
1843                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1844                 break;
1845         case MMC_TIMING_UHS_DDR50:
1846         case MMC_TIMING_MMC_DDR52:
1847                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1848                 break;
1849         case MMC_TIMING_MMC_HS400:
1850                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1851                 break;
1852         default:
1853                 pr_warn("%s: Invalid UHS-I mode selected\n",
1854                         mmc_hostname(host->mmc));
1855                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1856                 break;
1857         }
1858         return preset;
1859 }
1860
1861 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1862                    unsigned int *actual_clock)
1863 {
1864         int div = 0; /* Initialized for compiler warning */
1865         int real_div = div, clk_mul = 1;
1866         u16 clk = 0;
1867         bool switch_base_clk = false;
1868
1869         if (host->version >= SDHCI_SPEC_300) {
1870                 if (host->preset_enabled) {
1871                         u16 pre_val;
1872
1873                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1874                         pre_val = sdhci_get_preset_value(host);
1875                         div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1876                         if (host->clk_mul &&
1877                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1878                                 clk = SDHCI_PROG_CLOCK_MODE;
1879                                 real_div = div + 1;
1880                                 clk_mul = host->clk_mul;
1881                         } else {
1882                                 real_div = max_t(int, 1, div << 1);
1883                         }
1884                         goto clock_set;
1885                 }
1886
1887                 /*
1888                  * Check if the Host Controller supports Programmable Clock
1889                  * Mode.
1890                  */
1891                 if (host->clk_mul) {
1892                         for (div = 1; div <= 1024; div++) {
1893                                 if ((host->max_clk * host->clk_mul / div)
1894                                         <= clock)
1895                                         break;
1896                         }
1897                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1898                                 /*
1899                                  * Set Programmable Clock Mode in the Clock
1900                                  * Control register.
1901                                  */
1902                                 clk = SDHCI_PROG_CLOCK_MODE;
1903                                 real_div = div;
1904                                 clk_mul = host->clk_mul;
1905                                 div--;
1906                         } else {
1907                                 /*
1908                                  * Divisor can be too small to reach clock
1909                                  * speed requirement. Then use the base clock.
1910                                  */
1911                                 switch_base_clk = true;
1912                         }
1913                 }
1914
1915                 if (!host->clk_mul || switch_base_clk) {
1916                         /* Version 3.00 divisors must be a multiple of 2. */
1917                         if (host->max_clk <= clock)
1918                                 div = 1;
1919                         else {
1920                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1921                                      div += 2) {
1922                                         if ((host->max_clk / div) <= clock)
1923                                                 break;
1924                                 }
1925                         }
1926                         real_div = div;
1927                         div >>= 1;
1928                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1929                                 && !div && host->max_clk <= 25000000)
1930                                 div = 1;
1931                 }
1932         } else {
1933                 /* Version 2.00 divisors must be a power of 2. */
1934                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1935                         if ((host->max_clk / div) <= clock)
1936                                 break;
1937                 }
1938                 real_div = div;
1939                 div >>= 1;
1940         }
1941
1942 clock_set:
1943         if (real_div)
1944                 *actual_clock = (host->max_clk * clk_mul) / real_div;
1945         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1946         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1947                 << SDHCI_DIVIDER_HI_SHIFT;
1948
1949         return clk;
1950 }
1951 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1952
1953 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1954 {
1955         ktime_t timeout;
1956
1957         clk |= SDHCI_CLOCK_INT_EN;
1958         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1959
1960         /* Wait max 150 ms */
1961         timeout = ktime_add_ms(ktime_get(), 150);
1962         while (1) {
1963                 bool timedout = ktime_after(ktime_get(), timeout);
1964
1965                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1966                 if (clk & SDHCI_CLOCK_INT_STABLE)
1967                         break;
1968                 if (timedout) {
1969                         pr_err("%s: Internal clock never stabilised.\n",
1970                                mmc_hostname(host->mmc));
1971                         sdhci_dumpregs(host);
1972                         return;
1973                 }
1974                 udelay(10);
1975         }
1976
1977         if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1978                 clk |= SDHCI_CLOCK_PLL_EN;
1979                 clk &= ~SDHCI_CLOCK_INT_STABLE;
1980                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1981
1982                 /* Wait max 150 ms */
1983                 timeout = ktime_add_ms(ktime_get(), 150);
1984                 while (1) {
1985                         bool timedout = ktime_after(ktime_get(), timeout);
1986
1987                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1988                         if (clk & SDHCI_CLOCK_INT_STABLE)
1989                                 break;
1990                         if (timedout) {
1991                                 pr_err("%s: PLL clock never stabilised.\n",
1992                                        mmc_hostname(host->mmc));
1993                                 sdhci_dumpregs(host);
1994                                 return;
1995                         }
1996                         udelay(10);
1997                 }
1998         }
1999
2000         clk |= SDHCI_CLOCK_CARD_EN;
2001         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2002 }
2003 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
2004
2005 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2006 {
2007         u16 clk;
2008
2009         host->mmc->actual_clock = 0;
2010
2011         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2012
2013         if (clock == 0)
2014                 return;
2015
2016         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2017         sdhci_enable_clk(host, clk);
2018 }
2019 EXPORT_SYMBOL_GPL(sdhci_set_clock);
2020
2021 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2022                                 unsigned short vdd)
2023 {
2024         struct mmc_host *mmc = host->mmc;
2025
2026         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2027
2028         if (mode != MMC_POWER_OFF)
2029                 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2030         else
2031                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2032 }
2033
2034 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2035                            unsigned short vdd)
2036 {
2037         u8 pwr = 0;
2038
2039         if (mode != MMC_POWER_OFF) {
2040                 switch (1 << vdd) {
2041                 case MMC_VDD_165_195:
2042                 /*
2043                  * Without a regulator, SDHCI does not support 2.0v
2044                  * so we only get here if the driver deliberately
2045                  * added the 2.0v range to ocr_avail. Map it to 1.8v
2046                  * for the purpose of turning on the power.
2047                  */
2048                 case MMC_VDD_20_21:
2049                         pwr = SDHCI_POWER_180;
2050                         break;
2051                 case MMC_VDD_29_30:
2052                 case MMC_VDD_30_31:
2053                         pwr = SDHCI_POWER_300;
2054                         break;
2055                 case MMC_VDD_32_33:
2056                 case MMC_VDD_33_34:
2057                 /*
2058                  * 3.4 ~ 3.6V are valid only for those platforms where it's
2059                  * known that the voltage range is supported by hardware.
2060                  */
2061                 case MMC_VDD_34_35:
2062                 case MMC_VDD_35_36:
2063                         pwr = SDHCI_POWER_330;
2064                         break;
2065                 default:
2066                         WARN(1, "%s: Invalid vdd %#x\n",
2067                              mmc_hostname(host->mmc), vdd);
2068                         break;
2069                 }
2070         }
2071
2072         if (host->pwr == pwr)
2073                 return;
2074
2075         host->pwr = pwr;
2076
2077         if (pwr == 0) {
2078                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2079                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2080                         sdhci_runtime_pm_bus_off(host);
2081         } else {
2082                 /*
2083                  * Spec says that we should clear the power reg before setting
2084                  * a new value. Some controllers don't seem to like this though.
2085                  */
2086                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2087                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2088
2089                 /*
2090                  * At least the Marvell CaFe chip gets confused if we set the
2091                  * voltage and set turn on power at the same time, so set the
2092                  * voltage first.
2093                  */
2094                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2095                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2096
2097                 pwr |= SDHCI_POWER_ON;
2098
2099                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2100
2101                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2102                         sdhci_runtime_pm_bus_on(host);
2103
2104                 /*
2105                  * Some controllers need an extra 10ms delay of 10ms before
2106                  * they can apply clock after applying power
2107                  */
2108                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2109                         mdelay(10);
2110         }
2111 }
2112 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2113
2114 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2115                      unsigned short vdd)
2116 {
2117         if (IS_ERR(host->mmc->supply.vmmc))
2118                 sdhci_set_power_noreg(host, mode, vdd);
2119         else
2120                 sdhci_set_power_reg(host, mode, vdd);
2121 }
2122 EXPORT_SYMBOL_GPL(sdhci_set_power);
2123
2124 /*
2125  * Some controllers need to configure a valid bus voltage on their power
2126  * register regardless of whether an external regulator is taking care of power
2127  * supply. This helper function takes care of it if set as the controller's
2128  * sdhci_ops.set_power callback.
2129  */
2130 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2131                                      unsigned char mode,
2132                                      unsigned short vdd)
2133 {
2134         if (!IS_ERR(host->mmc->supply.vmmc)) {
2135                 struct mmc_host *mmc = host->mmc;
2136
2137                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2138         }
2139         sdhci_set_power_noreg(host, mode, vdd);
2140 }
2141 EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2142
2143 /*****************************************************************************\
2144  *                                                                           *
2145  * MMC callbacks                                                             *
2146  *                                                                           *
2147 \*****************************************************************************/
2148
2149 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2150 {
2151         struct sdhci_host *host = mmc_priv(mmc);
2152         struct mmc_command *cmd;
2153         unsigned long flags;
2154         bool present;
2155
2156         /* Firstly check card presence */
2157         present = mmc->ops->get_cd(mmc);
2158
2159         spin_lock_irqsave(&host->lock, flags);
2160
2161         sdhci_led_activate(host);
2162
2163         if (sdhci_present_error(host, mrq->cmd, present))
2164                 goto out_finish;
2165
2166         cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2167
2168         if (!sdhci_send_command_retry(host, cmd, flags))
2169                 goto out_finish;
2170
2171         spin_unlock_irqrestore(&host->lock, flags);
2172
2173         return;
2174
2175 out_finish:
2176         sdhci_finish_mrq(host, mrq);
2177         spin_unlock_irqrestore(&host->lock, flags);
2178 }
2179 EXPORT_SYMBOL_GPL(sdhci_request);
2180
2181 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2182 {
2183         struct sdhci_host *host = mmc_priv(mmc);
2184         struct mmc_command *cmd;
2185         unsigned long flags;
2186         int ret = 0;
2187
2188         spin_lock_irqsave(&host->lock, flags);
2189
2190         if (sdhci_present_error(host, mrq->cmd, true)) {
2191                 sdhci_finish_mrq(host, mrq);
2192                 goto out_finish;
2193         }
2194
2195         cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2196
2197         /*
2198          * The HSQ may send a command in interrupt context without polling
2199          * the busy signaling, which means we should return BUSY if controller
2200          * has not released inhibit bits to allow HSQ trying to send request
2201          * again in non-atomic context. So we should not finish this request
2202          * here.
2203          */
2204         if (!sdhci_send_command(host, cmd))
2205                 ret = -EBUSY;
2206         else
2207                 sdhci_led_activate(host);
2208
2209 out_finish:
2210         spin_unlock_irqrestore(&host->lock, flags);
2211         return ret;
2212 }
2213 EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2214
2215 void sdhci_set_bus_width(struct sdhci_host *host, int width)
2216 {
2217         u8 ctrl;
2218
2219         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2220         if (width == MMC_BUS_WIDTH_8) {
2221                 ctrl &= ~SDHCI_CTRL_4BITBUS;
2222                 ctrl |= SDHCI_CTRL_8BITBUS;
2223         } else {
2224                 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2225                         ctrl &= ~SDHCI_CTRL_8BITBUS;
2226                 if (width == MMC_BUS_WIDTH_4)
2227                         ctrl |= SDHCI_CTRL_4BITBUS;
2228                 else
2229                         ctrl &= ~SDHCI_CTRL_4BITBUS;
2230         }
2231         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2232 }
2233 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2234
2235 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2236 {
2237         u16 ctrl_2;
2238
2239         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2240         /* Select Bus Speed Mode for host */
2241         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2242         if ((timing == MMC_TIMING_MMC_HS200) ||
2243             (timing == MMC_TIMING_UHS_SDR104))
2244                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2245         else if (timing == MMC_TIMING_UHS_SDR12)
2246                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2247         else if (timing == MMC_TIMING_UHS_SDR25)
2248                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2249         else if (timing == MMC_TIMING_UHS_SDR50)
2250                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2251         else if ((timing == MMC_TIMING_UHS_DDR50) ||
2252                  (timing == MMC_TIMING_MMC_DDR52))
2253                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2254         else if (timing == MMC_TIMING_MMC_HS400)
2255                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2256         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2257 }
2258 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2259
2260 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2261 {
2262         struct sdhci_host *host = mmc_priv(mmc);
2263         u8 ctrl;
2264
2265         if (ios->power_mode == MMC_POWER_UNDEFINED)
2266                 return;
2267
2268         if (host->flags & SDHCI_DEVICE_DEAD) {
2269                 if (!IS_ERR(mmc->supply.vmmc) &&
2270                     ios->power_mode == MMC_POWER_OFF)
2271                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2272                 return;
2273         }
2274
2275         /*
2276          * Reset the chip on each power off.
2277          * Should clear out any weird states.
2278          */
2279         if (ios->power_mode == MMC_POWER_OFF) {
2280                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2281                 sdhci_reinit(host);
2282         }
2283
2284         if (host->version >= SDHCI_SPEC_300 &&
2285                 (ios->power_mode == MMC_POWER_UP) &&
2286                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2287                 sdhci_enable_preset_value(host, false);
2288
2289         if (!ios->clock || ios->clock != host->clock) {
2290                 host->ops->set_clock(host, ios->clock);
2291                 host->clock = ios->clock;
2292
2293                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2294                     host->clock) {
2295                         host->timeout_clk = mmc->actual_clock ?
2296                                                 mmc->actual_clock / 1000 :
2297                                                 host->clock / 1000;
2298                         mmc->max_busy_timeout =
2299                                 host->ops->get_max_timeout_count ?
2300                                 host->ops->get_max_timeout_count(host) :
2301                                 1 << 27;
2302                         mmc->max_busy_timeout /= host->timeout_clk;
2303                 }
2304         }
2305
2306         if (host->ops->set_power)
2307                 host->ops->set_power(host, ios->power_mode, ios->vdd);
2308         else
2309                 sdhci_set_power(host, ios->power_mode, ios->vdd);
2310
2311         if (host->ops->platform_send_init_74_clocks)
2312                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2313
2314         host->ops->set_bus_width(host, ios->bus_width);
2315
2316         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2317
2318         if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2319                 if (ios->timing == MMC_TIMING_SD_HS ||
2320                      ios->timing == MMC_TIMING_MMC_HS ||
2321                      ios->timing == MMC_TIMING_MMC_HS400 ||
2322                      ios->timing == MMC_TIMING_MMC_HS200 ||
2323                      ios->timing == MMC_TIMING_MMC_DDR52 ||
2324                      ios->timing == MMC_TIMING_UHS_SDR50 ||
2325                      ios->timing == MMC_TIMING_UHS_SDR104 ||
2326                      ios->timing == MMC_TIMING_UHS_DDR50 ||
2327                      ios->timing == MMC_TIMING_UHS_SDR25)
2328                         ctrl |= SDHCI_CTRL_HISPD;
2329                 else
2330                         ctrl &= ~SDHCI_CTRL_HISPD;
2331         }
2332
2333         if (host->version >= SDHCI_SPEC_300) {
2334                 u16 clk, ctrl_2;
2335
2336                 if (!host->preset_enabled) {
2337                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2338                         /*
2339                          * We only need to set Driver Strength if the
2340                          * preset value enable is not set.
2341                          */
2342                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2343                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2344                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2345                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2346                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2347                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2348                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2349                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2350                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2351                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2352                         else {
2353                                 pr_warn("%s: invalid driver type, default to driver type B\n",
2354                                         mmc_hostname(mmc));
2355                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2356                         }
2357
2358                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2359                 } else {
2360                         /*
2361                          * According to SDHC Spec v3.00, if the Preset Value
2362                          * Enable in the Host Control 2 register is set, we
2363                          * need to reset SD Clock Enable before changing High
2364                          * Speed Enable to avoid generating clock gliches.
2365                          */
2366
2367                         /* Reset SD Clock Enable */
2368                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2369                         clk &= ~SDHCI_CLOCK_CARD_EN;
2370                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2371
2372                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2373
2374                         /* Re-enable SD Clock */
2375                         host->ops->set_clock(host, host->clock);
2376                 }
2377
2378                 /* Reset SD Clock Enable */
2379                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2380                 clk &= ~SDHCI_CLOCK_CARD_EN;
2381                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2382
2383                 host->ops->set_uhs_signaling(host, ios->timing);
2384                 host->timing = ios->timing;
2385
2386                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2387                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2388                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
2389                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
2390                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
2391                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
2392                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
2393                         u16 preset;
2394
2395                         sdhci_enable_preset_value(host, true);
2396                         preset = sdhci_get_preset_value(host);
2397                         ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2398                                                   preset);
2399                 }
2400
2401                 /* Re-enable SD Clock */
2402                 host->ops->set_clock(host, host->clock);
2403         } else
2404                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2405
2406         /*
2407          * Some (ENE) controllers go apeshit on some ios operation,
2408          * signalling timeout and CRC errors even on CMD0. Resetting
2409          * it on each ios seems to solve the problem.
2410          */
2411         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2412                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2413 }
2414 EXPORT_SYMBOL_GPL(sdhci_set_ios);
2415
2416 static int sdhci_get_cd(struct mmc_host *mmc)
2417 {
2418         struct sdhci_host *host = mmc_priv(mmc);
2419         int gpio_cd = mmc_gpio_get_cd(mmc);
2420
2421         if (host->flags & SDHCI_DEVICE_DEAD)
2422                 return 0;
2423
2424         /* If nonremovable, assume that the card is always present. */
2425         if (!mmc_card_is_removable(mmc))
2426                 return 1;
2427
2428         /*
2429          * Try slot gpio detect, if defined it take precedence
2430          * over build in controller functionality
2431          */
2432         if (gpio_cd >= 0)
2433                 return !!gpio_cd;
2434
2435         /* If polling, assume that the card is always present. */
2436         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2437                 return 1;
2438
2439         /* Host native card detect */
2440         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2441 }
2442
2443 static int sdhci_check_ro(struct sdhci_host *host)
2444 {
2445         unsigned long flags;
2446         int is_readonly;
2447
2448         spin_lock_irqsave(&host->lock, flags);
2449
2450         if (host->flags & SDHCI_DEVICE_DEAD)
2451                 is_readonly = 0;
2452         else if (host->ops->get_ro)
2453                 is_readonly = host->ops->get_ro(host);
2454         else if (mmc_can_gpio_ro(host->mmc))
2455                 is_readonly = mmc_gpio_get_ro(host->mmc);
2456         else
2457                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2458                                 & SDHCI_WRITE_PROTECT);
2459
2460         spin_unlock_irqrestore(&host->lock, flags);
2461
2462         /* This quirk needs to be replaced by a callback-function later */
2463         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2464                 !is_readonly : is_readonly;
2465 }
2466
2467 #define SAMPLE_COUNT    5
2468
2469 static int sdhci_get_ro(struct mmc_host *mmc)
2470 {
2471         struct sdhci_host *host = mmc_priv(mmc);
2472         int i, ro_count;
2473
2474         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2475                 return sdhci_check_ro(host);
2476
2477         ro_count = 0;
2478         for (i = 0; i < SAMPLE_COUNT; i++) {
2479                 if (sdhci_check_ro(host)) {
2480                         if (++ro_count > SAMPLE_COUNT / 2)
2481                                 return 1;
2482                 }
2483                 msleep(30);
2484         }
2485         return 0;
2486 }
2487
2488 static void sdhci_hw_reset(struct mmc_host *mmc)
2489 {
2490         struct sdhci_host *host = mmc_priv(mmc);
2491
2492         if (host->ops && host->ops->hw_reset)
2493                 host->ops->hw_reset(host);
2494 }
2495
2496 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2497 {
2498         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2499                 if (enable)
2500                         host->ier |= SDHCI_INT_CARD_INT;
2501                 else
2502                         host->ier &= ~SDHCI_INT_CARD_INT;
2503
2504                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2505                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2506         }
2507 }
2508
2509 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2510 {
2511         struct sdhci_host *host = mmc_priv(mmc);
2512         unsigned long flags;
2513
2514         if (enable)
2515                 pm_runtime_get_noresume(mmc_dev(mmc));
2516
2517         spin_lock_irqsave(&host->lock, flags);
2518         sdhci_enable_sdio_irq_nolock(host, enable);
2519         spin_unlock_irqrestore(&host->lock, flags);
2520
2521         if (!enable)
2522                 pm_runtime_put_noidle(mmc_dev(mmc));
2523 }
2524 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2525
2526 static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2527 {
2528         struct sdhci_host *host = mmc_priv(mmc);
2529         unsigned long flags;
2530
2531         spin_lock_irqsave(&host->lock, flags);
2532         sdhci_enable_sdio_irq_nolock(host, true);
2533         spin_unlock_irqrestore(&host->lock, flags);
2534 }
2535
2536 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2537                                       struct mmc_ios *ios)
2538 {
2539         struct sdhci_host *host = mmc_priv(mmc);
2540         u16 ctrl;
2541         int ret;
2542
2543         /*
2544          * Signal Voltage Switching is only applicable for Host Controllers
2545          * v3.00 and above.
2546          */
2547         if (host->version < SDHCI_SPEC_300)
2548                 return 0;
2549
2550         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2551
2552         switch (ios->signal_voltage) {
2553         case MMC_SIGNAL_VOLTAGE_330:
2554                 if (!(host->flags & SDHCI_SIGNALING_330))
2555                         return -EINVAL;
2556                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2557                 ctrl &= ~SDHCI_CTRL_VDD_180;
2558                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2559
2560                 if (!IS_ERR(mmc->supply.vqmmc)) {
2561                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2562                         if (ret < 0) {
2563                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2564                                         mmc_hostname(mmc));
2565                                 return -EIO;
2566                         }
2567                 }
2568                 /* Wait for 5ms */
2569                 usleep_range(5000, 5500);
2570
2571                 /* 3.3V regulator output should be stable within 5 ms */
2572                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2573                 if (!(ctrl & SDHCI_CTRL_VDD_180))
2574                         return 0;
2575
2576                 pr_warn("%s: 3.3V regulator output did not become stable\n",
2577                         mmc_hostname(mmc));
2578
2579                 return -EAGAIN;
2580         case MMC_SIGNAL_VOLTAGE_180:
2581                 if (!(host->flags & SDHCI_SIGNALING_180))
2582                         return -EINVAL;
2583                 if (!IS_ERR(mmc->supply.vqmmc)) {
2584                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2585                         if (ret < 0) {
2586                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2587                                         mmc_hostname(mmc));
2588                                 return -EIO;
2589                         }
2590                 }
2591
2592                 /*
2593                  * Enable 1.8V Signal Enable in the Host Control2
2594                  * register
2595                  */
2596                 ctrl |= SDHCI_CTRL_VDD_180;
2597                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2598
2599                 /* Some controller need to do more when switching */
2600                 if (host->ops->voltage_switch)
2601                         host->ops->voltage_switch(host);
2602
2603                 /* 1.8V regulator output should be stable within 5 ms */
2604                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2605                 if (ctrl & SDHCI_CTRL_VDD_180)
2606                         return 0;
2607
2608                 pr_warn("%s: 1.8V regulator output did not become stable\n",
2609                         mmc_hostname(mmc));
2610
2611                 return -EAGAIN;
2612         case MMC_SIGNAL_VOLTAGE_120:
2613                 if (!(host->flags & SDHCI_SIGNALING_120))
2614                         return -EINVAL;
2615                 if (!IS_ERR(mmc->supply.vqmmc)) {
2616                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2617                         if (ret < 0) {
2618                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2619                                         mmc_hostname(mmc));
2620                                 return -EIO;
2621                         }
2622                 }
2623                 return 0;
2624         default:
2625                 /* No signal voltage switch required */
2626                 return 0;
2627         }
2628 }
2629 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2630
2631 static int sdhci_card_busy(struct mmc_host *mmc)
2632 {
2633         struct sdhci_host *host = mmc_priv(mmc);
2634         u32 present_state;
2635
2636         /* Check whether DAT[0] is 0 */
2637         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2638
2639         return !(present_state & SDHCI_DATA_0_LVL_MASK);
2640 }
2641
2642 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2643 {
2644         struct sdhci_host *host = mmc_priv(mmc);
2645         unsigned long flags;
2646
2647         spin_lock_irqsave(&host->lock, flags);
2648         host->flags |= SDHCI_HS400_TUNING;
2649         spin_unlock_irqrestore(&host->lock, flags);
2650
2651         return 0;
2652 }
2653
2654 void sdhci_start_tuning(struct sdhci_host *host)
2655 {
2656         u16 ctrl;
2657
2658         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2659         ctrl |= SDHCI_CTRL_EXEC_TUNING;
2660         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2661                 ctrl |= SDHCI_CTRL_TUNED_CLK;
2662         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2663
2664         /*
2665          * As per the Host Controller spec v3.00, tuning command
2666          * generates Buffer Read Ready interrupt, so enable that.
2667          *
2668          * Note: The spec clearly says that when tuning sequence
2669          * is being performed, the controller does not generate
2670          * interrupts other than Buffer Read Ready interrupt. But
2671          * to make sure we don't hit a controller bug, we _only_
2672          * enable Buffer Read Ready interrupt here.
2673          */
2674         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2675         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2676 }
2677 EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2678
2679 void sdhci_end_tuning(struct sdhci_host *host)
2680 {
2681         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2682         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2683 }
2684 EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2685
2686 void sdhci_reset_tuning(struct sdhci_host *host)
2687 {
2688         u16 ctrl;
2689
2690         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2691         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2692         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2693         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2694 }
2695 EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2696
2697 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2698 {
2699         sdhci_reset_tuning(host);
2700
2701         sdhci_do_reset(host, SDHCI_RESET_CMD);
2702         sdhci_do_reset(host, SDHCI_RESET_DATA);
2703
2704         sdhci_end_tuning(host);
2705
2706         mmc_send_abort_tuning(host->mmc, opcode);
2707 }
2708 EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2709
2710 /*
2711  * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2712  * tuning command does not have a data payload (or rather the hardware does it
2713  * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2714  * interrupt setup is different to other commands and there is no timeout
2715  * interrupt so special handling is needed.
2716  */
2717 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2718 {
2719         struct mmc_host *mmc = host->mmc;
2720         struct mmc_command cmd = {};
2721         struct mmc_request mrq = {};
2722         unsigned long flags;
2723         u32 b = host->sdma_boundary;
2724
2725         spin_lock_irqsave(&host->lock, flags);
2726
2727         cmd.opcode = opcode;
2728         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2729         cmd.mrq = &mrq;
2730
2731         mrq.cmd = &cmd;
2732         /*
2733          * In response to CMD19, the card sends 64 bytes of tuning
2734          * block to the Host Controller. So we set the block size
2735          * to 64 here.
2736          */
2737         if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2738             mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2739                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2740         else
2741                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2742
2743         /*
2744          * The tuning block is sent by the card to the host controller.
2745          * So we set the TRNS_READ bit in the Transfer Mode register.
2746          * This also takes care of setting DMA Enable and Multi Block
2747          * Select in the same register to 0.
2748          */
2749         sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2750
2751         if (!sdhci_send_command_retry(host, &cmd, flags)) {
2752                 spin_unlock_irqrestore(&host->lock, flags);
2753                 host->tuning_done = 0;
2754                 return;
2755         }
2756
2757         host->cmd = NULL;
2758
2759         sdhci_del_timer(host, &mrq);
2760
2761         host->tuning_done = 0;
2762
2763         spin_unlock_irqrestore(&host->lock, flags);
2764
2765         /* Wait for Buffer Read Ready interrupt */
2766         wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2767                            msecs_to_jiffies(50));
2768
2769 }
2770 EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2771
2772 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2773 {
2774         int i;
2775
2776         /*
2777          * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2778          * of loops reaches tuning loop count.
2779          */
2780         for (i = 0; i < host->tuning_loop_count; i++) {
2781                 u16 ctrl;
2782
2783                 sdhci_send_tuning(host, opcode);
2784
2785                 if (!host->tuning_done) {
2786                         pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2787                                  mmc_hostname(host->mmc));
2788                         sdhci_abort_tuning(host, opcode);
2789                         return -ETIMEDOUT;
2790                 }
2791
2792                 /* Spec does not require a delay between tuning cycles */
2793                 if (host->tuning_delay > 0)
2794                         mdelay(host->tuning_delay);
2795
2796                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2797                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2798                         if (ctrl & SDHCI_CTRL_TUNED_CLK)
2799                                 return 0; /* Success! */
2800                         break;
2801                 }
2802
2803         }
2804
2805         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2806                 mmc_hostname(host->mmc));
2807         sdhci_reset_tuning(host);
2808         return -EAGAIN;
2809 }
2810
2811 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2812 {
2813         struct sdhci_host *host = mmc_priv(mmc);
2814         int err = 0;
2815         unsigned int tuning_count = 0;
2816         bool hs400_tuning;
2817
2818         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2819
2820         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2821                 tuning_count = host->tuning_count;
2822
2823         /*
2824          * The Host Controller needs tuning in case of SDR104 and DDR50
2825          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2826          * the Capabilities register.
2827          * If the Host Controller supports the HS200 mode then the
2828          * tuning function has to be executed.
2829          */
2830         switch (host->timing) {
2831         /* HS400 tuning is done in HS200 mode */
2832         case MMC_TIMING_MMC_HS400:
2833                 err = -EINVAL;
2834                 goto out;
2835
2836         case MMC_TIMING_MMC_HS200:
2837                 /*
2838                  * Periodic re-tuning for HS400 is not expected to be needed, so
2839                  * disable it here.
2840                  */
2841                 if (hs400_tuning)
2842                         tuning_count = 0;
2843                 break;
2844
2845         case MMC_TIMING_UHS_SDR104:
2846         case MMC_TIMING_UHS_DDR50:
2847                 break;
2848
2849         case MMC_TIMING_UHS_SDR50:
2850                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2851                         break;
2852                 fallthrough;
2853
2854         default:
2855                 goto out;
2856         }
2857
2858         if (host->ops->platform_execute_tuning) {
2859                 err = host->ops->platform_execute_tuning(host, opcode);
2860                 goto out;
2861         }
2862
2863         mmc->retune_period = tuning_count;
2864
2865         if (host->tuning_delay < 0)
2866                 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2867
2868         sdhci_start_tuning(host);
2869
2870         host->tuning_err = __sdhci_execute_tuning(host, opcode);
2871
2872         sdhci_end_tuning(host);
2873 out:
2874         host->flags &= ~SDHCI_HS400_TUNING;
2875
2876         return err;
2877 }
2878 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2879
2880 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2881 {
2882         /* Host Controller v3.00 defines preset value registers */
2883         if (host->version < SDHCI_SPEC_300)
2884                 return;
2885
2886         /*
2887          * We only enable or disable Preset Value if they are not already
2888          * enabled or disabled respectively. Otherwise, we bail out.
2889          */
2890         if (host->preset_enabled != enable) {
2891                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2892
2893                 if (enable)
2894                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2895                 else
2896                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2897
2898                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2899
2900                 if (enable)
2901                         host->flags |= SDHCI_PV_ENABLED;
2902                 else
2903                         host->flags &= ~SDHCI_PV_ENABLED;
2904
2905                 host->preset_enabled = enable;
2906         }
2907 }
2908
2909 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2910                                 int err)
2911 {
2912         struct mmc_data *data = mrq->data;
2913
2914         if (data->host_cookie != COOKIE_UNMAPPED)
2915                 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
2916                              mmc_get_dma_dir(data));
2917
2918         data->host_cookie = COOKIE_UNMAPPED;
2919 }
2920
2921 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2922 {
2923         struct sdhci_host *host = mmc_priv(mmc);
2924
2925         mrq->data->host_cookie = COOKIE_UNMAPPED;
2926
2927         /*
2928          * No pre-mapping in the pre hook if we're using the bounce buffer,
2929          * for that we would need two bounce buffers since one buffer is
2930          * in flight when this is getting called.
2931          */
2932         if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2933                 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2934 }
2935
2936 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2937 {
2938         if (host->data_cmd) {
2939                 host->data_cmd->error = err;
2940                 sdhci_finish_mrq(host, host->data_cmd->mrq);
2941         }
2942
2943         if (host->cmd) {
2944                 host->cmd->error = err;
2945                 sdhci_finish_mrq(host, host->cmd->mrq);
2946         }
2947 }
2948
2949 static void sdhci_card_event(struct mmc_host *mmc)
2950 {
2951         struct sdhci_host *host = mmc_priv(mmc);
2952         unsigned long flags;
2953         int present;
2954
2955         /* First check if client has provided their own card event */
2956         if (host->ops->card_event)
2957                 host->ops->card_event(host);
2958
2959         present = mmc->ops->get_cd(mmc);
2960
2961         spin_lock_irqsave(&host->lock, flags);
2962
2963         /* Check sdhci_has_requests() first in case we are runtime suspended */
2964         if (sdhci_has_requests(host) && !present) {
2965                 pr_err("%s: Card removed during transfer!\n",
2966                         mmc_hostname(mmc));
2967                 pr_err("%s: Resetting controller.\n",
2968                         mmc_hostname(mmc));
2969
2970                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2971                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2972
2973                 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2974         }
2975
2976         spin_unlock_irqrestore(&host->lock, flags);
2977 }
2978
2979 static const struct mmc_host_ops sdhci_ops = {
2980         .request        = sdhci_request,
2981         .post_req       = sdhci_post_req,
2982         .pre_req        = sdhci_pre_req,
2983         .set_ios        = sdhci_set_ios,
2984         .get_cd         = sdhci_get_cd,
2985         .get_ro         = sdhci_get_ro,
2986         .hw_reset       = sdhci_hw_reset,
2987         .enable_sdio_irq = sdhci_enable_sdio_irq,
2988         .ack_sdio_irq    = sdhci_ack_sdio_irq,
2989         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2990         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2991         .execute_tuning                 = sdhci_execute_tuning,
2992         .card_event                     = sdhci_card_event,
2993         .card_busy      = sdhci_card_busy,
2994 };
2995
2996 /*****************************************************************************\
2997  *                                                                           *
2998  * Request done                                                              *
2999  *                                                                           *
3000 \*****************************************************************************/
3001
3002 static bool sdhci_request_done(struct sdhci_host *host)
3003 {
3004         unsigned long flags;
3005         struct mmc_request *mrq;
3006         int i;
3007
3008         spin_lock_irqsave(&host->lock, flags);
3009
3010         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3011                 mrq = host->mrqs_done[i];
3012                 if (mrq)
3013                         break;
3014         }
3015
3016         if (!mrq) {
3017                 spin_unlock_irqrestore(&host->lock, flags);
3018                 return true;
3019         }
3020
3021         /*
3022          * The controller needs a reset of internal state machines
3023          * upon error conditions.
3024          */
3025         if (sdhci_needs_reset(host, mrq)) {
3026                 /*
3027                  * Do not finish until command and data lines are available for
3028                  * reset. Note there can only be one other mrq, so it cannot
3029                  * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3030                  * would both be null.
3031                  */
3032                 if (host->cmd || host->data_cmd) {
3033                         spin_unlock_irqrestore(&host->lock, flags);
3034                         return true;
3035                 }
3036
3037                 /* Some controllers need this kick or reset won't work here */
3038                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3039                         /* This is to force an update */
3040                         host->ops->set_clock(host, host->clock);
3041
3042                 /*
3043                  * Spec says we should do both at the same time, but Ricoh
3044                  * controllers do not like that.
3045                  */
3046                 sdhci_do_reset(host, SDHCI_RESET_CMD);
3047                 sdhci_do_reset(host, SDHCI_RESET_DATA);
3048
3049                 host->pending_reset = false;
3050         }
3051
3052         /*
3053          * Always unmap the data buffers if they were mapped by
3054          * sdhci_prepare_data() whenever we finish with a request.
3055          * This avoids leaking DMA mappings on error.
3056          */
3057         if (host->flags & SDHCI_REQ_USE_DMA) {
3058                 struct mmc_data *data = mrq->data;
3059
3060                 if (host->use_external_dma && data &&
3061                     (mrq->cmd->error || data->error)) {
3062                         struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3063
3064                         host->mrqs_done[i] = NULL;
3065                         spin_unlock_irqrestore(&host->lock, flags);
3066                         dmaengine_terminate_sync(chan);
3067                         spin_lock_irqsave(&host->lock, flags);
3068                         sdhci_set_mrq_done(host, mrq);
3069                 }
3070
3071                 if (data && data->host_cookie == COOKIE_MAPPED) {
3072                         if (host->bounce_buffer) {
3073                                 /*
3074                                  * On reads, copy the bounced data into the
3075                                  * sglist
3076                                  */
3077                                 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3078                                         unsigned int length = data->bytes_xfered;
3079
3080                                         if (length > host->bounce_buffer_size) {
3081                                                 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3082                                                        mmc_hostname(host->mmc),
3083                                                        host->bounce_buffer_size,
3084                                                        data->bytes_xfered);
3085                                                 /* Cap it down and continue */
3086                                                 length = host->bounce_buffer_size;
3087                                         }
3088                                         dma_sync_single_for_cpu(
3089                                                 mmc_dev(host->mmc),
3090                                                 host->bounce_addr,
3091                                                 host->bounce_buffer_size,
3092                                                 DMA_FROM_DEVICE);
3093                                         sg_copy_from_buffer(data->sg,
3094                                                 data->sg_len,
3095                                                 host->bounce_buffer,
3096                                                 length);
3097                                 } else {
3098                                         /* No copying, just switch ownership */
3099                                         dma_sync_single_for_cpu(
3100                                                 mmc_dev(host->mmc),
3101                                                 host->bounce_addr,
3102                                                 host->bounce_buffer_size,
3103                                                 mmc_get_dma_dir(data));
3104                                 }
3105                         } else {
3106                                 /* Unmap the raw data */
3107                                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3108                                              data->sg_len,
3109                                              mmc_get_dma_dir(data));
3110                         }
3111                         data->host_cookie = COOKIE_UNMAPPED;
3112                 }
3113         }
3114
3115         host->mrqs_done[i] = NULL;
3116
3117         spin_unlock_irqrestore(&host->lock, flags);
3118
3119         if (host->ops->request_done)
3120                 host->ops->request_done(host, mrq);
3121         else
3122                 mmc_request_done(host->mmc, mrq);
3123
3124         return false;
3125 }
3126
3127 static void sdhci_complete_work(struct work_struct *work)
3128 {
3129         struct sdhci_host *host = container_of(work, struct sdhci_host,
3130                                                complete_work);
3131
3132         while (!sdhci_request_done(host))
3133                 ;
3134 }
3135
3136 static void sdhci_timeout_timer(struct timer_list *t)
3137 {
3138         struct sdhci_host *host;
3139         unsigned long flags;
3140
3141         host = from_timer(host, t, timer);
3142
3143         spin_lock_irqsave(&host->lock, flags);
3144
3145         if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3146                 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3147                        mmc_hostname(host->mmc));
3148                 sdhci_dumpregs(host);
3149
3150                 host->cmd->error = -ETIMEDOUT;
3151                 sdhci_finish_mrq(host, host->cmd->mrq);
3152         }
3153
3154         spin_unlock_irqrestore(&host->lock, flags);
3155 }
3156
3157 static void sdhci_timeout_data_timer(struct timer_list *t)
3158 {
3159         struct sdhci_host *host;
3160         unsigned long flags;
3161
3162         host = from_timer(host, t, data_timer);
3163
3164         spin_lock_irqsave(&host->lock, flags);
3165
3166         if (host->data || host->data_cmd ||
3167             (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3168                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3169                        mmc_hostname(host->mmc));
3170                 sdhci_dumpregs(host);
3171
3172                 if (host->data) {
3173                         host->data->error = -ETIMEDOUT;
3174                         __sdhci_finish_data(host, true);
3175                         queue_work(host->complete_wq, &host->complete_work);
3176                 } else if (host->data_cmd) {
3177                         host->data_cmd->error = -ETIMEDOUT;
3178                         sdhci_finish_mrq(host, host->data_cmd->mrq);
3179                 } else {
3180                         host->cmd->error = -ETIMEDOUT;
3181                         sdhci_finish_mrq(host, host->cmd->mrq);
3182                 }
3183         }
3184
3185         spin_unlock_irqrestore(&host->lock, flags);
3186 }
3187
3188 /*****************************************************************************\
3189  *                                                                           *
3190  * Interrupt handling                                                        *
3191  *                                                                           *
3192 \*****************************************************************************/
3193
3194 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3195 {
3196         /* Handle auto-CMD12 error */
3197         if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3198                 struct mmc_request *mrq = host->data_cmd->mrq;
3199                 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3200                 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3201                                    SDHCI_INT_DATA_TIMEOUT :
3202                                    SDHCI_INT_DATA_CRC;
3203
3204                 /* Treat auto-CMD12 error the same as data error */
3205                 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3206                         *intmask_p |= data_err_bit;
3207                         return;
3208                 }
3209         }
3210
3211         if (!host->cmd) {
3212                 /*
3213                  * SDHCI recovers from errors by resetting the cmd and data
3214                  * circuits.  Until that is done, there very well might be more
3215                  * interrupts, so ignore them in that case.
3216                  */
3217                 if (host->pending_reset)
3218                         return;
3219                 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3220                        mmc_hostname(host->mmc), (unsigned)intmask);
3221                 sdhci_dumpregs(host);
3222                 return;
3223         }
3224
3225         if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3226                        SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3227                 if (intmask & SDHCI_INT_TIMEOUT)
3228                         host->cmd->error = -ETIMEDOUT;
3229                 else
3230                         host->cmd->error = -EILSEQ;
3231
3232                 /* Treat data command CRC error the same as data CRC error */
3233                 if (host->cmd->data &&
3234                     (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3235                      SDHCI_INT_CRC) {
3236                         host->cmd = NULL;
3237                         *intmask_p |= SDHCI_INT_DATA_CRC;
3238                         return;
3239                 }
3240
3241                 __sdhci_finish_mrq(host, host->cmd->mrq);
3242                 return;
3243         }
3244
3245         /* Handle auto-CMD23 error */
3246         if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3247                 struct mmc_request *mrq = host->cmd->mrq;
3248                 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3249                 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3250                           -ETIMEDOUT :
3251                           -EILSEQ;
3252
3253                 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3254                         mrq->sbc->error = err;
3255                         __sdhci_finish_mrq(host, mrq);
3256                         return;
3257                 }
3258         }
3259
3260         if (intmask & SDHCI_INT_RESPONSE)
3261                 sdhci_finish_command(host);
3262 }
3263
3264 static void sdhci_adma_show_error(struct sdhci_host *host)
3265 {
3266         void *desc = host->adma_table;
3267         dma_addr_t dma = host->adma_addr;
3268
3269         sdhci_dumpregs(host);
3270
3271         while (true) {
3272                 struct sdhci_adma2_64_desc *dma_desc = desc;
3273
3274                 if (host->flags & SDHCI_USE_64_BIT_DMA)
3275                         SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3276                             (unsigned long long)dma,
3277                             le32_to_cpu(dma_desc->addr_hi),
3278                             le32_to_cpu(dma_desc->addr_lo),
3279                             le16_to_cpu(dma_desc->len),
3280                             le16_to_cpu(dma_desc->cmd));
3281                 else
3282                         SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3283                             (unsigned long long)dma,
3284                             le32_to_cpu(dma_desc->addr_lo),
3285                             le16_to_cpu(dma_desc->len),
3286                             le16_to_cpu(dma_desc->cmd));
3287
3288                 desc += host->desc_sz;
3289                 dma += host->desc_sz;
3290
3291                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3292                         break;
3293         }
3294 }
3295
3296 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3297 {
3298         u32 command;
3299
3300         /*
3301          * CMD19 generates _only_ Buffer Read Ready interrupt if
3302          * use sdhci_send_tuning.
3303          * Need to exclude this case: PIO mode and use mmc_send_tuning,
3304          * If not, sdhci_transfer_pio will never be called, make the
3305          * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
3306          */
3307         if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
3308                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3309                 if (command == MMC_SEND_TUNING_BLOCK ||
3310                     command == MMC_SEND_TUNING_BLOCK_HS200) {
3311                         host->tuning_done = 1;
3312                         wake_up(&host->buf_ready_int);
3313                         return;
3314                 }
3315         }
3316
3317         if (!host->data) {
3318                 struct mmc_command *data_cmd = host->data_cmd;
3319
3320                 /*
3321                  * The "data complete" interrupt is also used to
3322                  * indicate that a busy state has ended. See comment
3323                  * above in sdhci_cmd_irq().
3324                  */
3325                 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3326                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3327                                 host->data_cmd = NULL;
3328                                 data_cmd->error = -ETIMEDOUT;
3329                                 __sdhci_finish_mrq(host, data_cmd->mrq);
3330                                 return;
3331                         }
3332                         if (intmask & SDHCI_INT_DATA_END) {
3333                                 host->data_cmd = NULL;
3334                                 /*
3335                                  * Some cards handle busy-end interrupt
3336                                  * before the command completed, so make
3337                                  * sure we do things in the proper order.
3338                                  */
3339                                 if (host->cmd == data_cmd)
3340                                         return;
3341
3342                                 __sdhci_finish_mrq(host, data_cmd->mrq);
3343                                 return;
3344                         }
3345                 }
3346
3347                 /*
3348                  * SDHCI recovers from errors by resetting the cmd and data
3349                  * circuits. Until that is done, there very well might be more
3350                  * interrupts, so ignore them in that case.
3351                  */
3352                 if (host->pending_reset)
3353                         return;
3354
3355                 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3356                        mmc_hostname(host->mmc), (unsigned)intmask);
3357                 sdhci_dumpregs(host);
3358
3359                 return;
3360         }
3361
3362         if (intmask & SDHCI_INT_DATA_TIMEOUT)
3363                 host->data->error = -ETIMEDOUT;
3364         else if (intmask & SDHCI_INT_DATA_END_BIT)
3365                 host->data->error = -EILSEQ;
3366         else if ((intmask & SDHCI_INT_DATA_CRC) &&
3367                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3368                         != MMC_BUS_TEST_R)
3369                 host->data->error = -EILSEQ;
3370         else if (intmask & SDHCI_INT_ADMA_ERROR) {
3371                 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3372                        intmask);
3373                 sdhci_adma_show_error(host);
3374                 host->data->error = -EIO;
3375                 if (host->ops->adma_workaround)
3376                         host->ops->adma_workaround(host, intmask);
3377         }
3378
3379         if (host->data->error)
3380                 sdhci_finish_data(host);
3381         else {
3382                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3383                         sdhci_transfer_pio(host);
3384
3385                 /*
3386                  * We currently don't do anything fancy with DMA
3387                  * boundaries, but as we can't disable the feature
3388                  * we need to at least restart the transfer.
3389                  *
3390                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3391                  * should return a valid address to continue from, but as
3392                  * some controllers are faulty, don't trust them.
3393                  */
3394                 if (intmask & SDHCI_INT_DMA_END) {
3395                         dma_addr_t dmastart, dmanow;
3396
3397                         dmastart = sdhci_sdma_address(host);
3398                         dmanow = dmastart + host->data->bytes_xfered;
3399                         /*
3400                          * Force update to the next DMA block boundary.
3401                          */
3402                         dmanow = (dmanow &
3403                                 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3404                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
3405                         host->data->bytes_xfered = dmanow - dmastart;
3406                         DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3407                             &dmastart, host->data->bytes_xfered, &dmanow);
3408                         sdhci_set_sdma_addr(host, dmanow);
3409                 }
3410
3411                 if (intmask & SDHCI_INT_DATA_END) {
3412                         if (host->cmd == host->data_cmd) {
3413                                 /*
3414                                  * Data managed to finish before the
3415                                  * command completed. Make sure we do
3416                                  * things in the proper order.
3417                                  */
3418                                 host->data_early = 1;
3419                         } else {
3420                                 sdhci_finish_data(host);
3421                         }
3422                 }
3423         }
3424 }
3425
3426 static inline bool sdhci_defer_done(struct sdhci_host *host,
3427                                     struct mmc_request *mrq)
3428 {
3429         struct mmc_data *data = mrq->data;
3430
3431         return host->pending_reset || host->always_defer_done ||
3432                ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3433                 data->host_cookie == COOKIE_MAPPED);
3434 }
3435
3436 static irqreturn_t sdhci_irq(int irq, void *dev_id)
3437 {
3438         struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3439         irqreturn_t result = IRQ_NONE;
3440         struct sdhci_host *host = dev_id;
3441         u32 intmask, mask, unexpected = 0;
3442         int max_loops = 16;
3443         int i;
3444
3445         spin_lock(&host->lock);
3446
3447         if (host->runtime_suspended) {
3448                 spin_unlock(&host->lock);
3449                 return IRQ_NONE;
3450         }
3451
3452         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3453         if (!intmask || intmask == 0xffffffff) {
3454                 result = IRQ_NONE;
3455                 goto out;
3456         }
3457
3458         do {
3459                 DBG("IRQ status 0x%08x\n", intmask);
3460
3461                 if (host->ops->irq) {
3462                         intmask = host->ops->irq(host, intmask);
3463                         if (!intmask)
3464                                 goto cont;
3465                 }
3466
3467                 /* Clear selected interrupts. */
3468                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3469                                   SDHCI_INT_BUS_POWER);
3470                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3471
3472                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3473                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3474                                       SDHCI_CARD_PRESENT;
3475
3476                         /*
3477                          * There is a observation on i.mx esdhc.  INSERT
3478                          * bit will be immediately set again when it gets
3479                          * cleared, if a card is inserted.  We have to mask
3480                          * the irq to prevent interrupt storm which will
3481                          * freeze the system.  And the REMOVE gets the
3482                          * same situation.
3483                          *
3484                          * More testing are needed here to ensure it works
3485                          * for other platforms though.
3486                          */
3487                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
3488                                        SDHCI_INT_CARD_REMOVE);
3489                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3490                                                SDHCI_INT_CARD_INSERT;
3491                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3492                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3493
3494                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3495                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3496
3497                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3498                                                        SDHCI_INT_CARD_REMOVE);
3499                         result = IRQ_WAKE_THREAD;
3500                 }
3501
3502                 if (intmask & SDHCI_INT_CMD_MASK)
3503                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3504
3505                 if (intmask & SDHCI_INT_DATA_MASK)
3506                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3507
3508                 if (intmask & SDHCI_INT_BUS_POWER)
3509                         pr_err("%s: Card is consuming too much power!\n",
3510                                 mmc_hostname(host->mmc));
3511
3512                 if (intmask & SDHCI_INT_RETUNE)
3513                         mmc_retune_needed(host->mmc);
3514
3515                 if ((intmask & SDHCI_INT_CARD_INT) &&
3516                     (host->ier & SDHCI_INT_CARD_INT)) {
3517                         sdhci_enable_sdio_irq_nolock(host, false);
3518                         sdio_signal_irq(host->mmc);
3519                 }
3520
3521                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3522                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3523                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3524                              SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3525
3526                 if (intmask) {
3527                         unexpected |= intmask;
3528                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3529                 }
3530 cont:
3531                 if (result == IRQ_NONE)
3532                         result = IRQ_HANDLED;
3533
3534                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3535         } while (intmask && --max_loops);
3536
3537         /* Determine if mrqs can be completed immediately */
3538         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3539                 struct mmc_request *mrq = host->mrqs_done[i];
3540
3541                 if (!mrq)
3542                         continue;
3543
3544                 if (sdhci_defer_done(host, mrq)) {
3545                         result = IRQ_WAKE_THREAD;
3546                 } else {
3547                         mrqs_done[i] = mrq;
3548                         host->mrqs_done[i] = NULL;
3549                 }
3550         }
3551 out:
3552         if (host->deferred_cmd)
3553                 result = IRQ_WAKE_THREAD;
3554
3555         spin_unlock(&host->lock);
3556
3557         /* Process mrqs ready for immediate completion */
3558         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3559                 if (!mrqs_done[i])
3560                         continue;
3561
3562                 if (host->ops->request_done)
3563                         host->ops->request_done(host, mrqs_done[i]);
3564                 else
3565                         mmc_request_done(host->mmc, mrqs_done[i]);
3566         }
3567
3568         if (unexpected) {
3569                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3570                            mmc_hostname(host->mmc), unexpected);
3571                 sdhci_dumpregs(host);
3572         }
3573
3574         return result;
3575 }
3576
3577 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3578 {
3579         struct sdhci_host *host = dev_id;
3580         struct mmc_command *cmd;
3581         unsigned long flags;
3582         u32 isr;
3583
3584         while (!sdhci_request_done(host))
3585                 ;
3586
3587         spin_lock_irqsave(&host->lock, flags);
3588
3589         isr = host->thread_isr;
3590         host->thread_isr = 0;
3591
3592         cmd = host->deferred_cmd;
3593         if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3594                 sdhci_finish_mrq(host, cmd->mrq);
3595
3596         spin_unlock_irqrestore(&host->lock, flags);
3597
3598         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3599                 struct mmc_host *mmc = host->mmc;
3600
3601                 mmc->ops->card_event(mmc);
3602                 mmc_detect_change(mmc, msecs_to_jiffies(200));
3603         }
3604
3605         return IRQ_HANDLED;
3606 }
3607
3608 /*****************************************************************************\
3609  *                                                                           *
3610  * Suspend/resume                                                            *
3611  *                                                                           *
3612 \*****************************************************************************/
3613
3614 #ifdef CONFIG_PM
3615
3616 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3617 {
3618         return mmc_card_is_removable(host->mmc) &&
3619                !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3620                !mmc_can_gpio_cd(host->mmc);
3621 }
3622
3623 /*
3624  * To enable wakeup events, the corresponding events have to be enabled in
3625  * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3626  * Table' in the SD Host Controller Standard Specification.
3627  * It is useless to restore SDHCI_INT_ENABLE state in
3628  * sdhci_disable_irq_wakeups() since it will be set by
3629  * sdhci_enable_card_detection() or sdhci_init().
3630  */
3631 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3632 {
3633         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3634                   SDHCI_WAKE_ON_INT;
3635         u32 irq_val = 0;
3636         u8 wake_val = 0;
3637         u8 val;
3638
3639         if (sdhci_cd_irq_can_wakeup(host)) {
3640                 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3641                 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3642         }
3643
3644         if (mmc_card_wake_sdio_irq(host->mmc)) {
3645                 wake_val |= SDHCI_WAKE_ON_INT;
3646                 irq_val |= SDHCI_INT_CARD_INT;
3647         }
3648
3649         if (!irq_val)
3650                 return false;
3651
3652         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3653         val &= ~mask;
3654         val |= wake_val;
3655         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3656
3657         sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3658
3659         host->irq_wake_enabled = !enable_irq_wake(host->irq);
3660
3661         return host->irq_wake_enabled;
3662 }
3663
3664 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3665 {
3666         u8 val;
3667         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3668                         | SDHCI_WAKE_ON_INT;
3669
3670         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3671         val &= ~mask;
3672         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3673
3674         disable_irq_wake(host->irq);
3675
3676         host->irq_wake_enabled = false;
3677 }
3678
3679 int sdhci_suspend_host(struct sdhci_host *host)
3680 {
3681         sdhci_disable_card_detection(host);
3682
3683         mmc_retune_timer_stop(host->mmc);
3684
3685         if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3686             !sdhci_enable_irq_wakeups(host)) {
3687                 host->ier = 0;
3688                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3689                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3690                 free_irq(host->irq, host);
3691         }
3692
3693         return 0;
3694 }
3695
3696 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3697
3698 int sdhci_resume_host(struct sdhci_host *host)
3699 {
3700         struct mmc_host *mmc = host->mmc;
3701         int ret = 0;
3702
3703         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3704                 if (host->ops->enable_dma)
3705                         host->ops->enable_dma(host);
3706         }
3707
3708         if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3709             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3710                 /* Card keeps power but host controller does not */
3711                 sdhci_init(host, 0);
3712                 host->pwr = 0;
3713                 host->clock = 0;
3714                 mmc->ops->set_ios(mmc, &mmc->ios);
3715         } else {
3716                 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3717         }
3718
3719         if (host->irq_wake_enabled) {
3720                 sdhci_disable_irq_wakeups(host);
3721         } else {
3722                 ret = request_threaded_irq(host->irq, sdhci_irq,
3723                                            sdhci_thread_irq, IRQF_SHARED,
3724                                            mmc_hostname(mmc), host);
3725                 if (ret)
3726                         return ret;
3727         }
3728
3729         sdhci_enable_card_detection(host);
3730
3731         return ret;
3732 }
3733
3734 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3735
3736 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3737 {
3738         unsigned long flags;
3739
3740         mmc_retune_timer_stop(host->mmc);
3741
3742         spin_lock_irqsave(&host->lock, flags);
3743         host->ier &= SDHCI_INT_CARD_INT;
3744         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3745         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3746         spin_unlock_irqrestore(&host->lock, flags);
3747
3748         synchronize_hardirq(host->irq);
3749
3750         spin_lock_irqsave(&host->lock, flags);
3751         host->runtime_suspended = true;
3752         spin_unlock_irqrestore(&host->lock, flags);
3753
3754         return 0;
3755 }
3756 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3757
3758 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3759 {
3760         struct mmc_host *mmc = host->mmc;
3761         unsigned long flags;
3762         int host_flags = host->flags;
3763
3764         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3765                 if (host->ops->enable_dma)
3766                         host->ops->enable_dma(host);
3767         }
3768
3769         sdhci_init(host, soft_reset);
3770
3771         if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3772             mmc->ios.power_mode != MMC_POWER_OFF) {
3773                 /* Force clock and power re-program */
3774                 host->pwr = 0;
3775                 host->clock = 0;
3776                 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3777                 mmc->ops->set_ios(mmc, &mmc->ios);
3778
3779                 if ((host_flags & SDHCI_PV_ENABLED) &&
3780                     !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3781                         spin_lock_irqsave(&host->lock, flags);
3782                         sdhci_enable_preset_value(host, true);
3783                         spin_unlock_irqrestore(&host->lock, flags);
3784                 }
3785
3786                 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3787                     mmc->ops->hs400_enhanced_strobe)
3788                         mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3789         }
3790
3791         spin_lock_irqsave(&host->lock, flags);
3792
3793         host->runtime_suspended = false;
3794
3795         /* Enable SDIO IRQ */
3796         if (sdio_irq_claimed(mmc))
3797                 sdhci_enable_sdio_irq_nolock(host, true);
3798
3799         /* Enable Card Detection */
3800         sdhci_enable_card_detection(host);
3801
3802         spin_unlock_irqrestore(&host->lock, flags);
3803
3804         return 0;
3805 }
3806 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3807
3808 #endif /* CONFIG_PM */
3809
3810 /*****************************************************************************\
3811  *                                                                           *
3812  * Command Queue Engine (CQE) helpers                                        *
3813  *                                                                           *
3814 \*****************************************************************************/
3815
3816 void sdhci_cqe_enable(struct mmc_host *mmc)
3817 {
3818         struct sdhci_host *host = mmc_priv(mmc);
3819         unsigned long flags;
3820         u8 ctrl;
3821
3822         spin_lock_irqsave(&host->lock, flags);
3823
3824         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3825         ctrl &= ~SDHCI_CTRL_DMA_MASK;
3826         /*
3827          * Host from V4.10 supports ADMA3 DMA type.
3828          * ADMA3 performs integrated descriptor which is more suitable
3829          * for cmd queuing to fetch both command and transfer descriptors.
3830          */
3831         if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3832                 ctrl |= SDHCI_CTRL_ADMA3;
3833         else if (host->flags & SDHCI_USE_64_BIT_DMA)
3834                 ctrl |= SDHCI_CTRL_ADMA64;
3835         else
3836                 ctrl |= SDHCI_CTRL_ADMA32;
3837         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3838
3839         sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3840                      SDHCI_BLOCK_SIZE);
3841
3842         /* Set maximum timeout */
3843         sdhci_set_timeout(host, NULL);
3844
3845         host->ier = host->cqe_ier;
3846
3847         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3848         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3849
3850         host->cqe_on = true;
3851
3852         pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3853                  mmc_hostname(mmc), host->ier,
3854                  sdhci_readl(host, SDHCI_INT_STATUS));
3855
3856         spin_unlock_irqrestore(&host->lock, flags);
3857 }
3858 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3859
3860 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3861 {
3862         struct sdhci_host *host = mmc_priv(mmc);
3863         unsigned long flags;
3864
3865         spin_lock_irqsave(&host->lock, flags);
3866
3867         sdhci_set_default_irqs(host);
3868
3869         host->cqe_on = false;
3870
3871         if (recovery) {
3872                 sdhci_do_reset(host, SDHCI_RESET_CMD);
3873                 sdhci_do_reset(host, SDHCI_RESET_DATA);
3874         }
3875
3876         pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3877                  mmc_hostname(mmc), host->ier,
3878                  sdhci_readl(host, SDHCI_INT_STATUS));
3879
3880         spin_unlock_irqrestore(&host->lock, flags);
3881 }
3882 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3883
3884 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3885                    int *data_error)
3886 {
3887         u32 mask;
3888
3889         if (!host->cqe_on)
3890                 return false;
3891
3892         if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3893                 *cmd_error = -EILSEQ;
3894         else if (intmask & SDHCI_INT_TIMEOUT)
3895                 *cmd_error = -ETIMEDOUT;
3896         else
3897                 *cmd_error = 0;
3898
3899         if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3900                 *data_error = -EILSEQ;
3901         else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3902                 *data_error = -ETIMEDOUT;
3903         else if (intmask & SDHCI_INT_ADMA_ERROR)
3904                 *data_error = -EIO;
3905         else
3906                 *data_error = 0;
3907
3908         /* Clear selected interrupts. */
3909         mask = intmask & host->cqe_ier;
3910         sdhci_writel(host, mask, SDHCI_INT_STATUS);
3911
3912         if (intmask & SDHCI_INT_BUS_POWER)
3913                 pr_err("%s: Card is consuming too much power!\n",
3914                        mmc_hostname(host->mmc));
3915
3916         intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3917         if (intmask) {
3918                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3919                 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3920                        mmc_hostname(host->mmc), intmask);
3921                 sdhci_dumpregs(host);
3922         }
3923
3924         return true;
3925 }
3926 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3927
3928 /*****************************************************************************\
3929  *                                                                           *
3930  * Device allocation/registration                                            *
3931  *                                                                           *
3932 \*****************************************************************************/
3933
3934 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3935         size_t priv_size)
3936 {
3937         struct mmc_host *mmc;
3938         struct sdhci_host *host;
3939
3940         WARN_ON(dev == NULL);
3941
3942         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3943         if (!mmc)
3944                 return ERR_PTR(-ENOMEM);
3945
3946         host = mmc_priv(mmc);
3947         host->mmc = mmc;
3948         host->mmc_host_ops = sdhci_ops;
3949         mmc->ops = &host->mmc_host_ops;
3950
3951         host->flags = SDHCI_SIGNALING_330;
3952
3953         host->cqe_ier     = SDHCI_CQE_INT_MASK;
3954         host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3955
3956         host->tuning_delay = -1;
3957         host->tuning_loop_count = MAX_TUNING_LOOP;
3958
3959         host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3960
3961         /*
3962          * The DMA table descriptor count is calculated as the maximum
3963          * number of segments times 2, to allow for an alignment
3964          * descriptor for each segment, plus 1 for a nop end descriptor.
3965          */
3966         host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3967         host->max_adma = 65536;
3968
3969         host->max_timeout_count = 0xE;
3970
3971         return host;
3972 }
3973
3974 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3975
3976 static int sdhci_set_dma_mask(struct sdhci_host *host)
3977 {
3978         struct mmc_host *mmc = host->mmc;
3979         struct device *dev = mmc_dev(mmc);
3980         int ret = -EINVAL;
3981
3982         if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3983                 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3984
3985         /* Try 64-bit mask if hardware is capable  of it */
3986         if (host->flags & SDHCI_USE_64_BIT_DMA) {
3987                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3988                 if (ret) {
3989                         pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3990                                 mmc_hostname(mmc));
3991                         host->flags &= ~SDHCI_USE_64_BIT_DMA;
3992                 }
3993         }
3994
3995         /* 32-bit mask as default & fallback */
3996         if (ret) {
3997                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3998                 if (ret)
3999                         pr_warn("%s: Failed to set 32-bit DMA mask.\n",
4000                                 mmc_hostname(mmc));
4001         }
4002
4003         return ret;
4004 }
4005
4006 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4007                        const u32 *caps, const u32 *caps1)
4008 {
4009         u16 v;
4010         u64 dt_caps_mask = 0;
4011         u64 dt_caps = 0;
4012
4013         if (host->read_caps)
4014                 return;
4015
4016         host->read_caps = true;
4017
4018         if (debug_quirks)
4019                 host->quirks = debug_quirks;
4020
4021         if (debug_quirks2)
4022                 host->quirks2 = debug_quirks2;
4023
4024         sdhci_do_reset(host, SDHCI_RESET_ALL);
4025
4026         if (host->v4_mode)
4027                 sdhci_do_enable_v4_mode(host);
4028
4029         device_property_read_u64(mmc_dev(host->mmc),
4030                                  "sdhci-caps-mask", &dt_caps_mask);
4031         device_property_read_u64(mmc_dev(host->mmc),
4032                                  "sdhci-caps", &dt_caps);
4033
4034         v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4035         host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4036
4037         if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4038                 return;
4039
4040         if (caps) {
4041                 host->caps = *caps;
4042         } else {
4043                 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4044                 host->caps &= ~lower_32_bits(dt_caps_mask);
4045                 host->caps |= lower_32_bits(dt_caps);
4046         }
4047
4048         if (host->version < SDHCI_SPEC_300)
4049                 return;
4050
4051         if (caps1) {
4052                 host->caps1 = *caps1;
4053         } else {
4054                 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4055                 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4056                 host->caps1 |= upper_32_bits(dt_caps);
4057         }
4058 }
4059 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4060
4061 static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4062 {
4063         struct mmc_host *mmc = host->mmc;
4064         unsigned int max_blocks;
4065         unsigned int bounce_size;
4066         int ret;
4067
4068         /*
4069          * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4070          * has diminishing returns, this is probably because SD/MMC
4071          * cards are usually optimized to handle this size of requests.
4072          */
4073         bounce_size = SZ_64K;
4074         /*
4075          * Adjust downwards to maximum request size if this is less
4076          * than our segment size, else hammer down the maximum
4077          * request size to the maximum buffer size.
4078          */
4079         if (mmc->max_req_size < bounce_size)
4080                 bounce_size = mmc->max_req_size;
4081         max_blocks = bounce_size / 512;
4082
4083         /*
4084          * When we just support one segment, we can get significant
4085          * speedups by the help of a bounce buffer to group scattered
4086          * reads/writes together.
4087          */
4088         host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4089                                            bounce_size,
4090                                            GFP_KERNEL);
4091         if (!host->bounce_buffer) {
4092                 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4093                        mmc_hostname(mmc),
4094                        bounce_size);
4095                 /*
4096                  * Exiting with zero here makes sure we proceed with
4097                  * mmc->max_segs == 1.
4098                  */
4099                 return;
4100         }
4101
4102         host->bounce_addr = dma_map_single(mmc_dev(mmc),
4103                                            host->bounce_buffer,
4104                                            bounce_size,
4105                                            DMA_BIDIRECTIONAL);
4106         ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4107         if (ret) {
4108                 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4109                 host->bounce_buffer = NULL;
4110                 /* Again fall back to max_segs == 1 */
4111                 return;
4112         }
4113
4114         host->bounce_buffer_size = bounce_size;
4115
4116         /* Lie about this since we're bouncing */
4117         mmc->max_segs = max_blocks;
4118         mmc->max_seg_size = bounce_size;
4119         mmc->max_req_size = bounce_size;
4120
4121         pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4122                 mmc_hostname(mmc), max_blocks, bounce_size);
4123 }
4124
4125 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4126 {
4127         /*
4128          * According to SD Host Controller spec v4.10, bit[27] added from
4129          * version 4.10 in Capabilities Register is used as 64-bit System
4130          * Address support for V4 mode.
4131          */
4132         if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4133                 return host->caps & SDHCI_CAN_64BIT_V4;
4134
4135         return host->caps & SDHCI_CAN_64BIT;
4136 }
4137
4138 int sdhci_setup_host(struct sdhci_host *host)
4139 {
4140         struct mmc_host *mmc;
4141         u32 max_current_caps;
4142         unsigned int ocr_avail;
4143         unsigned int override_timeout_clk;
4144         u32 max_clk;
4145         int ret = 0;
4146         bool enable_vqmmc = false;
4147
4148         WARN_ON(host == NULL);
4149         if (host == NULL)
4150                 return -EINVAL;
4151
4152         mmc = host->mmc;
4153
4154         /*
4155          * If there are external regulators, get them. Note this must be done
4156          * early before resetting the host and reading the capabilities so that
4157          * the host can take the appropriate action if regulators are not
4158          * available.
4159          */
4160         if (!mmc->supply.vqmmc) {
4161                 ret = mmc_regulator_get_supply(mmc);
4162                 if (ret)
4163                         return ret;
4164                 enable_vqmmc  = true;
4165         }
4166
4167         DBG("Version:   0x%08x | Present:  0x%08x\n",
4168             sdhci_readw(host, SDHCI_HOST_VERSION),
4169             sdhci_readl(host, SDHCI_PRESENT_STATE));
4170         DBG("Caps:      0x%08x | Caps_1:   0x%08x\n",
4171             sdhci_readl(host, SDHCI_CAPABILITIES),
4172             sdhci_readl(host, SDHCI_CAPABILITIES_1));
4173
4174         sdhci_read_caps(host);
4175
4176         override_timeout_clk = host->timeout_clk;
4177
4178         if (host->version > SDHCI_SPEC_420) {
4179                 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4180                        mmc_hostname(mmc), host->version);
4181         }
4182
4183         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4184                 host->flags |= SDHCI_USE_SDMA;
4185         else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4186                 DBG("Controller doesn't have SDMA capability\n");
4187         else
4188                 host->flags |= SDHCI_USE_SDMA;
4189
4190         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4191                 (host->flags & SDHCI_USE_SDMA)) {
4192                 DBG("Disabling DMA as it is marked broken\n");
4193                 host->flags &= ~SDHCI_USE_SDMA;
4194         }
4195
4196         if ((host->version >= SDHCI_SPEC_200) &&
4197                 (host->caps & SDHCI_CAN_DO_ADMA2))
4198                 host->flags |= SDHCI_USE_ADMA;
4199
4200         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4201                 (host->flags & SDHCI_USE_ADMA)) {
4202                 DBG("Disabling ADMA as it is marked broken\n");
4203                 host->flags &= ~SDHCI_USE_ADMA;
4204         }
4205
4206         if (sdhci_can_64bit_dma(host))
4207                 host->flags |= SDHCI_USE_64_BIT_DMA;
4208
4209         if (host->use_external_dma) {
4210                 ret = sdhci_external_dma_init(host);
4211                 if (ret == -EPROBE_DEFER)
4212                         goto unreg;
4213                 /*
4214                  * Fall back to use the DMA/PIO integrated in standard SDHCI
4215                  * instead of external DMA devices.
4216                  */
4217                 else if (ret)
4218                         sdhci_switch_external_dma(host, false);
4219                 /* Disable internal DMA sources */
4220                 else
4221                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4222         }
4223
4224         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4225                 if (host->ops->set_dma_mask)
4226                         ret = host->ops->set_dma_mask(host);
4227                 else
4228                         ret = sdhci_set_dma_mask(host);
4229
4230                 if (!ret && host->ops->enable_dma)
4231                         ret = host->ops->enable_dma(host);
4232
4233                 if (ret) {
4234                         pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4235                                 mmc_hostname(mmc));
4236                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4237
4238                         ret = 0;
4239                 }
4240         }
4241
4242         /* SDMA does not support 64-bit DMA if v4 mode not set */
4243         if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4244                 host->flags &= ~SDHCI_USE_SDMA;
4245
4246         if (host->flags & SDHCI_USE_ADMA) {
4247                 dma_addr_t dma;
4248                 void *buf;
4249
4250                 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4251                         host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4252                 else if (!host->alloc_desc_sz)
4253                         host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4254
4255                 host->desc_sz = host->alloc_desc_sz;
4256                 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4257
4258                 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4259                 /*
4260                  * Use zalloc to zero the reserved high 32-bits of 128-bit
4261                  * descriptors so that they never need to be written.
4262                  */
4263                 buf = dma_alloc_coherent(mmc_dev(mmc),
4264                                          host->align_buffer_sz + host->adma_table_sz,
4265                                          &dma, GFP_KERNEL);
4266                 if (!buf) {
4267                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4268                                 mmc_hostname(mmc));
4269                         host->flags &= ~SDHCI_USE_ADMA;
4270                 } else if ((dma + host->align_buffer_sz) &
4271                            (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4272                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4273                                 mmc_hostname(mmc));
4274                         host->flags &= ~SDHCI_USE_ADMA;
4275                         dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4276                                           host->adma_table_sz, buf, dma);
4277                 } else {
4278                         host->align_buffer = buf;
4279                         host->align_addr = dma;
4280
4281                         host->adma_table = buf + host->align_buffer_sz;
4282                         host->adma_addr = dma + host->align_buffer_sz;
4283                 }
4284         }
4285
4286         /*
4287          * If we use DMA, then it's up to the caller to set the DMA
4288          * mask, but PIO does not need the hw shim so we set a new
4289          * mask here in that case.
4290          */
4291         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4292                 host->dma_mask = DMA_BIT_MASK(64);
4293                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4294         }
4295
4296         if (host->version >= SDHCI_SPEC_300)
4297                 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4298         else
4299                 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4300
4301         host->max_clk *= 1000000;
4302         if (host->max_clk == 0 || host->quirks &
4303                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4304                 if (!host->ops->get_max_clock) {
4305                         pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4306                                mmc_hostname(mmc));
4307                         ret = -ENODEV;
4308                         goto undma;
4309                 }
4310                 host->max_clk = host->ops->get_max_clock(host);
4311         }
4312
4313         /*
4314          * In case of Host Controller v3.00, find out whether clock
4315          * multiplier is supported.
4316          */
4317         host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4318
4319         /*
4320          * In case the value in Clock Multiplier is 0, then programmable
4321          * clock mode is not supported, otherwise the actual clock
4322          * multiplier is one more than the value of Clock Multiplier
4323          * in the Capabilities Register.
4324          */
4325         if (host->clk_mul)
4326                 host->clk_mul += 1;
4327
4328         /*
4329          * Set host parameters.
4330          */
4331         max_clk = host->max_clk;
4332
4333         if (host->ops->get_min_clock)
4334                 mmc->f_min = host->ops->get_min_clock(host);
4335         else if (host->version >= SDHCI_SPEC_300) {
4336                 if (host->clk_mul)
4337                         max_clk = host->max_clk * host->clk_mul;
4338                 /*
4339                  * Divided Clock Mode minimum clock rate is always less than
4340                  * Programmable Clock Mode minimum clock rate.
4341                  */
4342                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4343         } else
4344                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4345
4346         if (!mmc->f_max || mmc->f_max > max_clk)
4347                 mmc->f_max = max_clk;
4348
4349         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4350                 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4351
4352                 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4353                         host->timeout_clk *= 1000;
4354
4355                 if (host->timeout_clk == 0) {
4356                         if (!host->ops->get_timeout_clock) {
4357                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4358                                         mmc_hostname(mmc));
4359                                 ret = -ENODEV;
4360                                 goto undma;
4361                         }
4362
4363                         host->timeout_clk =
4364                                 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4365                                              1000);
4366                 }
4367
4368                 if (override_timeout_clk)
4369                         host->timeout_clk = override_timeout_clk;
4370
4371                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4372                         host->ops->get_max_timeout_count(host) : 1 << 27;
4373                 mmc->max_busy_timeout /= host->timeout_clk;
4374         }
4375
4376         if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4377             !host->ops->get_max_timeout_count)
4378                 mmc->max_busy_timeout = 0;
4379
4380         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4381         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4382
4383         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4384                 host->flags |= SDHCI_AUTO_CMD12;
4385
4386         /*
4387          * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4388          * For v4 mode, SDMA may use Auto-CMD23 as well.
4389          */
4390         if ((host->version >= SDHCI_SPEC_300) &&
4391             ((host->flags & SDHCI_USE_ADMA) ||
4392              !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4393              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4394                 host->flags |= SDHCI_AUTO_CMD23;
4395                 DBG("Auto-CMD23 available\n");
4396         } else {
4397                 DBG("Auto-CMD23 unavailable\n");
4398         }
4399
4400         /*
4401          * A controller may support 8-bit width, but the board itself
4402          * might not have the pins brought out.  Boards that support
4403          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4404          * their platform code before calling sdhci_add_host(), and we
4405          * won't assume 8-bit width for hosts without that CAP.
4406          */
4407         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4408                 mmc->caps |= MMC_CAP_4_BIT_DATA;
4409
4410         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4411                 mmc->caps &= ~MMC_CAP_CMD23;
4412
4413         if (host->caps & SDHCI_CAN_DO_HISPD)
4414                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4415
4416         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4417             mmc_card_is_removable(mmc) &&
4418             mmc_gpio_get_cd(mmc) < 0)
4419                 mmc->caps |= MMC_CAP_NEEDS_POLL;
4420
4421         if (!IS_ERR(mmc->supply.vqmmc)) {
4422                 if (enable_vqmmc) {
4423                         ret = regulator_enable(mmc->supply.vqmmc);
4424                         host->sdhci_core_to_disable_vqmmc = !ret;
4425                 }
4426
4427                 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4428                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4429                                                     1950000))
4430                         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4431                                          SDHCI_SUPPORT_SDR50 |
4432                                          SDHCI_SUPPORT_DDR50);
4433
4434                 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4435                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4436                                                     3600000))
4437                         host->flags &= ~SDHCI_SIGNALING_330;
4438
4439                 if (ret) {
4440                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4441                                 mmc_hostname(mmc), ret);
4442                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4443                 }
4444
4445         }
4446
4447         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4448                 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4449                                  SDHCI_SUPPORT_DDR50);
4450                 /*
4451                  * The SDHCI controller in a SoC might support HS200/HS400
4452                  * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4453                  * but if the board is modeled such that the IO lines are not
4454                  * connected to 1.8v then HS200/HS400 cannot be supported.
4455                  * Disable HS200/HS400 if the board does not have 1.8v connected
4456                  * to the IO lines. (Applicable for other modes in 1.8v)
4457                  */
4458                 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4459                 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4460         }
4461
4462         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4463         if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4464                            SDHCI_SUPPORT_DDR50))
4465                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4466
4467         /* SDR104 supports also implies SDR50 support */
4468         if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4469                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4470                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4471                  * field can be promoted to support HS200.
4472                  */
4473                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4474                         mmc->caps2 |= MMC_CAP2_HS200;
4475         } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4476                 mmc->caps |= MMC_CAP_UHS_SDR50;
4477         }
4478
4479         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4480             (host->caps1 & SDHCI_SUPPORT_HS400))
4481                 mmc->caps2 |= MMC_CAP2_HS400;
4482
4483         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4484             (IS_ERR(mmc->supply.vqmmc) ||
4485              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4486                                              1300000)))
4487                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4488
4489         if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4490             !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4491                 mmc->caps |= MMC_CAP_UHS_DDR50;
4492
4493         /* Does the host need tuning for SDR50? */
4494         if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4495                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4496
4497         /* Driver Type(s) (A, C, D) supported by the host */
4498         if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4499                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4500         if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4501                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4502         if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4503                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4504
4505         /* Initial value for re-tuning timer count */
4506         host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4507                                        host->caps1);
4508
4509         /*
4510          * In case Re-tuning Timer is not disabled, the actual value of
4511          * re-tuning timer will be 2 ^ (n - 1).
4512          */
4513         if (host->tuning_count)
4514                 host->tuning_count = 1 << (host->tuning_count - 1);
4515
4516         /* Re-tuning mode supported by the Host Controller */
4517         host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4518
4519         ocr_avail = 0;
4520
4521         /*
4522          * According to SD Host Controller spec v3.00, if the Host System
4523          * can afford more than 150mA, Host Driver should set XPC to 1. Also
4524          * the value is meaningful only if Voltage Support in the Capabilities
4525          * register is set. The actual current value is 4 times the register
4526          * value.
4527          */
4528         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4529         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4530                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4531                 if (curr > 0) {
4532
4533                         /* convert to SDHCI_MAX_CURRENT format */
4534                         curr = curr/1000;  /* convert to mA */
4535                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4536
4537                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4538                         max_current_caps =
4539                                 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4540                                 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4541                                 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4542                 }
4543         }
4544
4545         if (host->caps & SDHCI_CAN_VDD_330) {
4546                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4547
4548                 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4549                                                  max_current_caps) *
4550                                                 SDHCI_MAX_CURRENT_MULTIPLIER;
4551         }
4552         if (host->caps & SDHCI_CAN_VDD_300) {
4553                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4554
4555                 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4556                                                  max_current_caps) *
4557                                                 SDHCI_MAX_CURRENT_MULTIPLIER;
4558         }
4559         if (host->caps & SDHCI_CAN_VDD_180) {
4560                 ocr_avail |= MMC_VDD_165_195;
4561
4562                 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4563                                                  max_current_caps) *
4564                                                 SDHCI_MAX_CURRENT_MULTIPLIER;
4565         }
4566
4567         /* If OCR set by host, use it instead. */
4568         if (host->ocr_mask)
4569                 ocr_avail = host->ocr_mask;
4570
4571         /* If OCR set by external regulators, give it highest prio. */
4572         if (mmc->ocr_avail)
4573                 ocr_avail = mmc->ocr_avail;
4574
4575         mmc->ocr_avail = ocr_avail;
4576         mmc->ocr_avail_sdio = ocr_avail;
4577         if (host->ocr_avail_sdio)
4578                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4579         mmc->ocr_avail_sd = ocr_avail;
4580         if (host->ocr_avail_sd)
4581                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4582         else /* normal SD controllers don't support 1.8V */
4583                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4584         mmc->ocr_avail_mmc = ocr_avail;
4585         if (host->ocr_avail_mmc)
4586                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4587
4588         if (mmc->ocr_avail == 0) {
4589                 pr_err("%s: Hardware doesn't report any support voltages.\n",
4590                        mmc_hostname(mmc));
4591                 ret = -ENODEV;
4592                 goto unreg;
4593         }
4594
4595         if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4596                           MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4597                           MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4598             (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4599                 host->flags |= SDHCI_SIGNALING_180;
4600
4601         if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4602                 host->flags |= SDHCI_SIGNALING_120;
4603
4604         spin_lock_init(&host->lock);
4605
4606         /*
4607          * Maximum number of sectors in one transfer. Limited by SDMA boundary
4608          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4609          * is less anyway.
4610          */
4611         mmc->max_req_size = 524288;
4612
4613         /*
4614          * Maximum number of segments. Depends on if the hardware
4615          * can do scatter/gather or not.
4616          */
4617         if (host->flags & SDHCI_USE_ADMA) {
4618                 mmc->max_segs = SDHCI_MAX_SEGS;
4619         } else if (host->flags & SDHCI_USE_SDMA) {
4620                 mmc->max_segs = 1;
4621                 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4622                                           dma_max_mapping_size(mmc_dev(mmc)));
4623         } else { /* PIO */
4624                 mmc->max_segs = SDHCI_MAX_SEGS;
4625         }
4626
4627         /*
4628          * Maximum segment size. Could be one segment with the maximum number
4629          * of bytes. When doing hardware scatter/gather, each entry cannot
4630          * be larger than 64 KiB though.
4631          */
4632         if (host->flags & SDHCI_USE_ADMA) {
4633                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4634                         host->max_adma = 65532; /* 32-bit alignment */
4635                         mmc->max_seg_size = 65535;
4636                 } else {
4637                         mmc->max_seg_size = 65536;
4638                 }
4639         } else {
4640                 mmc->max_seg_size = mmc->max_req_size;
4641         }
4642
4643         /*
4644          * Maximum block size. This varies from controller to controller and
4645          * is specified in the capabilities register.
4646          */
4647         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4648                 mmc->max_blk_size = 2;
4649         } else {
4650                 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4651                                 SDHCI_MAX_BLOCK_SHIFT;
4652                 if (mmc->max_blk_size >= 3) {
4653                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4654                                 mmc_hostname(mmc));
4655                         mmc->max_blk_size = 0;
4656                 }
4657         }
4658
4659         mmc->max_blk_size = 512 << mmc->max_blk_size;
4660
4661         /*
4662          * Maximum block count.
4663          */
4664         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4665
4666         if (mmc->max_segs == 1)
4667                 /* This may alter mmc->*_blk_* parameters */
4668                 sdhci_allocate_bounce_buffer(host);
4669
4670         return 0;
4671
4672 unreg:
4673         if (host->sdhci_core_to_disable_vqmmc)
4674                 regulator_disable(mmc->supply.vqmmc);
4675 undma:
4676         if (host->align_buffer)
4677                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4678                                   host->adma_table_sz, host->align_buffer,
4679                                   host->align_addr);
4680         host->adma_table = NULL;
4681         host->align_buffer = NULL;
4682
4683         return ret;
4684 }
4685 EXPORT_SYMBOL_GPL(sdhci_setup_host);
4686
4687 void sdhci_cleanup_host(struct sdhci_host *host)
4688 {
4689         struct mmc_host *mmc = host->mmc;
4690
4691         if (host->sdhci_core_to_disable_vqmmc)
4692                 regulator_disable(mmc->supply.vqmmc);
4693
4694         if (host->align_buffer)
4695                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4696                                   host->adma_table_sz, host->align_buffer,
4697                                   host->align_addr);
4698
4699         if (host->use_external_dma)
4700                 sdhci_external_dma_release(host);
4701
4702         host->adma_table = NULL;
4703         host->align_buffer = NULL;
4704 }
4705 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4706
4707 int __sdhci_add_host(struct sdhci_host *host)
4708 {
4709         unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4710         struct mmc_host *mmc = host->mmc;
4711         int ret;
4712
4713         if ((mmc->caps2 & MMC_CAP2_CQE) &&
4714             (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4715                 mmc->caps2 &= ~MMC_CAP2_CQE;
4716                 mmc->cqe_ops = NULL;
4717         }
4718
4719         host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4720         if (!host->complete_wq)
4721                 return -ENOMEM;
4722
4723         INIT_WORK(&host->complete_work, sdhci_complete_work);
4724
4725         timer_setup(&host->timer, sdhci_timeout_timer, 0);
4726         timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4727
4728         init_waitqueue_head(&host->buf_ready_int);
4729
4730         sdhci_init(host, 0);
4731
4732         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4733                                    IRQF_SHARED, mmc_hostname(mmc), host);
4734         if (ret) {
4735                 pr_err("%s: Failed to request IRQ %d: %d\n",
4736                        mmc_hostname(mmc), host->irq, ret);
4737                 goto unwq;
4738         }
4739
4740         ret = sdhci_led_register(host);
4741         if (ret) {
4742                 pr_err("%s: Failed to register LED device: %d\n",
4743                        mmc_hostname(mmc), ret);
4744                 goto unirq;
4745         }
4746
4747         ret = mmc_add_host(mmc);
4748         if (ret)
4749                 goto unled;
4750
4751         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4752                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4753                 host->use_external_dma ? "External DMA" :
4754                 (host->flags & SDHCI_USE_ADMA) ?
4755                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4756                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4757
4758         sdhci_enable_card_detection(host);
4759
4760         return 0;
4761
4762 unled:
4763         sdhci_led_unregister(host);
4764 unirq:
4765         sdhci_do_reset(host, SDHCI_RESET_ALL);
4766         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4767         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4768         free_irq(host->irq, host);
4769 unwq:
4770         destroy_workqueue(host->complete_wq);
4771
4772         return ret;
4773 }
4774 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4775
4776 int sdhci_add_host(struct sdhci_host *host)
4777 {
4778         int ret;
4779
4780         ret = sdhci_setup_host(host);
4781         if (ret)
4782                 return ret;
4783
4784         ret = __sdhci_add_host(host);
4785         if (ret)
4786                 goto cleanup;
4787
4788         return 0;
4789
4790 cleanup:
4791         sdhci_cleanup_host(host);
4792
4793         return ret;
4794 }
4795 EXPORT_SYMBOL_GPL(sdhci_add_host);
4796
4797 void sdhci_remove_host(struct sdhci_host *host, int dead)
4798 {
4799         struct mmc_host *mmc = host->mmc;
4800         unsigned long flags;
4801
4802         if (dead) {
4803                 spin_lock_irqsave(&host->lock, flags);
4804
4805                 host->flags |= SDHCI_DEVICE_DEAD;
4806
4807                 if (sdhci_has_requests(host)) {
4808                         pr_err("%s: Controller removed during "
4809                                 " transfer!\n", mmc_hostname(mmc));
4810                         sdhci_error_out_mrqs(host, -ENOMEDIUM);
4811                 }
4812
4813                 spin_unlock_irqrestore(&host->lock, flags);
4814         }
4815
4816         sdhci_disable_card_detection(host);
4817
4818         mmc_remove_host(mmc);
4819
4820         sdhci_led_unregister(host);
4821
4822         if (!dead)
4823                 sdhci_do_reset(host, SDHCI_RESET_ALL);
4824
4825         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4826         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4827         free_irq(host->irq, host);
4828
4829         del_timer_sync(&host->timer);
4830         del_timer_sync(&host->data_timer);
4831
4832         destroy_workqueue(host->complete_wq);
4833
4834         if (host->sdhci_core_to_disable_vqmmc)
4835                 regulator_disable(mmc->supply.vqmmc);
4836
4837         if (host->align_buffer)
4838                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4839                                   host->adma_table_sz, host->align_buffer,
4840                                   host->align_addr);
4841
4842         if (host->use_external_dma)
4843                 sdhci_external_dma_release(host);
4844
4845         host->adma_table = NULL;
4846         host->align_buffer = NULL;
4847 }
4848
4849 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4850
4851 void sdhci_free_host(struct sdhci_host *host)
4852 {
4853         mmc_free_host(host->mmc);
4854 }
4855
4856 EXPORT_SYMBOL_GPL(sdhci_free_host);
4857
4858 /*****************************************************************************\
4859  *                                                                           *
4860  * Driver init/exit                                                          *
4861  *                                                                           *
4862 \*****************************************************************************/
4863
4864 static int __init sdhci_drv_init(void)
4865 {
4866         pr_info(DRIVER_NAME
4867                 ": Secure Digital Host Controller Interface driver\n");
4868         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4869
4870         return 0;
4871 }
4872
4873 static void __exit sdhci_drv_exit(void)
4874 {
4875 }
4876
4877 module_init(sdhci_drv_init);
4878 module_exit(sdhci_drv_exit);
4879
4880 module_param(debug_quirks, uint, 0444);
4881 module_param(debug_quirks2, uint, 0444);
4882
4883 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4884 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4885 MODULE_LICENSE("GPL");
4886
4887 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4888 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");