2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
22 #include <linux/leds.h>
24 #include <linux/mmc/host.h>
28 #define DRIVER_NAME "sdhci"
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
33 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
34 defined(CONFIG_MMC_SDHCI_MODULE))
35 #define SDHCI_USE_LEDS_CLASS
38 static unsigned int debug_quirks = 0;
40 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
41 static void sdhci_finish_data(struct sdhci_host *);
43 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
44 static void sdhci_finish_command(struct sdhci_host *);
46 static void sdhci_dumpregs(struct sdhci_host *host)
48 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
50 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
51 sdhci_readl(host, SDHCI_DMA_ADDRESS),
52 sdhci_readw(host, SDHCI_HOST_VERSION));
53 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
54 sdhci_readw(host, SDHCI_BLOCK_SIZE),
55 sdhci_readw(host, SDHCI_BLOCK_COUNT));
56 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
57 sdhci_readl(host, SDHCI_ARGUMENT),
58 sdhci_readw(host, SDHCI_TRANSFER_MODE));
59 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
60 sdhci_readl(host, SDHCI_PRESENT_STATE),
61 sdhci_readb(host, SDHCI_HOST_CONTROL));
62 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
63 sdhci_readb(host, SDHCI_POWER_CONTROL),
64 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
65 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
66 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
67 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
68 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
69 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
70 sdhci_readl(host, SDHCI_INT_STATUS));
71 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
72 sdhci_readl(host, SDHCI_INT_ENABLE),
73 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
74 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
75 sdhci_readw(host, SDHCI_ACMD12_ERR),
76 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
77 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
78 sdhci_readl(host, SDHCI_CAPABILITIES),
79 sdhci_readl(host, SDHCI_MAX_CURRENT));
81 if (host->flags & SDHCI_USE_ADMA)
82 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
83 readl(host->ioaddr + SDHCI_ADMA_ERROR),
84 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
86 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
89 /*****************************************************************************\
91 * Low level functions *
93 \*****************************************************************************/
95 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
99 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
102 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
103 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
106 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
108 sdhci_clear_set_irqs(host, 0, irqs);
111 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
113 sdhci_clear_set_irqs(host, irqs, 0);
116 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
118 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
120 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
124 sdhci_unmask_irqs(host, irqs);
126 sdhci_mask_irqs(host, irqs);
129 static void sdhci_enable_card_detection(struct sdhci_host *host)
131 sdhci_set_card_detection(host, true);
134 static void sdhci_disable_card_detection(struct sdhci_host *host)
136 sdhci_set_card_detection(host, false);
139 static void sdhci_reset(struct sdhci_host *host, u8 mask)
141 unsigned long timeout;
142 u32 uninitialized_var(ier);
144 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
145 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
150 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
151 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
153 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
155 if (mask & SDHCI_RESET_ALL)
158 /* Wait max 100 ms */
161 /* hw clears the bit when it's done */
162 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
164 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
165 mmc_hostname(host->mmc), (int)mask);
166 sdhci_dumpregs(host);
173 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
174 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
177 static void sdhci_init(struct sdhci_host *host)
179 sdhci_reset(host, SDHCI_RESET_ALL);
181 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
182 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
183 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
184 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
185 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
188 static void sdhci_reinit(struct sdhci_host *host)
191 sdhci_enable_card_detection(host);
194 static void sdhci_activate_led(struct sdhci_host *host)
198 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
199 ctrl |= SDHCI_CTRL_LED;
200 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
203 static void sdhci_deactivate_led(struct sdhci_host *host)
207 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
208 ctrl &= ~SDHCI_CTRL_LED;
209 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
212 #ifdef SDHCI_USE_LEDS_CLASS
213 static void sdhci_led_control(struct led_classdev *led,
214 enum led_brightness brightness)
216 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
219 spin_lock_irqsave(&host->lock, flags);
221 if (brightness == LED_OFF)
222 sdhci_deactivate_led(host);
224 sdhci_activate_led(host);
226 spin_unlock_irqrestore(&host->lock, flags);
230 /*****************************************************************************\
234 \*****************************************************************************/
236 static void sdhci_read_block_pio(struct sdhci_host *host)
239 size_t blksize, len, chunk;
240 u32 uninitialized_var(scratch);
243 DBG("PIO reading\n");
245 blksize = host->data->blksz;
248 local_irq_save(flags);
251 if (!sg_miter_next(&host->sg_miter))
254 len = min(host->sg_miter.length, blksize);
257 host->sg_miter.consumed = len;
259 buf = host->sg_miter.addr;
263 scratch = sdhci_readl(host, SDHCI_BUFFER);
267 *buf = scratch & 0xFF;
276 sg_miter_stop(&host->sg_miter);
278 local_irq_restore(flags);
281 static void sdhci_write_block_pio(struct sdhci_host *host)
284 size_t blksize, len, chunk;
288 DBG("PIO writing\n");
290 blksize = host->data->blksz;
294 local_irq_save(flags);
297 if (!sg_miter_next(&host->sg_miter))
300 len = min(host->sg_miter.length, blksize);
303 host->sg_miter.consumed = len;
305 buf = host->sg_miter.addr;
308 scratch |= (u32)*buf << (chunk * 8);
314 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
315 sdhci_writel(host, scratch, SDHCI_BUFFER);
322 sg_miter_stop(&host->sg_miter);
324 local_irq_restore(flags);
327 static void sdhci_transfer_pio(struct sdhci_host *host)
333 if (host->blocks == 0)
336 if (host->data->flags & MMC_DATA_READ)
337 mask = SDHCI_DATA_AVAILABLE;
339 mask = SDHCI_SPACE_AVAILABLE;
342 * Some controllers (JMicron JMB38x) mess up the buffer bits
343 * for transfers < 4 bytes. As long as it is just one block,
344 * we can ignore the bits.
346 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
347 (host->data->blocks == 1))
350 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
351 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
354 if (host->data->flags & MMC_DATA_READ)
355 sdhci_read_block_pio(host);
357 sdhci_write_block_pio(host);
360 if (host->blocks == 0)
364 DBG("PIO transfer complete.\n");
367 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
369 local_irq_save(*flags);
370 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
373 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
375 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
376 local_irq_restore(*flags);
379 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
381 __le32 *dataddr = (__le32 __force *)(desc + 4);
382 __le16 *cmdlen = (__le16 __force *)desc;
384 /* SDHCI specification says ADMA descriptors should be 4 byte
385 * aligned, so using 16 or 32bit operations should be safe. */
387 cmdlen[0] = cpu_to_le16(cmd);
388 cmdlen[1] = cpu_to_le16(len);
390 dataddr[0] = cpu_to_le32(addr);
393 static int sdhci_adma_table_pre(struct sdhci_host *host,
394 struct mmc_data *data)
401 dma_addr_t align_addr;
404 struct scatterlist *sg;
410 * The spec does not specify endianness of descriptor table.
411 * We currently guess that it is LE.
414 if (data->flags & MMC_DATA_READ)
415 direction = DMA_FROM_DEVICE;
417 direction = DMA_TO_DEVICE;
420 * The ADMA descriptor table is mapped further down as we
421 * need to fill it with data first.
424 host->align_addr = dma_map_single(mmc_dev(host->mmc),
425 host->align_buffer, 128 * 4, direction);
426 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
428 BUG_ON(host->align_addr & 0x3);
430 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
431 data->sg, data->sg_len, direction);
432 if (host->sg_count == 0)
435 desc = host->adma_desc;
436 align = host->align_buffer;
438 align_addr = host->align_addr;
440 for_each_sg(data->sg, sg, host->sg_count, i) {
441 addr = sg_dma_address(sg);
442 len = sg_dma_len(sg);
445 * The SDHCI specification states that ADMA
446 * addresses must be 32-bit aligned. If they
447 * aren't, then we use a bounce buffer for
448 * the (up to three) bytes that screw up the
451 offset = (4 - (addr & 0x3)) & 0x3;
453 if (data->flags & MMC_DATA_WRITE) {
454 buffer = sdhci_kmap_atomic(sg, &flags);
455 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
456 memcpy(align, buffer, offset);
457 sdhci_kunmap_atomic(buffer, &flags);
461 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
463 BUG_ON(offset > 65536);
477 sdhci_set_adma_desc(desc, addr, len, 0x21);
481 * If this triggers then we have a calculation bug
484 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
488 * Add a terminating entry.
491 /* nop, end, valid */
492 sdhci_set_adma_desc(desc, 0, 0, 0x3);
495 * Resync align buffer as we might have changed it.
497 if (data->flags & MMC_DATA_WRITE) {
498 dma_sync_single_for_device(mmc_dev(host->mmc),
499 host->align_addr, 128 * 4, direction);
502 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
503 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
504 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
506 BUG_ON(host->adma_addr & 0x3);
511 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
512 data->sg_len, direction);
514 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
520 static void sdhci_adma_table_post(struct sdhci_host *host,
521 struct mmc_data *data)
525 struct scatterlist *sg;
531 if (data->flags & MMC_DATA_READ)
532 direction = DMA_FROM_DEVICE;
534 direction = DMA_TO_DEVICE;
536 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
537 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
539 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
542 if (data->flags & MMC_DATA_READ) {
543 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
544 data->sg_len, direction);
546 align = host->align_buffer;
548 for_each_sg(data->sg, sg, host->sg_count, i) {
549 if (sg_dma_address(sg) & 0x3) {
550 size = 4 - (sg_dma_address(sg) & 0x3);
552 buffer = sdhci_kmap_atomic(sg, &flags);
553 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
554 memcpy(buffer, align, size);
555 sdhci_kunmap_atomic(buffer, &flags);
562 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
563 data->sg_len, direction);
566 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
569 unsigned target_timeout, current_timeout;
572 * If the host controller provides us with an incorrect timeout
573 * value, just skip the check and use 0xE. The hardware may take
574 * longer to time out, but that's much better than having a too-short
577 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
581 target_timeout = data->timeout_ns / 1000 +
582 data->timeout_clks / host->clock;
584 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
585 host->timeout_clk = host->clock / 1000;
588 * Figure out needed cycles.
589 * We do this in steps in order to fit inside a 32 bit int.
590 * The first step is the minimum timeout, which will have a
591 * minimum resolution of 6 bits:
592 * (1) 2^13*1000 > 2^22,
593 * (2) host->timeout_clk < 2^16
598 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
599 while (current_timeout < target_timeout) {
601 current_timeout <<= 1;
607 printk(KERN_WARNING "%s: Too large timeout requested!\n",
608 mmc_hostname(host->mmc));
615 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
617 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
618 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
620 if (host->flags & SDHCI_REQ_USE_DMA)
621 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
623 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
626 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
638 BUG_ON(data->blksz * data->blocks > 524288);
639 BUG_ON(data->blksz > host->mmc->max_blk_size);
640 BUG_ON(data->blocks > 65535);
643 host->data_early = 0;
645 count = sdhci_calc_timeout(host, data);
646 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
648 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
649 host->flags |= SDHCI_REQ_USE_DMA;
652 * FIXME: This doesn't account for merging when mapping the
655 if (host->flags & SDHCI_REQ_USE_DMA) {
657 struct scatterlist *sg;
660 if (host->flags & SDHCI_USE_ADMA) {
661 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
664 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
668 if (unlikely(broken)) {
669 for_each_sg(data->sg, sg, data->sg_len, i) {
670 if (sg->length & 0x3) {
671 DBG("Reverting to PIO because of "
672 "transfer size (%d)\n",
674 host->flags &= ~SDHCI_REQ_USE_DMA;
682 * The assumption here being that alignment is the same after
683 * translation to device address space.
685 if (host->flags & SDHCI_REQ_USE_DMA) {
687 struct scatterlist *sg;
690 if (host->flags & SDHCI_USE_ADMA) {
692 * As we use 3 byte chunks to work around
693 * alignment problems, we need to check this
696 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
699 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
703 if (unlikely(broken)) {
704 for_each_sg(data->sg, sg, data->sg_len, i) {
705 if (sg->offset & 0x3) {
706 DBG("Reverting to PIO because of "
708 host->flags &= ~SDHCI_REQ_USE_DMA;
715 if (host->flags & SDHCI_REQ_USE_DMA) {
716 if (host->flags & SDHCI_USE_ADMA) {
717 ret = sdhci_adma_table_pre(host, data);
720 * This only happens when someone fed
721 * us an invalid request.
724 host->flags &= ~SDHCI_REQ_USE_DMA;
726 sdhci_writel(host, host->adma_addr,
732 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
733 data->sg, data->sg_len,
734 (data->flags & MMC_DATA_READ) ?
739 * This only happens when someone fed
740 * us an invalid request.
743 host->flags &= ~SDHCI_REQ_USE_DMA;
745 WARN_ON(sg_cnt != 1);
746 sdhci_writel(host, sg_dma_address(data->sg),
753 * Always adjust the DMA selection as some controllers
754 * (e.g. JMicron) can't do PIO properly when the selection
757 if (host->version >= SDHCI_SPEC_200) {
758 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
759 ctrl &= ~SDHCI_CTRL_DMA_MASK;
760 if ((host->flags & SDHCI_REQ_USE_DMA) &&
761 (host->flags & SDHCI_USE_ADMA))
762 ctrl |= SDHCI_CTRL_ADMA32;
764 ctrl |= SDHCI_CTRL_SDMA;
765 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
768 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
771 flags = SG_MITER_ATOMIC;
772 if (host->data->flags & MMC_DATA_READ)
773 flags |= SG_MITER_TO_SG;
775 flags |= SG_MITER_FROM_SG;
776 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
777 host->blocks = data->blocks;
780 sdhci_set_transfer_irqs(host);
782 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
783 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
784 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
787 static void sdhci_set_transfer_mode(struct sdhci_host *host,
788 struct mmc_data *data)
795 WARN_ON(!host->data);
797 mode = SDHCI_TRNS_BLK_CNT_EN;
798 if (data->blocks > 1)
799 mode |= SDHCI_TRNS_MULTI;
800 if (data->flags & MMC_DATA_READ)
801 mode |= SDHCI_TRNS_READ;
802 if (host->flags & SDHCI_REQ_USE_DMA)
803 mode |= SDHCI_TRNS_DMA;
805 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
808 static void sdhci_finish_data(struct sdhci_host *host)
810 struct mmc_data *data;
817 if (host->flags & SDHCI_REQ_USE_DMA) {
818 if (host->flags & SDHCI_USE_ADMA)
819 sdhci_adma_table_post(host, data);
821 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
822 data->sg_len, (data->flags & MMC_DATA_READ) ?
823 DMA_FROM_DEVICE : DMA_TO_DEVICE);
828 * The specification states that the block count register must
829 * be updated, but it does not specify at what point in the
830 * data flow. That makes the register entirely useless to read
831 * back so we have to assume that nothing made it to the card
832 * in the event of an error.
835 data->bytes_xfered = 0;
837 data->bytes_xfered = data->blksz * data->blocks;
841 * The controller needs a reset of internal state machines
842 * upon error conditions.
845 sdhci_reset(host, SDHCI_RESET_CMD);
846 sdhci_reset(host, SDHCI_RESET_DATA);
849 sdhci_send_command(host, data->stop);
851 tasklet_schedule(&host->finish_tasklet);
854 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
858 unsigned long timeout;
865 mask = SDHCI_CMD_INHIBIT;
866 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
867 mask |= SDHCI_DATA_INHIBIT;
869 /* We shouldn't wait for data inihibit for stop commands, even
870 though they might use busy signaling */
871 if (host->mrq->data && (cmd == host->mrq->data->stop))
872 mask &= ~SDHCI_DATA_INHIBIT;
874 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
876 printk(KERN_ERR "%s: Controller never released "
877 "inhibit bit(s).\n", mmc_hostname(host->mmc));
878 sdhci_dumpregs(host);
880 tasklet_schedule(&host->finish_tasklet);
887 mod_timer(&host->timer, jiffies + 10 * HZ);
891 sdhci_prepare_data(host, cmd->data);
893 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
895 sdhci_set_transfer_mode(host, cmd->data);
897 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
898 printk(KERN_ERR "%s: Unsupported response type!\n",
899 mmc_hostname(host->mmc));
900 cmd->error = -EINVAL;
901 tasklet_schedule(&host->finish_tasklet);
905 if (!(cmd->flags & MMC_RSP_PRESENT))
906 flags = SDHCI_CMD_RESP_NONE;
907 else if (cmd->flags & MMC_RSP_136)
908 flags = SDHCI_CMD_RESP_LONG;
909 else if (cmd->flags & MMC_RSP_BUSY)
910 flags = SDHCI_CMD_RESP_SHORT_BUSY;
912 flags = SDHCI_CMD_RESP_SHORT;
914 if (cmd->flags & MMC_RSP_CRC)
915 flags |= SDHCI_CMD_CRC;
916 if (cmd->flags & MMC_RSP_OPCODE)
917 flags |= SDHCI_CMD_INDEX;
919 flags |= SDHCI_CMD_DATA;
921 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
924 static void sdhci_finish_command(struct sdhci_host *host)
928 BUG_ON(host->cmd == NULL);
930 if (host->cmd->flags & MMC_RSP_PRESENT) {
931 if (host->cmd->flags & MMC_RSP_136) {
932 /* CRC is stripped so we need to do some shifting. */
933 for (i = 0;i < 4;i++) {
934 host->cmd->resp[i] = sdhci_readl(host,
935 SDHCI_RESPONSE + (3-i)*4) << 8;
937 host->cmd->resp[i] |=
939 SDHCI_RESPONSE + (3-i)*4-1);
942 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
946 host->cmd->error = 0;
948 if (host->data && host->data_early)
949 sdhci_finish_data(host);
951 if (!host->cmd->data)
952 tasklet_schedule(&host->finish_tasklet);
957 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
961 unsigned long timeout;
963 if (clock == host->clock)
966 if (host->ops->set_clock) {
967 host->ops->set_clock(host, clock);
968 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
972 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
977 for (div = 1;div < 256;div *= 2) {
978 if ((host->max_clk / div) <= clock)
983 clk = div << SDHCI_DIVIDER_SHIFT;
984 clk |= SDHCI_CLOCK_INT_EN;
985 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
989 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
990 & SDHCI_CLOCK_INT_STABLE)) {
992 printk(KERN_ERR "%s: Internal clock never "
993 "stabilised.\n", mmc_hostname(host->mmc));
994 sdhci_dumpregs(host);
1001 clk |= SDHCI_CLOCK_CARD_EN;
1002 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1005 host->clock = clock;
1008 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1012 if (power == (unsigned short)-1)
1015 switch (1 << power) {
1016 case MMC_VDD_165_195:
1017 pwr = SDHCI_POWER_180;
1021 pwr = SDHCI_POWER_300;
1025 pwr = SDHCI_POWER_330;
1032 if (host->pwr == pwr)
1038 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1043 * Spec says that we should clear the power reg before setting
1044 * a new value. Some controllers don't seem to like this though.
1046 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1047 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1050 * At least the Marvell CaFe chip gets confused if we set the voltage
1051 * and set turn on power at the same time, so set the voltage first.
1053 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1054 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1056 pwr |= SDHCI_POWER_ON;
1058 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1061 * Some controllers need an extra 10ms delay of 10ms before they
1062 * can apply clock after applying power
1064 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1068 /*****************************************************************************\
1072 \*****************************************************************************/
1074 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1076 struct sdhci_host *host;
1078 unsigned long flags;
1080 host = mmc_priv(mmc);
1082 spin_lock_irqsave(&host->lock, flags);
1084 WARN_ON(host->mrq != NULL);
1086 #ifndef SDHCI_USE_LEDS_CLASS
1087 sdhci_activate_led(host);
1092 /* If polling, assume that the card is always present. */
1093 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1096 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1099 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1100 host->mrq->cmd->error = -ENOMEDIUM;
1101 tasklet_schedule(&host->finish_tasklet);
1103 sdhci_send_command(host, mrq->cmd);
1106 spin_unlock_irqrestore(&host->lock, flags);
1109 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1111 struct sdhci_host *host;
1112 unsigned long flags;
1115 host = mmc_priv(mmc);
1117 spin_lock_irqsave(&host->lock, flags);
1119 if (host->flags & SDHCI_DEVICE_DEAD)
1123 * Reset the chip on each power off.
1124 * Should clear out any weird states.
1126 if (ios->power_mode == MMC_POWER_OFF) {
1127 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1131 sdhci_set_clock(host, ios->clock);
1133 if (ios->power_mode == MMC_POWER_OFF)
1134 sdhci_set_power(host, -1);
1136 sdhci_set_power(host, ios->vdd);
1138 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1140 if (ios->bus_width == MMC_BUS_WIDTH_4)
1141 ctrl |= SDHCI_CTRL_4BITBUS;
1143 ctrl &= ~SDHCI_CTRL_4BITBUS;
1145 if (ios->timing == MMC_TIMING_SD_HS)
1146 ctrl |= SDHCI_CTRL_HISPD;
1148 ctrl &= ~SDHCI_CTRL_HISPD;
1150 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1153 * Some (ENE) controllers go apeshit on some ios operation,
1154 * signalling timeout and CRC errors even on CMD0. Resetting
1155 * it on each ios seems to solve the problem.
1157 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1158 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1162 spin_unlock_irqrestore(&host->lock, flags);
1165 static int sdhci_get_ro(struct mmc_host *mmc)
1167 struct sdhci_host *host;
1168 unsigned long flags;
1171 host = mmc_priv(mmc);
1173 spin_lock_irqsave(&host->lock, flags);
1175 if (host->flags & SDHCI_DEVICE_DEAD)
1178 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1180 spin_unlock_irqrestore(&host->lock, flags);
1182 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1183 return !!(present & SDHCI_WRITE_PROTECT);
1184 return !(present & SDHCI_WRITE_PROTECT);
1187 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1189 struct sdhci_host *host;
1190 unsigned long flags;
1192 host = mmc_priv(mmc);
1194 spin_lock_irqsave(&host->lock, flags);
1196 if (host->flags & SDHCI_DEVICE_DEAD)
1200 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1202 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1206 spin_unlock_irqrestore(&host->lock, flags);
1209 static const struct mmc_host_ops sdhci_ops = {
1210 .request = sdhci_request,
1211 .set_ios = sdhci_set_ios,
1212 .get_ro = sdhci_get_ro,
1213 .enable_sdio_irq = sdhci_enable_sdio_irq,
1216 /*****************************************************************************\
1220 \*****************************************************************************/
1222 static void sdhci_tasklet_card(unsigned long param)
1224 struct sdhci_host *host;
1225 unsigned long flags;
1227 host = (struct sdhci_host*)param;
1229 spin_lock_irqsave(&host->lock, flags);
1231 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1233 printk(KERN_ERR "%s: Card removed during transfer!\n",
1234 mmc_hostname(host->mmc));
1235 printk(KERN_ERR "%s: Resetting controller.\n",
1236 mmc_hostname(host->mmc));
1238 sdhci_reset(host, SDHCI_RESET_CMD);
1239 sdhci_reset(host, SDHCI_RESET_DATA);
1241 host->mrq->cmd->error = -ENOMEDIUM;
1242 tasklet_schedule(&host->finish_tasklet);
1246 spin_unlock_irqrestore(&host->lock, flags);
1248 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1251 static void sdhci_tasklet_finish(unsigned long param)
1253 struct sdhci_host *host;
1254 unsigned long flags;
1255 struct mmc_request *mrq;
1257 host = (struct sdhci_host*)param;
1259 spin_lock_irqsave(&host->lock, flags);
1261 del_timer(&host->timer);
1266 * The controller needs a reset of internal state machines
1267 * upon error conditions.
1269 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1271 (mrq->data && (mrq->data->error ||
1272 (mrq->data->stop && mrq->data->stop->error))) ||
1273 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1275 /* Some controllers need this kick or reset won't work here */
1276 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1279 /* This is to force an update */
1280 clock = host->clock;
1282 sdhci_set_clock(host, clock);
1285 /* Spec says we should do both at the same time, but Ricoh
1286 controllers do not like that. */
1287 sdhci_reset(host, SDHCI_RESET_CMD);
1288 sdhci_reset(host, SDHCI_RESET_DATA);
1295 #ifndef SDHCI_USE_LEDS_CLASS
1296 sdhci_deactivate_led(host);
1300 spin_unlock_irqrestore(&host->lock, flags);
1302 mmc_request_done(host->mmc, mrq);
1305 static void sdhci_timeout_timer(unsigned long data)
1307 struct sdhci_host *host;
1308 unsigned long flags;
1310 host = (struct sdhci_host*)data;
1312 spin_lock_irqsave(&host->lock, flags);
1315 printk(KERN_ERR "%s: Timeout waiting for hardware "
1316 "interrupt.\n", mmc_hostname(host->mmc));
1317 sdhci_dumpregs(host);
1320 host->data->error = -ETIMEDOUT;
1321 sdhci_finish_data(host);
1324 host->cmd->error = -ETIMEDOUT;
1326 host->mrq->cmd->error = -ETIMEDOUT;
1328 tasklet_schedule(&host->finish_tasklet);
1333 spin_unlock_irqrestore(&host->lock, flags);
1336 /*****************************************************************************\
1338 * Interrupt handling *
1340 \*****************************************************************************/
1342 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1344 BUG_ON(intmask == 0);
1347 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1348 "though no command operation was in progress.\n",
1349 mmc_hostname(host->mmc), (unsigned)intmask);
1350 sdhci_dumpregs(host);
1354 if (intmask & SDHCI_INT_TIMEOUT)
1355 host->cmd->error = -ETIMEDOUT;
1356 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1358 host->cmd->error = -EILSEQ;
1360 if (host->cmd->error) {
1361 tasklet_schedule(&host->finish_tasklet);
1366 * The host can send and interrupt when the busy state has
1367 * ended, allowing us to wait without wasting CPU cycles.
1368 * Unfortunately this is overloaded on the "data complete"
1369 * interrupt, so we need to take some care when handling
1372 * Note: The 1.0 specification is a bit ambiguous about this
1373 * feature so there might be some problems with older
1376 if (host->cmd->flags & MMC_RSP_BUSY) {
1377 if (host->cmd->data)
1378 DBG("Cannot wait for busy signal when also "
1379 "doing a data transfer");
1380 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1383 /* The controller does not support the end-of-busy IRQ,
1384 * fall through and take the SDHCI_INT_RESPONSE */
1387 if (intmask & SDHCI_INT_RESPONSE)
1388 sdhci_finish_command(host);
1392 static void sdhci_show_adma_error(struct sdhci_host *host)
1394 const char *name = mmc_hostname(host->mmc);
1395 u8 *desc = host->adma_desc;
1400 sdhci_dumpregs(host);
1403 dma = (__le32 *)(desc + 4);
1404 len = (__le16 *)(desc + 2);
1407 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1408 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1417 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1420 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1422 BUG_ON(intmask == 0);
1426 * The "data complete" interrupt is also used to
1427 * indicate that a busy state has ended. See comment
1428 * above in sdhci_cmd_irq().
1430 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1431 if (intmask & SDHCI_INT_DATA_END) {
1432 sdhci_finish_command(host);
1437 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1438 "though no data operation was in progress.\n",
1439 mmc_hostname(host->mmc), (unsigned)intmask);
1440 sdhci_dumpregs(host);
1445 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1446 host->data->error = -ETIMEDOUT;
1447 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1448 host->data->error = -EILSEQ;
1449 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1450 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1451 sdhci_show_adma_error(host);
1452 host->data->error = -EIO;
1455 if (host->data->error)
1456 sdhci_finish_data(host);
1458 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1459 sdhci_transfer_pio(host);
1462 * We currently don't do anything fancy with DMA
1463 * boundaries, but as we can't disable the feature
1464 * we need to at least restart the transfer.
1466 if (intmask & SDHCI_INT_DMA_END)
1467 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1470 if (intmask & SDHCI_INT_DATA_END) {
1473 * Data managed to finish before the
1474 * command completed. Make sure we do
1475 * things in the proper order.
1477 host->data_early = 1;
1479 sdhci_finish_data(host);
1485 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1488 struct sdhci_host* host = dev_id;
1492 spin_lock(&host->lock);
1494 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1496 if (!intmask || intmask == 0xffffffff) {
1501 DBG("*** %s got interrupt: 0x%08x\n",
1502 mmc_hostname(host->mmc), intmask);
1504 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1505 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1506 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1507 tasklet_schedule(&host->card_tasklet);
1510 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1512 if (intmask & SDHCI_INT_CMD_MASK) {
1513 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1515 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1518 if (intmask & SDHCI_INT_DATA_MASK) {
1519 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1521 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1524 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1526 intmask &= ~SDHCI_INT_ERROR;
1528 if (intmask & SDHCI_INT_BUS_POWER) {
1529 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1530 mmc_hostname(host->mmc));
1531 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1534 intmask &= ~SDHCI_INT_BUS_POWER;
1536 if (intmask & SDHCI_INT_CARD_INT)
1539 intmask &= ~SDHCI_INT_CARD_INT;
1542 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1543 mmc_hostname(host->mmc), intmask);
1544 sdhci_dumpregs(host);
1546 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1549 result = IRQ_HANDLED;
1553 spin_unlock(&host->lock);
1556 * We have to delay this as it calls back into the driver.
1559 mmc_signal_sdio_irq(host->mmc);
1564 /*****************************************************************************\
1568 \*****************************************************************************/
1572 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1576 sdhci_disable_card_detection(host);
1578 ret = mmc_suspend_host(host->mmc, state);
1582 free_irq(host->irq, host);
1587 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1589 int sdhci_resume_host(struct sdhci_host *host)
1593 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1594 if (host->ops->enable_dma)
1595 host->ops->enable_dma(host);
1598 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1599 mmc_hostname(host->mmc), host);
1606 ret = mmc_resume_host(host->mmc);
1610 sdhci_enable_card_detection(host);
1615 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1617 #endif /* CONFIG_PM */
1619 /*****************************************************************************\
1621 * Device allocation/registration *
1623 \*****************************************************************************/
1625 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1628 struct mmc_host *mmc;
1629 struct sdhci_host *host;
1631 WARN_ON(dev == NULL);
1633 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1635 return ERR_PTR(-ENOMEM);
1637 host = mmc_priv(mmc);
1643 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1645 int sdhci_add_host(struct sdhci_host *host)
1647 struct mmc_host *mmc;
1651 WARN_ON(host == NULL);
1658 host->quirks = debug_quirks;
1660 sdhci_reset(host, SDHCI_RESET_ALL);
1662 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1663 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1664 >> SDHCI_SPEC_VER_SHIFT;
1665 if (host->version > SDHCI_SPEC_200) {
1666 printk(KERN_ERR "%s: Unknown controller version (%d). "
1667 "You may experience problems.\n", mmc_hostname(mmc),
1671 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1673 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1674 host->flags |= SDHCI_USE_SDMA;
1675 else if (!(caps & SDHCI_CAN_DO_SDMA))
1676 DBG("Controller doesn't have SDMA capability\n");
1678 host->flags |= SDHCI_USE_SDMA;
1680 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1681 (host->flags & SDHCI_USE_SDMA)) {
1682 DBG("Disabling DMA as it is marked broken\n");
1683 host->flags &= ~SDHCI_USE_SDMA;
1686 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1687 host->flags |= SDHCI_USE_ADMA;
1689 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1690 (host->flags & SDHCI_USE_ADMA)) {
1691 DBG("Disabling ADMA as it is marked broken\n");
1692 host->flags &= ~SDHCI_USE_ADMA;
1695 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1696 if (host->ops->enable_dma) {
1697 if (host->ops->enable_dma(host)) {
1698 printk(KERN_WARNING "%s: No suitable DMA "
1699 "available. Falling back to PIO.\n",
1702 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1707 if (host->flags & SDHCI_USE_ADMA) {
1709 * We need to allocate descriptors for all sg entries
1710 * (128) and potentially one alignment transfer for
1711 * each of those entries.
1713 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1714 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1715 if (!host->adma_desc || !host->align_buffer) {
1716 kfree(host->adma_desc);
1717 kfree(host->align_buffer);
1718 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1719 "buffers. Falling back to standard DMA.\n",
1721 host->flags &= ~SDHCI_USE_ADMA;
1726 * If we use DMA, then it's up to the caller to set the DMA
1727 * mask, but PIO does not need the hw shim so we set a new
1728 * mask here in that case.
1730 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1731 host->dma_mask = DMA_BIT_MASK(64);
1732 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1736 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1737 host->max_clk *= 1000000;
1738 if (host->max_clk == 0) {
1739 if (!host->ops->get_max_clock) {
1741 "%s: Hardware doesn't specify base clock "
1742 "frequency.\n", mmc_hostname(mmc));
1745 host->max_clk = host->ops->get_max_clock(host);
1749 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1750 if (host->timeout_clk == 0) {
1751 if (host->ops->get_timeout_clock) {
1752 host->timeout_clk = host->ops->get_timeout_clock(host);
1753 } else if (!(host->quirks &
1754 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1756 "%s: Hardware doesn't specify timeout clock "
1757 "frequency.\n", mmc_hostname(mmc));
1761 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1762 host->timeout_clk *= 1000;
1765 * Set host parameters.
1767 mmc->ops = &sdhci_ops;
1768 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
1769 host->ops->set_clock && host->ops->get_min_clock)
1770 mmc->f_min = host->ops->get_min_clock(host);
1772 mmc->f_min = host->max_clk / 256;
1773 mmc->f_max = host->max_clk;
1774 mmc->caps = MMC_CAP_SDIO_IRQ;
1776 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1777 mmc->caps |= MMC_CAP_4_BIT_DATA;
1779 if (caps & SDHCI_CAN_DO_HISPD)
1780 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1782 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1783 mmc->caps |= MMC_CAP_NEEDS_POLL;
1786 if (caps & SDHCI_CAN_VDD_330)
1787 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1788 if (caps & SDHCI_CAN_VDD_300)
1789 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1790 if (caps & SDHCI_CAN_VDD_180)
1791 mmc->ocr_avail |= MMC_VDD_165_195;
1793 if (mmc->ocr_avail == 0) {
1794 printk(KERN_ERR "%s: Hardware doesn't report any "
1795 "support voltages.\n", mmc_hostname(mmc));
1799 spin_lock_init(&host->lock);
1802 * Maximum number of segments. Depends on if the hardware
1803 * can do scatter/gather or not.
1805 if (host->flags & SDHCI_USE_ADMA)
1806 mmc->max_hw_segs = 128;
1807 else if (host->flags & SDHCI_USE_SDMA)
1808 mmc->max_hw_segs = 1;
1810 mmc->max_hw_segs = 128;
1811 mmc->max_phys_segs = 128;
1814 * Maximum number of sectors in one transfer. Limited by DMA boundary
1817 mmc->max_req_size = 524288;
1820 * Maximum segment size. Could be one segment with the maximum number
1821 * of bytes. When doing hardware scatter/gather, each entry cannot
1822 * be larger than 64 KiB though.
1824 if (host->flags & SDHCI_USE_ADMA)
1825 mmc->max_seg_size = 65536;
1827 mmc->max_seg_size = mmc->max_req_size;
1830 * Maximum block size. This varies from controller to controller and
1831 * is specified in the capabilities register.
1833 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1834 mmc->max_blk_size = 2;
1836 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1837 SDHCI_MAX_BLOCK_SHIFT;
1838 if (mmc->max_blk_size >= 3) {
1839 printk(KERN_WARNING "%s: Invalid maximum block size, "
1840 "assuming 512 bytes\n", mmc_hostname(mmc));
1841 mmc->max_blk_size = 0;
1845 mmc->max_blk_size = 512 << mmc->max_blk_size;
1848 * Maximum block count.
1850 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1855 tasklet_init(&host->card_tasklet,
1856 sdhci_tasklet_card, (unsigned long)host);
1857 tasklet_init(&host->finish_tasklet,
1858 sdhci_tasklet_finish, (unsigned long)host);
1860 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1862 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1863 mmc_hostname(mmc), host);
1869 #ifdef CONFIG_MMC_DEBUG
1870 sdhci_dumpregs(host);
1873 #ifdef SDHCI_USE_LEDS_CLASS
1874 snprintf(host->led_name, sizeof(host->led_name),
1875 "%s::", mmc_hostname(mmc));
1876 host->led.name = host->led_name;
1877 host->led.brightness = LED_OFF;
1878 host->led.default_trigger = mmc_hostname(mmc);
1879 host->led.brightness_set = sdhci_led_control;
1881 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1890 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1891 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1892 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1893 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1895 sdhci_enable_card_detection(host);
1899 #ifdef SDHCI_USE_LEDS_CLASS
1901 sdhci_reset(host, SDHCI_RESET_ALL);
1902 free_irq(host->irq, host);
1905 tasklet_kill(&host->card_tasklet);
1906 tasklet_kill(&host->finish_tasklet);
1911 EXPORT_SYMBOL_GPL(sdhci_add_host);
1913 void sdhci_remove_host(struct sdhci_host *host, int dead)
1915 unsigned long flags;
1918 spin_lock_irqsave(&host->lock, flags);
1920 host->flags |= SDHCI_DEVICE_DEAD;
1923 printk(KERN_ERR "%s: Controller removed during "
1924 " transfer!\n", mmc_hostname(host->mmc));
1926 host->mrq->cmd->error = -ENOMEDIUM;
1927 tasklet_schedule(&host->finish_tasklet);
1930 spin_unlock_irqrestore(&host->lock, flags);
1933 sdhci_disable_card_detection(host);
1935 mmc_remove_host(host->mmc);
1937 #ifdef SDHCI_USE_LEDS_CLASS
1938 led_classdev_unregister(&host->led);
1942 sdhci_reset(host, SDHCI_RESET_ALL);
1944 free_irq(host->irq, host);
1946 del_timer_sync(&host->timer);
1948 tasklet_kill(&host->card_tasklet);
1949 tasklet_kill(&host->finish_tasklet);
1951 kfree(host->adma_desc);
1952 kfree(host->align_buffer);
1954 host->adma_desc = NULL;
1955 host->align_buffer = NULL;
1958 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1960 void sdhci_free_host(struct sdhci_host *host)
1962 mmc_free_host(host->mmc);
1965 EXPORT_SYMBOL_GPL(sdhci_free_host);
1967 /*****************************************************************************\
1969 * Driver init/exit *
1971 \*****************************************************************************/
1973 static int __init sdhci_drv_init(void)
1975 printk(KERN_INFO DRIVER_NAME
1976 ": Secure Digital Host Controller Interface driver\n");
1977 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1982 static void __exit sdhci_drv_exit(void)
1986 module_init(sdhci_drv_init);
1987 module_exit(sdhci_drv_exit);
1989 module_param(debug_quirks, uint, 0444);
1991 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1992 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1993 MODULE_LICENSE("GPL");
1995 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");