drivers/mmc/host/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   4  *
   5  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   6  *
   7  * Thanks to the following companies for their support:
   8  *
   9  *     - JMicron (hardware and technical support)
  10  */
  11
  12 #include <linux/bitfield.h>
  13 #include <linux/delay.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/ktime.h>
  16 #include <linux/highmem.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/sizes.h>
  23 #include <linux/swiotlb.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/of.h>
  27
  28 #include <linux/leds.h>
  29
  30 #include <linux/mmc/mmc.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mmc/sdio.h>
  34 #include <linux/mmc/slot-gpio.h>
  35
  36 #include "sdhci.h"
  37
  38 #define DRIVER_NAME "sdhci"
  39
  40 #define DBG(f, x...) \
  41         pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  42
  43 #define SDHCI_DUMP(f, x...) \
  44         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  52
  53 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
  54
  55 void sdhci_dumpregs(struct sdhci_host *host)
  56 {
  57         SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
  58
  59         SDHCI_DUMP("Sys addr:  0x%08x | Version:  0x%08x\n",
  60                    sdhci_readl(host, SDHCI_DMA_ADDRESS),
  61                    sdhci_readw(host, SDHCI_HOST_VERSION));
  62         SDHCI_DUMP("Blk size:  0x%08x | Blk cnt:  0x%08x\n",
  63                    sdhci_readw(host, SDHCI_BLOCK_SIZE),
  64                    sdhci_readw(host, SDHCI_BLOCK_COUNT));
  65         SDHCI_DUMP("Argument:  0x%08x | Trn mode: 0x%08x\n",
  66                    sdhci_readl(host, SDHCI_ARGUMENT),
  67                    sdhci_readw(host, SDHCI_TRANSFER_MODE));
  68         SDHCI_DUMP("Present:   0x%08x | Host ctl: 0x%08x\n",
  69                    sdhci_readl(host, SDHCI_PRESENT_STATE),
  70                    sdhci_readb(host, SDHCI_HOST_CONTROL));
  71         SDHCI_DUMP("Power:     0x%08x | Blk gap:  0x%08x\n",
  72                    sdhci_readb(host, SDHCI_POWER_CONTROL),
  73                    sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  74         SDHCI_DUMP("Wake-up:   0x%08x | Clock:    0x%08x\n",
  75                    sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  76                    sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  77         SDHCI_DUMP("Timeout:   0x%08x | Int stat: 0x%08x\n",
  78                    sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  79                    sdhci_readl(host, SDHCI_INT_STATUS));
  80         SDHCI_DUMP("Int enab:  0x%08x | Sig enab: 0x%08x\n",
  81                    sdhci_readl(host, SDHCI_INT_ENABLE),
  82                    sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  83         SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
  84                    sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
  85                    sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  86         SDHCI_DUMP("Caps:      0x%08x | Caps_1:   0x%08x\n",
  87                    sdhci_readl(host, SDHCI_CAPABILITIES),
  88                    sdhci_readl(host, SDHCI_CAPABILITIES_1));
  89         SDHCI_DUMP("Cmd:       0x%08x | Max curr: 0x%08x\n",
  90                    sdhci_readw(host, SDHCI_COMMAND),
  91                    sdhci_readl(host, SDHCI_MAX_CURRENT));
  92         SDHCI_DUMP("Resp[0]:   0x%08x | Resp[1]:  0x%08x\n",
  93                    sdhci_readl(host, SDHCI_RESPONSE),
  94                    sdhci_readl(host, SDHCI_RESPONSE + 4));
  95         SDHCI_DUMP("Resp[2]:   0x%08x | Resp[3]:  0x%08x\n",
  96                    sdhci_readl(host, SDHCI_RESPONSE + 8),
  97                    sdhci_readl(host, SDHCI_RESPONSE + 12));
  98         SDHCI_DUMP("Host ctl2: 0x%08x\n",
  99                    sdhci_readw(host, SDHCI_HOST_CONTROL2));
 100
 101         if (host->flags & SDHCI_USE_ADMA) {
 102                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
 103                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x%08x\n",
 104                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 105                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
 106                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 107                 } else {
 108                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x\n",
 109                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 110                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 111                 }
 112         }
 113
 114         if (host->ops->dump_vendor_regs)
 115                 host->ops->dump_vendor_regs(host);
 116
 117         SDHCI_DUMP("============================================\n");
 118 }
 119 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
 120
 121 /*****************************************************************************\
 122  *                                                                           *
 123  * Low level functions                                                       *
 124  *                                                                           *
 125 \*****************************************************************************/
 126
 127 static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
 128 {
 129         u16 ctrl2;
 130
 131         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 132         if (ctrl2 & SDHCI_CTRL_V4_MODE)
 133                 return;
 134
 135         ctrl2 |= SDHCI_CTRL_V4_MODE;
 136         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 137 }
 138
 139 /*
 140  * This can be called before sdhci_add_host() by Vendor's host controller
 141  * driver to enable v4 mode if supported.
 142  */
 143 void sdhci_enable_v4_mode(struct sdhci_host *host)
 144 {
 145         host->v4_mode = true;
 146         sdhci_do_enable_v4_mode(host);
 147 }
 148 EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
 149
 150 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
 151 {
 152         return cmd->data || cmd->flags & MMC_RSP_BUSY;
 153 }
 154
 155 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 156 {
 157         u32 present;
 158
 159         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 160             !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
 161                 return;
 162
 163         if (enable) {
 164                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 165                                       SDHCI_CARD_PRESENT;
 166
 167                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 168                                        SDHCI_INT_CARD_INSERT;
 169         } else {
 170                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 171         }
 172
 173         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 174         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 175 }
 176
 177 static void sdhci_enable_card_detection(struct sdhci_host *host)
 178 {
 179         sdhci_set_card_detection(host, true);
 180 }
 181
 182 static void sdhci_disable_card_detection(struct sdhci_host *host)
 183 {
 184         sdhci_set_card_detection(host, false);
 185 }
 186
 187 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
 188 {
 189         if (host->bus_on)
 190                 return;
 191         host->bus_on = true;
 192         pm_runtime_get_noresume(host->mmc->parent);
 193 }
 194
 195 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
 196 {
 197         if (!host->bus_on)
 198                 return;
 199         host->bus_on = false;
 200         pm_runtime_put_noidle(host->mmc->parent);
 201 }
 202
 203 void sdhci_reset(struct sdhci_host *host, u8 mask)
 204 {
 205         ktime_t timeout;
 206
 207         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 208
 209         if (mask & SDHCI_RESET_ALL) {
 210                 host->clock = 0;
 211                 /* Reset-all turns off SD Bus Power */
 212                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 213                         sdhci_runtime_pm_bus_off(host);
 214         }
 215
 216         /* Wait max 100 ms */
 217         timeout = ktime_add_ms(ktime_get(), 100);
 218
 219         /* hw clears the bit when it's done */
 220         while (1) {
 221                 bool timedout = ktime_after(ktime_get(), timeout);
 222
 223                 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
 224                         break;
 225                 if (timedout) {
 226                         pr_err("%s: Reset 0x%x never completed.\n",
 227                                 mmc_hostname(host->mmc), (int)mask);
 228                         sdhci_dumpregs(host);
 229                         return;
 230                 }
 231                 udelay(10);
 232         }
 233 }
 234 EXPORT_SYMBOL_GPL(sdhci_reset);
 235
 236 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 237 {
 238         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 239                 struct mmc_host *mmc = host->mmc;
 240
 241                 if (!mmc->ops->get_cd(mmc))
 242                         return;
 243         }
 244
 245         host->ops->reset(host, mask);
 246
 247         if (mask & SDHCI_RESET_ALL) {
 248                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 249                         if (host->ops->enable_dma)
 250                                 host->ops->enable_dma(host);
 251                 }
 252
 253                 /* Resetting the controller clears many */
 254                 host->preset_enabled = false;
 255         }
 256 }
 257
 258 static void sdhci_set_default_irqs(struct sdhci_host *host)
 259 {
 260         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 261                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 262                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 263                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 264                     SDHCI_INT_RESPONSE;
 265
 266         if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
 267             host->tuning_mode == SDHCI_TUNING_MODE_3)
 268                 host->ier |= SDHCI_INT_RETUNE;
 269
 270         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 271         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 272 }
 273
 274 static void sdhci_config_dma(struct sdhci_host *host)
 275 {
 276         u8 ctrl;
 277         u16 ctrl2;
 278
 279         if (host->version < SDHCI_SPEC_200)
 280                 return;
 281
 282         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 283
 284         /*
 285          * Always adjust the DMA selection as some controllers
 286          * (e.g. JMicron) can't do PIO properly when the selection
 287          * is ADMA.
 288          */
 289         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 290         if (!(host->flags & SDHCI_REQ_USE_DMA))
 291                 goto out;
 292
 293         /* Note if DMA Select is zero then SDMA is selected */
 294         if (host->flags & SDHCI_USE_ADMA)
 295                 ctrl |= SDHCI_CTRL_ADMA32;
 296
 297         if (host->flags & SDHCI_USE_64_BIT_DMA) {
 298                 /*
 299                  * If v4 mode, all supported DMA can be 64-bit addressing if
 300                  * controller supports 64-bit system address, otherwise only
 301                  * ADMA can support 64-bit addressing.
 302                  */
 303                 if (host->v4_mode) {
 304                         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 305                         ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
 306                         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 307                 } else if (host->flags & SDHCI_USE_ADMA) {
 308                         /*
 309                          * Don't need to undo SDHCI_CTRL_ADMA32 in order to
 310                          * set SDHCI_CTRL_ADMA64.
 311                          */
 312                         ctrl |= SDHCI_CTRL_ADMA64;
 313                 }
 314         }
 315
 316 out:
 317         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 318 }
 319
 320 static void sdhci_init(struct sdhci_host *host, int soft)
 321 {
 322         struct mmc_host *mmc = host->mmc;
 323         unsigned long flags;
 324
 325         if (soft)
 326                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 327         else
 328                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 329
 330         if (host->v4_mode)
 331                 sdhci_do_enable_v4_mode(host);
 332
 333         spin_lock_irqsave(&host->lock, flags);
 334         sdhci_set_default_irqs(host);
 335         spin_unlock_irqrestore(&host->lock, flags);
 336
 337         host->cqe_on = false;
 338
 339         if (soft) {
 340                 /* force clock reconfiguration */
 341                 host->clock = 0;
 342                 mmc->ops->set_ios(mmc, &mmc->ios);
 343         }
 344 }
 345
 346 static void sdhci_reinit(struct sdhci_host *host)
 347 {
 348         u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 349
 350         sdhci_init(host, 0);
 351         sdhci_enable_card_detection(host);
 352
 353         /*
 354          * A change to the card detect bits indicates a change in present state,
 355          * refer sdhci_set_card_detection(). A card detect interrupt might have
 356          * been missed while the host controller was being reset, so trigger a
 357          * rescan to check.
 358          */
 359         if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
 360                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
 361 }
 362
 363 static void __sdhci_led_activate(struct sdhci_host *host)
 364 {
 365         u8 ctrl;
 366
 367         if (host->quirks & SDHCI_QUIRK_NO_LED)
 368                 return;
 369
 370         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 371         ctrl |= SDHCI_CTRL_LED;
 372         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 373 }
 374
 375 static void __sdhci_led_deactivate(struct sdhci_host *host)
 376 {
 377         u8 ctrl;
 378
 379         if (host->quirks & SDHCI_QUIRK_NO_LED)
 380                 return;
 381
 382         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 383         ctrl &= ~SDHCI_CTRL_LED;
 384         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 385 }
 386
 387 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
 388 static void sdhci_led_control(struct led_classdev *led,
 389                               enum led_brightness brightness)
 390 {
 391         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 392         unsigned long flags;
 393
 394         spin_lock_irqsave(&host->lock, flags);
 395
 396         if (host->runtime_suspended)
 397                 goto out;
 398
 399         if (brightness == LED_OFF)
 400                 __sdhci_led_deactivate(host);
 401         else
 402                 __sdhci_led_activate(host);
 403 out:
 404         spin_unlock_irqrestore(&host->lock, flags);
 405 }
 406
 407 static int sdhci_led_register(struct sdhci_host *host)
 408 {
 409         struct mmc_host *mmc = host->mmc;
 410
 411         if (host->quirks & SDHCI_QUIRK_NO_LED)
 412                 return 0;
 413
 414         snprintf(host->led_name, sizeof(host->led_name),
 415                  "%s::", mmc_hostname(mmc));
 416
 417         host->led.name = host->led_name;
 418         host->led.brightness = LED_OFF;
 419         host->led.default_trigger = mmc_hostname(mmc);
 420         host->led.brightness_set = sdhci_led_control;
 421
 422         return led_classdev_register(mmc_dev(mmc), &host->led);
 423 }
 424
 425 static void sdhci_led_unregister(struct sdhci_host *host)
 426 {
 427         if (host->quirks & SDHCI_QUIRK_NO_LED)
 428                 return;
 429
 430         led_classdev_unregister(&host->led);
 431 }
 432
 433 static inline void sdhci_led_activate(struct sdhci_host *host)
 434 {
 435 }
 436
 437 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 438 {
 439 }
 440
 441 #else
 442
 443 static inline int sdhci_led_register(struct sdhci_host *host)
 444 {
 445         return 0;
 446 }
 447
 448 static inline void sdhci_led_unregister(struct sdhci_host *host)
 449 {
 450 }
 451
 452 static inline void sdhci_led_activate(struct sdhci_host *host)
 453 {
 454         __sdhci_led_activate(host);
 455 }
 456
 457 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 458 {
 459         __sdhci_led_deactivate(host);
 460 }
 461
 462 #endif
 463
 464 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
 465                             unsigned long timeout)
 466 {
 467         if (sdhci_data_line_cmd(mrq->cmd))
 468                 mod_timer(&host->data_timer, timeout);
 469         else
 470                 mod_timer(&host->timer, timeout);
 471 }
 472
 473 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
 474 {
 475         if (sdhci_data_line_cmd(mrq->cmd))
 476                 del_timer(&host->data_timer);
 477         else
 478                 del_timer(&host->timer);
 479 }
 480
 481 static inline bool sdhci_has_requests(struct sdhci_host *host)
 482 {
 483         return host->cmd || host->data_cmd;
 484 }
 485
 486 /*****************************************************************************\
 487  *                                                                           *
 488  * Core functions                                                            *
 489  *                                                                           *
 490 \*****************************************************************************/
 491
 492 static void sdhci_read_block_pio(struct sdhci_host *host)
 493 {
 494         unsigned long flags;
 495         size_t blksize, len, chunk;
 496         u32 scratch;
 497         u8 *buf;
 498
 499         DBG("PIO reading\n");
 500
 501         blksize = host->data->blksz;
 502         chunk = 0;
 503
 504         local_irq_save(flags);
 505
 506         while (blksize) {
 507                 BUG_ON(!sg_miter_next(&host->sg_miter));
 508
 509                 len = min(host->sg_miter.length, blksize);
 510
 511                 blksize -= len;
 512                 host->sg_miter.consumed = len;
 513
 514                 buf = host->sg_miter.addr;
 515
 516                 while (len) {
 517                         if (chunk == 0) {
 518                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 519                                 chunk = 4;
 520                         }
 521
 522                         *buf = scratch & 0xFF;
 523
 524                         buf++;
 525                         scratch >>= 8;
 526                         chunk--;
 527                         len--;
 528                 }
 529         }
 530
 531         sg_miter_stop(&host->sg_miter);
 532
 533         local_irq_restore(flags);
 534 }
 535
 536 static void sdhci_write_block_pio(struct sdhci_host *host)
 537 {
 538         unsigned long flags;
 539         size_t blksize, len, chunk;
 540         u32 scratch;
 541         u8 *buf;
 542
 543         DBG("PIO writing\n");
 544
 545         blksize = host->data->blksz;
 546         chunk = 0;
 547         scratch = 0;
 548
 549         local_irq_save(flags);
 550
 551         while (blksize) {
 552                 BUG_ON(!sg_miter_next(&host->sg_miter));
 553
 554                 len = min(host->sg_miter.length, blksize);
 555
 556                 blksize -= len;
 557                 host->sg_miter.consumed = len;
 558
 559                 buf = host->sg_miter.addr;
 560
 561                 while (len) {
 562                         scratch |= (u32)*buf << (chunk * 8);
 563
 564                         buf++;
 565                         chunk++;
 566                         len--;
 567
 568                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 569                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 570                                 chunk = 0;
 571                                 scratch = 0;
 572                         }
 573                 }
 574         }
 575
 576         sg_miter_stop(&host->sg_miter);
 577
 578         local_irq_restore(flags);
 579 }
 580
 581 static void sdhci_transfer_pio(struct sdhci_host *host)
 582 {
 583         u32 mask;
 584
 585         if (host->blocks == 0)
 586                 return;
 587
 588         if (host->data->flags & MMC_DATA_READ)
 589                 mask = SDHCI_DATA_AVAILABLE;
 590         else
 591                 mask = SDHCI_SPACE_AVAILABLE;
 592
 593         /*
 594          * Some controllers (JMicron JMB38x) mess up the buffer bits
 595          * for transfers < 4 bytes. As long as it is just one block,
 596          * we can ignore the bits.
 597          */
 598         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 599                 (host->data->blocks == 1))
 600                 mask = ~0;
 601
 602         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 603                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 604                         udelay(100);
 605
 606                 if (host->data->flags & MMC_DATA_READ)
 607                         sdhci_read_block_pio(host);
 608                 else
 609                         sdhci_write_block_pio(host);
 610
 611                 host->blocks--;
 612                 if (host->blocks == 0)
 613                         break;
 614         }
 615
 616         DBG("PIO transfer complete.\n");
 617 }
 618
 619 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
 620                                   struct mmc_data *data, int cookie)
 621 {
 622         int sg_count;
 623
 624         /*
 625          * If the data buffers are already mapped, return the previous
 626          * dma_map_sg() result.
 627          */
 628         if (data->host_cookie == COOKIE_PRE_MAPPED)
 629                 return data->sg_count;
 630
 631         /* Bounce write requests to the bounce buffer */
 632         if (host->bounce_buffer) {
 633                 unsigned int length = data->blksz * data->blocks;
 634
 635                 if (length > host->bounce_buffer_size) {
 636                         pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
 637                                mmc_hostname(host->mmc), length,
 638                                host->bounce_buffer_size);
 639                         return -EIO;
 640                 }
 641                 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
 642                         /* Copy the data to the bounce buffer */
 643                         if (host->ops->copy_to_bounce_buffer) {
 644                                 host->ops->copy_to_bounce_buffer(host,
 645                                                                  data, length);
 646                         } else {
 647                                 sg_copy_to_buffer(data->sg, data->sg_len,
 648                                                   host->bounce_buffer, length);
 649                         }
 650                 }
 651                 /* Switch ownership to the DMA */
 652                 dma_sync_single_for_device(host->mmc->parent,
 653                                            host->bounce_addr,
 654                                            host->bounce_buffer_size,
 655                                            mmc_get_dma_dir(data));
 656                 /* Just a dummy value */
 657                 sg_count = 1;
 658         } else {
 659                 /* Just access the data directly from memory */
 660                 sg_count = dma_map_sg(mmc_dev(host->mmc),
 661                                       data->sg, data->sg_len,
 662                                       mmc_get_dma_dir(data));
 663         }
 664
 665         if (sg_count == 0)
 666                 return -ENOSPC;
 667
 668         data->sg_count = sg_count;
 669         data->host_cookie = cookie;
 670
 671         return sg_count;
 672 }
 673
 674 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 675 {
 676         local_irq_save(*flags);
 677         return kmap_atomic(sg_page(sg)) + sg->offset;
 678 }
 679
 680 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 681 {
 682         kunmap_atomic(buffer);
 683         local_irq_restore(*flags);
 684 }
 685
 686 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
 687                            dma_addr_t addr, int len, unsigned int cmd)
 688 {
 689         struct sdhci_adma2_64_desc *dma_desc = *desc;
 690
 691         /* 32-bit and 64-bit descriptors have these members in same position */
 692         dma_desc->cmd = cpu_to_le16(cmd);
 693         dma_desc->len = cpu_to_le16(len);
 694         dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
 695
 696         if (host->flags & SDHCI_USE_64_BIT_DMA)
 697                 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
 698
 699         *desc += host->desc_sz;
 700 }
 701 EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
 702
 703 static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
 704                                            void **desc, dma_addr_t addr,
 705                                            int len, unsigned int cmd)
 706 {
 707         if (host->ops->adma_write_desc)
 708                 host->ops->adma_write_desc(host, desc, addr, len, cmd);
 709         else
 710                 sdhci_adma_write_desc(host, desc, addr, len, cmd);
 711 }
 712
 713 static void sdhci_adma_mark_end(void *desc)
 714 {
 715         struct sdhci_adma2_64_desc *dma_desc = desc;
 716
 717         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 718         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 719 }
 720
 721 static void sdhci_adma_table_pre(struct sdhci_host *host,
 722         struct mmc_data *data, int sg_count)
 723 {
 724         struct scatterlist *sg;
 725         unsigned long flags;
 726         dma_addr_t addr, align_addr;
 727         void *desc, *align;
 728         char *buffer;
 729         int len, offset, i;
 730
 731         /*
 732          * The spec does not specify endianness of descriptor table.
 733          * We currently guess that it is LE.
 734          */
 735
 736         host->sg_count = sg_count;
 737
 738         desc = host->adma_table;
 739         align = host->align_buffer;
 740
 741         align_addr = host->align_addr;
 742
 743         for_each_sg(data->sg, sg, host->sg_count, i) {
 744                 addr = sg_dma_address(sg);
 745                 len = sg_dma_len(sg);
 746
 747                 /*
 748                  * The SDHCI specification states that ADMA addresses must
 749                  * be 32-bit aligned. If they aren't, then we use a bounce
 750                  * buffer for the (up to three) bytes that screw up the
 751                  * alignment.
 752                  */
 753                 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
 754                          SDHCI_ADMA2_MASK;
 755                 if (offset) {
 756                         if (data->flags & MMC_DATA_WRITE) {
 757                                 buffer = sdhci_kmap_atomic(sg, &flags);
 758                                 memcpy(align, buffer, offset);
 759                                 sdhci_kunmap_atomic(buffer, &flags);
 760                         }
 761
 762                         /* tran, valid */
 763                         __sdhci_adma_write_desc(host, &desc, align_addr,
 764                                                 offset, ADMA2_TRAN_VALID);
 765
 766                         BUG_ON(offset > 65536);
 767
 768                         align += SDHCI_ADMA2_ALIGN;
 769                         align_addr += SDHCI_ADMA2_ALIGN;
 770
 771                         addr += offset;
 772                         len -= offset;
 773                 }
 774
 775                 BUG_ON(len > 65536);
 776
 777                 /* tran, valid */
 778                 if (len)
 779                         __sdhci_adma_write_desc(host, &desc, addr, len,
 780                                                 ADMA2_TRAN_VALID);
 781
 782                 /*
 783                  * If this triggers then we have a calculation bug
 784                  * somewhere. :/
 785                  */
 786                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 787         }
 788
 789         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 790                 /* Mark the last descriptor as the terminating descriptor */
 791                 if (desc != host->adma_table) {
 792                         desc -= host->desc_sz;
 793                         sdhci_adma_mark_end(desc);
 794                 }
 795         } else {
 796                 /* Add a terminating entry - nop, end, valid */
 797                 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
 798         }
 799 }
 800
 801 static void sdhci_adma_table_post(struct sdhci_host *host,
 802         struct mmc_data *data)
 803 {
 804         struct scatterlist *sg;
 805         int i, size;
 806         void *align;
 807         char *buffer;
 808         unsigned long flags;
 809
 810         if (data->flags & MMC_DATA_READ) {
 811                 bool has_unaligned = false;
 812
 813                 /* Do a quick scan of the SG list for any unaligned mappings */
 814                 for_each_sg(data->sg, sg, host->sg_count, i)
 815                         if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 816                                 has_unaligned = true;
 817                                 break;
 818                         }
 819
 820                 if (has_unaligned) {
 821                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 822                                             data->sg_len, DMA_FROM_DEVICE);
 823
 824                         align = host->align_buffer;
 825
 826                         for_each_sg(data->sg, sg, host->sg_count, i) {
 827                                 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 828                                         size = SDHCI_ADMA2_ALIGN -
 829                                                (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
 830
 831                                         buffer = sdhci_kmap_atomic(sg, &flags);
 832                                         memcpy(buffer, align, size);
 833                                         sdhci_kunmap_atomic(buffer, &flags);
 834
 835                                         align += SDHCI_ADMA2_ALIGN;
 836                                 }
 837                         }
 838                 }
 839         }
 840 }
 841
 842 static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
 843 {
 844         sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
 845         if (host->flags & SDHCI_USE_64_BIT_DMA)
 846                 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
 847 }
 848
 849 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
 850 {
 851         if (host->bounce_buffer)
 852                 return host->bounce_addr;
 853         else
 854                 return sg_dma_address(host->data->sg);
 855 }
 856
 857 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
 858 {
 859         if (host->v4_mode)
 860                 sdhci_set_adma_addr(host, addr);
 861         else
 862                 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
 863 }
 864
 865 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
 866                                          struct mmc_command *cmd,
 867                                          struct mmc_data *data)
 868 {
 869         unsigned int target_timeout;
 870
 871         /* timeout in us */
 872         if (!data) {
 873                 target_timeout = cmd->busy_timeout * 1000;
 874         } else {
 875                 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
 876                 if (host->clock && data->timeout_clks) {
 877                         unsigned long long val;
 878
 879                         /*
 880                          * data->timeout_clks is in units of clock cycles.
 881                          * host->clock is in Hz.  target_timeout is in us.
 882                          * Hence, us = 1000000 * cycles / Hz.  Round up.
 883                          */
 884                         val = 1000000ULL * data->timeout_clks;
 885                         if (do_div(val, host->clock))
 886                                 target_timeout++;
 887                         target_timeout += val;
 888                 }
 889         }
 890
 891         return target_timeout;
 892 }
 893
 894 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
 895                                   struct mmc_command *cmd)
 896 {
 897         struct mmc_data *data = cmd->data;
 898         struct mmc_host *mmc = host->mmc;
 899         struct mmc_ios *ios = &mmc->ios;
 900         unsigned char bus_width = 1 << ios->bus_width;
 901         unsigned int blksz;
 902         unsigned int freq;
 903         u64 target_timeout;
 904         u64 transfer_time;
 905
 906         target_timeout = sdhci_target_timeout(host, cmd, data);
 907         target_timeout *= NSEC_PER_USEC;
 908
 909         if (data) {
 910                 blksz = data->blksz;
 911                 freq = host->mmc->actual_clock ? : host->clock;
 912                 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
 913                 do_div(transfer_time, freq);
 914                 /* multiply by '2' to account for any unknowns */
 915                 transfer_time = transfer_time * 2;
 916                 /* calculate timeout for the entire data */
 917                 host->data_timeout = data->blocks * target_timeout +
 918                                      transfer_time;
 919         } else {
 920                 host->data_timeout = target_timeout;
 921         }
 922
 923         if (host->data_timeout)
 924                 host->data_timeout += MMC_CMD_TRANSFER_TIME;
 925 }
 926
 927 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
 928                              bool *too_big)
 929 {
 930         u8 count;
 931         struct mmc_data *data;
 932         unsigned target_timeout, current_timeout;
 933
 934         *too_big = true;
 935
 936         /*
 937          * If the host controller provides us with an incorrect timeout
 938          * value, just skip the check and use 0xE.  The hardware may take
 939          * longer to time out, but that's much better than having a too-short
 940          * timeout value.
 941          */
 942         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 943                 return 0xE;
 944
 945         /* Unspecified command, asume max */
 946         if (cmd == NULL)
 947                 return 0xE;
 948
 949         data = cmd->data;
 950         /* Unspecified timeout, assume max */
 951         if (!data && !cmd->busy_timeout)
 952                 return 0xE;
 953
 954         /* timeout in us */
 955         target_timeout = sdhci_target_timeout(host, cmd, data);
 956
 957         /*
 958          * Figure out needed cycles.
 959          * We do this in steps in order to fit inside a 32 bit int.
 960          * The first step is the minimum timeout, which will have a
 961          * minimum resolution of 6 bits:
 962          * (1) 2^13*1000 > 2^22,
 963          * (2) host->timeout_clk < 2^16
 964          *     =>
 965          *     (1) / (2) > 2^6
 966          */
 967         count = 0;
 968         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 969         while (current_timeout < target_timeout) {
 970                 count++;
 971                 current_timeout <<= 1;
 972                 if (count >= 0xF)
 973                         break;
 974         }
 975
 976         if (count >= 0xF) {
 977                 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
 978                         DBG("Too large timeout 0x%x requested for CMD%d!\n",
 979                             count, cmd->opcode);
 980                 count = 0xE;
 981         } else {
 982                 *too_big = false;
 983         }
 984
 985         return count;
 986 }
 987
 988 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 989 {
 990         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 991         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 992
 993         if (host->flags & SDHCI_REQ_USE_DMA)
 994                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 995         else
 996                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 997
 998         if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
 999                 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1000         else
1001                 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1002
1003         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1004         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1005 }
1006
1007 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1008 {
1009         if (enable)
1010                 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1011         else
1012                 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1013         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1014         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1015 }
1016 EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1017
1018 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1019 {
1020         bool too_big = false;
1021         u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1022
1023         if (too_big &&
1024             host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1025                 sdhci_calc_sw_timeout(host, cmd);
1026                 sdhci_set_data_timeout_irq(host, false);
1027         } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1028                 sdhci_set_data_timeout_irq(host, true);
1029         }
1030
1031         sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1032 }
1033 EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1034
1035 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1036 {
1037         if (host->ops->set_timeout)
1038                 host->ops->set_timeout(host, cmd);
1039         else
1040                 __sdhci_set_timeout(host, cmd);
1041 }
1042
1043 static void sdhci_initialize_data(struct sdhci_host *host,
1044                                   struct mmc_data *data)
1045 {
1046         WARN_ON(host->data);
1047
1048         /* Sanity checks */
1049         BUG_ON(data->blksz * data->blocks > 524288);
1050         BUG_ON(data->blksz > host->mmc->max_blk_size);
1051         BUG_ON(data->blocks > 65535);
1052
1053         host->data = data;
1054         host->data_early = 0;
1055         host->data->bytes_xfered = 0;
1056 }
1057
1058 static inline void sdhci_set_block_info(struct sdhci_host *host,
1059                                         struct mmc_data *data)
1060 {
1061         /* Set the DMA boundary value and block size */
1062         sdhci_writew(host,
1063                      SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1064                      SDHCI_BLOCK_SIZE);
1065         /*
1066          * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1067          * can be supported, in that case 16-bit block count register must be 0.
1068          */
1069         if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1070             (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1071                 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1072                         sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1073                 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1074         } else {
1075                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1076         }
1077 }
1078
1079 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1080 {
1081         struct mmc_data *data = cmd->data;
1082
1083         sdhci_initialize_data(host, data);
1084
1085         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1086                 struct scatterlist *sg;
1087                 unsigned int length_mask, offset_mask;
1088                 int i;
1089
1090                 host->flags |= SDHCI_REQ_USE_DMA;
1091
1092                 /*
1093                  * FIXME: This doesn't account for merging when mapping the
1094                  * scatterlist.
1095                  *
1096                  * The assumption here being that alignment and lengths are
1097                  * the same after DMA mapping to device address space.
1098                  */
1099                 length_mask = 0;
1100                 offset_mask = 0;
1101                 if (host->flags & SDHCI_USE_ADMA) {
1102                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1103                                 length_mask = 3;
1104                                 /*
1105                                  * As we use up to 3 byte chunks to work
1106                                  * around alignment problems, we need to
1107                                  * check the offset as well.
1108                                  */
1109                                 offset_mask = 3;
1110                         }
1111                 } else {
1112                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1113                                 length_mask = 3;
1114                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1115                                 offset_mask = 3;
1116                 }
1117
1118                 if (unlikely(length_mask | offset_mask)) {
1119                         for_each_sg(data->sg, sg, data->sg_len, i) {
1120                                 if (sg->length & length_mask) {
1121                                         DBG("Reverting to PIO because of transfer size (%d)\n",
1122                                             sg->length);
1123                                         host->flags &= ~SDHCI_REQ_USE_DMA;
1124                                         break;
1125                                 }
1126                                 if (sg->offset & offset_mask) {
1127                                         DBG("Reverting to PIO because of bad alignment\n");
1128                                         host->flags &= ~SDHCI_REQ_USE_DMA;
1129                                         break;
1130                                 }
1131                         }
1132                 }
1133         }
1134
1135         if (host->flags & SDHCI_REQ_USE_DMA) {
1136                 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1137
1138                 if (sg_cnt <= 0) {
1139                         /*
1140                          * This only happens when someone fed
1141                          * us an invalid request.
1142                          */
1143                         WARN_ON(1);
1144                         host->flags &= ~SDHCI_REQ_USE_DMA;
1145                 } else if (host->flags & SDHCI_USE_ADMA) {
1146                         sdhci_adma_table_pre(host, data, sg_cnt);
1147                         sdhci_set_adma_addr(host, host->adma_addr);
1148                 } else {
1149                         WARN_ON(sg_cnt != 1);
1150                         sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1151                 }
1152         }
1153
1154         sdhci_config_dma(host);
1155
1156         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1157                 int flags;
1158
1159                 flags = SG_MITER_ATOMIC;
1160                 if (host->data->flags & MMC_DATA_READ)
1161                         flags |= SG_MITER_TO_SG;
1162                 else
1163                         flags |= SG_MITER_FROM_SG;
1164                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1165                 host->blocks = data->blocks;
1166         }
1167
1168         sdhci_set_transfer_irqs(host);
1169
1170         sdhci_set_block_info(host, data);
1171 }
1172
1173 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1174
1175 static int sdhci_external_dma_init(struct sdhci_host *host)
1176 {
1177         int ret = 0;
1178         struct mmc_host *mmc = host->mmc;
1179
1180         host->tx_chan = dma_request_chan(mmc->parent, "tx");
1181         if (IS_ERR(host->tx_chan)) {
1182                 ret = PTR_ERR(host->tx_chan);
1183                 if (ret != -EPROBE_DEFER)
1184                         pr_warn("Failed to request TX DMA channel.\n");
1185                 host->tx_chan = NULL;
1186                 return ret;
1187         }
1188
1189         host->rx_chan = dma_request_chan(mmc->parent, "rx");
1190         if (IS_ERR(host->rx_chan)) {
1191                 if (host->tx_chan) {
1192                         dma_release_channel(host->tx_chan);
1193                         host->tx_chan = NULL;
1194                 }
1195
1196                 ret = PTR_ERR(host->rx_chan);
1197                 if (ret != -EPROBE_DEFER)
1198                         pr_warn("Failed to request RX DMA channel.\n");
1199                 host->rx_chan = NULL;
1200         }
1201
1202         return ret;
1203 }
1204
1205 static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1206                                                    struct mmc_data *data)
1207 {
1208         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1209 }
1210
1211 static int sdhci_external_dma_setup(struct sdhci_host *host,
1212                                     struct mmc_command *cmd)
1213 {
1214         int ret, i;
1215         enum dma_transfer_direction dir;
1216         struct dma_async_tx_descriptor *desc;
1217         struct mmc_data *data = cmd->data;
1218         struct dma_chan *chan;
1219         struct dma_slave_config cfg;
1220         dma_cookie_t cookie;
1221         int sg_cnt;
1222
1223         if (!host->mapbase)
1224                 return -EINVAL;
1225
1226         cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1227         cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1228         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1229         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1230         cfg.src_maxburst = data->blksz / 4;
1231         cfg.dst_maxburst = data->blksz / 4;
1232
1233         /* Sanity check: all the SG entries must be aligned by block size. */
1234         for (i = 0; i < data->sg_len; i++) {
1235                 if ((data->sg + i)->length % data->blksz)
1236                         return -EINVAL;
1237         }
1238
1239         chan = sdhci_external_dma_channel(host, data);
1240
1241         ret = dmaengine_slave_config(chan, &cfg);
1242         if (ret)
1243                 return ret;
1244
1245         sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1246         if (sg_cnt <= 0)
1247                 return -EINVAL;
1248
1249         dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1250         desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1251                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1252         if (!desc)
1253                 return -EINVAL;
1254
1255         desc->callback = NULL;
1256         desc->callback_param = NULL;
1257
1258         cookie = dmaengine_submit(desc);
1259         if (dma_submit_error(cookie))
1260                 ret = cookie;
1261
1262         return ret;
1263 }
1264
1265 static void sdhci_external_dma_release(struct sdhci_host *host)
1266 {
1267         if (host->tx_chan) {
1268                 dma_release_channel(host->tx_chan);
1269                 host->tx_chan = NULL;
1270         }
1271
1272         if (host->rx_chan) {
1273                 dma_release_channel(host->rx_chan);
1274                 host->rx_chan = NULL;
1275         }
1276
1277         sdhci_switch_external_dma(host, false);
1278 }
1279
1280 static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1281                                               struct mmc_command *cmd)
1282 {
1283         struct mmc_data *data = cmd->data;
1284
1285         sdhci_initialize_data(host, data);
1286
1287         host->flags |= SDHCI_REQ_USE_DMA;
1288         sdhci_set_transfer_irqs(host);
1289
1290         sdhci_set_block_info(host, data);
1291 }
1292
1293 static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1294                                             struct mmc_command *cmd)
1295 {
1296         if (!sdhci_external_dma_setup(host, cmd)) {
1297                 __sdhci_external_dma_prepare_data(host, cmd);
1298         } else {
1299                 sdhci_external_dma_release(host);
1300                 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1301                        mmc_hostname(host->mmc));
1302                 sdhci_prepare_data(host, cmd);
1303         }
1304 }
1305
1306 static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1307                                             struct mmc_command *cmd)
1308 {
1309         struct dma_chan *chan;
1310
1311         if (!cmd->data)
1312                 return;
1313
1314         chan = sdhci_external_dma_channel(host, cmd->data);
1315         if (chan)
1316                 dma_async_issue_pending(chan);
1317 }
1318
1319 #else
1320
1321 static inline int sdhci_external_dma_init(struct sdhci_host *host)
1322 {
1323         return -EOPNOTSUPP;
1324 }
1325
1326 static inline void sdhci_external_dma_release(struct sdhci_host *host)
1327 {
1328 }
1329
1330 static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1331                                                    struct mmc_command *cmd)
1332 {
1333         /* This should never happen */
1334         WARN_ON_ONCE(1);
1335 }
1336
1337 static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1338                                                    struct mmc_command *cmd)
1339 {
1340 }
1341
1342 static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1343                                                           struct mmc_data *data)
1344 {
1345         return NULL;
1346 }
1347
1348 #endif
1349
1350 void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1351 {
1352         host->use_external_dma = en;
1353 }
1354 EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1355
1356 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1357                                     struct mmc_request *mrq)
1358 {
1359         return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1360                !mrq->cap_cmd_during_tfr;
1361 }
1362
1363 static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1364                                     struct mmc_request *mrq)
1365 {
1366         return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1367 }
1368
1369 static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1370                                       struct mmc_request *mrq)
1371 {
1372         return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1373 }
1374
1375 static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1376                                          struct mmc_command *cmd,
1377                                          u16 *mode)
1378 {
1379         bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1380                          (cmd->opcode != SD_IO_RW_EXTENDED);
1381         bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1382         u16 ctrl2;
1383
1384         /*
1385          * In case of Version 4.10 or later, use of 'Auto CMD Auto
1386          * Select' is recommended rather than use of 'Auto CMD12
1387          * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1388          * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1389          */
1390         if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1391             (use_cmd12 || use_cmd23)) {
1392                 *mode |= SDHCI_TRNS_AUTO_SEL;
1393
1394                 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1395                 if (use_cmd23)
1396                         ctrl2 |= SDHCI_CMD23_ENABLE;
1397                 else
1398                         ctrl2 &= ~SDHCI_CMD23_ENABLE;
1399                 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1400
1401                 return;
1402         }
1403
1404         /*
1405          * If we are sending CMD23, CMD12 never gets sent
1406          * on successful completion (so no Auto-CMD12).
1407          */
1408         if (use_cmd12)
1409                 *mode |= SDHCI_TRNS_AUTO_CMD12;
1410         else if (use_cmd23)
1411                 *mode |= SDHCI_TRNS_AUTO_CMD23;
1412 }
1413
1414 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1415         struct mmc_command *cmd)
1416 {
1417         u16 mode = 0;
1418         struct mmc_data *data = cmd->data;
1419
1420         if (data == NULL) {
1421                 if (host->quirks2 &
1422                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1423                         /* must not clear SDHCI_TRANSFER_MODE when tuning */
1424                         if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1425                                 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1426                 } else {
1427                 /* clear Auto CMD settings for no data CMDs */
1428                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1429                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1430                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1431                 }
1432                 return;
1433         }
1434
1435         WARN_ON(!host->data);
1436
1437         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1438                 mode = SDHCI_TRNS_BLK_CNT_EN;
1439
1440         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1441                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1442                 sdhci_auto_cmd_select(host, cmd, &mode);
1443                 if (sdhci_auto_cmd23(host, cmd->mrq))
1444                         sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1445         }
1446
1447         if (data->flags & MMC_DATA_READ)
1448                 mode |= SDHCI_TRNS_READ;
1449         if (host->flags & SDHCI_REQ_USE_DMA)
1450                 mode |= SDHCI_TRNS_DMA;
1451
1452         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1453 }
1454
1455 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1456 {
1457         return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1458                 ((mrq->cmd && mrq->cmd->error) ||
1459                  (mrq->sbc && mrq->sbc->error) ||
1460                  (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1461                  (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1462 }
1463
1464 static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1465 {
1466         int i;
1467
1468         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1469                 if (host->mrqs_done[i] == mrq) {
1470                         WARN_ON(1);
1471                         return;
1472                 }
1473         }
1474
1475         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1476                 if (!host->mrqs_done[i]) {
1477                         host->mrqs_done[i] = mrq;
1478                         break;
1479                 }
1480         }
1481
1482         WARN_ON(i >= SDHCI_MAX_MRQS);
1483 }
1484
1485 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1486 {
1487         if (host->cmd && host->cmd->mrq == mrq)
1488                 host->cmd = NULL;
1489
1490         if (host->data_cmd && host->data_cmd->mrq == mrq)
1491                 host->data_cmd = NULL;
1492
1493         if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1494                 host->deferred_cmd = NULL;
1495
1496         if (host->data && host->data->mrq == mrq)
1497                 host->data = NULL;
1498
1499         if (sdhci_needs_reset(host, mrq))
1500                 host->pending_reset = true;
1501
1502         sdhci_set_mrq_done(host, mrq);
1503
1504         sdhci_del_timer(host, mrq);
1505
1506         if (!sdhci_has_requests(host))
1507                 sdhci_led_deactivate(host);
1508 }
1509
1510 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1511 {
1512         __sdhci_finish_mrq(host, mrq);
1513
1514         queue_work(host->complete_wq, &host->complete_work);
1515 }
1516
1517 static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1518 {
1519         struct mmc_command *data_cmd = host->data_cmd;
1520         struct mmc_data *data = host->data;
1521
1522         host->data = NULL;
1523         host->data_cmd = NULL;
1524
1525         /*
1526          * The controller needs a reset of internal state machines upon error
1527          * conditions.
1528          */
1529         if (data->error) {
1530                 if (!host->cmd || host->cmd == data_cmd)
1531                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1532                 sdhci_do_reset(host, SDHCI_RESET_DATA);
1533         }
1534
1535         if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1536             (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1537                 sdhci_adma_table_post(host, data);
1538
1539         /*
1540          * The specification states that the block count register must
1541          * be updated, but it does not specify at what point in the
1542          * data flow. That makes the register entirely useless to read
1543          * back so we have to assume that nothing made it to the card
1544          * in the event of an error.
1545          */
1546         if (data->error)
1547                 data->bytes_xfered = 0;
1548         else
1549                 data->bytes_xfered = data->blksz * data->blocks;
1550
1551         /*
1552          * Need to send CMD12 if -
1553          * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1554          * b) error in multiblock transfer
1555          */
1556         if (data->stop &&
1557             ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1558              data->error)) {
1559                 /*
1560                  * 'cap_cmd_during_tfr' request must not use the command line
1561                  * after mmc_command_done() has been called. It is upper layer's
1562                  * responsibility to send the stop command if required.
1563                  */
1564                 if (data->mrq->cap_cmd_during_tfr) {
1565                         __sdhci_finish_mrq(host, data->mrq);
1566                 } else {
1567                         /* Avoid triggering warning in sdhci_send_command() */
1568                         host->cmd = NULL;
1569                         if (!sdhci_send_command(host, data->stop)) {
1570                                 if (sw_data_timeout) {
1571                                         /*
1572                                          * This is anyway a sw data timeout, so
1573                                          * give up now.
1574                                          */
1575                                         data->stop->error = -EIO;
1576                                         __sdhci_finish_mrq(host, data->mrq);
1577                                 } else {
1578                                         WARN_ON(host->deferred_cmd);
1579                                         host->deferred_cmd = data->stop;
1580                                 }
1581                         }
1582                 }
1583         } else {
1584                 __sdhci_finish_mrq(host, data->mrq);
1585         }
1586 }
1587
1588 static void sdhci_finish_data(struct sdhci_host *host)
1589 {
1590         __sdhci_finish_data(host, false);
1591 }
1592
1593 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1594 {
1595         int flags;
1596         u32 mask;
1597         unsigned long timeout;
1598
1599         WARN_ON(host->cmd);
1600
1601         /* Initially, a command has no error */
1602         cmd->error = 0;
1603
1604         if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1605             cmd->opcode == MMC_STOP_TRANSMISSION)
1606                 cmd->flags |= MMC_RSP_BUSY;
1607
1608         mask = SDHCI_CMD_INHIBIT;
1609         if (sdhci_data_line_cmd(cmd))
1610                 mask |= SDHCI_DATA_INHIBIT;
1611
1612         /* We shouldn't wait for data inihibit for stop commands, even
1613            though they might use busy signaling */
1614         if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1615                 mask &= ~SDHCI_DATA_INHIBIT;
1616
1617         if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1618                 return false;
1619
1620         host->cmd = cmd;
1621         host->data_timeout = 0;
1622         if (sdhci_data_line_cmd(cmd)) {
1623                 WARN_ON(host->data_cmd);
1624                 host->data_cmd = cmd;
1625                 sdhci_set_timeout(host, cmd);
1626         }
1627
1628         if (cmd->data) {
1629                 if (host->use_external_dma)
1630                         sdhci_external_dma_prepare_data(host, cmd);
1631                 else
1632                         sdhci_prepare_data(host, cmd);
1633         }
1634
1635         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1636
1637         sdhci_set_transfer_mode(host, cmd);
1638
1639         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1640                 WARN_ONCE(1, "Unsupported response type!\n");
1641                 /*
1642                  * This does not happen in practice because 136-bit response
1643                  * commands never have busy waiting, so rather than complicate
1644                  * the error path, just remove busy waiting and continue.
1645                  */
1646                 cmd->flags &= ~MMC_RSP_BUSY;
1647         }
1648
1649         if (!(cmd->flags & MMC_RSP_PRESENT))
1650                 flags = SDHCI_CMD_RESP_NONE;
1651         else if (cmd->flags & MMC_RSP_136)
1652                 flags = SDHCI_CMD_RESP_LONG;
1653         else if (cmd->flags & MMC_RSP_BUSY)
1654                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1655         else
1656                 flags = SDHCI_CMD_RESP_SHORT;
1657
1658         if (cmd->flags & MMC_RSP_CRC)
1659                 flags |= SDHCI_CMD_CRC;
1660         if (cmd->flags & MMC_RSP_OPCODE)
1661                 flags |= SDHCI_CMD_INDEX;
1662
1663         /* CMD19 is special in that the Data Present Select should be set */
1664         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1665             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1666                 flags |= SDHCI_CMD_DATA;
1667
1668         timeout = jiffies;
1669         if (host->data_timeout)
1670                 timeout += nsecs_to_jiffies(host->data_timeout);
1671         else if (!cmd->data && cmd->busy_timeout > 9000)
1672                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1673         else
1674                 timeout += 10 * HZ;
1675         sdhci_mod_timer(host, cmd->mrq, timeout);
1676
1677         if (host->use_external_dma)
1678                 sdhci_external_dma_pre_transfer(host, cmd);
1679
1680         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1681
1682         return true;
1683 }
1684
1685 static bool sdhci_present_error(struct sdhci_host *host,
1686                                 struct mmc_command *cmd, bool present)
1687 {
1688         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1689                 cmd->error = -ENOMEDIUM;
1690                 return true;
1691         }
1692
1693         return false;
1694 }
1695
1696 static bool sdhci_send_command_retry(struct sdhci_host *host,
1697                                      struct mmc_command *cmd,
1698                                      unsigned long flags)
1699         __releases(host->lock)
1700         __acquires(host->lock)
1701 {
1702         struct mmc_command *deferred_cmd = host->deferred_cmd;
1703         int timeout = 10; /* Approx. 10 ms */
1704         bool present;
1705
1706         while (!sdhci_send_command(host, cmd)) {
1707                 if (!timeout--) {
1708                         pr_err("%s: Controller never released inhibit bit(s).\n",
1709                                mmc_hostname(host->mmc));
1710                         sdhci_dumpregs(host);
1711                         cmd->error = -EIO;
1712                         return false;
1713                 }
1714
1715                 spin_unlock_irqrestore(&host->lock, flags);
1716
1717                 usleep_range(1000, 1250);
1718
1719                 present = host->mmc->ops->get_cd(host->mmc);
1720
1721                 spin_lock_irqsave(&host->lock, flags);
1722
1723                 /* A deferred command might disappear, handle that */
1724                 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1725                         return true;
1726
1727                 if (sdhci_present_error(host, cmd, present))
1728                         return false;
1729         }
1730
1731         if (cmd == host->deferred_cmd)
1732                 host->deferred_cmd = NULL;
1733
1734         return true;
1735 }
1736
1737 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1738 {
1739         int i, reg;
1740
1741         for (i = 0; i < 4; i++) {
1742                 reg = SDHCI_RESPONSE + (3 - i) * 4;
1743                 cmd->resp[i] = sdhci_readl(host, reg);
1744         }
1745
1746         if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1747                 return;
1748
1749         /* CRC is stripped so we need to do some shifting */
1750         for (i = 0; i < 4; i++) {
1751                 cmd->resp[i] <<= 8;
1752                 if (i != 3)
1753                         cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1754         }
1755 }
1756
1757 static void sdhci_finish_command(struct sdhci_host *host)
1758 {
1759         struct mmc_command *cmd = host->cmd;
1760
1761         host->cmd = NULL;
1762
1763         if (cmd->flags & MMC_RSP_PRESENT) {
1764                 if (cmd->flags & MMC_RSP_136) {
1765                         sdhci_read_rsp_136(host, cmd);
1766                 } else {
1767                         cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1768                 }
1769         }
1770
1771         if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1772                 mmc_command_done(host->mmc, cmd->mrq);
1773
1774         /*
1775          * The host can send and interrupt when the busy state has
1776          * ended, allowing us to wait without wasting CPU cycles.
1777          * The busy signal uses DAT0 so this is similar to waiting
1778          * for data to complete.
1779          *
1780          * Note: The 1.0 specification is a bit ambiguous about this
1781          *       feature so there might be some problems with older
1782          *       controllers.
1783          */
1784         if (cmd->flags & MMC_RSP_BUSY) {
1785                 if (cmd->data) {
1786                         DBG("Cannot wait for busy signal when also doing a data transfer");
1787                 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1788                            cmd == host->data_cmd) {
1789                         /* Command complete before busy is ended */
1790                         return;
1791                 }
1792         }
1793
1794         /* Finished CMD23, now send actual command. */
1795         if (cmd == cmd->mrq->sbc) {
1796                 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1797                         WARN_ON(host->deferred_cmd);
1798                         host->deferred_cmd = cmd->mrq->cmd;
1799                 }
1800         } else {
1801
1802                 /* Processed actual command. */
1803                 if (host->data && host->data_early)
1804                         sdhci_finish_data(host);
1805
1806                 if (!cmd->data)
1807                         __sdhci_finish_mrq(host, cmd->mrq);
1808         }
1809 }
1810
1811 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1812 {
1813         u16 preset = 0;
1814
1815         switch (host->timing) {
1816         case MMC_TIMING_UHS_SDR12:
1817                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1818                 break;
1819         case MMC_TIMING_UHS_SDR25:
1820                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1821                 break;
1822         case MMC_TIMING_UHS_SDR50:
1823                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1824                 break;
1825         case MMC_TIMING_UHS_SDR104:
1826         case MMC_TIMING_MMC_HS200:
1827                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1828                 break;
1829         case MMC_TIMING_UHS_DDR50:
1830         case MMC_TIMING_MMC_DDR52:
1831                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1832                 break;
1833         case MMC_TIMING_MMC_HS400:
1834                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1835                 break;
1836         default:
1837                 pr_warn("%s: Invalid UHS-I mode selected\n",
1838                         mmc_hostname(host->mmc));
1839                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1840                 break;
1841         }
1842         return preset;
1843 }
1844
1845 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1846                    unsigned int *actual_clock)
1847 {
1848         int div = 0; /* Initialized for compiler warning */
1849         int real_div = div, clk_mul = 1;
1850         u16 clk = 0;
1851         bool switch_base_clk = false;
1852
1853         if (host->version >= SDHCI_SPEC_300) {
1854                 if (host->preset_enabled) {
1855                         u16 pre_val;
1856
1857                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1858                         pre_val = sdhci_get_preset_value(host);
1859                         div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1860                         if (host->clk_mul &&
1861                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1862                                 clk = SDHCI_PROG_CLOCK_MODE;
1863                                 real_div = div + 1;
1864                                 clk_mul = host->clk_mul;
1865                         } else {
1866                                 real_div = max_t(int, 1, div << 1);
1867                         }
1868                         goto clock_set;
1869                 }
1870
1871                 /*
1872                  * Check if the Host Controller supports Programmable Clock
1873                  * Mode.
1874                  */
1875                 if (host->clk_mul) {
1876                         for (div = 1; div <= 1024; div++) {
1877                                 if ((host->max_clk * host->clk_mul / div)
1878                                         <= clock)
1879                                         break;
1880                         }
1881                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1882                                 /*
1883                                  * Set Programmable Clock Mode in the Clock
1884                                  * Control register.
1885                                  */
1886                                 clk = SDHCI_PROG_CLOCK_MODE;
1887                                 real_div = div;
1888                                 clk_mul = host->clk_mul;
1889                                 div--;
1890                         } else {
1891                                 /*
1892                                  * Divisor can be too small to reach clock
1893                                  * speed requirement. Then use the base clock.
1894                                  */
1895                                 switch_base_clk = true;
1896                         }
1897                 }
1898
1899                 if (!host->clk_mul || switch_base_clk) {
1900                         /* Version 3.00 divisors must be a multiple of 2. */
1901                         if (host->max_clk <= clock)
1902                                 div = 1;
1903                         else {
1904                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1905                                      div += 2) {
1906                                         if ((host->max_clk / div) <= clock)
1907                                                 break;
1908                                 }
1909                         }
1910                         real_div = div;
1911                         div >>= 1;
1912                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1913                                 && !div && host->max_clk <= 25000000)
1914                                 div = 1;
1915                 }
1916         } else {
1917                 /* Version 2.00 divisors must be a power of 2. */
1918                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1919                         if ((host->max_clk / div) <= clock)
1920                                 break;
1921                 }
1922                 real_div = div;
1923                 div >>= 1;
1924         }
1925
1926 clock_set:
1927         if (real_div)
1928                 *actual_clock = (host->max_clk * clk_mul) / real_div;
1929         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1930         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1931                 << SDHCI_DIVIDER_HI_SHIFT;
1932
1933         return clk;
1934 }
1935 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1936
1937 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1938 {
1939         ktime_t timeout;
1940
1941         clk |= SDHCI_CLOCK_INT_EN;
1942         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1943
1944         /* Wait max 150 ms */
1945         timeout = ktime_add_ms(ktime_get(), 150);
1946         while (1) {
1947                 bool timedout = ktime_after(ktime_get(), timeout);
1948
1949                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1950                 if (clk & SDHCI_CLOCK_INT_STABLE)
1951                         break;
1952                 if (timedout) {
1953                         pr_err("%s: Internal clock never stabilised.\n",
1954                                mmc_hostname(host->mmc));
1955                         sdhci_dumpregs(host);
1956                         return;
1957                 }
1958                 udelay(10);
1959         }
1960
1961         if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1962                 clk |= SDHCI_CLOCK_PLL_EN;
1963                 clk &= ~SDHCI_CLOCK_INT_STABLE;
1964                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1965
1966                 /* Wait max 150 ms */
1967                 timeout = ktime_add_ms(ktime_get(), 150);
1968                 while (1) {
1969                         bool timedout = ktime_after(ktime_get(), timeout);
1970
1971                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1972                         if (clk & SDHCI_CLOCK_INT_STABLE)
1973                                 break;
1974                         if (timedout) {
1975                                 pr_err("%s: PLL clock never stabilised.\n",
1976                                        mmc_hostname(host->mmc));
1977                                 sdhci_dumpregs(host);
1978                                 return;
1979                         }
1980                         udelay(10);
1981                 }
1982         }
1983
1984         clk |= SDHCI_CLOCK_CARD_EN;
1985         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1986 }
1987 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1988
1989 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1990 {
1991         u16 clk;
1992
1993         host->mmc->actual_clock = 0;
1994
1995         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1996
1997         if (clock == 0)
1998                 return;
1999
2000         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2001         sdhci_enable_clk(host, clk);
2002 }
2003 EXPORT_SYMBOL_GPL(sdhci_set_clock);
2004
2005 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2006                                 unsigned short vdd)
2007 {
2008         struct mmc_host *mmc = host->mmc;
2009
2010         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2011
2012         if (mode != MMC_POWER_OFF)
2013                 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2014         else
2015                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2016 }
2017
2018 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2019                            unsigned short vdd)
2020 {
2021         u8 pwr = 0;
2022
2023         if (mode != MMC_POWER_OFF) {
2024                 switch (1 << vdd) {
2025                 case MMC_VDD_165_195:
2026                 /*
2027                  * Without a regulator, SDHCI does not support 2.0v
2028                  * so we only get here if the driver deliberately
2029                  * added the 2.0v range to ocr_avail. Map it to 1.8v
2030                  * for the purpose of turning on the power.
2031                  */
2032                 case MMC_VDD_20_21:
2033                         pwr = SDHCI_POWER_180;
2034                         break;
2035                 case MMC_VDD_29_30:
2036                 case MMC_VDD_30_31:
2037                         pwr = SDHCI_POWER_300;
2038                         break;
2039                 case MMC_VDD_32_33:
2040                 case MMC_VDD_33_34:
2041                         pwr = SDHCI_POWER_330;
2042                         break;
2043                 default:
2044                         WARN(1, "%s: Invalid vdd %#x\n",
2045                              mmc_hostname(host->mmc), vdd);
2046                         break;
2047                 }
2048         }
2049
2050         if (host->pwr == pwr)
2051                 return;
2052
2053         host->pwr = pwr;
2054
2055         if (pwr == 0) {
2056                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2057                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2058                         sdhci_runtime_pm_bus_off(host);
2059         } else {
2060                 /*
2061                  * Spec says that we should clear the power reg before setting
2062                  * a new value. Some controllers don't seem to like this though.
2063                  */
2064                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2065                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2066
2067                 /*
2068                  * At least the Marvell CaFe chip gets confused if we set the
2069                  * voltage and set turn on power at the same time, so set the
2070                  * voltage first.
2071                  */
2072                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2073                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2074
2075                 pwr |= SDHCI_POWER_ON;
2076
2077                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2078
2079                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2080                         sdhci_runtime_pm_bus_on(host);
2081
2082                 /*
2083                  * Some controllers need an extra 10ms delay of 10ms before
2084                  * they can apply clock after applying power
2085                  */
2086                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2087                         mdelay(10);
2088         }
2089 }
2090 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2091
2092 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2093                      unsigned short vdd)
2094 {
2095         if (IS_ERR(host->mmc->supply.vmmc))
2096                 sdhci_set_power_noreg(host, mode, vdd);
2097         else
2098                 sdhci_set_power_reg(host, mode, vdd);
2099 }
2100 EXPORT_SYMBOL_GPL(sdhci_set_power);
2101
2102 /*
2103  * Some controllers need to configure a valid bus voltage on their power
2104  * register regardless of whether an external regulator is taking care of power
2105  * supply. This helper function takes care of it if set as the controller's
2106  * sdhci_ops.set_power callback.
2107  */
2108 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2109                                      unsigned char mode,
2110                                      unsigned short vdd)
2111 {
2112         if (!IS_ERR(host->mmc->supply.vmmc)) {
2113                 struct mmc_host *mmc = host->mmc;
2114
2115                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2116         }
2117         sdhci_set_power_noreg(host, mode, vdd);
2118 }
2119 EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2120
2121 /*****************************************************************************\
2122  *                                                                           *
2123  * MMC callbacks                                                             *
2124  *                                                                           *
2125 \*****************************************************************************/
2126
2127 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2128 {
2129         struct sdhci_host *host = mmc_priv(mmc);
2130         struct mmc_command *cmd;
2131         unsigned long flags;
2132         bool present;
2133
2134         /* Firstly check card presence */
2135         present = mmc->ops->get_cd(mmc);
2136
2137         spin_lock_irqsave(&host->lock, flags);
2138
2139         sdhci_led_activate(host);
2140
2141         if (sdhci_present_error(host, mrq->cmd, present))
2142                 goto out_finish;
2143
2144         cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2145
2146         if (!sdhci_send_command_retry(host, cmd, flags))
2147                 goto out_finish;
2148
2149         spin_unlock_irqrestore(&host->lock, flags);
2150
2151         return;
2152
2153 out_finish:
2154         sdhci_finish_mrq(host, mrq);
2155         spin_unlock_irqrestore(&host->lock, flags);
2156 }
2157 EXPORT_SYMBOL_GPL(sdhci_request);
2158
2159 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2160 {
2161         struct sdhci_host *host = mmc_priv(mmc);
2162         struct mmc_command *cmd;
2163         unsigned long flags;
2164         int ret = 0;
2165
2166         spin_lock_irqsave(&host->lock, flags);
2167
2168         if (sdhci_present_error(host, mrq->cmd, true)) {
2169                 sdhci_finish_mrq(host, mrq);
2170                 goto out_finish;
2171         }
2172
2173         cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2174
2175         /*
2176          * The HSQ may send a command in interrupt context without polling
2177          * the busy signaling, which means we should return BUSY if controller
2178          * has not released inhibit bits to allow HSQ trying to send request
2179          * again in non-atomic context. So we should not finish this request
2180          * here.
2181          */
2182         if (!sdhci_send_command(host, cmd))
2183                 ret = -EBUSY;
2184         else
2185                 sdhci_led_activate(host);
2186
2187 out_finish:
2188         spin_unlock_irqrestore(&host->lock, flags);
2189         return ret;
2190 }
2191 EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2192
2193 void sdhci_set_bus_width(struct sdhci_host *host, int width)
2194 {
2195         u8 ctrl;
2196
2197         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2198         if (width == MMC_BUS_WIDTH_8) {
2199                 ctrl &= ~SDHCI_CTRL_4BITBUS;
2200                 ctrl |= SDHCI_CTRL_8BITBUS;
2201         } else {
2202                 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2203                         ctrl &= ~SDHCI_CTRL_8BITBUS;
2204                 if (width == MMC_BUS_WIDTH_4)
2205                         ctrl |= SDHCI_CTRL_4BITBUS;
2206                 else
2207                         ctrl &= ~SDHCI_CTRL_4BITBUS;
2208         }
2209         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2210 }
2211 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2212
2213 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2214 {
2215         u16 ctrl_2;
2216
2217         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2218         /* Select Bus Speed Mode for host */
2219         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2220         if ((timing == MMC_TIMING_MMC_HS200) ||
2221             (timing == MMC_TIMING_UHS_SDR104))
2222                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2223         else if (timing == MMC_TIMING_UHS_SDR12)
2224                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2225         else if (timing == MMC_TIMING_UHS_SDR25)
2226                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2227         else if (timing == MMC_TIMING_UHS_SDR50)
2228                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2229         else if ((timing == MMC_TIMING_UHS_DDR50) ||
2230                  (timing == MMC_TIMING_MMC_DDR52))
2231                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2232         else if (timing == MMC_TIMING_MMC_HS400)
2233                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2234         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2235 }
2236 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2237
2238 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2239 {
2240         struct sdhci_host *host = mmc_priv(mmc);
2241         u8 ctrl;
2242
2243         if (ios->power_mode == MMC_POWER_UNDEFINED)
2244                 return;
2245
2246         if (host->flags & SDHCI_DEVICE_DEAD) {
2247                 if (!IS_ERR(mmc->supply.vmmc) &&
2248                     ios->power_mode == MMC_POWER_OFF)
2249                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2250                 return;
2251         }
2252
2253         /*
2254          * Reset the chip on each power off.
2255          * Should clear out any weird states.
2256          */
2257         if (ios->power_mode == MMC_POWER_OFF) {
2258                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2259                 sdhci_reinit(host);
2260         }
2261
2262         if (host->version >= SDHCI_SPEC_300 &&
2263                 (ios->power_mode == MMC_POWER_UP) &&
2264                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2265                 sdhci_enable_preset_value(host, false);
2266
2267         if (!ios->clock || ios->clock != host->clock) {
2268                 host->ops->set_clock(host, ios->clock);
2269                 host->clock = ios->clock;
2270
2271                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2272                     host->clock) {
2273                         host->timeout_clk = host->mmc->actual_clock ?
2274                                                 host->mmc->actual_clock / 1000 :
2275                                                 host->clock / 1000;
2276                         host->mmc->max_busy_timeout =
2277                                 host->ops->get_max_timeout_count ?
2278                                 host->ops->get_max_timeout_count(host) :
2279                                 1 << 27;
2280                         host->mmc->max_busy_timeout /= host->timeout_clk;
2281                 }
2282         }
2283
2284         if (host->ops->set_power)
2285                 host->ops->set_power(host, ios->power_mode, ios->vdd);
2286         else
2287                 sdhci_set_power(host, ios->power_mode, ios->vdd);
2288
2289         if (host->ops->platform_send_init_74_clocks)
2290                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2291
2292         host->ops->set_bus_width(host, ios->bus_width);
2293
2294         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2295
2296         if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2297                 if (ios->timing == MMC_TIMING_SD_HS ||
2298                      ios->timing == MMC_TIMING_MMC_HS ||
2299                      ios->timing == MMC_TIMING_MMC_HS400 ||
2300                      ios->timing == MMC_TIMING_MMC_HS200 ||
2301                      ios->timing == MMC_TIMING_MMC_DDR52 ||
2302                      ios->timing == MMC_TIMING_UHS_SDR50 ||
2303                      ios->timing == MMC_TIMING_UHS_SDR104 ||
2304                      ios->timing == MMC_TIMING_UHS_DDR50 ||
2305                      ios->timing == MMC_TIMING_UHS_SDR25)
2306                         ctrl |= SDHCI_CTRL_HISPD;
2307                 else
2308                         ctrl &= ~SDHCI_CTRL_HISPD;
2309         }
2310
2311         if (host->version >= SDHCI_SPEC_300) {
2312                 u16 clk, ctrl_2;
2313
2314                 if (!host->preset_enabled) {
2315                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2316                         /*
2317                          * We only need to set Driver Strength if the
2318                          * preset value enable is not set.
2319                          */
2320                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2321                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2322                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2323                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2324                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2325                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2326                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2327                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2328                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2329                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2330                         else {
2331                                 pr_warn("%s: invalid driver type, default to driver type B\n",
2332                                         mmc_hostname(mmc));
2333                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2334                         }
2335
2336                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2337                 } else {
2338                         /*
2339                          * According to SDHC Spec v3.00, if the Preset Value
2340                          * Enable in the Host Control 2 register is set, we
2341                          * need to reset SD Clock Enable before changing High
2342                          * Speed Enable to avoid generating clock gliches.
2343                          */
2344
2345                         /* Reset SD Clock Enable */
2346                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2347                         clk &= ~SDHCI_CLOCK_CARD_EN;
2348                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2349
2350                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2351
2352                         /* Re-enable SD Clock */
2353                         host->ops->set_clock(host, host->clock);
2354                 }
2355
2356                 /* Reset SD Clock Enable */
2357                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2358                 clk &= ~SDHCI_CLOCK_CARD_EN;
2359                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2360
2361                 host->ops->set_uhs_signaling(host, ios->timing);
2362                 host->timing = ios->timing;
2363
2364                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2365                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2366                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
2367                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
2368                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
2369                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
2370                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
2371                         u16 preset;
2372
2373                         sdhci_enable_preset_value(host, true);
2374                         preset = sdhci_get_preset_value(host);
2375                         ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2376                                                   preset);
2377                 }
2378
2379                 /* Re-enable SD Clock */
2380                 host->ops->set_clock(host, host->clock);
2381         } else
2382                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2383
2384         /*
2385          * Some (ENE) controllers go apeshit on some ios operation,
2386          * signalling timeout and CRC errors even on CMD0. Resetting
2387          * it on each ios seems to solve the problem.
2388          */
2389         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2390                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2391 }
2392 EXPORT_SYMBOL_GPL(sdhci_set_ios);
2393
2394 static int sdhci_get_cd(struct mmc_host *mmc)
2395 {
2396         struct sdhci_host *host = mmc_priv(mmc);
2397         int gpio_cd = mmc_gpio_get_cd(mmc);
2398
2399         if (host->flags & SDHCI_DEVICE_DEAD)
2400                 return 0;
2401
2402         /* If nonremovable, assume that the card is always present. */
2403         if (!mmc_card_is_removable(host->mmc))
2404                 return 1;
2405
2406         /*
2407          * Try slot gpio detect, if defined it take precedence
2408          * over build in controller functionality
2409          */
2410         if (gpio_cd >= 0)
2411                 return !!gpio_cd;
2412
2413         /* If polling, assume that the card is always present. */
2414         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2415                 return 1;
2416
2417         /* Host native card detect */
2418         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2419 }
2420
2421 static int sdhci_check_ro(struct sdhci_host *host)
2422 {
2423         unsigned long flags;
2424         int is_readonly;
2425
2426         spin_lock_irqsave(&host->lock, flags);
2427
2428         if (host->flags & SDHCI_DEVICE_DEAD)
2429                 is_readonly = 0;
2430         else if (host->ops->get_ro)
2431                 is_readonly = host->ops->get_ro(host);
2432         else if (mmc_can_gpio_ro(host->mmc))
2433                 is_readonly = mmc_gpio_get_ro(host->mmc);
2434         else
2435                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2436                                 & SDHCI_WRITE_PROTECT);
2437
2438         spin_unlock_irqrestore(&host->lock, flags);
2439
2440         /* This quirk needs to be replaced by a callback-function later */
2441         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2442                 !is_readonly : is_readonly;
2443 }
2444
2445 #define SAMPLE_COUNT    5
2446
2447 static int sdhci_get_ro(struct mmc_host *mmc)
2448 {
2449         struct sdhci_host *host = mmc_priv(mmc);
2450         int i, ro_count;
2451
2452         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2453                 return sdhci_check_ro(host);
2454
2455         ro_count = 0;
2456         for (i = 0; i < SAMPLE_COUNT; i++) {
2457                 if (sdhci_check_ro(host)) {
2458                         if (++ro_count > SAMPLE_COUNT / 2)
2459                                 return 1;
2460                 }
2461                 msleep(30);
2462         }
2463         return 0;
2464 }
2465
2466 static void sdhci_hw_reset(struct mmc_host *mmc)
2467 {
2468         struct sdhci_host *host = mmc_priv(mmc);
2469
2470         if (host->ops && host->ops->hw_reset)
2471                 host->ops->hw_reset(host);
2472 }
2473
2474 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2475 {
2476         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2477                 if (enable)
2478                         host->ier |= SDHCI_INT_CARD_INT;
2479                 else
2480                         host->ier &= ~SDHCI_INT_CARD_INT;
2481
2482                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2483                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2484         }
2485 }
2486
2487 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2488 {
2489         struct sdhci_host *host = mmc_priv(mmc);
2490         unsigned long flags;
2491
2492         if (enable)
2493                 pm_runtime_get_noresume(host->mmc->parent);
2494
2495         spin_lock_irqsave(&host->lock, flags);
2496         sdhci_enable_sdio_irq_nolock(host, enable);
2497         spin_unlock_irqrestore(&host->lock, flags);
2498
2499         if (!enable)
2500                 pm_runtime_put_noidle(host->mmc->parent);
2501 }
2502 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2503
2504 static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2505 {
2506         struct sdhci_host *host = mmc_priv(mmc);
2507         unsigned long flags;
2508
2509         spin_lock_irqsave(&host->lock, flags);
2510         sdhci_enable_sdio_irq_nolock(host, true);
2511         spin_unlock_irqrestore(&host->lock, flags);
2512 }
2513
2514 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2515                                       struct mmc_ios *ios)
2516 {
2517         struct sdhci_host *host = mmc_priv(mmc);
2518         u16 ctrl;
2519         int ret;
2520
2521         /*
2522          * Signal Voltage Switching is only applicable for Host Controllers
2523          * v3.00 and above.
2524          */
2525         if (host->version < SDHCI_SPEC_300)
2526                 return 0;
2527
2528         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2529
2530         switch (ios->signal_voltage) {
2531         case MMC_SIGNAL_VOLTAGE_330:
2532                 if (!(host->flags & SDHCI_SIGNALING_330))
2533                         return -EINVAL;
2534                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2535                 ctrl &= ~SDHCI_CTRL_VDD_180;
2536                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2537
2538                 if (!IS_ERR(mmc->supply.vqmmc)) {
2539                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2540                         if (ret < 0) {
2541                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2542                                         mmc_hostname(mmc));
2543                                 return -EIO;
2544                         }
2545                 }
2546                 /* Wait for 5ms */
2547                 usleep_range(5000, 5500);
2548
2549                 /* 3.3V regulator output should be stable within 5 ms */
2550                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2551                 if (!(ctrl & SDHCI_CTRL_VDD_180))
2552                         return 0;
2553
2554                 pr_warn("%s: 3.3V regulator output did not become stable\n",
2555                         mmc_hostname(mmc));
2556
2557                 return -EAGAIN;
2558         case MMC_SIGNAL_VOLTAGE_180:
2559                 if (!(host->flags & SDHCI_SIGNALING_180))
2560                         return -EINVAL;
2561                 if (!IS_ERR(mmc->supply.vqmmc)) {
2562                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2563                         if (ret < 0) {
2564                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2565                                         mmc_hostname(mmc));
2566                                 return -EIO;
2567                         }
2568                 }
2569
2570                 /*
2571                  * Enable 1.8V Signal Enable in the Host Control2
2572                  * register
2573                  */
2574                 ctrl |= SDHCI_CTRL_VDD_180;
2575                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2576
2577                 /* Some controller need to do more when switching */
2578                 if (host->ops->voltage_switch)
2579                         host->ops->voltage_switch(host);
2580
2581                 /* 1.8V regulator output should be stable within 5 ms */
2582                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2583                 if (ctrl & SDHCI_CTRL_VDD_180)
2584                         return 0;
2585
2586                 pr_warn("%s: 1.8V regulator output did not become stable\n",
2587                         mmc_hostname(mmc));
2588
2589                 return -EAGAIN;
2590         case MMC_SIGNAL_VOLTAGE_120:
2591                 if (!(host->flags & SDHCI_SIGNALING_120))
2592                         return -EINVAL;
2593                 if (!IS_ERR(mmc->supply.vqmmc)) {
2594                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2595                         if (ret < 0) {
2596                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2597                                         mmc_hostname(mmc));
2598                                 return -EIO;
2599                         }
2600                 }
2601                 return 0;
2602         default:
2603                 /* No signal voltage switch required */
2604                 return 0;
2605         }
2606 }
2607 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2608
2609 static int sdhci_card_busy(struct mmc_host *mmc)
2610 {
2611         struct sdhci_host *host = mmc_priv(mmc);
2612         u32 present_state;
2613
2614         /* Check whether DAT[0] is 0 */
2615         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2616
2617         return !(present_state & SDHCI_DATA_0_LVL_MASK);
2618 }
2619
2620 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2621 {
2622         struct sdhci_host *host = mmc_priv(mmc);
2623         unsigned long flags;
2624
2625         spin_lock_irqsave(&host->lock, flags);
2626         host->flags |= SDHCI_HS400_TUNING;
2627         spin_unlock_irqrestore(&host->lock, flags);
2628
2629         return 0;
2630 }
2631
2632 void sdhci_start_tuning(struct sdhci_host *host)
2633 {
2634         u16 ctrl;
2635
2636         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2637         ctrl |= SDHCI_CTRL_EXEC_TUNING;
2638         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2639                 ctrl |= SDHCI_CTRL_TUNED_CLK;
2640         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2641
2642         /*
2643          * As per the Host Controller spec v3.00, tuning command
2644          * generates Buffer Read Ready interrupt, so enable that.
2645          *
2646          * Note: The spec clearly says that when tuning sequence
2647          * is being performed, the controller does not generate
2648          * interrupts other than Buffer Read Ready interrupt. But
2649          * to make sure we don't hit a controller bug, we _only_
2650          * enable Buffer Read Ready interrupt here.
2651          */
2652         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2653         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2654 }
2655 EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2656
2657 void sdhci_end_tuning(struct sdhci_host *host)
2658 {
2659         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2660         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2661 }
2662 EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2663
2664 void sdhci_reset_tuning(struct sdhci_host *host)
2665 {
2666         u16 ctrl;
2667
2668         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2669         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2670         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2671         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2672 }
2673 EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2674
2675 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2676 {
2677         sdhci_reset_tuning(host);
2678
2679         sdhci_do_reset(host, SDHCI_RESET_CMD);
2680         sdhci_do_reset(host, SDHCI_RESET_DATA);
2681
2682         sdhci_end_tuning(host);
2683
2684         mmc_abort_tuning(host->mmc, opcode);
2685 }
2686 EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2687
2688 /*
2689  * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2690  * tuning command does not have a data payload (or rather the hardware does it
2691  * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2692  * interrupt setup is different to other commands and there is no timeout
2693  * interrupt so special handling is needed.
2694  */
2695 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2696 {
2697         struct mmc_host *mmc = host->mmc;
2698         struct mmc_command cmd = {};
2699         struct mmc_request mrq = {};
2700         unsigned long flags;
2701         u32 b = host->sdma_boundary;
2702
2703         spin_lock_irqsave(&host->lock, flags);
2704
2705         cmd.opcode = opcode;
2706         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2707         cmd.mrq = &mrq;
2708
2709         mrq.cmd = &cmd;
2710         /*
2711          * In response to CMD19, the card sends 64 bytes of tuning
2712          * block to the Host Controller. So we set the block size
2713          * to 64 here.
2714          */
2715         if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2716             mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2717                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2718         else
2719                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2720
2721         /*
2722          * The tuning block is sent by the card to the host controller.
2723          * So we set the TRNS_READ bit in the Transfer Mode register.
2724          * This also takes care of setting DMA Enable and Multi Block
2725          * Select in the same register to 0.
2726          */
2727         sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2728
2729         if (!sdhci_send_command_retry(host, &cmd, flags)) {
2730                 spin_unlock_irqrestore(&host->lock, flags);
2731                 host->tuning_done = 0;
2732                 return;
2733         }
2734
2735         host->cmd = NULL;
2736
2737         sdhci_del_timer(host, &mrq);
2738
2739         host->tuning_done = 0;
2740
2741         spin_unlock_irqrestore(&host->lock, flags);
2742
2743         /* Wait for Buffer Read Ready interrupt */
2744         wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2745                            msecs_to_jiffies(50));
2746
2747 }
2748 EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2749
2750 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2751 {
2752         int i;
2753
2754         /*
2755          * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2756          * of loops reaches tuning loop count.
2757          */
2758         for (i = 0; i < host->tuning_loop_count; i++) {
2759                 u16 ctrl;
2760
2761                 sdhci_send_tuning(host, opcode);
2762
2763                 if (!host->tuning_done) {
2764                         pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2765                                  mmc_hostname(host->mmc));
2766                         sdhci_abort_tuning(host, opcode);
2767                         return -ETIMEDOUT;
2768                 }
2769
2770                 /* Spec does not require a delay between tuning cycles */
2771                 if (host->tuning_delay > 0)
2772                         mdelay(host->tuning_delay);
2773
2774                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2775                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2776                         if (ctrl & SDHCI_CTRL_TUNED_CLK)
2777                                 return 0; /* Success! */
2778                         break;
2779                 }
2780
2781         }
2782
2783         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2784                 mmc_hostname(host->mmc));
2785         sdhci_reset_tuning(host);
2786         return -EAGAIN;
2787 }
2788
2789 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2790 {
2791         struct sdhci_host *host = mmc_priv(mmc);
2792         int err = 0;
2793         unsigned int tuning_count = 0;
2794         bool hs400_tuning;
2795
2796         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2797
2798         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2799                 tuning_count = host->tuning_count;
2800
2801         /*
2802          * The Host Controller needs tuning in case of SDR104 and DDR50
2803          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2804          * the Capabilities register.
2805          * If the Host Controller supports the HS200 mode then the
2806          * tuning function has to be executed.
2807          */
2808         switch (host->timing) {
2809         /* HS400 tuning is done in HS200 mode */
2810         case MMC_TIMING_MMC_HS400:
2811                 err = -EINVAL;
2812                 goto out;
2813
2814         case MMC_TIMING_MMC_HS200:
2815                 /*
2816                  * Periodic re-tuning for HS400 is not expected to be needed, so
2817                  * disable it here.
2818                  */
2819                 if (hs400_tuning)
2820                         tuning_count = 0;
2821                 break;
2822
2823         case MMC_TIMING_UHS_SDR104:
2824         case MMC_TIMING_UHS_DDR50:
2825                 break;
2826
2827         case MMC_TIMING_UHS_SDR50:
2828                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2829                         break;
2830                 fallthrough;
2831
2832         default:
2833                 goto out;
2834         }
2835
2836         if (host->ops->platform_execute_tuning) {
2837                 err = host->ops->platform_execute_tuning(host, opcode);
2838                 goto out;
2839         }
2840
2841         host->mmc->retune_period = tuning_count;
2842
2843         if (host->tuning_delay < 0)
2844                 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2845
2846         sdhci_start_tuning(host);
2847
2848         host->tuning_err = __sdhci_execute_tuning(host, opcode);
2849
2850         sdhci_end_tuning(host);
2851 out:
2852         host->flags &= ~SDHCI_HS400_TUNING;
2853
2854         return err;
2855 }
2856 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2857
2858 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2859 {
2860         /* Host Controller v3.00 defines preset value registers */
2861         if (host->version < SDHCI_SPEC_300)
2862                 return;
2863
2864         /*
2865          * We only enable or disable Preset Value if they are not already
2866          * enabled or disabled respectively. Otherwise, we bail out.
2867          */
2868         if (host->preset_enabled != enable) {
2869                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2870
2871                 if (enable)
2872                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2873                 else
2874                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2875
2876                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2877
2878                 if (enable)
2879                         host->flags |= SDHCI_PV_ENABLED;
2880                 else
2881                         host->flags &= ~SDHCI_PV_ENABLED;
2882
2883                 host->preset_enabled = enable;
2884         }
2885 }
2886
2887 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2888                                 int err)
2889 {
2890         struct sdhci_host *host = mmc_priv(mmc);
2891         struct mmc_data *data = mrq->data;
2892
2893         if (data->host_cookie != COOKIE_UNMAPPED)
2894                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2895                              mmc_get_dma_dir(data));
2896
2897         data->host_cookie = COOKIE_UNMAPPED;
2898 }
2899
2900 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2901 {
2902         struct sdhci_host *host = mmc_priv(mmc);
2903
2904         mrq->data->host_cookie = COOKIE_UNMAPPED;
2905
2906         /*
2907          * No pre-mapping in the pre hook if we're using the bounce buffer,
2908          * for that we would need two bounce buffers since one buffer is
2909          * in flight when this is getting called.
2910          */
2911         if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2912                 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2913 }
2914
2915 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2916 {
2917         if (host->data_cmd) {
2918                 host->data_cmd->error = err;
2919                 sdhci_finish_mrq(host, host->data_cmd->mrq);
2920         }
2921
2922         if (host->cmd) {
2923                 host->cmd->error = err;
2924                 sdhci_finish_mrq(host, host->cmd->mrq);
2925         }
2926 }
2927
2928 static void sdhci_card_event(struct mmc_host *mmc)
2929 {
2930         struct sdhci_host *host = mmc_priv(mmc);
2931         unsigned long flags;
2932         int present;
2933
2934         /* First check if client has provided their own card event */
2935         if (host->ops->card_event)
2936                 host->ops->card_event(host);
2937
2938         present = mmc->ops->get_cd(mmc);
2939
2940         spin_lock_irqsave(&host->lock, flags);
2941
2942         /* Check sdhci_has_requests() first in case we are runtime suspended */
2943         if (sdhci_has_requests(host) && !present) {
2944                 pr_err("%s: Card removed during transfer!\n",
2945                         mmc_hostname(host->mmc));
2946                 pr_err("%s: Resetting controller.\n",
2947                         mmc_hostname(host->mmc));
2948
2949                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2950                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2951
2952                 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2953         }
2954
2955         spin_unlock_irqrestore(&host->lock, flags);
2956 }
2957
2958 static const struct mmc_host_ops sdhci_ops = {
2959         .request        = sdhci_request,
2960         .post_req       = sdhci_post_req,
2961         .pre_req        = sdhci_pre_req,
2962         .set_ios        = sdhci_set_ios,
2963         .get_cd         = sdhci_get_cd,
2964         .get_ro         = sdhci_get_ro,
2965         .hw_reset       = sdhci_hw_reset,
2966         .enable_sdio_irq = sdhci_enable_sdio_irq,
2967         .ack_sdio_irq    = sdhci_ack_sdio_irq,
2968         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2969         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2970         .execute_tuning                 = sdhci_execute_tuning,
2971         .card_event                     = sdhci_card_event,
2972         .card_busy      = sdhci_card_busy,
2973 };
2974
2975 /*****************************************************************************\
2976  *                                                                           *
2977  * Request done                                                              *
2978  *                                                                           *
2979 \*****************************************************************************/
2980
2981 static bool sdhci_request_done(struct sdhci_host *host)
2982 {
2983         unsigned long flags;
2984         struct mmc_request *mrq;
2985         int i;
2986
2987         spin_lock_irqsave(&host->lock, flags);
2988
2989         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2990                 mrq = host->mrqs_done[i];
2991                 if (mrq)
2992                         break;
2993         }
2994
2995         if (!mrq) {
2996                 spin_unlock_irqrestore(&host->lock, flags);
2997                 return true;
2998         }
2999
3000         /*
3001          * Always unmap the data buffers if they were mapped by
3002          * sdhci_prepare_data() whenever we finish with a request.
3003          * This avoids leaking DMA mappings on error.
3004          */
3005         if (host->flags & SDHCI_REQ_USE_DMA) {
3006                 struct mmc_data *data = mrq->data;
3007
3008                 if (host->use_external_dma && data &&
3009                     (mrq->cmd->error || data->error)) {
3010                         struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3011
3012                         host->mrqs_done[i] = NULL;
3013                         spin_unlock_irqrestore(&host->lock, flags);
3014                         dmaengine_terminate_sync(chan);
3015                         spin_lock_irqsave(&host->lock, flags);
3016                         sdhci_set_mrq_done(host, mrq);
3017                 }
3018
3019                 if (data && data->host_cookie == COOKIE_MAPPED) {
3020                         if (host->bounce_buffer) {
3021                                 /*
3022                                  * On reads, copy the bounced data into the
3023                                  * sglist
3024                                  */
3025                                 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3026                                         unsigned int length = data->bytes_xfered;
3027
3028                                         if (length > host->bounce_buffer_size) {
3029                                                 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3030                                                        mmc_hostname(host->mmc),
3031                                                        host->bounce_buffer_size,
3032                                                        data->bytes_xfered);
3033                                                 /* Cap it down and continue */
3034                                                 length = host->bounce_buffer_size;
3035                                         }
3036                                         dma_sync_single_for_cpu(
3037                                                 host->mmc->parent,
3038                                                 host->bounce_addr,
3039                                                 host->bounce_buffer_size,
3040                                                 DMA_FROM_DEVICE);
3041                                         sg_copy_from_buffer(data->sg,
3042                                                 data->sg_len,
3043                                                 host->bounce_buffer,
3044                                                 length);
3045                                 } else {
3046                                         /* No copying, just switch ownership */
3047                                         dma_sync_single_for_cpu(
3048                                                 host->mmc->parent,
3049                                                 host->bounce_addr,
3050                                                 host->bounce_buffer_size,
3051                                                 mmc_get_dma_dir(data));
3052                                 }
3053                         } else {
3054                                 /* Unmap the raw data */
3055                                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3056                                              data->sg_len,
3057                                              mmc_get_dma_dir(data));
3058                         }
3059                         data->host_cookie = COOKIE_UNMAPPED;
3060                 }
3061         }
3062
3063         /*
3064          * The controller needs a reset of internal state machines
3065          * upon error conditions.
3066          */
3067         if (sdhci_needs_reset(host, mrq)) {
3068                 /*
3069                  * Do not finish until command and data lines are available for
3070                  * reset. Note there can only be one other mrq, so it cannot
3071                  * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3072                  * would both be null.
3073                  */
3074                 if (host->cmd || host->data_cmd) {
3075                         spin_unlock_irqrestore(&host->lock, flags);
3076                         return true;
3077                 }
3078
3079                 /* Some controllers need this kick or reset won't work here */
3080                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3081                         /* This is to force an update */
3082                         host->ops->set_clock(host, host->clock);
3083
3084                 /* Spec says we should do both at the same time, but Ricoh
3085                    controllers do not like that. */
3086                 sdhci_do_reset(host, SDHCI_RESET_CMD);
3087                 sdhci_do_reset(host, SDHCI_RESET_DATA);
3088
3089                 host->pending_reset = false;
3090         }
3091
3092         host->mrqs_done[i] = NULL;
3093
3094         spin_unlock_irqrestore(&host->lock, flags);
3095
3096         if (host->ops->request_done)
3097                 host->ops->request_done(host, mrq);
3098         else
3099                 mmc_request_done(host->mmc, mrq);
3100
3101         return false;
3102 }
3103
3104 static void sdhci_complete_work(struct work_struct *work)
3105 {
3106         struct sdhci_host *host = container_of(work, struct sdhci_host,
3107                                                complete_work);
3108
3109         while (!sdhci_request_done(host))
3110                 ;
3111 }
3112
3113 static void sdhci_timeout_timer(struct timer_list *t)
3114 {
3115         struct sdhci_host *host;
3116         unsigned long flags;
3117
3118         host = from_timer(host, t, timer);
3119
3120         spin_lock_irqsave(&host->lock, flags);
3121
3122         if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3123                 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3124                        mmc_hostname(host->mmc));
3125                 sdhci_dumpregs(host);
3126
3127                 host->cmd->error = -ETIMEDOUT;
3128                 sdhci_finish_mrq(host, host->cmd->mrq);
3129         }
3130
3131         spin_unlock_irqrestore(&host->lock, flags);
3132 }
3133
3134 static void sdhci_timeout_data_timer(struct timer_list *t)
3135 {
3136         struct sdhci_host *host;
3137         unsigned long flags;
3138
3139         host = from_timer(host, t, data_timer);
3140
3141         spin_lock_irqsave(&host->lock, flags);
3142
3143         if (host->data || host->data_cmd ||
3144             (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3145                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3146                        mmc_hostname(host->mmc));
3147                 sdhci_dumpregs(host);
3148
3149                 if (host->data) {
3150                         host->data->error = -ETIMEDOUT;
3151                         __sdhci_finish_data(host, true);
3152                         queue_work(host->complete_wq, &host->complete_work);
3153                 } else if (host->data_cmd) {
3154                         host->data_cmd->error = -ETIMEDOUT;
3155                         sdhci_finish_mrq(host, host->data_cmd->mrq);
3156                 } else {
3157                         host->cmd->error = -ETIMEDOUT;
3158                         sdhci_finish_mrq(host, host->cmd->mrq);
3159                 }
3160         }
3161
3162         spin_unlock_irqrestore(&host->lock, flags);
3163 }
3164
3165 /*****************************************************************************\
3166  *                                                                           *
3167  * Interrupt handling                                                        *
3168  *                                                                           *
3169 \*****************************************************************************/
3170
3171 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3172 {
3173         /* Handle auto-CMD12 error */
3174         if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3175                 struct mmc_request *mrq = host->data_cmd->mrq;
3176                 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3177                 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3178                                    SDHCI_INT_DATA_TIMEOUT :
3179                                    SDHCI_INT_DATA_CRC;
3180
3181                 /* Treat auto-CMD12 error the same as data error */
3182                 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3183                         *intmask_p |= data_err_bit;
3184                         return;
3185                 }
3186         }
3187
3188         if (!host->cmd) {
3189                 /*
3190                  * SDHCI recovers from errors by resetting the cmd and data
3191                  * circuits.  Until that is done, there very well might be more
3192                  * interrupts, so ignore them in that case.
3193                  */
3194                 if (host->pending_reset)
3195                         return;
3196                 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3197                        mmc_hostname(host->mmc), (unsigned)intmask);
3198                 sdhci_dumpregs(host);
3199                 return;
3200         }
3201
3202         if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3203                        SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3204                 if (intmask & SDHCI_INT_TIMEOUT)
3205                         host->cmd->error = -ETIMEDOUT;
3206                 else
3207                         host->cmd->error = -EILSEQ;
3208
3209                 /* Treat data command CRC error the same as data CRC error */
3210                 if (host->cmd->data &&
3211                     (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3212                      SDHCI_INT_CRC) {
3213                         host->cmd = NULL;
3214                         *intmask_p |= SDHCI_INT_DATA_CRC;
3215                         return;
3216                 }
3217
3218                 __sdhci_finish_mrq(host, host->cmd->mrq);
3219                 return;
3220         }
3221
3222         /* Handle auto-CMD23 error */
3223         if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3224                 struct mmc_request *mrq = host->cmd->mrq;
3225                 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3226                 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3227                           -ETIMEDOUT :
3228                           -EILSEQ;
3229
3230                 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3231                         mrq->sbc->error = err;
3232                         __sdhci_finish_mrq(host, mrq);
3233                         return;
3234                 }
3235         }
3236
3237         if (intmask & SDHCI_INT_RESPONSE)
3238                 sdhci_finish_command(host);
3239 }
3240
3241 static void sdhci_adma_show_error(struct sdhci_host *host)
3242 {
3243         void *desc = host->adma_table;
3244         dma_addr_t dma = host->adma_addr;
3245
3246         sdhci_dumpregs(host);
3247
3248         while (true) {
3249                 struct sdhci_adma2_64_desc *dma_desc = desc;
3250
3251                 if (host->flags & SDHCI_USE_64_BIT_DMA)
3252                         SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3253                             (unsigned long long)dma,
3254                             le32_to_cpu(dma_desc->addr_hi),
3255                             le32_to_cpu(dma_desc->addr_lo),
3256                             le16_to_cpu(dma_desc->len),
3257                             le16_to_cpu(dma_desc->cmd));
3258                 else
3259                         SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3260                             (unsigned long long)dma,
3261                             le32_to_cpu(dma_desc->addr_lo),
3262                             le16_to_cpu(dma_desc->len),
3263                             le16_to_cpu(dma_desc->cmd));
3264
3265                 desc += host->desc_sz;
3266                 dma += host->desc_sz;
3267
3268                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3269                         break;
3270         }
3271 }
3272
3273 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3274 {
3275         u32 command;
3276
3277         /* CMD19 generates _only_ Buffer Read Ready interrupt */
3278         if (intmask & SDHCI_INT_DATA_AVAIL) {
3279                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3280                 if (command == MMC_SEND_TUNING_BLOCK ||
3281                     command == MMC_SEND_TUNING_BLOCK_HS200) {
3282                         host->tuning_done = 1;
3283                         wake_up(&host->buf_ready_int);
3284                         return;
3285                 }
3286         }
3287
3288         if (!host->data) {
3289                 struct mmc_command *data_cmd = host->data_cmd;
3290
3291                 /*
3292                  * The "data complete" interrupt is also used to
3293                  * indicate that a busy state has ended. See comment
3294                  * above in sdhci_cmd_irq().
3295                  */
3296                 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3297                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3298                                 host->data_cmd = NULL;
3299                                 data_cmd->error = -ETIMEDOUT;
3300                                 __sdhci_finish_mrq(host, data_cmd->mrq);
3301                                 return;
3302                         }
3303                         if (intmask & SDHCI_INT_DATA_END) {
3304                                 host->data_cmd = NULL;
3305                                 /*
3306                                  * Some cards handle busy-end interrupt
3307                                  * before the command completed, so make
3308                                  * sure we do things in the proper order.
3309                                  */
3310                                 if (host->cmd == data_cmd)
3311                                         return;
3312
3313                                 __sdhci_finish_mrq(host, data_cmd->mrq);
3314                                 return;
3315                         }
3316                 }
3317
3318                 /*
3319                  * SDHCI recovers from errors by resetting the cmd and data
3320                  * circuits. Until that is done, there very well might be more
3321                  * interrupts, so ignore them in that case.
3322                  */
3323                 if (host->pending_reset)
3324                         return;
3325
3326                 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3327                        mmc_hostname(host->mmc), (unsigned)intmask);
3328                 sdhci_dumpregs(host);
3329
3330                 return;
3331         }
3332
3333         if (intmask & SDHCI_INT_DATA_TIMEOUT)
3334                 host->data->error = -ETIMEDOUT;
3335         else if (intmask & SDHCI_INT_DATA_END_BIT)
3336                 host->data->error = -EILSEQ;
3337         else if ((intmask & SDHCI_INT_DATA_CRC) &&
3338                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3339                         != MMC_BUS_TEST_R)
3340                 host->data->error = -EILSEQ;
3341         else if (intmask & SDHCI_INT_ADMA_ERROR) {
3342                 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3343                        intmask);
3344                 sdhci_adma_show_error(host);
3345                 host->data->error = -EIO;
3346                 if (host->ops->adma_workaround)
3347                         host->ops->adma_workaround(host, intmask);
3348         }
3349
3350         if (host->data->error)
3351                 sdhci_finish_data(host);
3352         else {
3353                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3354                         sdhci_transfer_pio(host);
3355
3356                 /*
3357                  * We currently don't do anything fancy with DMA
3358                  * boundaries, but as we can't disable the feature
3359                  * we need to at least restart the transfer.
3360                  *
3361                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3362                  * should return a valid address to continue from, but as
3363                  * some controllers are faulty, don't trust them.
3364                  */
3365                 if (intmask & SDHCI_INT_DMA_END) {
3366                         dma_addr_t dmastart, dmanow;
3367
3368                         dmastart = sdhci_sdma_address(host);
3369                         dmanow = dmastart + host->data->bytes_xfered;
3370                         /*
3371                          * Force update to the next DMA block boundary.
3372                          */
3373                         dmanow = (dmanow &
3374                                 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3375                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
3376                         host->data->bytes_xfered = dmanow - dmastart;
3377                         DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3378                             &dmastart, host->data->bytes_xfered, &dmanow);
3379                         sdhci_set_sdma_addr(host, dmanow);
3380                 }
3381
3382                 if (intmask & SDHCI_INT_DATA_END) {
3383                         if (host->cmd == host->data_cmd) {
3384                                 /*
3385                                  * Data managed to finish before the
3386                                  * command completed. Make sure we do
3387                                  * things in the proper order.
3388                                  */
3389                                 host->data_early = 1;
3390                         } else {
3391                                 sdhci_finish_data(host);
3392                         }
3393                 }
3394         }
3395 }
3396
3397 static inline bool sdhci_defer_done(struct sdhci_host *host,
3398                                     struct mmc_request *mrq)
3399 {
3400         struct mmc_data *data = mrq->data;
3401
3402         return host->pending_reset || host->always_defer_done ||
3403                ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3404                 data->host_cookie == COOKIE_MAPPED);
3405 }
3406
3407 static irqreturn_t sdhci_irq(int irq, void *dev_id)
3408 {
3409         struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3410         irqreturn_t result = IRQ_NONE;
3411         struct sdhci_host *host = dev_id;
3412         u32 intmask, mask, unexpected = 0;
3413         int max_loops = 16;
3414         int i;
3415
3416         spin_lock(&host->lock);
3417
3418         if (host->runtime_suspended) {
3419                 spin_unlock(&host->lock);
3420                 return IRQ_NONE;
3421         }
3422
3423         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3424         if (!intmask || intmask == 0xffffffff) {
3425                 result = IRQ_NONE;
3426                 goto out;
3427         }
3428
3429         do {
3430                 DBG("IRQ status 0x%08x\n", intmask);
3431
3432                 if (host->ops->irq) {
3433                         intmask = host->ops->irq(host, intmask);
3434                         if (!intmask)
3435                                 goto cont;
3436                 }
3437
3438                 /* Clear selected interrupts. */
3439                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3440                                   SDHCI_INT_BUS_POWER);
3441                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3442
3443                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3444                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3445                                       SDHCI_CARD_PRESENT;
3446
3447                         /*
3448                          * There is a observation on i.mx esdhc.  INSERT
3449                          * bit will be immediately set again when it gets
3450                          * cleared, if a card is inserted.  We have to mask
3451                          * the irq to prevent interrupt storm which will
3452                          * freeze the system.  And the REMOVE gets the
3453                          * same situation.
3454                          *
3455                          * More testing are needed here to ensure it works
3456                          * for other platforms though.
3457                          */
3458                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
3459                                        SDHCI_INT_CARD_REMOVE);
3460                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3461                                                SDHCI_INT_CARD_INSERT;
3462                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3463                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3464
3465                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3466                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3467
3468                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3469                                                        SDHCI_INT_CARD_REMOVE);
3470                         result = IRQ_WAKE_THREAD;
3471                 }
3472
3473                 if (intmask & SDHCI_INT_CMD_MASK)
3474                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3475
3476                 if (intmask & SDHCI_INT_DATA_MASK)
3477                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3478
3479                 if (intmask & SDHCI_INT_BUS_POWER)
3480                         pr_err("%s: Card is consuming too much power!\n",
3481                                 mmc_hostname(host->mmc));
3482
3483                 if (intmask & SDHCI_INT_RETUNE)
3484                         mmc_retune_needed(host->mmc);
3485
3486                 if ((intmask & SDHCI_INT_CARD_INT) &&
3487                     (host->ier & SDHCI_INT_CARD_INT)) {
3488                         sdhci_enable_sdio_irq_nolock(host, false);
3489                         sdio_signal_irq(host->mmc);
3490                 }
3491
3492                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3493                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3494                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3495                              SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3496
3497                 if (intmask) {
3498                         unexpected |= intmask;
3499                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3500                 }
3501 cont:
3502                 if (result == IRQ_NONE)
3503                         result = IRQ_HANDLED;
3504
3505                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3506         } while (intmask && --max_loops);
3507
3508         /* Determine if mrqs can be completed immediately */
3509         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3510                 struct mmc_request *mrq = host->mrqs_done[i];
3511
3512                 if (!mrq)
3513                         continue;
3514
3515                 if (sdhci_defer_done(host, mrq)) {
3516                         result = IRQ_WAKE_THREAD;
3517                 } else {
3518                         mrqs_done[i] = mrq;
3519                         host->mrqs_done[i] = NULL;
3520                 }
3521         }
3522 out:
3523         if (host->deferred_cmd)
3524                 result = IRQ_WAKE_THREAD;
3525
3526         spin_unlock(&host->lock);
3527
3528         /* Process mrqs ready for immediate completion */
3529         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3530                 if (!mrqs_done[i])
3531                         continue;
3532
3533                 if (host->ops->request_done)
3534                         host->ops->request_done(host, mrqs_done[i]);
3535                 else
3536                         mmc_request_done(host->mmc, mrqs_done[i]);
3537         }
3538
3539         if (unexpected) {
3540                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3541                            mmc_hostname(host->mmc), unexpected);
3542                 sdhci_dumpregs(host);
3543         }
3544
3545         return result;
3546 }
3547
3548 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3549 {
3550         struct sdhci_host *host = dev_id;
3551         struct mmc_command *cmd;
3552         unsigned long flags;
3553         u32 isr;
3554
3555         while (!sdhci_request_done(host))
3556                 ;
3557
3558         spin_lock_irqsave(&host->lock, flags);
3559
3560         isr = host->thread_isr;
3561         host->thread_isr = 0;
3562
3563         cmd = host->deferred_cmd;
3564         if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3565                 sdhci_finish_mrq(host, cmd->mrq);
3566
3567         spin_unlock_irqrestore(&host->lock, flags);
3568
3569         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3570                 struct mmc_host *mmc = host->mmc;
3571
3572                 mmc->ops->card_event(mmc);
3573                 mmc_detect_change(mmc, msecs_to_jiffies(200));
3574         }
3575
3576         return IRQ_HANDLED;
3577 }
3578
3579 /*****************************************************************************\
3580  *                                                                           *
3581  * Suspend/resume                                                            *
3582  *                                                                           *
3583 \*****************************************************************************/
3584
3585 #ifdef CONFIG_PM
3586
3587 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3588 {
3589         return mmc_card_is_removable(host->mmc) &&
3590                !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3591                !mmc_can_gpio_cd(host->mmc);
3592 }
3593
3594 /*
3595  * To enable wakeup events, the corresponding events have to be enabled in
3596  * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3597  * Table' in the SD Host Controller Standard Specification.
3598  * It is useless to restore SDHCI_INT_ENABLE state in
3599  * sdhci_disable_irq_wakeups() since it will be set by
3600  * sdhci_enable_card_detection() or sdhci_init().
3601  */
3602 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3603 {
3604         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3605                   SDHCI_WAKE_ON_INT;
3606         u32 irq_val = 0;
3607         u8 wake_val = 0;
3608         u8 val;
3609
3610         if (sdhci_cd_irq_can_wakeup(host)) {
3611                 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3612                 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3613         }
3614
3615         if (mmc_card_wake_sdio_irq(host->mmc)) {
3616                 wake_val |= SDHCI_WAKE_ON_INT;
3617                 irq_val |= SDHCI_INT_CARD_INT;
3618         }
3619
3620         if (!irq_val)
3621                 return false;
3622
3623         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3624         val &= ~mask;
3625         val |= wake_val;
3626         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3627
3628         sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3629
3630         host->irq_wake_enabled = !enable_irq_wake(host->irq);
3631
3632         return host->irq_wake_enabled;
3633 }
3634
3635 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3636 {
3637         u8 val;
3638         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3639                         | SDHCI_WAKE_ON_INT;
3640
3641         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3642         val &= ~mask;
3643         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3644
3645         disable_irq_wake(host->irq);
3646
3647         host->irq_wake_enabled = false;
3648 }
3649
3650 int sdhci_suspend_host(struct sdhci_host *host)
3651 {
3652         sdhci_disable_card_detection(host);
3653
3654         mmc_retune_timer_stop(host->mmc);
3655
3656         if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3657             !sdhci_enable_irq_wakeups(host)) {
3658                 host->ier = 0;
3659                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3660                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3661                 free_irq(host->irq, host);
3662         }
3663
3664         return 0;
3665 }
3666
3667 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3668
3669 int sdhci_resume_host(struct sdhci_host *host)
3670 {
3671         struct mmc_host *mmc = host->mmc;
3672         int ret = 0;
3673
3674         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3675                 if (host->ops->enable_dma)
3676                         host->ops->enable_dma(host);
3677         }
3678
3679         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3680             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3681                 /* Card keeps power but host controller does not */
3682                 sdhci_init(host, 0);
3683                 host->pwr = 0;
3684                 host->clock = 0;
3685                 mmc->ops->set_ios(mmc, &mmc->ios);
3686         } else {
3687                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3688         }
3689
3690         if (host->irq_wake_enabled) {
3691                 sdhci_disable_irq_wakeups(host);
3692         } else {
3693                 ret = request_threaded_irq(host->irq, sdhci_irq,
3694                                            sdhci_thread_irq, IRQF_SHARED,
3695                                            mmc_hostname(host->mmc), host);
3696                 if (ret)
3697                         return ret;
3698         }
3699
3700         sdhci_enable_card_detection(host);
3701
3702         return ret;
3703 }
3704
3705 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3706
3707 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3708 {
3709         unsigned long flags;
3710
3711         mmc_retune_timer_stop(host->mmc);
3712
3713         spin_lock_irqsave(&host->lock, flags);
3714         host->ier &= SDHCI_INT_CARD_INT;
3715         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3716         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3717         spin_unlock_irqrestore(&host->lock, flags);
3718
3719         synchronize_hardirq(host->irq);
3720
3721         spin_lock_irqsave(&host->lock, flags);
3722         host->runtime_suspended = true;
3723         spin_unlock_irqrestore(&host->lock, flags);
3724
3725         return 0;
3726 }
3727 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3728
3729 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3730 {
3731         struct mmc_host *mmc = host->mmc;
3732         unsigned long flags;
3733         int host_flags = host->flags;
3734
3735         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3736                 if (host->ops->enable_dma)
3737                         host->ops->enable_dma(host);
3738         }
3739
3740         sdhci_init(host, soft_reset);
3741
3742         if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3743             mmc->ios.power_mode != MMC_POWER_OFF) {
3744                 /* Force clock and power re-program */
3745                 host->pwr = 0;
3746                 host->clock = 0;
3747                 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3748                 mmc->ops->set_ios(mmc, &mmc->ios);
3749
3750                 if ((host_flags & SDHCI_PV_ENABLED) &&
3751                     !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3752                         spin_lock_irqsave(&host->lock, flags);
3753                         sdhci_enable_preset_value(host, true);
3754                         spin_unlock_irqrestore(&host->lock, flags);
3755                 }
3756
3757                 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3758                     mmc->ops->hs400_enhanced_strobe)
3759                         mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3760         }
3761
3762         spin_lock_irqsave(&host->lock, flags);
3763
3764         host->runtime_suspended = false;
3765
3766         /* Enable SDIO IRQ */
3767         if (sdio_irq_claimed(mmc))
3768                 sdhci_enable_sdio_irq_nolock(host, true);
3769
3770         /* Enable Card Detection */
3771         sdhci_enable_card_detection(host);
3772
3773         spin_unlock_irqrestore(&host->lock, flags);
3774
3775         return 0;
3776 }
3777 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3778
3779 #endif /* CONFIG_PM */
3780
3781 /*****************************************************************************\
3782  *                                                                           *
3783  * Command Queue Engine (CQE) helpers                                        *
3784  *                                                                           *
3785 \*****************************************************************************/
3786
3787 void sdhci_cqe_enable(struct mmc_host *mmc)
3788 {
3789         struct sdhci_host *host = mmc_priv(mmc);
3790         unsigned long flags;
3791         u8 ctrl;
3792
3793         spin_lock_irqsave(&host->lock, flags);
3794
3795         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3796         ctrl &= ~SDHCI_CTRL_DMA_MASK;
3797         /*
3798          * Host from V4.10 supports ADMA3 DMA type.
3799          * ADMA3 performs integrated descriptor which is more suitable
3800          * for cmd queuing to fetch both command and transfer descriptors.
3801          */
3802         if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3803                 ctrl |= SDHCI_CTRL_ADMA3;
3804         else if (host->flags & SDHCI_USE_64_BIT_DMA)
3805                 ctrl |= SDHCI_CTRL_ADMA64;
3806         else
3807                 ctrl |= SDHCI_CTRL_ADMA32;
3808         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3809
3810         sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3811                      SDHCI_BLOCK_SIZE);
3812
3813         /* Set maximum timeout */
3814         sdhci_set_timeout(host, NULL);
3815
3816         host->ier = host->cqe_ier;
3817
3818         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3819         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3820
3821         host->cqe_on = true;
3822
3823         pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3824                  mmc_hostname(mmc), host->ier,
3825                  sdhci_readl(host, SDHCI_INT_STATUS));
3826
3827         spin_unlock_irqrestore(&host->lock, flags);
3828 }
3829 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3830
3831 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3832 {
3833         struct sdhci_host *host = mmc_priv(mmc);
3834         unsigned long flags;
3835
3836         spin_lock_irqsave(&host->lock, flags);
3837
3838         sdhci_set_default_irqs(host);
3839
3840         host->cqe_on = false;
3841
3842         if (recovery) {
3843                 sdhci_do_reset(host, SDHCI_RESET_CMD);
3844                 sdhci_do_reset(host, SDHCI_RESET_DATA);
3845         }
3846
3847         pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3848                  mmc_hostname(mmc), host->ier,
3849                  sdhci_readl(host, SDHCI_INT_STATUS));
3850
3851         spin_unlock_irqrestore(&host->lock, flags);
3852 }
3853 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3854
3855 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3856                    int *data_error)
3857 {
3858         u32 mask;
3859
3860         if (!host->cqe_on)
3861                 return false;
3862
3863         if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3864                 *cmd_error = -EILSEQ;
3865         else if (intmask & SDHCI_INT_TIMEOUT)
3866                 *cmd_error = -ETIMEDOUT;
3867         else
3868                 *cmd_error = 0;
3869
3870         if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3871                 *data_error = -EILSEQ;
3872         else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3873                 *data_error = -ETIMEDOUT;
3874         else if (intmask & SDHCI_INT_ADMA_ERROR)
3875                 *data_error = -EIO;
3876         else
3877                 *data_error = 0;
3878
3879         /* Clear selected interrupts. */
3880         mask = intmask & host->cqe_ier;
3881         sdhci_writel(host, mask, SDHCI_INT_STATUS);
3882
3883         if (intmask & SDHCI_INT_BUS_POWER)
3884                 pr_err("%s: Card is consuming too much power!\n",
3885                        mmc_hostname(host->mmc));
3886
3887         intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3888         if (intmask) {
3889                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3890                 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3891                        mmc_hostname(host->mmc), intmask);
3892                 sdhci_dumpregs(host);
3893         }
3894
3895         return true;
3896 }
3897 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3898
3899 /*****************************************************************************\
3900  *                                                                           *
3901  * Device allocation/registration                                            *
3902  *                                                                           *
3903 \*****************************************************************************/
3904
3905 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3906         size_t priv_size)
3907 {
3908         struct mmc_host *mmc;
3909         struct sdhci_host *host;
3910
3911         WARN_ON(dev == NULL);
3912
3913         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3914         if (!mmc)
3915                 return ERR_PTR(-ENOMEM);
3916
3917         host = mmc_priv(mmc);
3918         host->mmc = mmc;
3919         host->mmc_host_ops = sdhci_ops;
3920         mmc->ops = &host->mmc_host_ops;
3921
3922         host->flags = SDHCI_SIGNALING_330;
3923
3924         host->cqe_ier     = SDHCI_CQE_INT_MASK;
3925         host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3926
3927         host->tuning_delay = -1;
3928         host->tuning_loop_count = MAX_TUNING_LOOP;
3929
3930         host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3931
3932         /*
3933          * The DMA table descriptor count is calculated as the maximum
3934          * number of segments times 2, to allow for an alignment
3935          * descriptor for each segment, plus 1 for a nop end descriptor.
3936          */
3937         host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3938
3939         return host;
3940 }
3941
3942 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3943
3944 static int sdhci_set_dma_mask(struct sdhci_host *host)
3945 {
3946         struct mmc_host *mmc = host->mmc;
3947         struct device *dev = mmc_dev(mmc);
3948         int ret = -EINVAL;
3949
3950         if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3951                 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3952
3953         /* Try 64-bit mask if hardware is capable  of it */
3954         if (host->flags & SDHCI_USE_64_BIT_DMA) {
3955                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3956                 if (ret) {
3957                         pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3958                                 mmc_hostname(mmc));
3959                         host->flags &= ~SDHCI_USE_64_BIT_DMA;
3960                 }
3961         }
3962
3963         /* 32-bit mask as default & fallback */
3964         if (ret) {
3965                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3966                 if (ret)
3967                         pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3968                                 mmc_hostname(mmc));
3969         }
3970
3971         return ret;
3972 }
3973
3974 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3975                        const u32 *caps, const u32 *caps1)
3976 {
3977         u16 v;
3978         u64 dt_caps_mask = 0;
3979         u64 dt_caps = 0;
3980
3981         if (host->read_caps)
3982                 return;
3983
3984         host->read_caps = true;
3985
3986         if (debug_quirks)
3987                 host->quirks = debug_quirks;
3988
3989         if (debug_quirks2)
3990                 host->quirks2 = debug_quirks2;
3991
3992         sdhci_do_reset(host, SDHCI_RESET_ALL);
3993
3994         if (host->v4_mode)
3995                 sdhci_do_enable_v4_mode(host);
3996
3997         of_property_read_u64(mmc_dev(host->mmc)->of_node,
3998                              "sdhci-caps-mask", &dt_caps_mask);
3999         of_property_read_u64(mmc_dev(host->mmc)->of_node,
4000                              "sdhci-caps", &dt_caps);
4001
4002         v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4003         host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4004
4005         if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4006                 return;
4007
4008         if (caps) {
4009                 host->caps = *caps;
4010         } else {
4011                 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4012                 host->caps &= ~lower_32_bits(dt_caps_mask);
4013                 host->caps |= lower_32_bits(dt_caps);
4014         }
4015
4016         if (host->version < SDHCI_SPEC_300)
4017                 return;
4018
4019         if (caps1) {
4020                 host->caps1 = *caps1;
4021         } else {
4022                 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4023                 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4024                 host->caps1 |= upper_32_bits(dt_caps);
4025         }
4026 }
4027 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4028
4029 static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4030 {
4031         struct mmc_host *mmc = host->mmc;
4032         unsigned int max_blocks;
4033         unsigned int bounce_size;
4034         int ret;
4035
4036         /*
4037          * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4038          * has diminishing returns, this is probably because SD/MMC
4039          * cards are usually optimized to handle this size of requests.
4040          */
4041         bounce_size = SZ_64K;
4042         /*
4043          * Adjust downwards to maximum request size if this is less
4044          * than our segment size, else hammer down the maximum
4045          * request size to the maximum buffer size.
4046          */
4047         if (mmc->max_req_size < bounce_size)
4048                 bounce_size = mmc->max_req_size;
4049         max_blocks = bounce_size / 512;
4050
4051         /*
4052          * When we just support one segment, we can get significant
4053          * speedups by the help of a bounce buffer to group scattered
4054          * reads/writes together.
4055          */
4056         host->bounce_buffer = devm_kmalloc(mmc->parent,
4057                                            bounce_size,
4058                                            GFP_KERNEL);
4059         if (!host->bounce_buffer) {
4060                 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4061                        mmc_hostname(mmc),
4062                        bounce_size);
4063                 /*
4064                  * Exiting with zero here makes sure we proceed with
4065                  * mmc->max_segs == 1.
4066                  */
4067                 return;
4068         }
4069
4070         host->bounce_addr = dma_map_single(mmc->parent,
4071                                            host->bounce_buffer,
4072                                            bounce_size,
4073                                            DMA_BIDIRECTIONAL);
4074         ret = dma_mapping_error(mmc->parent, host->bounce_addr);
4075         if (ret)
4076                 /* Again fall back to max_segs == 1 */
4077                 return;
4078         host->bounce_buffer_size = bounce_size;
4079
4080         /* Lie about this since we're bouncing */
4081         mmc->max_segs = max_blocks;
4082         mmc->max_seg_size = bounce_size;
4083         mmc->max_req_size = bounce_size;
4084
4085         pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4086                 mmc_hostname(mmc), max_blocks, bounce_size);
4087 }
4088
4089 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4090 {
4091         /*
4092          * According to SD Host Controller spec v4.10, bit[27] added from
4093          * version 4.10 in Capabilities Register is used as 64-bit System
4094          * Address support for V4 mode.
4095          */
4096         if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4097                 return host->caps & SDHCI_CAN_64BIT_V4;
4098
4099         return host->caps & SDHCI_CAN_64BIT;
4100 }
4101
4102 int sdhci_setup_host(struct sdhci_host *host)
4103 {
4104         struct mmc_host *mmc;
4105         u32 max_current_caps;
4106         unsigned int ocr_avail;
4107         unsigned int override_timeout_clk;
4108         u32 max_clk;
4109         int ret = 0;
4110         bool enable_vqmmc = false;
4111
4112         WARN_ON(host == NULL);
4113         if (host == NULL)
4114                 return -EINVAL;
4115
4116         mmc = host->mmc;
4117
4118         /*
4119          * If there are external regulators, get them. Note this must be done
4120          * early before resetting the host and reading the capabilities so that
4121          * the host can take the appropriate action if regulators are not
4122          * available.
4123          */
4124         if (!mmc->supply.vqmmc) {
4125                 ret = mmc_regulator_get_supply(mmc);
4126                 if (ret)
4127                         return ret;
4128                 enable_vqmmc  = true;
4129         }
4130
4131         DBG("Version:   0x%08x | Present:  0x%08x\n",
4132             sdhci_readw(host, SDHCI_HOST_VERSION),
4133             sdhci_readl(host, SDHCI_PRESENT_STATE));
4134         DBG("Caps:      0x%08x | Caps_1:   0x%08x\n",
4135             sdhci_readl(host, SDHCI_CAPABILITIES),
4136             sdhci_readl(host, SDHCI_CAPABILITIES_1));
4137
4138         sdhci_read_caps(host);
4139
4140         override_timeout_clk = host->timeout_clk;
4141
4142         if (host->version > SDHCI_SPEC_420) {
4143                 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4144                        mmc_hostname(mmc), host->version);
4145         }
4146
4147         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4148                 host->flags |= SDHCI_USE_SDMA;
4149         else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4150                 DBG("Controller doesn't have SDMA capability\n");
4151         else
4152                 host->flags |= SDHCI_USE_SDMA;
4153
4154         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4155                 (host->flags & SDHCI_USE_SDMA)) {
4156                 DBG("Disabling DMA as it is marked broken\n");
4157                 host->flags &= ~SDHCI_USE_SDMA;
4158         }
4159
4160         if ((host->version >= SDHCI_SPEC_200) &&
4161                 (host->caps & SDHCI_CAN_DO_ADMA2))
4162                 host->flags |= SDHCI_USE_ADMA;
4163
4164         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4165                 (host->flags & SDHCI_USE_ADMA)) {
4166                 DBG("Disabling ADMA as it is marked broken\n");
4167                 host->flags &= ~SDHCI_USE_ADMA;
4168         }
4169
4170         if (sdhci_can_64bit_dma(host))
4171                 host->flags |= SDHCI_USE_64_BIT_DMA;
4172
4173         if (host->use_external_dma) {
4174                 ret = sdhci_external_dma_init(host);
4175                 if (ret == -EPROBE_DEFER)
4176                         goto unreg;
4177                 /*
4178                  * Fall back to use the DMA/PIO integrated in standard SDHCI
4179                  * instead of external DMA devices.
4180                  */
4181                 else if (ret)
4182                         sdhci_switch_external_dma(host, false);
4183                 /* Disable internal DMA sources */
4184                 else
4185                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4186         }
4187
4188         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4189                 if (host->ops->set_dma_mask)
4190                         ret = host->ops->set_dma_mask(host);
4191                 else
4192                         ret = sdhci_set_dma_mask(host);
4193
4194                 if (!ret && host->ops->enable_dma)
4195                         ret = host->ops->enable_dma(host);
4196
4197                 if (ret) {
4198                         pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4199                                 mmc_hostname(mmc));
4200                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4201
4202                         ret = 0;
4203                 }
4204         }
4205
4206         /* SDMA does not support 64-bit DMA if v4 mode not set */
4207         if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4208                 host->flags &= ~SDHCI_USE_SDMA;
4209
4210         if (host->flags & SDHCI_USE_ADMA) {
4211                 dma_addr_t dma;
4212                 void *buf;
4213
4214                 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4215                         host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4216                 else if (!host->alloc_desc_sz)
4217                         host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4218
4219                 host->desc_sz = host->alloc_desc_sz;
4220                 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4221
4222                 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4223                 /*
4224                  * Use zalloc to zero the reserved high 32-bits of 128-bit
4225                  * descriptors so that they never need to be written.
4226                  */
4227                 buf = dma_alloc_coherent(mmc_dev(mmc),
4228                                          host->align_buffer_sz + host->adma_table_sz,
4229                                          &dma, GFP_KERNEL);
4230                 if (!buf) {
4231                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4232                                 mmc_hostname(mmc));
4233                         host->flags &= ~SDHCI_USE_ADMA;
4234                 } else if ((dma + host->align_buffer_sz) &
4235                            (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4236                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4237                                 mmc_hostname(mmc));
4238                         host->flags &= ~SDHCI_USE_ADMA;
4239                         dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4240                                           host->adma_table_sz, buf, dma);
4241                 } else {
4242                         host->align_buffer = buf;
4243                         host->align_addr = dma;
4244
4245                         host->adma_table = buf + host->align_buffer_sz;
4246                         host->adma_addr = dma + host->align_buffer_sz;
4247                 }
4248         }
4249
4250         /*
4251          * If we use DMA, then it's up to the caller to set the DMA
4252          * mask, but PIO does not need the hw shim so we set a new
4253          * mask here in that case.
4254          */
4255         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4256                 host->dma_mask = DMA_BIT_MASK(64);
4257                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4258         }
4259
4260         if (host->version >= SDHCI_SPEC_300)
4261                 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4262         else
4263                 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4264
4265         host->max_clk *= 1000000;
4266         if (host->max_clk == 0 || host->quirks &
4267                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4268                 if (!host->ops->get_max_clock) {
4269                         pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4270                                mmc_hostname(mmc));
4271                         ret = -ENODEV;
4272                         goto undma;
4273                 }
4274                 host->max_clk = host->ops->get_max_clock(host);
4275         }
4276
4277         /*
4278          * In case of Host Controller v3.00, find out whether clock
4279          * multiplier is supported.
4280          */
4281         host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4282
4283         /*
4284          * In case the value in Clock Multiplier is 0, then programmable
4285          * clock mode is not supported, otherwise the actual clock
4286          * multiplier is one more than the value of Clock Multiplier
4287          * in the Capabilities Register.
4288          */
4289         if (host->clk_mul)
4290                 host->clk_mul += 1;
4291
4292         /*
4293          * Set host parameters.
4294          */
4295         max_clk = host->max_clk;
4296
4297         if (host->ops->get_min_clock)
4298                 mmc->f_min = host->ops->get_min_clock(host);
4299         else if (host->version >= SDHCI_SPEC_300) {
4300                 if (host->clk_mul)
4301                         max_clk = host->max_clk * host->clk_mul;
4302                 /*
4303                  * Divided Clock Mode minimum clock rate is always less than
4304                  * Programmable Clock Mode minimum clock rate.
4305                  */
4306                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4307         } else
4308                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4309
4310         if (!mmc->f_max || mmc->f_max > max_clk)
4311                 mmc->f_max = max_clk;
4312
4313         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4314                 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4315
4316                 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4317                         host->timeout_clk *= 1000;
4318
4319                 if (host->timeout_clk == 0) {
4320                         if (!host->ops->get_timeout_clock) {
4321                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4322                                         mmc_hostname(mmc));
4323                                 ret = -ENODEV;
4324                                 goto undma;
4325                         }
4326
4327                         host->timeout_clk =
4328                                 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4329                                              1000);
4330                 }
4331
4332                 if (override_timeout_clk)
4333                         host->timeout_clk = override_timeout_clk;
4334
4335                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4336                         host->ops->get_max_timeout_count(host) : 1 << 27;
4337                 mmc->max_busy_timeout /= host->timeout_clk;
4338         }
4339
4340         if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4341             !host->ops->get_max_timeout_count)
4342                 mmc->max_busy_timeout = 0;
4343
4344         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4345         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4346
4347         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4348                 host->flags |= SDHCI_AUTO_CMD12;
4349
4350         /*
4351          * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4352          * For v4 mode, SDMA may use Auto-CMD23 as well.
4353          */
4354         if ((host->version >= SDHCI_SPEC_300) &&
4355             ((host->flags & SDHCI_USE_ADMA) ||
4356              !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4357              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4358                 host->flags |= SDHCI_AUTO_CMD23;
4359                 DBG("Auto-CMD23 available\n");
4360         } else {
4361                 DBG("Auto-CMD23 unavailable\n");
4362         }
4363
4364         /*
4365          * A controller may support 8-bit width, but the board itself
4366          * might not have the pins brought out.  Boards that support
4367          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4368          * their platform code before calling sdhci_add_host(), and we
4369          * won't assume 8-bit width for hosts without that CAP.
4370          */
4371         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4372                 mmc->caps |= MMC_CAP_4_BIT_DATA;
4373
4374         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4375                 mmc->caps &= ~MMC_CAP_CMD23;
4376
4377         if (host->caps & SDHCI_CAN_DO_HISPD)
4378                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4379
4380         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4381             mmc_card_is_removable(mmc) &&
4382             mmc_gpio_get_cd(host->mmc) < 0)
4383                 mmc->caps |= MMC_CAP_NEEDS_POLL;
4384
4385         if (!IS_ERR(mmc->supply.vqmmc)) {
4386                 if (enable_vqmmc) {
4387                         ret = regulator_enable(mmc->supply.vqmmc);
4388                         host->sdhci_core_to_disable_vqmmc = !ret;
4389                 }
4390
4391                 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4392                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4393                                                     1950000))
4394                         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4395                                          SDHCI_SUPPORT_SDR50 |
4396                                          SDHCI_SUPPORT_DDR50);
4397
4398                 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4399                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4400                                                     3600000))
4401                         host->flags &= ~SDHCI_SIGNALING_330;
4402
4403                 if (ret) {
4404                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4405                                 mmc_hostname(mmc), ret);
4406                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4407                 }
4408
4409         }
4410
4411         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4412                 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4413                                  SDHCI_SUPPORT_DDR50);
4414                 /*
4415                  * The SDHCI controller in a SoC might support HS200/HS400
4416                  * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4417                  * but if the board is modeled such that the IO lines are not
4418                  * connected to 1.8v then HS200/HS400 cannot be supported.
4419                  * Disable HS200/HS400 if the board does not have 1.8v connected
4420                  * to the IO lines. (Applicable for other modes in 1.8v)
4421                  */
4422                 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4423                 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4424         }
4425
4426         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4427         if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4428                            SDHCI_SUPPORT_DDR50))
4429                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4430
4431         /* SDR104 supports also implies SDR50 support */
4432         if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4433                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4434                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4435                  * field can be promoted to support HS200.
4436                  */
4437                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4438                         mmc->caps2 |= MMC_CAP2_HS200;
4439         } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4440                 mmc->caps |= MMC_CAP_UHS_SDR50;
4441         }
4442
4443         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4444             (host->caps1 & SDHCI_SUPPORT_HS400))
4445                 mmc->caps2 |= MMC_CAP2_HS400;
4446
4447         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4448             (IS_ERR(mmc->supply.vqmmc) ||
4449              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4450                                              1300000)))
4451                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4452
4453         if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4454             !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4455                 mmc->caps |= MMC_CAP_UHS_DDR50;
4456
4457         /* Does the host need tuning for SDR50? */
4458         if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4459                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4460
4461         /* Driver Type(s) (A, C, D) supported by the host */
4462         if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4463                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4464         if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4465                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4466         if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4467                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4468
4469         /* Initial value for re-tuning timer count */
4470         host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4471                                        host->caps1);
4472
4473         /*
4474          * In case Re-tuning Timer is not disabled, the actual value of
4475          * re-tuning timer will be 2 ^ (n - 1).
4476          */
4477         if (host->tuning_count)
4478                 host->tuning_count = 1 << (host->tuning_count - 1);
4479
4480         /* Re-tuning mode supported by the Host Controller */
4481         host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4482
4483         ocr_avail = 0;
4484
4485         /*
4486          * According to SD Host Controller spec v3.00, if the Host System
4487          * can afford more than 150mA, Host Driver should set XPC to 1. Also
4488          * the value is meaningful only if Voltage Support in the Capabilities
4489          * register is set. The actual current value is 4 times the register
4490          * value.
4491          */
4492         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4493         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4494                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4495                 if (curr > 0) {
4496
4497                         /* convert to SDHCI_MAX_CURRENT format */
4498                         curr = curr/1000;  /* convert to mA */
4499                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4500
4501                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4502                         max_current_caps =
4503                                 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4504                                 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4505                                 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4506                 }
4507         }
4508
4509         if (host->caps & SDHCI_CAN_VDD_330) {
4510                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4511
4512                 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4513                                                  max_current_caps) *
4514                                                 SDHCI_MAX_CURRENT_MULTIPLIER;
4515         }
4516         if (host->caps & SDHCI_CAN_VDD_300) {
4517                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4518
4519                 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4520                                                  max_current_caps) *
4521                                                 SDHCI_MAX_CURRENT_MULTIPLIER;
4522         }
4523         if (host->caps & SDHCI_CAN_VDD_180) {
4524                 ocr_avail |= MMC_VDD_165_195;
4525
4526                 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4527                                                  max_current_caps) *
4528                                                 SDHCI_MAX_CURRENT_MULTIPLIER;
4529         }
4530
4531         /* If OCR set by host, use it instead. */
4532         if (host->ocr_mask)
4533                 ocr_avail = host->ocr_mask;
4534
4535         /* If OCR set by external regulators, give it highest prio. */
4536         if (mmc->ocr_avail)
4537                 ocr_avail = mmc->ocr_avail;
4538
4539         mmc->ocr_avail = ocr_avail;
4540         mmc->ocr_avail_sdio = ocr_avail;
4541         if (host->ocr_avail_sdio)
4542                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4543         mmc->ocr_avail_sd = ocr_avail;
4544         if (host->ocr_avail_sd)
4545                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4546         else /* normal SD controllers don't support 1.8V */
4547                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4548         mmc->ocr_avail_mmc = ocr_avail;
4549         if (host->ocr_avail_mmc)
4550                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4551
4552         if (mmc->ocr_avail == 0) {
4553                 pr_err("%s: Hardware doesn't report any support voltages.\n",
4554                        mmc_hostname(mmc));
4555                 ret = -ENODEV;
4556                 goto unreg;
4557         }
4558
4559         if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4560                           MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4561                           MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4562             (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4563                 host->flags |= SDHCI_SIGNALING_180;
4564
4565         if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4566                 host->flags |= SDHCI_SIGNALING_120;
4567
4568         spin_lock_init(&host->lock);
4569
4570         /*
4571          * Maximum number of sectors in one transfer. Limited by SDMA boundary
4572          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4573          * is less anyway.
4574          */
4575         mmc->max_req_size = 524288;
4576
4577         /*
4578          * Maximum number of segments. Depends on if the hardware
4579          * can do scatter/gather or not.
4580          */
4581         if (host->flags & SDHCI_USE_ADMA) {
4582                 mmc->max_segs = SDHCI_MAX_SEGS;
4583         } else if (host->flags & SDHCI_USE_SDMA) {
4584                 mmc->max_segs = 1;
4585                 if (swiotlb_max_segment()) {
4586                         unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4587                                                 IO_TLB_SEGSIZE;
4588                         mmc->max_req_size = min(mmc->max_req_size,
4589                                                 max_req_size);
4590                 }
4591         } else { /* PIO */
4592                 mmc->max_segs = SDHCI_MAX_SEGS;
4593         }
4594
4595         /*
4596          * Maximum segment size. Could be one segment with the maximum number
4597          * of bytes. When doing hardware scatter/gather, each entry cannot
4598          * be larger than 64 KiB though.
4599          */
4600         if (host->flags & SDHCI_USE_ADMA) {
4601                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4602                         mmc->max_seg_size = 65535;
4603                 else
4604                         mmc->max_seg_size = 65536;
4605         } else {
4606                 mmc->max_seg_size = mmc->max_req_size;
4607         }
4608
4609         /*
4610          * Maximum block size. This varies from controller to controller and
4611          * is specified in the capabilities register.
4612          */
4613         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4614                 mmc->max_blk_size = 2;
4615         } else {
4616                 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4617                                 SDHCI_MAX_BLOCK_SHIFT;
4618                 if (mmc->max_blk_size >= 3) {
4619                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4620                                 mmc_hostname(mmc));
4621                         mmc->max_blk_size = 0;
4622                 }
4623         }
4624
4625         mmc->max_blk_size = 512 << mmc->max_blk_size;
4626
4627         /*
4628          * Maximum block count.
4629          */
4630         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4631
4632         if (mmc->max_segs == 1)
4633                 /* This may alter mmc->*_blk_* parameters */
4634                 sdhci_allocate_bounce_buffer(host);
4635
4636         return 0;
4637
4638 unreg:
4639         if (host->sdhci_core_to_disable_vqmmc)
4640                 regulator_disable(mmc->supply.vqmmc);
4641 undma:
4642         if (host->align_buffer)
4643                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4644                                   host->adma_table_sz, host->align_buffer,
4645                                   host->align_addr);
4646         host->adma_table = NULL;
4647         host->align_buffer = NULL;
4648
4649         return ret;
4650 }
4651 EXPORT_SYMBOL_GPL(sdhci_setup_host);
4652
4653 void sdhci_cleanup_host(struct sdhci_host *host)
4654 {
4655         struct mmc_host *mmc = host->mmc;
4656
4657         if (host->sdhci_core_to_disable_vqmmc)
4658                 regulator_disable(mmc->supply.vqmmc);
4659
4660         if (host->align_buffer)
4661                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4662                                   host->adma_table_sz, host->align_buffer,
4663                                   host->align_addr);
4664
4665         if (host->use_external_dma)
4666                 sdhci_external_dma_release(host);
4667
4668         host->adma_table = NULL;
4669         host->align_buffer = NULL;
4670 }
4671 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4672
4673 int __sdhci_add_host(struct sdhci_host *host)
4674 {
4675         unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4676         struct mmc_host *mmc = host->mmc;
4677         int ret;
4678
4679         if ((mmc->caps2 & MMC_CAP2_CQE) &&
4680             (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4681                 mmc->caps2 &= ~MMC_CAP2_CQE;
4682                 mmc->cqe_ops = NULL;
4683         }
4684
4685         host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4686         if (!host->complete_wq)
4687                 return -ENOMEM;
4688
4689         INIT_WORK(&host->complete_work, sdhci_complete_work);
4690
4691         timer_setup(&host->timer, sdhci_timeout_timer, 0);
4692         timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4693
4694         init_waitqueue_head(&host->buf_ready_int);
4695
4696         sdhci_init(host, 0);
4697
4698         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4699                                    IRQF_SHARED, mmc_hostname(mmc), host);
4700         if (ret) {
4701                 pr_err("%s: Failed to request IRQ %d: %d\n",
4702                        mmc_hostname(mmc), host->irq, ret);
4703                 goto unwq;
4704         }
4705
4706         ret = sdhci_led_register(host);
4707         if (ret) {
4708                 pr_err("%s: Failed to register LED device: %d\n",
4709                        mmc_hostname(mmc), ret);
4710                 goto unirq;
4711         }
4712
4713         ret = mmc_add_host(mmc);
4714         if (ret)
4715                 goto unled;
4716
4717         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4718                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4719                 host->use_external_dma ? "External DMA" :
4720                 (host->flags & SDHCI_USE_ADMA) ?
4721                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4722                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4723
4724         sdhci_enable_card_detection(host);
4725
4726         return 0;
4727
4728 unled:
4729         sdhci_led_unregister(host);
4730 unirq:
4731         sdhci_do_reset(host, SDHCI_RESET_ALL);
4732         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4733         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4734         free_irq(host->irq, host);
4735 unwq:
4736         destroy_workqueue(host->complete_wq);
4737
4738         return ret;
4739 }
4740 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4741
4742 int sdhci_add_host(struct sdhci_host *host)
4743 {
4744         int ret;
4745
4746         ret = sdhci_setup_host(host);
4747         if (ret)
4748                 return ret;
4749
4750         ret = __sdhci_add_host(host);
4751         if (ret)
4752                 goto cleanup;
4753
4754         return 0;
4755
4756 cleanup:
4757         sdhci_cleanup_host(host);
4758
4759         return ret;
4760 }
4761 EXPORT_SYMBOL_GPL(sdhci_add_host);
4762
4763 void sdhci_remove_host(struct sdhci_host *host, int dead)
4764 {
4765         struct mmc_host *mmc = host->mmc;
4766         unsigned long flags;
4767
4768         if (dead) {
4769                 spin_lock_irqsave(&host->lock, flags);
4770
4771                 host->flags |= SDHCI_DEVICE_DEAD;
4772
4773                 if (sdhci_has_requests(host)) {
4774                         pr_err("%s: Controller removed during "
4775                                 " transfer!\n", mmc_hostname(mmc));
4776                         sdhci_error_out_mrqs(host, -ENOMEDIUM);
4777                 }
4778
4779                 spin_unlock_irqrestore(&host->lock, flags);
4780         }
4781
4782         sdhci_disable_card_detection(host);
4783
4784         mmc_remove_host(mmc);
4785
4786         sdhci_led_unregister(host);
4787
4788         if (!dead)
4789                 sdhci_do_reset(host, SDHCI_RESET_ALL);
4790
4791         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4792         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4793         free_irq(host->irq, host);
4794
4795         del_timer_sync(&host->timer);
4796         del_timer_sync(&host->data_timer);
4797
4798         destroy_workqueue(host->complete_wq);
4799
4800         if (host->sdhci_core_to_disable_vqmmc)
4801                 regulator_disable(mmc->supply.vqmmc);
4802
4803         if (host->align_buffer)
4804                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4805                                   host->adma_table_sz, host->align_buffer,
4806                                   host->align_addr);
4807
4808         if (host->use_external_dma)
4809                 sdhci_external_dma_release(host);
4810
4811         host->adma_table = NULL;
4812         host->align_buffer = NULL;
4813 }
4814
4815 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4816
4817 void sdhci_free_host(struct sdhci_host *host)
4818 {
4819         mmc_free_host(host->mmc);
4820 }
4821
4822 EXPORT_SYMBOL_GPL(sdhci_free_host);
4823
4824 /*****************************************************************************\
4825  *                                                                           *
4826  * Driver init/exit                                                          *
4827  *                                                                           *
4828 \*****************************************************************************/
4829
4830 static int __init sdhci_drv_init(void)
4831 {
4832         pr_info(DRIVER_NAME
4833                 ": Secure Digital Host Controller Interface driver\n");
4834         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4835
4836         return 0;
4837 }
4838
4839 static void __exit sdhci_drv_exit(void)
4840 {
4841 }
4842
4843 module_init(sdhci_drv_init);
4844 module_exit(sdhci_drv_exit);
4845
4846 module_param(debug_quirks, uint, 0444);
4847 module_param(debug_quirks2, uint, 0444);
4848
4849 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4850 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4851 MODULE_LICENSE("GPL");
4852
4853 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4854 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");