1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/spinlock.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/mmc-sdhci-s3c.h>
20 #include <linux/slab.h>
21 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <linux/module.h>
26 #include <linux/of_gpio.h>
28 #include <linux/pm_runtime.h>
30 #include <linux/mmc/host.h>
34 #define MAX_BUS_CLK (4)
36 #define S3C_SDHCI_CONTROL2 (0x80)
37 #define S3C_SDHCI_CONTROL3 (0x84)
38 #define S3C64XX_SDHCI_CONTROL4 (0x8C)
40 #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
41 #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
42 #define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
43 #define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
45 #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
46 #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
47 #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
49 #define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
50 #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
51 #define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
53 #define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
54 #define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
55 #define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
56 #define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
57 #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
59 #define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
60 #define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
61 #define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
62 #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
63 #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
64 #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
66 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
67 #define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
68 #define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
69 #define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
70 #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
71 #define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
72 #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
73 #define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
75 #define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
76 #define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
77 #define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
78 #define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
80 #define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
81 #define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
82 #define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
84 #define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
85 #define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
86 #define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
88 #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
89 #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
90 #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
92 #define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
93 #define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
94 #define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
96 #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
97 #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
98 #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
99 #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
100 #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
101 #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
103 #define S3C64XX_SDHCI_CONTROL4_BUSY (1)
106 * struct sdhci_s3c - S3C SDHCI instance
107 * @host: The SDHCI host created
108 * @pdev: The platform device we where created from.
109 * @ioarea: The resource created when we claimed the IO area.
110 * @pdata: The platform data for this controller.
111 * @cur_clk: The index of the current bus clock.
112 * @clk_io: The clock for the internal bus interface.
113 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
116 struct sdhci_host *host;
117 struct platform_device *pdev;
118 struct resource *ioarea;
119 struct s3c_sdhci_platdata *pdata;
125 struct clk *clk_bus[MAX_BUS_CLK];
126 unsigned long clk_rates[MAX_BUS_CLK];
132 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
133 * @sdhci_quirks: sdhci host specific quirks.
135 * Specifies platform specific configuration of sdhci controller.
136 * Note: A structure for driver specific platform data is used for future
137 * expansion of its usage.
139 struct sdhci_s3c_drv_data {
140 unsigned int sdhci_quirks;
144 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
146 return sdhci_priv(host);
150 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
151 * @host: The SDHCI host instance.
153 * Callback to return the maximum clock rate acheivable by the controller.
155 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
157 struct sdhci_s3c *ourhost = to_s3c(host);
158 unsigned long rate, max = 0;
161 for (src = 0; src < MAX_BUS_CLK; src++) {
162 rate = ourhost->clk_rates[src];
171 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
172 * @ourhost: Our SDHCI instance.
173 * @src: The source clock index.
174 * @wanted: The clock frequency wanted.
176 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
181 struct clk *clksrc = ourhost->clk_bus[src];
188 * If controller uses a non-standard clock division, find the best clock
189 * speed possible with selected clock source and skip the division.
191 if (ourhost->no_divider) {
192 spin_unlock_irq(&ourhost->host->lock);
193 rate = clk_round_rate(clksrc, wanted);
194 spin_lock_irq(&ourhost->host->lock);
195 return wanted - rate;
198 rate = ourhost->clk_rates[src];
200 for (shift = 0; shift <= 8; ++shift) {
201 if ((rate >> shift) <= wanted)
206 dev_dbg(&ourhost->pdev->dev,
207 "clk %d: rate %ld, min rate %lu > wanted %u\n",
208 src, rate, rate / 256, wanted);
212 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
213 src, rate, wanted, rate >> shift);
215 return wanted - (rate >> shift);
219 * sdhci_s3c_set_clock - callback on clock change
220 * @host: The SDHCI host being changed
221 * @clock: The clock rate being requested.
223 * When the card's clock is going to be changed, look at the new frequency
224 * and find the best clock source to go with it.
226 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
228 struct sdhci_s3c *ourhost = to_s3c(host);
229 unsigned int best = UINT_MAX;
235 host->mmc->actual_clock = 0;
237 /* don't bother if the clock is going off. */
239 sdhci_set_clock(host, clock);
243 for (src = 0; src < MAX_BUS_CLK; src++) {
244 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
251 dev_dbg(&ourhost->pdev->dev,
252 "selected source %d, clock %d, delta %d\n",
253 best_src, clock, best);
255 /* select the new clock source */
256 if (ourhost->cur_clk != best_src) {
257 struct clk *clk = ourhost->clk_bus[best_src];
259 clk_prepare_enable(clk);
260 if (ourhost->cur_clk >= 0)
261 clk_disable_unprepare(
262 ourhost->clk_bus[ourhost->cur_clk]);
264 ourhost->cur_clk = best_src;
265 host->max_clk = ourhost->clk_rates[best_src];
268 /* turn clock off to card before changing clock source */
269 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
271 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
272 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
273 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
274 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
276 /* reprogram default hardware configuration */
277 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
278 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
280 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
281 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
282 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
283 S3C_SDHCI_CTRL2_ENFBCLKRX |
284 S3C_SDHCI_CTRL2_DFCNT_NONE |
285 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
286 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
288 /* reconfigure the controller for new clock rate */
289 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
290 if (clock < 25 * 1000000)
291 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
292 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
294 sdhci_set_clock(host, clock);
298 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
299 * @host: The SDHCI host being queried
301 * To init mmc host properly a minimal clock value is needed. For high system
302 * bus clock's values the standard formula gives values out of allowed range.
303 * The clock still can be set to lower values, if clock source other then
304 * system bus is selected.
306 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
308 struct sdhci_s3c *ourhost = to_s3c(host);
309 unsigned long rate, min = ULONG_MAX;
312 for (src = 0; src < MAX_BUS_CLK; src++) {
313 rate = ourhost->clk_rates[src] / 256;
323 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
324 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
326 struct sdhci_s3c *ourhost = to_s3c(host);
327 unsigned long rate, max = 0;
330 for (src = 0; src < MAX_BUS_CLK; src++) {
333 clk = ourhost->clk_bus[src];
337 rate = clk_round_rate(clk, ULONG_MAX);
345 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
346 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
348 struct sdhci_s3c *ourhost = to_s3c(host);
349 unsigned long rate, min = ULONG_MAX;
352 for (src = 0; src < MAX_BUS_CLK; src++) {
355 clk = ourhost->clk_bus[src];
359 rate = clk_round_rate(clk, 0);
367 /* sdhci_cmu_set_clock - callback on clock change.*/
368 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
370 struct sdhci_s3c *ourhost = to_s3c(host);
371 struct device *dev = &ourhost->pdev->dev;
372 unsigned long timeout;
376 host->mmc->actual_clock = 0;
378 /* If the clock is going off, set to 0 at clock control register */
380 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
384 sdhci_s3c_set_clock(host, clock);
386 /* Reset SD Clock Enable */
387 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
388 clk &= ~SDHCI_CLOCK_CARD_EN;
389 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
391 spin_unlock_irq(&host->lock);
392 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
393 spin_lock_irq(&host->lock);
395 dev_err(dev, "%s: failed to set clock rate %uHz\n",
396 mmc_hostname(host->mmc), clock);
400 clk = SDHCI_CLOCK_INT_EN;
401 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
405 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
406 & SDHCI_CLOCK_INT_STABLE)) {
408 dev_err(dev, "%s: Internal clock never stabilised.\n",
409 mmc_hostname(host->mmc));
416 clk |= SDHCI_CLOCK_CARD_EN;
417 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
421 * sdhci_s3c_set_bus_width - support 8bit buswidth
422 * @host: The SDHCI host being queried
423 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
425 * We have 8-bit width support but is not a v3 controller.
426 * So we add platform_bus_width() and support 8bit width.
428 static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width)
432 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
435 case MMC_BUS_WIDTH_8:
436 ctrl |= SDHCI_CTRL_8BITBUS;
437 ctrl &= ~SDHCI_CTRL_4BITBUS;
439 case MMC_BUS_WIDTH_4:
440 ctrl |= SDHCI_CTRL_4BITBUS;
441 ctrl &= ~SDHCI_CTRL_8BITBUS;
444 ctrl &= ~SDHCI_CTRL_4BITBUS;
445 ctrl &= ~SDHCI_CTRL_8BITBUS;
449 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
452 static struct sdhci_ops sdhci_s3c_ops = {
453 .get_max_clock = sdhci_s3c_get_max_clk,
454 .set_clock = sdhci_s3c_set_clock,
455 .get_min_clock = sdhci_s3c_get_min_clock,
456 .set_bus_width = sdhci_s3c_set_bus_width,
457 .reset = sdhci_reset,
458 .set_uhs_signaling = sdhci_set_uhs_signaling,
462 static int sdhci_s3c_parse_dt(struct device *dev,
463 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
465 struct device_node *node = dev->of_node;
468 /* if the bus-width property is not specified, assume width as 1 */
469 if (of_property_read_u32(node, "bus-width", &max_width))
471 pdata->max_width = max_width;
473 /* get the card detection method */
474 if (of_get_property(node, "broken-cd", NULL)) {
475 pdata->cd_type = S3C_SDHCI_CD_NONE;
479 if (of_get_property(node, "non-removable", NULL)) {
480 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
484 if (of_get_named_gpio(node, "cd-gpios", 0))
487 /* assuming internal card detect that will be configured by pinctrl */
488 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
492 static int sdhci_s3c_parse_dt(struct device *dev,
493 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
499 static const struct of_device_id sdhci_s3c_dt_match[];
501 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
502 struct platform_device *pdev)
505 if (pdev->dev.of_node) {
506 const struct of_device_id *match;
507 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
508 return (struct sdhci_s3c_drv_data *)match->data;
511 return (struct sdhci_s3c_drv_data *)
512 platform_get_device_id(pdev)->driver_data;
515 static int sdhci_s3c_probe(struct platform_device *pdev)
517 struct s3c_sdhci_platdata *pdata;
518 struct sdhci_s3c_drv_data *drv_data;
519 struct device *dev = &pdev->dev;
520 struct sdhci_host *host;
521 struct sdhci_s3c *sc;
522 struct resource *res;
523 int ret, irq, ptr, clks;
525 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
526 dev_err(dev, "no device data specified\n");
530 irq = platform_get_irq(pdev, 0);
532 dev_err(dev, "no irq specified\n");
536 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
538 dev_err(dev, "sdhci_alloc_host() failed\n");
539 return PTR_ERR(host);
541 sc = sdhci_priv(host);
543 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
546 goto err_pdata_io_clk;
549 if (pdev->dev.of_node) {
550 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
552 goto err_pdata_io_clk;
554 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
555 sc->ext_cd_gpio = -1; /* invalid gpio number */
558 drv_data = sdhci_s3c_get_driver_data(pdev);
565 platform_set_drvdata(pdev, host);
567 sc->clk_io = devm_clk_get(dev, "hsmmc");
568 if (IS_ERR(sc->clk_io)) {
569 dev_err(dev, "failed to get io clock\n");
570 ret = PTR_ERR(sc->clk_io);
571 goto err_pdata_io_clk;
574 /* enable the local io clock and keep it running for the moment. */
575 clk_prepare_enable(sc->clk_io);
577 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
580 snprintf(name, 14, "mmc_busclk.%d", ptr);
581 sc->clk_bus[ptr] = devm_clk_get(dev, name);
582 if (IS_ERR(sc->clk_bus[ptr]))
586 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
588 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
589 ptr, name, sc->clk_rates[ptr]);
593 dev_err(dev, "failed to find any bus clocks\n");
598 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
599 host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
600 if (IS_ERR(host->ioaddr)) {
601 ret = PTR_ERR(host->ioaddr);
605 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
607 pdata->cfg_gpio(pdev, pdata->max_width);
609 host->hw_name = "samsung-hsmmc";
610 host->ops = &sdhci_s3c_ops;
615 /* Setup quirks for the controller */
616 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
617 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
619 host->quirks |= drv_data->sdhci_quirks;
620 sc->no_divider = drv_data->no_divider;
623 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
625 /* we currently see overruns on errors, so disable the SDMA
626 * support as well. */
627 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
629 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
631 /* It seems we do not get an DATA transfer complete on non-busy
632 * transfers, not sure if this is a problem with this specific
633 * SDHCI block, or a missing configuration that needs to be set. */
634 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
636 /* This host supports the Auto CMD12 */
637 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
639 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
640 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
642 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
643 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
644 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
646 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
647 host->mmc->caps = MMC_CAP_NONREMOVABLE;
649 switch (pdata->max_width) {
651 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
653 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
658 host->mmc->pm_caps |= pdata->pm_caps;
660 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
661 SDHCI_QUIRK_32BIT_DMA_SIZE);
663 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
664 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
667 * If controller does not have internal clock divider,
668 * we can use overriding functions instead of default.
670 if (sc->no_divider) {
671 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
672 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
673 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
676 /* It supports additional host capabilities if needed */
677 if (pdata->host_caps)
678 host->mmc->caps |= pdata->host_caps;
680 if (pdata->host_caps2)
681 host->mmc->caps2 |= pdata->host_caps2;
683 pm_runtime_enable(&pdev->dev);
684 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
685 pm_runtime_use_autosuspend(&pdev->dev);
686 pm_suspend_ignore_children(&pdev->dev, 1);
688 ret = mmc_of_parse(host->mmc);
692 ret = sdhci_add_host(host);
694 dev_err(dev, "sdhci_add_host() failed\n");
699 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
700 clk_disable_unprepare(sc->clk_io);
705 pm_runtime_disable(&pdev->dev);
708 clk_disable_unprepare(sc->clk_io);
711 sdhci_free_host(host);
716 static int sdhci_s3c_remove(struct platform_device *pdev)
718 struct sdhci_host *host = platform_get_drvdata(pdev);
719 struct sdhci_s3c *sc = sdhci_priv(host);
722 free_irq(sc->ext_cd_irq, sc);
725 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
726 clk_prepare_enable(sc->clk_io);
728 sdhci_remove_host(host, 1);
730 pm_runtime_dont_use_autosuspend(&pdev->dev);
731 pm_runtime_disable(&pdev->dev);
733 clk_disable_unprepare(sc->clk_io);
735 sdhci_free_host(host);
740 #ifdef CONFIG_PM_SLEEP
741 static int sdhci_s3c_suspend(struct device *dev)
743 struct sdhci_host *host = dev_get_drvdata(dev);
745 return sdhci_suspend_host(host);
748 static int sdhci_s3c_resume(struct device *dev)
750 struct sdhci_host *host = dev_get_drvdata(dev);
752 return sdhci_resume_host(host);
757 static int sdhci_s3c_runtime_suspend(struct device *dev)
759 struct sdhci_host *host = dev_get_drvdata(dev);
760 struct sdhci_s3c *ourhost = to_s3c(host);
761 struct clk *busclk = ourhost->clk_io;
764 ret = sdhci_runtime_suspend_host(host);
766 if (ourhost->cur_clk >= 0)
767 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
768 clk_disable_unprepare(busclk);
772 static int sdhci_s3c_runtime_resume(struct device *dev)
774 struct sdhci_host *host = dev_get_drvdata(dev);
775 struct sdhci_s3c *ourhost = to_s3c(host);
776 struct clk *busclk = ourhost->clk_io;
779 clk_prepare_enable(busclk);
780 if (ourhost->cur_clk >= 0)
781 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
782 ret = sdhci_runtime_resume_host(host);
787 static const struct dev_pm_ops sdhci_s3c_pmops = {
788 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
789 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
793 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
794 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
797 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
799 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
802 static const struct platform_device_id sdhci_s3c_driver_ids[] = {
805 .driver_data = (kernel_ulong_t)NULL,
807 .name = "exynos4-sdhci",
808 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
812 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
815 static const struct of_device_id sdhci_s3c_dt_match[] = {
816 { .compatible = "samsung,s3c6410-sdhci", },
817 { .compatible = "samsung,exynos4210-sdhci",
818 .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
821 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
824 static struct platform_driver sdhci_s3c_driver = {
825 .probe = sdhci_s3c_probe,
826 .remove = sdhci_s3c_remove,
827 .id_table = sdhci_s3c_driver_ids,
830 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
831 .pm = &sdhci_s3c_pmops,
835 module_platform_driver(sdhci_s3c_driver);
837 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
838 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
839 MODULE_LICENSE("GPL v2");
840 MODULE_ALIAS("platform:s3c-sdhci");