1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/clk.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
24 #include <linux/of_gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pinctrl/consumer.h>
29 #include <linux/mmc/host.h>
31 #include <plat/sdhci.h>
32 #include <plat/regs-sdhci.h>
36 #define MAX_BUS_CLK (4)
38 /* Number of gpio's used is max data bus width + command and clock lines */
39 #define NUM_GPIOS(x) (x + 2)
42 * struct sdhci_s3c - S3C SDHCI instance
43 * @host: The SDHCI host created
44 * @pdev: The platform device we where created from.
45 * @ioarea: The resource created when we claimed the IO area.
46 * @pdata: The platform data for this controller.
47 * @cur_clk: The index of the current bus clock.
48 * @gpios: List of gpio numbers parsed from device tree.
49 * @clk_io: The clock for the internal bus interface.
50 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
53 struct sdhci_host *host;
54 struct platform_device *pdev;
55 struct resource *ioarea;
56 struct s3c_sdhci_platdata *pdata;
61 struct pinctrl *pctrl;
64 struct clk *clk_bus[MAX_BUS_CLK];
68 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
69 * @sdhci_quirks: sdhci host specific quirks.
71 * Specifies platform specific configuration of sdhci controller.
72 * Note: A structure for driver specific platform data is used for future
73 * expansion of its usage.
75 struct sdhci_s3c_drv_data {
76 unsigned int sdhci_quirks;
79 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
81 return sdhci_priv(host);
85 * get_curclk - convert ctrl2 register to clock source number
86 * @ctrl2: Control2 register value.
88 static u32 get_curclk(u32 ctrl2)
90 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
91 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
96 static void sdhci_s3c_check_sclk(struct sdhci_host *host)
98 struct sdhci_s3c *ourhost = to_s3c(host);
99 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
101 if (get_curclk(tmp) != ourhost->cur_clk) {
102 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
104 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
105 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
106 writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2);
111 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
112 * @host: The SDHCI host instance.
114 * Callback to return the maximum clock rate acheivable by the controller.
116 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
118 struct sdhci_s3c *ourhost = to_s3c(host);
120 unsigned int rate, max;
123 /* note, a reset will reset the clock source */
125 sdhci_s3c_check_sclk(host);
127 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
128 busclk = ourhost->clk_bus[clk];
132 rate = clk_get_rate(busclk);
141 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
142 * @ourhost: Our SDHCI instance.
143 * @src: The source clock index.
144 * @wanted: The clock frequency wanted.
146 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
151 struct clk *clksrc = ourhost->clk_bus[src];
158 * If controller uses a non-standard clock division, find the best clock
159 * speed possible with selected clock source and skip the division.
161 if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
162 rate = clk_round_rate(clksrc, wanted);
163 return wanted - rate;
166 rate = clk_get_rate(clksrc);
168 for (div = 1; div < 256; div *= 2) {
169 if ((rate / div) <= wanted)
173 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
174 src, rate, wanted, rate / div);
176 return wanted - (rate / div);
180 * sdhci_s3c_set_clock - callback on clock change
181 * @host: The SDHCI host being changed
182 * @clock: The clock rate being requested.
184 * When the card's clock is going to be changed, look at the new frequency
185 * and find the best clock source to go with it.
187 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
189 struct sdhci_s3c *ourhost = to_s3c(host);
190 unsigned int best = UINT_MAX;
196 /* don't bother if the clock is going off. */
200 for (src = 0; src < MAX_BUS_CLK; src++) {
201 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
208 dev_dbg(&ourhost->pdev->dev,
209 "selected source %d, clock %d, delta %d\n",
210 best_src, clock, best);
212 /* select the new clock source */
213 if (ourhost->cur_clk != best_src) {
214 struct clk *clk = ourhost->clk_bus[best_src];
216 clk_prepare_enable(clk);
217 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
219 /* turn clock off to card before changing clock source */
220 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
222 ourhost->cur_clk = best_src;
223 host->max_clk = clk_get_rate(clk);
225 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
226 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
227 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
228 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
231 /* reprogram default hardware configuration */
232 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
233 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
235 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
236 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
237 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
238 S3C_SDHCI_CTRL2_ENFBCLKRX |
239 S3C_SDHCI_CTRL2_DFCNT_NONE |
240 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
241 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
243 /* reconfigure the controller for new clock rate */
244 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
245 if (clock < 25 * 1000000)
246 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
247 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
251 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
252 * @host: The SDHCI host being queried
254 * To init mmc host properly a minimal clock value is needed. For high system
255 * bus clock's values the standard formula gives values out of allowed range.
256 * The clock still can be set to lower values, if clock source other then
257 * system bus is selected.
259 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
261 struct sdhci_s3c *ourhost = to_s3c(host);
262 unsigned int delta, min = UINT_MAX;
265 for (src = 0; src < MAX_BUS_CLK; src++) {
266 delta = sdhci_s3c_consider_clock(ourhost, src, 0);
267 if (delta == UINT_MAX)
269 /* delta is a negative value in this case */
276 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
277 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
279 struct sdhci_s3c *ourhost = to_s3c(host);
281 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX);
284 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
285 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
287 struct sdhci_s3c *ourhost = to_s3c(host);
290 * initial clock can be in the frequency range of
291 * 100KHz-400KHz, so we set it as max value.
293 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000);
296 /* sdhci_cmu_set_clock - callback on clock change.*/
297 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
299 struct sdhci_s3c *ourhost = to_s3c(host);
300 struct device *dev = &ourhost->pdev->dev;
301 unsigned long timeout;
304 /* don't bother if the clock is going off */
308 sdhci_s3c_set_clock(host, clock);
310 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
314 clk = SDHCI_CLOCK_INT_EN;
315 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
319 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
320 & SDHCI_CLOCK_INT_STABLE)) {
322 dev_err(dev, "%s: Internal clock never stabilised.\n",
323 mmc_hostname(host->mmc));
330 clk |= SDHCI_CLOCK_CARD_EN;
331 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
335 * sdhci_s3c_platform_bus_width - support 8bit buswidth
336 * @host: The SDHCI host being queried
337 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
339 * We have 8-bit width support but is not a v3 controller.
340 * So we add platform_bus_width() and support 8bit width.
342 static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width)
346 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
349 case MMC_BUS_WIDTH_8:
350 ctrl |= SDHCI_CTRL_8BITBUS;
351 ctrl &= ~SDHCI_CTRL_4BITBUS;
353 case MMC_BUS_WIDTH_4:
354 ctrl |= SDHCI_CTRL_4BITBUS;
355 ctrl &= ~SDHCI_CTRL_8BITBUS;
358 ctrl &= ~SDHCI_CTRL_4BITBUS;
359 ctrl &= ~SDHCI_CTRL_8BITBUS;
363 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
368 static struct sdhci_ops sdhci_s3c_ops = {
369 .get_max_clock = sdhci_s3c_get_max_clk,
370 .set_clock = sdhci_s3c_set_clock,
371 .get_min_clock = sdhci_s3c_get_min_clock,
372 .platform_bus_width = sdhci_s3c_platform_bus_width,
375 static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
377 struct sdhci_host *host = platform_get_drvdata(dev);
378 #ifdef CONFIG_PM_RUNTIME
379 struct sdhci_s3c *sc = sdhci_priv(host);
384 spin_lock_irqsave(&host->lock, flags);
386 dev_dbg(&dev->dev, "card inserted.\n");
387 #ifdef CONFIG_PM_RUNTIME
388 clk_prepare_enable(sc->clk_io);
390 host->flags &= ~SDHCI_DEVICE_DEAD;
391 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
393 dev_dbg(&dev->dev, "card removed.\n");
394 host->flags |= SDHCI_DEVICE_DEAD;
395 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
396 #ifdef CONFIG_PM_RUNTIME
397 clk_disable_unprepare(sc->clk_io);
400 tasklet_schedule(&host->card_tasklet);
401 spin_unlock_irqrestore(&host->lock, flags);
405 static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id)
407 struct sdhci_s3c *sc = dev_id;
408 int status = gpio_get_value(sc->ext_cd_gpio);
409 if (sc->pdata->ext_cd_gpio_invert)
411 sdhci_s3c_notify_change(sc->pdev, status);
415 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
417 struct s3c_sdhci_platdata *pdata = sc->pdata;
418 struct device *dev = &sc->pdev->dev;
420 if (devm_gpio_request(dev, pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) {
421 sc->ext_cd_gpio = pdata->ext_cd_gpio;
422 sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
423 if (sc->ext_cd_irq &&
424 request_threaded_irq(sc->ext_cd_irq, NULL,
425 sdhci_s3c_gpio_card_detect_thread,
426 IRQF_TRIGGER_RISING |
427 IRQF_TRIGGER_FALLING |
429 dev_name(dev), sc) == 0) {
430 int status = gpio_get_value(sc->ext_cd_gpio);
431 if (pdata->ext_cd_gpio_invert)
433 sdhci_s3c_notify_change(sc->pdev, status);
435 dev_warn(dev, "cannot request irq for card detect\n");
439 dev_err(dev, "cannot request gpio for card detect\n");
444 static int sdhci_s3c_parse_dt(struct device *dev,
445 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
447 struct device_node *node = dev->of_node;
448 struct sdhci_s3c *ourhost = to_s3c(host);
452 /* if the bus-width property is not specified, assume width as 1 */
453 if (of_property_read_u32(node, "bus-width", &max_width))
455 pdata->max_width = max_width;
457 ourhost->gpios = devm_kzalloc(dev, NUM_GPIOS(pdata->max_width) *
458 sizeof(int), GFP_KERNEL);
462 /* get the card detection method */
463 if (of_get_property(node, "broken-cd", NULL)) {
464 pdata->cd_type = S3C_SDHCI_CD_NONE;
468 if (of_get_property(node, "non-removable", NULL)) {
469 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
473 gpio = of_get_named_gpio(node, "cd-gpios", 0);
474 if (gpio_is_valid(gpio)) {
475 pdata->cd_type = S3C_SDHCI_CD_GPIO;
477 } else if (gpio != -ENOENT) {
478 dev_err(dev, "invalid card detect gpio specified\n");
482 gpio = of_get_named_gpio(node, "samsung,cd-pinmux-gpio", 0);
483 if (gpio_is_valid(gpio)) {
484 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
486 } else if (gpio != -ENOENT) {
487 dev_err(dev, "invalid card detect gpio specified\n");
491 /* assuming internal card detect that will be configured by pinctrl */
492 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
496 if (pdata->cd_type == S3C_SDHCI_CD_GPIO) {
497 pdata->ext_cd_gpio = gpio;
498 ourhost->ext_cd_gpio = -1;
499 if (of_get_property(node, "cd-inverted", NULL))
500 pdata->ext_cd_gpio_invert = 1;
501 } else if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
502 ret = devm_gpio_request(dev, gpio, "sdhci-cd");
504 dev_err(dev, "card detect gpio request failed\n");
507 ourhost->ext_cd_gpio = gpio;
511 if (!IS_ERR(ourhost->pctrl))
514 /* get the gpios for command, clock and data lines */
515 for (cnt = 0; cnt < NUM_GPIOS(pdata->max_width); cnt++) {
516 gpio = of_get_gpio(node, cnt);
517 if (!gpio_is_valid(gpio)) {
518 dev_err(dev, "invalid gpio[%d]\n", cnt);
521 ourhost->gpios[cnt] = gpio;
524 for (cnt = 0; cnt < NUM_GPIOS(pdata->max_width); cnt++) {
525 ret = devm_gpio_request(dev, ourhost->gpios[cnt], "sdhci-gpio");
527 dev_err(dev, "gpio[%d] request failed\n", cnt);
535 static int sdhci_s3c_parse_dt(struct device *dev,
536 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
542 static const struct of_device_id sdhci_s3c_dt_match[];
544 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
545 struct platform_device *pdev)
548 if (pdev->dev.of_node) {
549 const struct of_device_id *match;
550 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
551 return (struct sdhci_s3c_drv_data *)match->data;
554 return (struct sdhci_s3c_drv_data *)
555 platform_get_device_id(pdev)->driver_data;
558 static int sdhci_s3c_probe(struct platform_device *pdev)
560 struct s3c_sdhci_platdata *pdata;
561 struct sdhci_s3c_drv_data *drv_data;
562 struct device *dev = &pdev->dev;
563 struct sdhci_host *host;
564 struct sdhci_s3c *sc;
565 struct resource *res;
566 int ret, irq, ptr, clks;
568 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
569 dev_err(dev, "no device data specified\n");
573 irq = platform_get_irq(pdev, 0);
575 dev_err(dev, "no irq specified\n");
579 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
581 dev_err(dev, "sdhci_alloc_host() failed\n");
582 return PTR_ERR(host);
584 sc = sdhci_priv(host);
586 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
589 goto err_pdata_io_clk;
592 sc->pctrl = devm_pinctrl_get_select_default(&pdev->dev);
594 if (pdev->dev.of_node) {
595 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
597 goto err_pdata_io_clk;
599 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
600 sc->ext_cd_gpio = -1; /* invalid gpio number */
603 drv_data = sdhci_s3c_get_driver_data(pdev);
609 platform_set_drvdata(pdev, host);
611 sc->clk_io = clk_get(dev, "hsmmc");
612 if (IS_ERR(sc->clk_io)) {
613 dev_err(dev, "failed to get io clock\n");
614 ret = PTR_ERR(sc->clk_io);
615 goto err_pdata_io_clk;
618 /* enable the local io clock and keep it running for the moment. */
619 clk_prepare_enable(sc->clk_io);
621 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
625 snprintf(name, 14, "mmc_busclk.%d", ptr);
626 clk = clk_get(dev, name);
631 sc->clk_bus[ptr] = clk;
634 * save current clock index to know which clock bus
635 * is used later in overriding functions.
639 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
640 ptr, name, clk_get_rate(clk));
644 dev_err(dev, "failed to find any bus clocks\n");
649 #ifndef CONFIG_PM_RUNTIME
650 clk_prepare_enable(sc->clk_bus[sc->cur_clk]);
653 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
654 host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
655 if (IS_ERR(host->ioaddr)) {
656 ret = PTR_ERR(host->ioaddr);
660 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
662 pdata->cfg_gpio(pdev, pdata->max_width);
664 host->hw_name = "samsung-hsmmc";
665 host->ops = &sdhci_s3c_ops;
669 /* Setup quirks for the controller */
670 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
671 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
673 host->quirks |= drv_data->sdhci_quirks;
675 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
677 /* we currently see overruns on errors, so disable the SDMA
678 * support as well. */
679 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
681 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
683 /* It seems we do not get an DATA transfer complete on non-busy
684 * transfers, not sure if this is a problem with this specific
685 * SDHCI block, or a missing configuration that needs to be set. */
686 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
688 /* This host supports the Auto CMD12 */
689 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
691 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
692 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
694 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
695 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
696 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
698 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
699 host->mmc->caps = MMC_CAP_NONREMOVABLE;
701 switch (pdata->max_width) {
703 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
705 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
710 host->mmc->pm_caps |= pdata->pm_caps;
712 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
713 SDHCI_QUIRK_32BIT_DMA_SIZE);
715 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
716 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
719 * If controller does not have internal clock divider,
720 * we can use overriding functions instead of default.
722 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
723 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
724 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
725 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
728 /* It supports additional host capabilities if needed */
729 if (pdata->host_caps)
730 host->mmc->caps |= pdata->host_caps;
732 if (pdata->host_caps2)
733 host->mmc->caps2 |= pdata->host_caps2;
735 pm_runtime_enable(&pdev->dev);
736 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
737 pm_runtime_use_autosuspend(&pdev->dev);
738 pm_suspend_ignore_children(&pdev->dev, 1);
740 ret = sdhci_add_host(host);
742 dev_err(dev, "sdhci_add_host() failed\n");
743 pm_runtime_forbid(&pdev->dev);
744 pm_runtime_get_noresume(&pdev->dev);
748 /* The following two methods of card detection might call
749 sdhci_s3c_notify_change() immediately, so they can be called
750 only after sdhci_add_host(). Setup errors are ignored. */
751 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
752 pdata->ext_cd_init(&sdhci_s3c_notify_change);
753 if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
754 gpio_is_valid(pdata->ext_cd_gpio))
755 sdhci_s3c_setup_card_detect_gpio(sc);
757 #ifdef CONFIG_PM_RUNTIME
758 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
759 clk_disable_unprepare(sc->clk_io);
764 #ifndef CONFIG_PM_RUNTIME
765 clk_disable_unprepare(sc->clk_bus[sc->cur_clk]);
767 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
768 if (sc->clk_bus[ptr]) {
769 clk_put(sc->clk_bus[ptr]);
774 clk_disable_unprepare(sc->clk_io);
778 sdhci_free_host(host);
783 static int sdhci_s3c_remove(struct platform_device *pdev)
785 struct sdhci_host *host = platform_get_drvdata(pdev);
786 struct sdhci_s3c *sc = sdhci_priv(host);
787 struct s3c_sdhci_platdata *pdata = sc->pdata;
790 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
791 pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
794 free_irq(sc->ext_cd_irq, sc);
796 #ifdef CONFIG_PM_RUNTIME
797 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
798 clk_prepare_enable(sc->clk_io);
800 sdhci_remove_host(host, 1);
802 pm_runtime_dont_use_autosuspend(&pdev->dev);
803 pm_runtime_disable(&pdev->dev);
805 #ifndef CONFIG_PM_RUNTIME
806 clk_disable_unprepare(sc->clk_bus[sc->cur_clk]);
808 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
809 if (sc->clk_bus[ptr]) {
810 clk_put(sc->clk_bus[ptr]);
813 clk_disable_unprepare(sc->clk_io);
816 sdhci_free_host(host);
817 platform_set_drvdata(pdev, NULL);
822 #ifdef CONFIG_PM_SLEEP
823 static int sdhci_s3c_suspend(struct device *dev)
825 struct sdhci_host *host = dev_get_drvdata(dev);
827 return sdhci_suspend_host(host);
830 static int sdhci_s3c_resume(struct device *dev)
832 struct sdhci_host *host = dev_get_drvdata(dev);
834 return sdhci_resume_host(host);
838 #ifdef CONFIG_PM_RUNTIME
839 static int sdhci_s3c_runtime_suspend(struct device *dev)
841 struct sdhci_host *host = dev_get_drvdata(dev);
842 struct sdhci_s3c *ourhost = to_s3c(host);
843 struct clk *busclk = ourhost->clk_io;
846 ret = sdhci_runtime_suspend_host(host);
848 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
849 clk_disable_unprepare(busclk);
853 static int sdhci_s3c_runtime_resume(struct device *dev)
855 struct sdhci_host *host = dev_get_drvdata(dev);
856 struct sdhci_s3c *ourhost = to_s3c(host);
857 struct clk *busclk = ourhost->clk_io;
860 clk_prepare_enable(busclk);
861 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
862 ret = sdhci_runtime_resume_host(host);
868 static const struct dev_pm_ops sdhci_s3c_pmops = {
869 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
870 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
874 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
877 #define SDHCI_S3C_PMOPS NULL
880 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
881 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
882 .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
884 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
886 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
889 static struct platform_device_id sdhci_s3c_driver_ids[] = {
892 .driver_data = (kernel_ulong_t)NULL,
894 .name = "exynos4-sdhci",
895 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
899 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
902 static const struct of_device_id sdhci_s3c_dt_match[] = {
903 { .compatible = "samsung,s3c6410-sdhci", },
904 { .compatible = "samsung,exynos4210-sdhci",
905 .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
908 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
911 static struct platform_driver sdhci_s3c_driver = {
912 .probe = sdhci_s3c_probe,
913 .remove = sdhci_s3c_remove,
914 .id_table = sdhci_s3c_driver_ids,
916 .owner = THIS_MODULE,
918 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
919 .pm = SDHCI_S3C_PMOPS,
923 module_platform_driver(sdhci_s3c_driver);
925 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
926 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
927 MODULE_LICENSE("GPL v2");
928 MODULE_ALIAS("platform:s3c-sdhci");