drivers/mmc/host/sdhci-omap.c

   1 /**
   2  * SDHCI Controller driver for TI's OMAP SoCs
   3  *
   4  * Copyright (C) 2017 Texas Instruments
   5  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 of
   9  * the License as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/mmc/slot-gpio.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/pinctrl/consumer.h>
  29
  30 #include "sdhci-pltfm.h"
  31
  32 #define SDHCI_OMAP_CON          0x12c
  33 #define CON_DW8                 BIT(5)
  34 #define CON_DMA_MASTER          BIT(20)
  35 #define CON_DDR                 BIT(19)
  36 #define CON_CLKEXTFREE          BIT(16)
  37 #define CON_PADEN               BIT(15)
  38 #define CON_INIT                BIT(1)
  39 #define CON_OD                  BIT(0)
  40
  41 #define SDHCI_OMAP_DLL          0x0134
  42 #define DLL_SWT                 BIT(20)
  43 #define DLL_FORCE_SR_C_SHIFT    13
  44 #define DLL_FORCE_SR_C_MASK     (0x7f << DLL_FORCE_SR_C_SHIFT)
  45 #define DLL_FORCE_VALUE         BIT(12)
  46 #define DLL_CALIB               BIT(1)
  47
  48 #define SDHCI_OMAP_CMD          0x20c
  49
  50 #define SDHCI_OMAP_PSTATE       0x0224
  51 #define PSTATE_DLEV_DAT0        BIT(20)
  52 #define PSTATE_DATI             BIT(1)
  53
  54 #define SDHCI_OMAP_HCTL         0x228
  55 #define HCTL_SDBP               BIT(8)
  56 #define HCTL_SDVS_SHIFT         9
  57 #define HCTL_SDVS_MASK          (0x7 << HCTL_SDVS_SHIFT)
  58 #define HCTL_SDVS_33            (0x7 << HCTL_SDVS_SHIFT)
  59 #define HCTL_SDVS_30            (0x6 << HCTL_SDVS_SHIFT)
  60 #define HCTL_SDVS_18            (0x5 << HCTL_SDVS_SHIFT)
  61
  62 #define SDHCI_OMAP_SYSCTL       0x22c
  63 #define SYSCTL_CEN              BIT(2)
  64 #define SYSCTL_CLKD_SHIFT       6
  65 #define SYSCTL_CLKD_MASK        0x3ff
  66
  67 #define SDHCI_OMAP_STAT         0x230
  68
  69 #define SDHCI_OMAP_IE           0x234
  70 #define INT_CC_EN               BIT(0)
  71
  72 #define SDHCI_OMAP_AC12         0x23c
  73 #define AC12_V1V8_SIGEN         BIT(19)
  74 #define AC12_SCLK_SEL           BIT(23)
  75
  76 #define SDHCI_OMAP_CAPA         0x240
  77 #define CAPA_VS33               BIT(24)
  78 #define CAPA_VS30               BIT(25)
  79 #define CAPA_VS18               BIT(26)
  80
  81 #define SDHCI_OMAP_CAPA2        0x0244
  82 #define CAPA2_TSDR50            BIT(13)
  83
  84 #define SDHCI_OMAP_TIMEOUT      1               /* 1 msec */
  85
  86 #define SYSCTL_CLKD_MAX         0x3FF
  87
  88 #define IOV_1V8                 1800000         /* 180000 uV */
  89 #define IOV_3V0                 3000000         /* 300000 uV */
  90 #define IOV_3V3                 3300000         /* 330000 uV */
  91
  92 #define MAX_PHASE_DELAY         0x7C
  93
  94 /* sdhci-omap controller flags */
  95 #define SDHCI_OMAP_REQUIRE_IODELAY      BIT(0)
  96
  97 struct sdhci_omap_data {
  98         u32 offset;
  99         u8 flags;
 100 };
 101
 102 struct sdhci_omap_host {
 103         void __iomem            *base;
 104         struct device           *dev;
 105         struct  regulator       *pbias;
 106         bool                    pbias_enabled;
 107         struct sdhci_host       *host;
 108         u8                      bus_mode;
 109         u8                      power_mode;
 110         u8                      timing;
 111         u8                      flags;
 112
 113         struct pinctrl          *pinctrl;
 114         struct pinctrl_state    **pinctrl_state;
 115 };
 116
 117 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
 118 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
 119
 120 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
 121                                    unsigned int offset)
 122 {
 123         return readl(host->base + offset);
 124 }
 125
 126 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
 127                                      unsigned int offset, u32 data)
 128 {
 129         writel(data, host->base + offset);
 130 }
 131
 132 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
 133                                 bool power_on, unsigned int iov)
 134 {
 135         int ret;
 136         struct device *dev = omap_host->dev;
 137
 138         if (IS_ERR(omap_host->pbias))
 139                 return 0;
 140
 141         if (power_on) {
 142                 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
 143                 if (ret) {
 144                         dev_err(dev, "pbias set voltage failed\n");
 145                         return ret;
 146                 }
 147
 148                 if (omap_host->pbias_enabled)
 149                         return 0;
 150
 151                 ret = regulator_enable(omap_host->pbias);
 152                 if (ret) {
 153                         dev_err(dev, "pbias reg enable fail\n");
 154                         return ret;
 155                 }
 156
 157                 omap_host->pbias_enabled = true;
 158         } else {
 159                 if (!omap_host->pbias_enabled)
 160                         return 0;
 161
 162                 ret = regulator_disable(omap_host->pbias);
 163                 if (ret) {
 164                         dev_err(dev, "pbias reg disable fail\n");
 165                         return ret;
 166                 }
 167                 omap_host->pbias_enabled = false;
 168         }
 169
 170         return 0;
 171 }
 172
 173 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
 174                                  unsigned int iov)
 175 {
 176         int ret;
 177         struct sdhci_host *host = omap_host->host;
 178         struct mmc_host *mmc = host->mmc;
 179
 180         ret = sdhci_omap_set_pbias(omap_host, false, 0);
 181         if (ret)
 182                 return ret;
 183
 184         if (!IS_ERR(mmc->supply.vqmmc)) {
 185                 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
 186                 if (ret) {
 187                         dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
 188                         return ret;
 189                 }
 190         }
 191
 192         ret = sdhci_omap_set_pbias(omap_host, true, iov);
 193         if (ret)
 194                 return ret;
 195
 196         return 0;
 197 }
 198
 199 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
 200                                       unsigned char signal_voltage)
 201 {
 202         u32 reg;
 203         ktime_t timeout;
 204
 205         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
 206         reg &= ~HCTL_SDVS_MASK;
 207
 208         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 209                 reg |= HCTL_SDVS_33;
 210         else
 211                 reg |= HCTL_SDVS_18;
 212
 213         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 214
 215         reg |= HCTL_SDBP;
 216         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 217
 218         /* wait 1ms */
 219         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 220         while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)) {
 221                 if (WARN_ON(ktime_after(ktime_get(), timeout)))
 222                         return;
 223                 usleep_range(5, 10);
 224         }
 225 }
 226
 227 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
 228                                       int count)
 229 {
 230         int i;
 231         u32 reg;
 232
 233         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 234         reg |= DLL_FORCE_VALUE;
 235         reg &= ~DLL_FORCE_SR_C_MASK;
 236         reg |= (count << DLL_FORCE_SR_C_SHIFT);
 237         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 238
 239         reg |= DLL_CALIB;
 240         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 241         for (i = 0; i < 1000; i++) {
 242                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 243                 if (reg & DLL_CALIB)
 244                         break;
 245         }
 246         reg &= ~DLL_CALIB;
 247         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 248 }
 249
 250 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
 251 {
 252         u32 reg;
 253
 254         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 255         reg &= ~AC12_SCLK_SEL;
 256         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 257
 258         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 259         reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
 260         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 261 }
 262
 263 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
 264 {
 265         struct sdhci_host *host = mmc_priv(mmc);
 266         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 267         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 268         struct device *dev = omap_host->dev;
 269         struct mmc_ios *ios = &mmc->ios;
 270         u32 start_window = 0, max_window = 0;
 271         u8 cur_match, prev_match = 0;
 272         u32 length = 0, max_len = 0;
 273         u32 ier = host->ier;
 274         u32 phase_delay = 0;
 275         int ret = 0;
 276         u32 reg;
 277
 278         pltfm_host = sdhci_priv(host);
 279         omap_host = sdhci_pltfm_priv(pltfm_host);
 280         dev = omap_host->dev;
 281
 282         /* clock tuning is not needed for upto 52MHz */
 283         if (ios->clock <= 52000000)
 284                 return 0;
 285
 286         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
 287         if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
 288                 return 0;
 289
 290         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 291         reg |= DLL_SWT;
 292         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 293
 294         /*
 295          * OMAP5/DRA74X/DRA72x Errata i802:
 296          * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
 297          * during the tuning procedure. So disable it during the
 298          * tuning procedure.
 299          */
 300         ier &= ~SDHCI_INT_DATA_CRC;
 301         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 302         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 303
 304         while (phase_delay <= MAX_PHASE_DELAY) {
 305                 sdhci_omap_set_dll(omap_host, phase_delay);
 306
 307                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 308                 if (cur_match) {
 309                         if (prev_match) {
 310                                 length++;
 311                         } else {
 312                                 start_window = phase_delay;
 313                                 length = 1;
 314                         }
 315                 }
 316
 317                 if (length > max_len) {
 318                         max_window = start_window;
 319                         max_len = length;
 320                 }
 321
 322                 prev_match = cur_match;
 323                 phase_delay += 4;
 324         }
 325
 326         if (!max_len) {
 327                 dev_err(dev, "Unable to find match\n");
 328                 ret = -EIO;
 329                 goto tuning_error;
 330         }
 331
 332         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 333         if (!(reg & AC12_SCLK_SEL)) {
 334                 ret = -EIO;
 335                 goto tuning_error;
 336         }
 337
 338         phase_delay = max_window + 4 * (max_len >> 1);
 339         sdhci_omap_set_dll(omap_host, phase_delay);
 340
 341         goto ret;
 342
 343 tuning_error:
 344         dev_err(dev, "Tuning failed\n");
 345         sdhci_omap_disable_tuning(omap_host);
 346
 347 ret:
 348         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 349         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 350         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 351         return ret;
 352 }
 353
 354 static int sdhci_omap_card_busy(struct mmc_host *mmc)
 355 {
 356         u32 reg, ac12;
 357         int ret = false;
 358         struct sdhci_host *host = mmc_priv(mmc);
 359         struct sdhci_pltfm_host *pltfm_host;
 360         struct sdhci_omap_host *omap_host;
 361         u32 ier = host->ier;
 362
 363         pltfm_host = sdhci_priv(host);
 364         omap_host = sdhci_pltfm_priv(pltfm_host);
 365
 366         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 367         ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 368         reg &= ~CON_CLKEXTFREE;
 369         if (ac12 & AC12_V1V8_SIGEN)
 370                 reg |= CON_CLKEXTFREE;
 371         reg |= CON_PADEN;
 372         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 373
 374         disable_irq(host->irq);
 375         ier |= SDHCI_INT_CARD_INT;
 376         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 377         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 378
 379         /*
 380          * Delay is required for PSTATE to correctly reflect
 381          * DLEV/CLEV values after PADEN is set.
 382          */
 383         usleep_range(50, 100);
 384         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
 385         if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
 386                 ret = true;
 387
 388         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 389         reg &= ~(CON_CLKEXTFREE | CON_PADEN);
 390         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 391
 392         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 393         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 394         enable_irq(host->irq);
 395
 396         return ret;
 397 }
 398
 399 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
 400                                                   struct mmc_ios *ios)
 401 {
 402         u32 reg;
 403         int ret;
 404         unsigned int iov;
 405         struct sdhci_host *host = mmc_priv(mmc);
 406         struct sdhci_pltfm_host *pltfm_host;
 407         struct sdhci_omap_host *omap_host;
 408         struct device *dev;
 409
 410         pltfm_host = sdhci_priv(host);
 411         omap_host = sdhci_pltfm_priv(pltfm_host);
 412         dev = omap_host->dev;
 413
 414         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 415                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 416                 if (!(reg & CAPA_VS33))
 417                         return -EOPNOTSUPP;
 418
 419                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 420
 421                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 422                 reg &= ~AC12_V1V8_SIGEN;
 423                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 424
 425                 iov = IOV_3V3;
 426         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 427                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 428                 if (!(reg & CAPA_VS18))
 429                         return -EOPNOTSUPP;
 430
 431                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 432
 433                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 434                 reg |= AC12_V1V8_SIGEN;
 435                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 436
 437                 iov = IOV_1V8;
 438         } else {
 439                 return -EOPNOTSUPP;
 440         }
 441
 442         ret = sdhci_omap_enable_iov(omap_host, iov);
 443         if (ret) {
 444                 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
 445                 return ret;
 446         }
 447
 448         dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
 449         return 0;
 450 }
 451
 452 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
 453 {
 454         int ret;
 455         struct pinctrl_state *pinctrl_state;
 456         struct device *dev = omap_host->dev;
 457
 458         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 459                 return;
 460
 461         if (omap_host->timing == timing)
 462                 return;
 463
 464         sdhci_omap_stop_clock(omap_host);
 465
 466         pinctrl_state = omap_host->pinctrl_state[timing];
 467         ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
 468         if (ret) {
 469                 dev_err(dev, "failed to select pinctrl state\n");
 470                 return;
 471         }
 472
 473         sdhci_omap_start_clock(omap_host);
 474         omap_host->timing = timing;
 475 }
 476
 477 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
 478                                       u8 power_mode)
 479 {
 480         if (omap_host->bus_mode == MMC_POWER_OFF)
 481                 sdhci_omap_disable_tuning(omap_host);
 482         omap_host->power_mode = power_mode;
 483 }
 484
 485 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
 486                                     unsigned int mode)
 487 {
 488         u32 reg;
 489
 490         if (omap_host->bus_mode == mode)
 491                 return;
 492
 493         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 494         if (mode == MMC_BUSMODE_OPENDRAIN)
 495                 reg |= CON_OD;
 496         else
 497                 reg &= ~CON_OD;
 498         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 499
 500         omap_host->bus_mode = mode;
 501 }
 502
 503 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 504 {
 505         struct sdhci_host *host = mmc_priv(mmc);
 506         struct sdhci_pltfm_host *pltfm_host;
 507         struct sdhci_omap_host *omap_host;
 508
 509         pltfm_host = sdhci_priv(host);
 510         omap_host = sdhci_pltfm_priv(pltfm_host);
 511
 512         sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
 513         sdhci_omap_set_timing(omap_host, ios->timing);
 514         sdhci_set_ios(mmc, ios);
 515         sdhci_omap_set_power_mode(omap_host, ios->power_mode);
 516 }
 517
 518 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
 519                                    unsigned int clock)
 520 {
 521         u16 dsor;
 522
 523         dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
 524         if (dsor > SYSCTL_CLKD_MAX)
 525                 dsor = SYSCTL_CLKD_MAX;
 526
 527         return dsor;
 528 }
 529
 530 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
 531 {
 532         u32 reg;
 533
 534         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 535         reg |= SYSCTL_CEN;
 536         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 537 }
 538
 539 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
 540 {
 541         u32 reg;
 542
 543         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 544         reg &= ~SYSCTL_CEN;
 545         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 546 }
 547
 548 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
 549 {
 550         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 551         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 552         unsigned long clkdiv;
 553
 554         sdhci_omap_stop_clock(omap_host);
 555
 556         if (!clock)
 557                 return;
 558
 559         clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
 560         clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
 561         sdhci_enable_clk(host, clkdiv);
 562
 563         sdhci_omap_start_clock(omap_host);
 564 }
 565
 566 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
 567                           unsigned short vdd)
 568 {
 569         struct mmc_host *mmc = host->mmc;
 570
 571         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 572 }
 573
 574 static int sdhci_omap_enable_dma(struct sdhci_host *host)
 575 {
 576         u32 reg;
 577         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 578         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 579
 580         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 581         reg |= CON_DMA_MASTER;
 582         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 583
 584         return 0;
 585 }
 586
 587 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
 588 {
 589         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 590
 591         return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
 592 }
 593
 594 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
 595 {
 596         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 597         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 598         u32 reg;
 599
 600         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 601         if (width == MMC_BUS_WIDTH_8)
 602                 reg |= CON_DW8;
 603         else
 604                 reg &= ~CON_DW8;
 605         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 606
 607         sdhci_set_bus_width(host, width);
 608 }
 609
 610 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 611 {
 612         u32 reg;
 613         ktime_t timeout;
 614         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 615         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 616
 617         if (omap_host->power_mode == power_mode)
 618                 return;
 619
 620         if (power_mode != MMC_POWER_ON)
 621                 return;
 622
 623         disable_irq(host->irq);
 624
 625         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 626         reg |= CON_INIT;
 627         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 628         sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
 629
 630         /* wait 1ms */
 631         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 632         while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)) {
 633                 if (WARN_ON(ktime_after(ktime_get(), timeout)))
 634                         return;
 635                 usleep_range(5, 10);
 636         }
 637
 638         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 639         reg &= ~CON_INIT;
 640         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 641         sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
 642
 643         enable_irq(host->irq);
 644 }
 645
 646 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
 647                                          unsigned int timing)
 648 {
 649         u32 reg;
 650         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 651         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 652
 653         sdhci_omap_stop_clock(omap_host);
 654
 655         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 656         if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 657                 reg |= CON_DDR;
 658         else
 659                 reg &= ~CON_DDR;
 660         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 661
 662         sdhci_set_uhs_signaling(host, timing);
 663         sdhci_omap_start_clock(omap_host);
 664 }
 665
 666 static struct sdhci_ops sdhci_omap_ops = {
 667         .set_clock = sdhci_omap_set_clock,
 668         .set_power = sdhci_omap_set_power,
 669         .enable_dma = sdhci_omap_enable_dma,
 670         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 671         .get_min_clock = sdhci_omap_get_min_clock,
 672         .set_bus_width = sdhci_omap_set_bus_width,
 673         .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
 674         .reset = sdhci_reset,
 675         .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
 676 };
 677
 678 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
 679 {
 680         u32 reg;
 681         int ret = 0;
 682         struct device *dev = omap_host->dev;
 683         struct regulator *vqmmc;
 684
 685         vqmmc = regulator_get(dev, "vqmmc");
 686         if (IS_ERR(vqmmc)) {
 687                 ret = PTR_ERR(vqmmc);
 688                 goto reg_put;
 689         }
 690
 691         /* voltage capabilities might be set by boot loader, clear it */
 692         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 693         reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
 694
 695         if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
 696                 reg |= CAPA_VS33;
 697         if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
 698                 reg |= CAPA_VS18;
 699
 700         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
 701
 702 reg_put:
 703         regulator_put(vqmmc);
 704
 705         return ret;
 706 }
 707
 708 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
 709         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 710                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 711                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 712                   SDHCI_QUIRK_NO_HISPD_BIT |
 713                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 714         .quirks2 = SDHCI_QUIRK2_NO_1_8_V |
 715                    SDHCI_QUIRK2_ACMD23_BROKEN |
 716                    SDHCI_QUIRK2_RSP_136_HAS_CRC,
 717         .ops = &sdhci_omap_ops,
 718 };
 719
 720 static const struct sdhci_omap_data dra7_data = {
 721         .offset = 0x200,
 722         .flags  = SDHCI_OMAP_REQUIRE_IODELAY,
 723 };
 724
 725 static const struct of_device_id omap_sdhci_match[] = {
 726         { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
 727         {},
 728 };
 729 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
 730
 731 static struct pinctrl_state
 732 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
 733                                   u32 *caps, u32 capmask)
 734 {
 735         struct device *dev = omap_host->dev;
 736         struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
 737
 738         if (!(*caps & capmask))
 739                 goto ret;
 740
 741         pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
 742         if (IS_ERR(pinctrl_state)) {
 743                 dev_err(dev, "no pinctrl state for %s mode", mode);
 744                 *caps &= ~capmask;
 745         }
 746
 747 ret:
 748         return pinctrl_state;
 749 }
 750
 751 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
 752                                                    *omap_host)
 753 {
 754         struct device *dev = omap_host->dev;
 755         struct sdhci_host *host = omap_host->host;
 756         struct mmc_host *mmc = host->mmc;
 757         u32 *caps = &mmc->caps;
 758         u32 *caps2 = &mmc->caps2;
 759         struct pinctrl_state *state;
 760         struct pinctrl_state **pinctrl_state;
 761
 762         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 763                 return 0;
 764
 765         pinctrl_state = devm_kzalloc(dev, sizeof(*pinctrl_state) *
 766                                      (MMC_TIMING_MMC_HS200 + 1), GFP_KERNEL);
 767         if (!pinctrl_state)
 768                 return -ENOMEM;
 769
 770         omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
 771         if (IS_ERR(omap_host->pinctrl)) {
 772                 dev_err(dev, "Cannot get pinctrl\n");
 773                 return PTR_ERR(omap_host->pinctrl);
 774         }
 775
 776         state = pinctrl_lookup_state(omap_host->pinctrl, "default");
 777         if (IS_ERR(state)) {
 778                 dev_err(dev, "no pinctrl state for default mode\n");
 779                 return PTR_ERR(state);
 780         }
 781         pinctrl_state[MMC_TIMING_LEGACY] = state;
 782
 783         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
 784                                                  MMC_CAP_UHS_SDR104);
 785         if (!IS_ERR(state))
 786                 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
 787
 788         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
 789                                                  MMC_CAP_UHS_DDR50);
 790         if (!IS_ERR(state))
 791                 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
 792
 793         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
 794                                                  MMC_CAP_UHS_SDR50);
 795         if (!IS_ERR(state))
 796                 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
 797
 798         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
 799                                                  MMC_CAP_UHS_SDR25);
 800         if (!IS_ERR(state))
 801                 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
 802
 803         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
 804                                                  MMC_CAP_UHS_SDR12);
 805         if (!IS_ERR(state))
 806                 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
 807
 808         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
 809                                                  MMC_CAP_1_8V_DDR);
 810         if (!IS_ERR(state))
 811                 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
 812
 813         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
 814                                                  MMC_CAP_SD_HIGHSPEED);
 815         if (!IS_ERR(state))
 816                 pinctrl_state[MMC_TIMING_SD_HS] = state;
 817
 818         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
 819                                                  MMC_CAP_MMC_HIGHSPEED);
 820         if (!IS_ERR(state))
 821                 pinctrl_state[MMC_TIMING_MMC_HS] = state;
 822
 823         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
 824                                                  MMC_CAP2_HS200_1_8V_SDR);
 825         if (!IS_ERR(state))
 826                 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
 827
 828         omap_host->pinctrl_state = pinctrl_state;
 829
 830         return 0;
 831 }
 832
 833 static int sdhci_omap_probe(struct platform_device *pdev)
 834 {
 835         int ret;
 836         u32 offset;
 837         struct device *dev = &pdev->dev;
 838         struct sdhci_host *host;
 839         struct sdhci_pltfm_host *pltfm_host;
 840         struct sdhci_omap_host *omap_host;
 841         struct mmc_host *mmc;
 842         const struct of_device_id *match;
 843         struct sdhci_omap_data *data;
 844
 845         match = of_match_device(omap_sdhci_match, dev);
 846         if (!match)
 847                 return -EINVAL;
 848
 849         data = (struct sdhci_omap_data *)match->data;
 850         if (!data) {
 851                 dev_err(dev, "no sdhci omap data\n");
 852                 return -EINVAL;
 853         }
 854         offset = data->offset;
 855
 856         host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
 857                                 sizeof(*omap_host));
 858         if (IS_ERR(host)) {
 859                 dev_err(dev, "Failed sdhci_pltfm_init\n");
 860                 return PTR_ERR(host);
 861         }
 862
 863         pltfm_host = sdhci_priv(host);
 864         omap_host = sdhci_pltfm_priv(pltfm_host);
 865         omap_host->host = host;
 866         omap_host->base = host->ioaddr;
 867         omap_host->dev = dev;
 868         omap_host->power_mode = MMC_POWER_UNDEFINED;
 869         omap_host->timing = MMC_TIMING_LEGACY;
 870         omap_host->flags = data->flags;
 871         host->ioaddr += offset;
 872
 873         mmc = host->mmc;
 874         ret = mmc_of_parse(mmc);
 875         if (ret)
 876                 goto err_pltfm_free;
 877
 878         pltfm_host->clk = devm_clk_get(dev, "fck");
 879         if (IS_ERR(pltfm_host->clk)) {
 880                 ret = PTR_ERR(pltfm_host->clk);
 881                 goto err_pltfm_free;
 882         }
 883
 884         ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
 885         if (ret) {
 886                 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
 887                 goto err_pltfm_free;
 888         }
 889
 890         omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
 891         if (IS_ERR(omap_host->pbias)) {
 892                 ret = PTR_ERR(omap_host->pbias);
 893                 if (ret != -ENODEV)
 894                         goto err_pltfm_free;
 895                 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
 896         }
 897         omap_host->pbias_enabled = false;
 898
 899         /*
 900          * omap_device_pm_domain has callbacks to enable the main
 901          * functional clock, interface clock and also configure the
 902          * SYSCONFIG register of omap devices. The callback will be invoked
 903          * as part of pm_runtime_get_sync.
 904          */
 905         pm_runtime_enable(dev);
 906         ret = pm_runtime_get_sync(dev);
 907         if (ret < 0) {
 908                 dev_err(dev, "pm_runtime_get_sync failed\n");
 909                 pm_runtime_put_noidle(dev);
 910                 goto err_rpm_disable;
 911         }
 912
 913         ret = sdhci_omap_set_capabilities(omap_host);
 914         if (ret) {
 915                 dev_err(dev, "failed to set system capabilities\n");
 916                 goto err_put_sync;
 917         }
 918
 919         ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
 920         if (ret)
 921                 goto err_put_sync;
 922
 923         host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
 924         host->mmc_host_ops.start_signal_voltage_switch =
 925                                         sdhci_omap_start_signal_voltage_switch;
 926         host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
 927         host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
 928         host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
 929
 930         sdhci_read_caps(host);
 931         host->caps |= SDHCI_CAN_DO_ADMA2;
 932
 933         ret = sdhci_add_host(host);
 934         if (ret)
 935                 goto err_put_sync;
 936
 937         return 0;
 938
 939 err_put_sync:
 940         pm_runtime_put_sync(dev);
 941
 942 err_rpm_disable:
 943         pm_runtime_disable(dev);
 944
 945 err_pltfm_free:
 946         sdhci_pltfm_free(pdev);
 947         return ret;
 948 }
 949
 950 static int sdhci_omap_remove(struct platform_device *pdev)
 951 {
 952         struct device *dev = &pdev->dev;
 953         struct sdhci_host *host = platform_get_drvdata(pdev);
 954
 955         sdhci_remove_host(host, true);
 956         pm_runtime_put_sync(dev);
 957         pm_runtime_disable(dev);
 958         sdhci_pltfm_free(pdev);
 959
 960         return 0;
 961 }
 962
 963 static struct platform_driver sdhci_omap_driver = {
 964         .probe = sdhci_omap_probe,
 965         .remove = sdhci_omap_remove,
 966         .driver = {
 967                    .name = "sdhci-omap",
 968                    .of_match_table = omap_sdhci_match,
 969                   },
 970 };
 971
 972 module_platform_driver(sdhci_omap_driver);
 973
 974 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
 975 MODULE_AUTHOR("Texas Instruments Inc.");
 976 MODULE_LICENSE("GPL v2");
 977 MODULE_ALIAS("platform:sdhci_omap");