1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
5 * Copyright (C) 2018 Synaptics Incorporated
7 * Author: Jisheng Zhang <jszhang@kernel.org>
10 #include <linux/acpi.h>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/reset.h>
19 #include <linux/sizes.h>
21 #include "sdhci-pltfm.h"
23 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
25 /* DWCMSHC specific Mode Select value */
26 #define DWCMSHC_CTRL_HS400 0x7
28 /* DWC IP vendor area 1 pointer */
29 #define DWCMSHC_P_VENDOR_AREA1 0xe8
30 #define DWCMSHC_AREA1_MASK GENMASK(11, 0)
31 /* Offset inside the vendor area 1 */
32 #define DWCMSHC_HOST_CTRL3 0x8
33 #define DWCMSHC_EMMC_CONTROL 0x2c
34 #define DWCMSHC_CARD_IS_EMMC BIT(0)
35 #define DWCMSHC_ENHANCED_STROBE BIT(8)
36 #define DWCMSHC_EMMC_ATCTRL 0x40
38 /* Rockchip specific Registers */
39 #define DWCMSHC_EMMC_DLL_CTRL 0x800
40 #define DWCMSHC_EMMC_DLL_RXCLK 0x804
41 #define DWCMSHC_EMMC_DLL_TXCLK 0x808
42 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c
43 #define DECMSHC_EMMC_DLL_CMDOUT 0x810
44 #define DWCMSHC_EMMC_DLL_STATUS0 0x840
45 #define DWCMSHC_EMMC_DLL_START BIT(0)
46 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
47 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
48 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
49 #define DWCMSHC_EMMC_DLL_START_POINT 16
50 #define DWCMSHC_EMMC_DLL_INC 8
51 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
52 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
53 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
54 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
55 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8
56 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
57 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
58 #define DLL_STRBIN_DELAY_NUM_OFFSET 16
59 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
60 #define DLL_RXCLK_NO_INVERTER 1
61 #define DLL_RXCLK_INVERTER 0
62 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
63 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
64 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
65 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
67 #define DLL_LOCK_WO_TMOUT(x) \
68 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
69 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
70 #define RK35xx_MAX_CLKS 3
72 #define BOUNDARY_OK(addr, len) \
73 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
75 enum dwcmshc_rk_type {
81 /* Rockchip specified optional clocks */
82 struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
83 struct reset_control *reset;
84 enum dwcmshc_rk_type devtype;
90 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
91 void *priv; /* pointer to SoC private stuff */
95 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
96 * so that each DMA transfer doesn't exceed the boundary.
98 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
99 dma_addr_t addr, int len, unsigned int cmd)
103 if (likely(!len || BOUNDARY_OK(addr, len))) {
104 sdhci_adma_write_desc(host, desc, addr, len, cmd);
108 offset = addr & (SZ_128M - 1);
109 tmplen = SZ_128M - offset;
110 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
114 sdhci_adma_write_desc(host, desc, addr, len, cmd);
117 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
119 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
122 return sdhci_pltfm_clk_get_max_clock(host);
124 return pltfm_host->clock;
127 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
128 struct mmc_request *mrq)
130 struct sdhci_host *host = mmc_priv(mmc);
133 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
134 * block count register which doesn't support stuff bits of
135 * CMD23 argument on dwcmsch host controller.
137 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
138 host->flags &= ~SDHCI_AUTO_CMD23;
140 host->flags |= SDHCI_AUTO_CMD23;
143 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
145 dwcmshc_check_auto_cmd23(mmc, mrq);
147 sdhci_request(mmc, mrq);
150 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
153 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
154 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
157 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
158 /* Select Bus Speed Mode for host */
159 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
160 if ((timing == MMC_TIMING_MMC_HS200) ||
161 (timing == MMC_TIMING_UHS_SDR104))
162 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
163 else if (timing == MMC_TIMING_UHS_SDR12)
164 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
165 else if ((timing == MMC_TIMING_UHS_SDR25) ||
166 (timing == MMC_TIMING_MMC_HS))
167 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
168 else if (timing == MMC_TIMING_UHS_SDR50)
169 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
170 else if ((timing == MMC_TIMING_UHS_DDR50) ||
171 (timing == MMC_TIMING_MMC_DDR52))
172 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
173 else if (timing == MMC_TIMING_MMC_HS400) {
174 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
175 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
176 ctrl |= DWCMSHC_CARD_IS_EMMC;
177 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
179 ctrl_2 |= DWCMSHC_CTRL_HS400;
182 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
185 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
189 struct sdhci_host *host = mmc_priv(mmc);
190 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
191 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
192 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
194 vendor = sdhci_readl(host, reg);
195 if (ios->enhanced_strobe)
196 vendor |= DWCMSHC_ENHANCED_STROBE;
198 vendor &= ~DWCMSHC_ENHANCED_STROBE;
200 sdhci_writel(host, vendor, reg);
203 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
205 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
206 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
207 struct rk35xx_priv *priv = dwc_priv->priv;
208 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
212 host->mmc->actual_clock = 0;
215 /* Disable interface clock at initial state. */
216 sdhci_set_clock(host, clock);
220 /* Rockchip platform only support 375KHz for identify mode */
224 err = clk_set_rate(pltfm_host->clk, clock);
226 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
228 sdhci_set_clock(host, clock);
230 /* Disable cmd conflict check */
231 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
232 extra = sdhci_readl(host, reg);
234 sdhci_writel(host, extra, reg);
236 if (clock <= 52000000) {
237 /* Disable DLL and reset both of sample and drive clock */
238 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
239 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
240 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
241 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
243 * Before switching to hs400es mode, the driver will enable
244 * enhanced strobe first. PHY needs to configure the parameters
245 * of enhanced strobe first.
247 extra = DWCMSHC_EMMC_DLL_DLYENA |
248 DLL_STRBIN_DELAY_NUM_SEL |
249 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
250 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
255 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
257 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
260 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
261 * we must set it in higher speed mode.
263 extra = DWCMSHC_EMMC_DLL_DLYENA;
264 if (priv->devtype == DWCMSHC_RK3568)
265 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
266 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
268 /* Init DLL settings */
269 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
270 0x2 << DWCMSHC_EMMC_DLL_INC |
271 DWCMSHC_EMMC_DLL_START;
272 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
273 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
274 extra, DLL_LOCK_WO_TMOUT(extra), 1,
275 500 * USEC_PER_MSEC);
277 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
281 extra = 0x1 << 16 | /* tune clock stop en */
282 0x2 << 17 | /* pre-change delay */
283 0x3 << 19; /* post-change delay */
284 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
286 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
287 host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
288 txclk_tapnum = priv->txclk_tapnum;
290 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
291 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
293 extra = DLL_CMDOUT_SRC_CLK_NEG |
294 DLL_CMDOUT_EN_SRC_CLK_NEG |
295 DWCMSHC_EMMC_DLL_DLYENA |
296 DLL_CMDOUT_TAPNUM_90_DEGREES |
297 DLL_CMDOUT_TAPNUM_FROM_SW;
298 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
301 extra = DWCMSHC_EMMC_DLL_DLYENA |
302 DLL_TXCLK_TAPNUM_FROM_SW |
303 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
305 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
307 extra = DWCMSHC_EMMC_DLL_DLYENA |
308 DLL_STRBIN_TAPNUM_DEFAULT |
309 DLL_STRBIN_TAPNUM_FROM_SW;
310 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
313 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
315 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
316 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
317 struct rk35xx_priv *priv = dwc_priv->priv;
319 if (mask & SDHCI_RESET_ALL && priv->reset) {
320 reset_control_assert(priv->reset);
322 reset_control_deassert(priv->reset);
325 sdhci_reset(host, mask);
328 static const struct sdhci_ops sdhci_dwcmshc_ops = {
329 .set_clock = sdhci_set_clock,
330 .set_bus_width = sdhci_set_bus_width,
331 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
332 .get_max_clock = dwcmshc_get_max_clock,
333 .reset = sdhci_reset,
334 .adma_write_desc = dwcmshc_adma_write_desc,
337 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
338 .set_clock = dwcmshc_rk3568_set_clock,
339 .set_bus_width = sdhci_set_bus_width,
340 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
341 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
342 .reset = rk35xx_sdhci_reset,
343 .adma_write_desc = dwcmshc_adma_write_desc,
346 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
347 .ops = &sdhci_dwcmshc_ops,
348 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
349 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
353 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
354 .ops = &sdhci_dwcmshc_ops,
355 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
356 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
357 SDHCI_QUIRK2_ACMD23_BROKEN,
361 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
362 .ops = &sdhci_dwcmshc_rk35xx_ops,
363 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
364 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
365 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
366 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
369 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
372 struct rk35xx_priv *priv = dwc_priv->priv;
374 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
375 if (IS_ERR(priv->reset)) {
376 err = PTR_ERR(priv->reset);
377 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
381 priv->rockchip_clks[0].id = "axi";
382 priv->rockchip_clks[1].id = "block";
383 priv->rockchip_clks[2].id = "timer";
384 err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
385 priv->rockchip_clks);
387 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
391 err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
393 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
397 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
398 &priv->txclk_tapnum))
399 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
401 /* Disable cmd conflict check */
402 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
403 /* Reset previous settings */
404 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
405 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
410 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
413 * Don't support highspeed bus mode with low clk speed as we
414 * cannot use DLL for this condition.
416 if (host->mmc->f_max <= 52000000) {
417 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
419 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
420 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
424 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
426 .compatible = "rockchip,rk3588-dwcmshc",
427 .data = &sdhci_dwcmshc_rk35xx_pdata,
430 .compatible = "rockchip,rk3568-dwcmshc",
431 .data = &sdhci_dwcmshc_rk35xx_pdata,
434 .compatible = "snps,dwcmshc-sdhci",
435 .data = &sdhci_dwcmshc_pdata,
439 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
442 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
445 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
451 static int dwcmshc_probe(struct platform_device *pdev)
453 struct device *dev = &pdev->dev;
454 struct sdhci_pltfm_host *pltfm_host;
455 struct sdhci_host *host;
456 struct dwcmshc_priv *priv;
457 struct rk35xx_priv *rk_priv = NULL;
458 const struct sdhci_pltfm_data *pltfm_data;
462 pltfm_data = device_get_match_data(&pdev->dev);
464 dev_err(&pdev->dev, "Error: No device match data found\n");
468 host = sdhci_pltfm_init(pdev, pltfm_data,
469 sizeof(struct dwcmshc_priv));
471 return PTR_ERR(host);
474 * extra adma table cnt for cross 128M boundary handling.
476 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
477 if (extra > SDHCI_MAX_SEGS)
478 extra = SDHCI_MAX_SEGS;
479 host->adma_table_cnt += extra;
481 pltfm_host = sdhci_priv(host);
482 priv = sdhci_pltfm_priv(pltfm_host);
485 pltfm_host->clk = devm_clk_get(dev, "core");
486 if (IS_ERR(pltfm_host->clk)) {
487 err = PTR_ERR(pltfm_host->clk);
488 dev_err(dev, "failed to get core clk: %d\n", err);
491 err = clk_prepare_enable(pltfm_host->clk);
495 priv->bus_clk = devm_clk_get(dev, "bus");
496 if (!IS_ERR(priv->bus_clk))
497 clk_prepare_enable(priv->bus_clk);
500 err = mmc_of_parse(host->mmc);
504 sdhci_get_of_property(pdev);
506 priv->vendor_specific_area1 =
507 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
509 host->mmc_host_ops.request = dwcmshc_request;
510 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
512 if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) {
513 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
519 if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
520 rk_priv->devtype = DWCMSHC_RK3588;
522 rk_priv->devtype = DWCMSHC_RK3568;
524 priv->priv = rk_priv;
526 err = dwcmshc_rk35xx_init(host, priv);
531 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
533 err = sdhci_setup_host(host);
538 dwcmshc_rk35xx_postinit(host, priv);
540 err = __sdhci_add_host(host);
547 sdhci_cleanup_host(host);
549 clk_disable_unprepare(pltfm_host->clk);
550 clk_disable_unprepare(priv->bus_clk);
552 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
553 rk_priv->rockchip_clks);
555 sdhci_pltfm_free(pdev);
559 static int dwcmshc_remove(struct platform_device *pdev)
561 struct sdhci_host *host = platform_get_drvdata(pdev);
562 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
563 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
564 struct rk35xx_priv *rk_priv = priv->priv;
566 sdhci_remove_host(host, 0);
568 clk_disable_unprepare(pltfm_host->clk);
569 clk_disable_unprepare(priv->bus_clk);
571 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
572 rk_priv->rockchip_clks);
573 sdhci_pltfm_free(pdev);
578 #ifdef CONFIG_PM_SLEEP
579 static int dwcmshc_suspend(struct device *dev)
581 struct sdhci_host *host = dev_get_drvdata(dev);
582 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
583 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
584 struct rk35xx_priv *rk_priv = priv->priv;
587 ret = sdhci_suspend_host(host);
591 clk_disable_unprepare(pltfm_host->clk);
592 if (!IS_ERR(priv->bus_clk))
593 clk_disable_unprepare(priv->bus_clk);
596 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
597 rk_priv->rockchip_clks);
602 static int dwcmshc_resume(struct device *dev)
604 struct sdhci_host *host = dev_get_drvdata(dev);
605 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
606 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
607 struct rk35xx_priv *rk_priv = priv->priv;
610 ret = clk_prepare_enable(pltfm_host->clk);
614 if (!IS_ERR(priv->bus_clk)) {
615 ret = clk_prepare_enable(priv->bus_clk);
621 ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
622 rk_priv->rockchip_clks);
627 return sdhci_resume_host(host);
631 static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
633 static struct platform_driver sdhci_dwcmshc_driver = {
635 .name = "sdhci-dwcmshc",
636 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
637 .of_match_table = sdhci_dwcmshc_dt_ids,
638 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
639 .pm = &dwcmshc_pmops,
641 .probe = dwcmshc_probe,
642 .remove = dwcmshc_remove,
644 module_platform_driver(sdhci_dwcmshc_driver);
646 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
647 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
648 MODULE_LICENSE("GPL v2");