drivers/mmc/host/sdhci-of-dwcmshc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
   4  *
   5  * Copyright (C) 2018 Synaptics Incorporated
   6  *
   7  * Author: Jisheng Zhang <jszhang@kernel.org>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/clk.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/reset.h>
  20 #include <linux/sizes.h>
  21
  22 #include "sdhci-pltfm.h"
  23
  24 #define SDHCI_DWCMSHC_ARG2_STUFF        GENMASK(31, 16)
  25
  26 /* DWCMSHC specific Mode Select value */
  27 #define DWCMSHC_CTRL_HS400              0x7
  28
  29 /* DWC IP vendor area 1 pointer */
  30 #define DWCMSHC_P_VENDOR_AREA1          0xe8
  31 #define DWCMSHC_AREA1_MASK              GENMASK(11, 0)
  32 /* Offset inside the  vendor area 1 */
  33 #define DWCMSHC_HOST_CTRL3              0x8
  34 #define DWCMSHC_EMMC_CONTROL            0x2c
  35 #define DWCMSHC_CARD_IS_EMMC            BIT(0)
  36 #define DWCMSHC_ENHANCED_STROBE         BIT(8)
  37 #define DWCMSHC_EMMC_ATCTRL             0x40
  38
  39 /* Rockchip specific Registers */
  40 #define DWCMSHC_EMMC_DLL_CTRL           0x800
  41 #define DWCMSHC_EMMC_DLL_RXCLK          0x804
  42 #define DWCMSHC_EMMC_DLL_TXCLK          0x808
  43 #define DWCMSHC_EMMC_DLL_STRBIN         0x80c
  44 #define DECMSHC_EMMC_DLL_CMDOUT         0x810
  45 #define DWCMSHC_EMMC_DLL_STATUS0        0x840
  46 #define DWCMSHC_EMMC_DLL_START          BIT(0)
  47 #define DWCMSHC_EMMC_DLL_LOCKED         BIT(8)
  48 #define DWCMSHC_EMMC_DLL_TIMEOUT        BIT(9)
  49 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL   29
  50 #define DWCMSHC_EMMC_DLL_START_POINT    16
  51 #define DWCMSHC_EMMC_DLL_INC            8
  52 #define DWCMSHC_EMMC_DLL_BYPASS         BIT(24)
  53 #define DWCMSHC_EMMC_DLL_DLYENA         BIT(27)
  54 #define DLL_TXCLK_TAPNUM_DEFAULT        0x10
  55 #define DLL_TXCLK_TAPNUM_90_DEGREES     0xA
  56 #define DLL_TXCLK_TAPNUM_FROM_SW        BIT(24)
  57 #define DLL_STRBIN_TAPNUM_DEFAULT       0x8
  58 #define DLL_STRBIN_TAPNUM_FROM_SW       BIT(24)
  59 #define DLL_STRBIN_DELAY_NUM_SEL        BIT(26)
  60 #define DLL_STRBIN_DELAY_NUM_OFFSET     16
  61 #define DLL_STRBIN_DELAY_NUM_DEFAULT    0x16
  62 #define DLL_RXCLK_NO_INVERTER           1
  63 #define DLL_RXCLK_INVERTER              0
  64 #define DLL_CMDOUT_TAPNUM_90_DEGREES    0x8
  65 #define DLL_RXCLK_ORI_GATE              BIT(31)
  66 #define DLL_CMDOUT_TAPNUM_FROM_SW       BIT(24)
  67 #define DLL_CMDOUT_SRC_CLK_NEG          BIT(28)
  68 #define DLL_CMDOUT_EN_SRC_CLK_NEG       BIT(29)
  69
  70 #define DLL_LOCK_WO_TMOUT(x) \
  71         ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
  72         (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
  73 #define RK35xx_MAX_CLKS 3
  74
  75 #define BOUNDARY_OK(addr, len) \
  76         ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
  77
  78 enum dwcmshc_rk_type {
  79         DWCMSHC_RK3568,
  80         DWCMSHC_RK3588,
  81 };
  82
  83 struct rk35xx_priv {
  84         /* Rockchip specified optional clocks */
  85         struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
  86         struct reset_control *reset;
  87         enum dwcmshc_rk_type devtype;
  88         u8 txclk_tapnum;
  89 };
  90
  91 struct dwcmshc_priv {
  92         struct clk      *bus_clk;
  93         struct clk      *sdio_clk;
  94         int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
  95         void *priv; /* pointer to SoC private stuff */
  96 };
  97
  98 /*
  99  * If DMA addr spans 128MB boundary, we split the DMA transfer into two
 100  * so that each DMA transfer doesn't exceed the boundary.
 101  */
 102 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
 103                                     dma_addr_t addr, int len, unsigned int cmd)
 104 {
 105         int tmplen, offset;
 106
 107         if (likely(!len || BOUNDARY_OK(addr, len))) {
 108                 sdhci_adma_write_desc(host, desc, addr, len, cmd);
 109                 return;
 110         }
 111
 112         offset = addr & (SZ_128M - 1);
 113         tmplen = SZ_128M - offset;
 114         sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
 115
 116         addr += tmplen;
 117         len -= tmplen;
 118         sdhci_adma_write_desc(host, desc, addr, len, cmd);
 119 }
 120
 121 static void dwcmshc_set_clock(struct sdhci_host *host, unsigned int clock)
 122 {
 123         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 124         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 125
 126         if (priv->sdio_clk)
 127                 clk_set_rate(priv->sdio_clk, clock);
 128
 129         sdhci_set_clock(host, clock);
 130 }
 131
 132 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
 133 {
 134         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 135
 136         if (pltfm_host->clk)
 137                 return sdhci_pltfm_clk_get_max_clock(host);
 138         else
 139                 return pltfm_host->clock;
 140 }
 141
 142 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
 143 {
 144         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 145
 146         return clk_round_rate(pltfm_host->clk, ULONG_MAX);
 147 }
 148
 149 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
 150                                      struct mmc_request *mrq)
 151 {
 152         struct sdhci_host *host = mmc_priv(mmc);
 153
 154         /*
 155          * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
 156          * block count register which doesn't support stuff bits of
 157          * CMD23 argument on dwcmsch host controller.
 158          */
 159         if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
 160                 host->flags &= ~SDHCI_AUTO_CMD23;
 161         else
 162                 host->flags |= SDHCI_AUTO_CMD23;
 163 }
 164
 165 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 166 {
 167         dwcmshc_check_auto_cmd23(mmc, mrq);
 168
 169         sdhci_request(mmc, mrq);
 170 }
 171
 172 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
 173                                       unsigned int timing)
 174 {
 175         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 176         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 177         u16 ctrl, ctrl_2;
 178
 179         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 180         /* Select Bus Speed Mode for host */
 181         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 182         if ((timing == MMC_TIMING_MMC_HS200) ||
 183             (timing == MMC_TIMING_UHS_SDR104))
 184                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 185         else if (timing == MMC_TIMING_UHS_SDR12)
 186                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 187         else if ((timing == MMC_TIMING_UHS_SDR25) ||
 188                  (timing == MMC_TIMING_MMC_HS))
 189                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 190         else if (timing == MMC_TIMING_UHS_SDR50)
 191                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 192         else if ((timing == MMC_TIMING_UHS_DDR50) ||
 193                  (timing == MMC_TIMING_MMC_DDR52))
 194                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 195         else if (timing == MMC_TIMING_MMC_HS400) {
 196                 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
 197                 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
 198                 ctrl |= DWCMSHC_CARD_IS_EMMC;
 199                 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
 200
 201                 ctrl_2 |= DWCMSHC_CTRL_HS400;
 202         }
 203
 204         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 205 }
 206
 207 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
 208                                           struct mmc_ios *ios)
 209 {
 210         u32 vendor;
 211         struct sdhci_host *host = mmc_priv(mmc);
 212         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 213         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 214         int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
 215
 216         vendor = sdhci_readl(host, reg);
 217         if (ios->enhanced_strobe)
 218                 vendor |= DWCMSHC_ENHANCED_STROBE;
 219         else
 220                 vendor &= ~DWCMSHC_ENHANCED_STROBE;
 221
 222         sdhci_writel(host, vendor, reg);
 223 }
 224
 225 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
 226 {
 227         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 228         struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
 229         struct rk35xx_priv *priv = dwc_priv->priv;
 230         u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
 231         u32 extra, reg;
 232         int err;
 233
 234         host->mmc->actual_clock = 0;
 235
 236         if (clock == 0) {
 237                 /* Disable interface clock at initial state. */
 238                 sdhci_set_clock(host, clock);
 239                 return;
 240         }
 241
 242         /* Rockchip platform only support 375KHz for identify mode */
 243         if (clock <= 400000)
 244                 clock = 375000;
 245
 246         err = clk_set_rate(pltfm_host->clk, clock);
 247         if (err)
 248                 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
 249
 250         sdhci_set_clock(host, clock);
 251
 252         /* Disable cmd conflict check */
 253         reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
 254         extra = sdhci_readl(host, reg);
 255         extra &= ~BIT(0);
 256         sdhci_writel(host, extra, reg);
 257
 258         if (clock <= 52000000) {
 259                 /*
 260                  * Disable DLL and reset both of sample and drive clock.
 261                  * The bypass bit and start bit need to be set if DLL is not locked.
 262                  */
 263                 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
 264                 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
 265                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 266                 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
 267                 /*
 268                  * Before switching to hs400es mode, the driver will enable
 269                  * enhanced strobe first. PHY needs to configure the parameters
 270                  * of enhanced strobe first.
 271                  */
 272                 extra = DWCMSHC_EMMC_DLL_DLYENA |
 273                         DLL_STRBIN_DELAY_NUM_SEL |
 274                         DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
 275                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 276                 return;
 277         }
 278
 279         /* Reset DLL */
 280         sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
 281         udelay(1);
 282         sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
 283
 284         /*
 285          * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
 286          * we must set it in higher speed mode.
 287          */
 288         extra = DWCMSHC_EMMC_DLL_DLYENA;
 289         if (priv->devtype == DWCMSHC_RK3568)
 290                 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 291         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 292
 293         /* Init DLL settings */
 294         extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
 295                 0x2 << DWCMSHC_EMMC_DLL_INC |
 296                 DWCMSHC_EMMC_DLL_START;
 297         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
 298         err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
 299                                  extra, DLL_LOCK_WO_TMOUT(extra), 1,
 300                                  500 * USEC_PER_MSEC);
 301         if (err) {
 302                 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
 303                 return;
 304         }
 305
 306         extra = 0x1 << 16 | /* tune clock stop en */
 307                 0x3 << 17 | /* pre-change delay */
 308                 0x3 << 19;  /* post-change delay */
 309         sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
 310
 311         if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
 312             host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
 313                 txclk_tapnum = priv->txclk_tapnum;
 314
 315         if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
 316                 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
 317
 318                 extra = DLL_CMDOUT_SRC_CLK_NEG |
 319                         DLL_CMDOUT_EN_SRC_CLK_NEG |
 320                         DWCMSHC_EMMC_DLL_DLYENA |
 321                         DLL_CMDOUT_TAPNUM_90_DEGREES |
 322                         DLL_CMDOUT_TAPNUM_FROM_SW;
 323                 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
 324         }
 325
 326         extra = DWCMSHC_EMMC_DLL_DLYENA |
 327                 DLL_TXCLK_TAPNUM_FROM_SW |
 328                 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
 329                 txclk_tapnum;
 330         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
 331
 332         extra = DWCMSHC_EMMC_DLL_DLYENA |
 333                 DLL_STRBIN_TAPNUM_DEFAULT |
 334                 DLL_STRBIN_TAPNUM_FROM_SW;
 335         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 336 }
 337
 338 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
 339 {
 340         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 341         struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
 342         struct rk35xx_priv *priv = dwc_priv->priv;
 343
 344         if (mask & SDHCI_RESET_ALL && priv->reset) {
 345                 reset_control_assert(priv->reset);
 346                 udelay(1);
 347                 reset_control_deassert(priv->reset);
 348         }
 349
 350         sdhci_reset(host, mask);
 351 }
 352
 353 static const struct sdhci_ops sdhci_dwcmshc_ops = {
 354         .set_clock              = dwcmshc_set_clock,
 355         .set_bus_width          = sdhci_set_bus_width,
 356         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
 357         .get_max_clock          = dwcmshc_get_max_clock,
 358         .get_timeout_clock      = sdhci_pltfm_clk_get_timeout_clock,
 359         .reset                  = sdhci_reset,
 360         .adma_write_desc        = dwcmshc_adma_write_desc,
 361 };
 362
 363 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
 364         .set_clock              = dwcmshc_rk3568_set_clock,
 365         .set_bus_width          = sdhci_set_bus_width,
 366         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
 367         .get_max_clock          = rk35xx_get_max_clock,
 368         .reset                  = rk35xx_sdhci_reset,
 369         .adma_write_desc        = dwcmshc_adma_write_desc,
 370 };
 371
 372 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
 373         .ops = &sdhci_dwcmshc_ops,
 374         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 375                   SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 376         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 377                    SDHCI_QUIRK2_BROKEN_HS200,
 378 };
 379
 380 #ifdef CONFIG_ACPI
 381 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
 382         .ops = &sdhci_dwcmshc_ops,
 383         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 384         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 385                    SDHCI_QUIRK2_ACMD23_BROKEN,
 386 };
 387 #endif
 388
 389 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
 390         .ops = &sdhci_dwcmshc_rk35xx_ops,
 391         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 392                   SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
 393         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 394                    SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
 395                     SDHCI_QUIRK2_NO_SDR50 |
 396                     SDHCI_QUIRK2_NO_SDR104 |
 397                     SDHCI_QUIRK2_NO_SDR25,
 398 };
 399
 400 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
 401 {
 402         int err;
 403         struct rk35xx_priv *priv = dwc_priv->priv;
 404
 405         priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
 406         if (IS_ERR(priv->reset)) {
 407                 err = PTR_ERR(priv->reset);
 408                 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
 409                 return err;
 410         }
 411
 412         priv->rockchip_clks[0].id = "axi";
 413         priv->rockchip_clks[1].id = "block";
 414         priv->rockchip_clks[2].id = "timer";
 415         err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
 416                                          priv->rockchip_clks);
 417         if (err) {
 418                 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
 419                 return err;
 420         }
 421
 422         err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
 423         if (err) {
 424                 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
 425                 return err;
 426         }
 427
 428         if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
 429                                 &priv->txclk_tapnum))
 430                 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
 431
 432         /* Disable cmd conflict check */
 433         sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
 434         /* Reset previous settings */
 435         sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 436         sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
 437
 438         return 0;
 439 }
 440
 441 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
 442 {
 443         /*
 444          * Don't support highspeed bus mode with low clk speed as we
 445          * cannot use DLL for this condition.
 446          */
 447         if (host->mmc->f_max <= 52000000) {
 448                 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
 449                          host->mmc->f_max);
 450                 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
 451                 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
 452         }
 453 }
 454
 455 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
 456         {
 457                 .compatible = "rockchip,rk3588-dwcmshc",
 458                 .data = &sdhci_dwcmshc_rk35xx_pdata,
 459         },
 460         {
 461                 .compatible = "rockchip,rk3568-dwcmshc",
 462                 .data = &sdhci_dwcmshc_rk35xx_pdata,
 463         },
 464         {
 465                 .compatible = "snps,dwcmshc-sdhci",
 466                 .data = &sdhci_dwcmshc_pdata,
 467         },
 468         {},
 469 };
 470 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
 471
 472 #ifdef CONFIG_ACPI
 473 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
 474         {
 475                 .id = "MLNXBF30",
 476                 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
 477         },
 478         {}
 479 };
 480 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids);
 481 #endif
 482
 483 static int dwcmshc_probe(struct platform_device *pdev)
 484 {
 485         struct device *dev = &pdev->dev;
 486         struct sdhci_pltfm_host *pltfm_host;
 487         struct sdhci_host *host;
 488         struct dwcmshc_priv *priv;
 489         struct rk35xx_priv *rk_priv = NULL;
 490         const struct sdhci_pltfm_data *pltfm_data;
 491         int err;
 492         u32 extra;
 493
 494         pltfm_data = device_get_match_data(&pdev->dev);
 495         if (!pltfm_data) {
 496                 dev_err(&pdev->dev, "Error: No device match data found\n");
 497                 return -ENODEV;
 498         }
 499
 500         host = sdhci_pltfm_init(pdev, pltfm_data,
 501                                 sizeof(struct dwcmshc_priv));
 502         if (IS_ERR(host))
 503                 return PTR_ERR(host);
 504
 505         /*
 506          * extra adma table cnt for cross 128M boundary handling.
 507          */
 508         extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
 509         if (extra > SDHCI_MAX_SEGS)
 510                 extra = SDHCI_MAX_SEGS;
 511         host->adma_table_cnt += extra;
 512
 513         pltfm_host = sdhci_priv(host);
 514         priv = sdhci_pltfm_priv(pltfm_host);
 515
 516         if (dev->of_node) {
 517                 pltfm_host->clk = devm_clk_get(dev, "core");
 518                 if (IS_ERR(pltfm_host->clk)) {
 519                         err = PTR_ERR(pltfm_host->clk);
 520                         dev_err(dev, "failed to get core clk: %d\n", err);
 521                         goto free_pltfm;
 522                 }
 523                 err = clk_prepare_enable(pltfm_host->clk);
 524                 if (err)
 525                         goto free_pltfm;
 526
 527                 priv->bus_clk = devm_clk_get(dev, "bus");
 528                 if (!IS_ERR(priv->bus_clk))
 529                         clk_prepare_enable(priv->bus_clk);
 530
 531                 pltfm_host->timeout_clk = devm_clk_get(dev, "timeout");
 532                 if (!IS_ERR(pltfm_host->timeout_clk))
 533                         err = clk_prepare_enable(pltfm_host->timeout_clk);
 534                 if (err)
 535                         goto free_pltfm;
 536
 537                 priv->sdio_clk = devm_clk_get_optional(&pdev->dev, "sdio");
 538         }
 539
 540         pltfm_host->timeout_clk = devm_clk_get(&pdev->dev, "timeout");
 541         if (IS_ERR(pltfm_host->timeout_clk)) {
 542                 err = PTR_ERR(pltfm_host->timeout_clk);
 543                 dev_err(&pdev->dev, "failed to get timeout clk: %d\n", err);
 544                 goto free_pltfm;
 545         }
 546         err = clk_prepare_enable(pltfm_host->timeout_clk);
 547         if (err)
 548                 goto free_pltfm;
 549
 550         err = mmc_of_parse(host->mmc);
 551         if (err)
 552                 goto err_clk;
 553
 554         sdhci_get_of_property(pdev);
 555         sdhci_enable_v4_mode(host);
 556
 557         priv->vendor_specific_area1 =
 558                 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
 559
 560         host->mmc_host_ops.request = dwcmshc_request;
 561         host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
 562
 563         if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) {
 564                 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
 565                 if (!rk_priv) {
 566                         err = -ENOMEM;
 567                         goto err_clk;
 568                 }
 569
 570                 if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
 571                         rk_priv->devtype = DWCMSHC_RK3588;
 572                 else
 573                         rk_priv->devtype = DWCMSHC_RK3568;
 574
 575                 priv->priv = rk_priv;
 576
 577                 err = dwcmshc_rk35xx_init(host, priv);
 578                 if (err)
 579                         goto err_clk;
 580         }
 581
 582 #ifdef CONFIG_ACPI
 583         if (pltfm_data == &sdhci_dwcmshc_bf3_pdata)
 584                 sdhci_enable_v4_mode(host);
 585 #endif
 586
 587         host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
 588
 589         pm_runtime_get_noresume(dev);
 590         pm_runtime_set_active(dev);
 591         pm_runtime_enable(dev);
 592
 593         err = sdhci_setup_host(host);
 594         if (err)
 595                 goto err_rpm;
 596
 597         if (rk_priv)
 598                 dwcmshc_rk35xx_postinit(host, priv);
 599
 600         err = __sdhci_add_host(host);
 601         if (err)
 602                 goto err_setup_host;
 603
 604         pm_runtime_put(dev);
 605
 606         return 0;
 607
 608 err_setup_host:
 609         sdhci_cleanup_host(host);
 610 err_rpm:
 611         pm_runtime_disable(dev);
 612         pm_runtime_put_noidle(dev);
 613 err_clk:
 614         clk_disable_unprepare(pltfm_host->clk);
 615         clk_disable_unprepare(pltfm_host->timeout_clk);
 616         clk_disable_unprepare(priv->bus_clk);
 617         if (rk_priv)
 618                 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
 619                                            rk_priv->rockchip_clks);
 620 free_pltfm:
 621         sdhci_pltfm_free(pdev);
 622         return err;
 623 }
 624
 625 static void dwcmshc_remove(struct platform_device *pdev)
 626 {
 627         struct sdhci_host *host = platform_get_drvdata(pdev);
 628         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 629         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 630         struct rk35xx_priv *rk_priv = priv->priv;
 631
 632         sdhci_remove_host(host, 0);
 633
 634         clk_disable_unprepare(pltfm_host->clk);
 635         clk_disable_unprepare(priv->bus_clk);
 636         if (rk_priv)
 637                 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
 638                                            rk_priv->rockchip_clks);
 639         sdhci_pltfm_free(pdev);
 640 }
 641
 642 #ifdef CONFIG_PM_SLEEP
 643 static int dwcmshc_suspend(struct device *dev)
 644 {
 645         struct sdhci_host *host = dev_get_drvdata(dev);
 646         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 647         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 648         struct rk35xx_priv *rk_priv = priv->priv;
 649         int ret;
 650
 651         pm_runtime_resume(dev);
 652
 653         ret = sdhci_suspend_host(host);
 654         if (ret)
 655                 return ret;
 656
 657         clk_disable_unprepare(pltfm_host->clk);
 658         if (!IS_ERR(priv->bus_clk))
 659                 clk_disable_unprepare(priv->bus_clk);
 660
 661         if (rk_priv)
 662                 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
 663                                            rk_priv->rockchip_clks);
 664
 665         return ret;
 666 }
 667
 668 static int dwcmshc_resume(struct device *dev)
 669 {
 670         struct sdhci_host *host = dev_get_drvdata(dev);
 671         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 672         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 673         struct rk35xx_priv *rk_priv = priv->priv;
 674         int ret;
 675
 676         ret = clk_prepare_enable(pltfm_host->clk);
 677         if (ret)
 678                 return ret;
 679
 680         if (!IS_ERR(priv->bus_clk)) {
 681                 ret = clk_prepare_enable(priv->bus_clk);
 682                 if (ret)
 683                         goto disable_clk;
 684         }
 685
 686         if (rk_priv) {
 687                 ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
 688                                               rk_priv->rockchip_clks);
 689                 if (ret)
 690                         goto disable_bus_clk;
 691         }
 692
 693         ret = sdhci_resume_host(host);
 694         if (ret)
 695                 goto disable_rockchip_clks;
 696
 697         return 0;
 698
 699 disable_rockchip_clks:
 700         if (rk_priv)
 701                 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
 702                                            rk_priv->rockchip_clks);
 703 disable_bus_clk:
 704         if (!IS_ERR(priv->bus_clk))
 705                 clk_disable_unprepare(priv->bus_clk);
 706 disable_clk:
 707         clk_disable_unprepare(pltfm_host->clk);
 708         return ret;
 709 }
 710 #endif
 711
 712 #ifdef CONFIG_PM
 713
 714 static void dwcmshc_enable_card_clk(struct sdhci_host *host)
 715 {
 716         u16 ctrl;
 717
 718         ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 719         if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) {
 720                 ctrl |= SDHCI_CLOCK_CARD_EN;
 721                 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
 722         }
 723 }
 724
 725 static void dwcmshc_disable_card_clk(struct sdhci_host *host)
 726 {
 727         u16 ctrl;
 728
 729         ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 730         if (ctrl & SDHCI_CLOCK_CARD_EN) {
 731                 ctrl &= ~SDHCI_CLOCK_CARD_EN;
 732                 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
 733         }
 734 }
 735
 736 static int dwcmshc_runtime_suspend(struct device *dev)
 737 {
 738         struct sdhci_host *host = dev_get_drvdata(dev);
 739
 740         dwcmshc_disable_card_clk(host);
 741
 742         return 0;
 743 }
 744
 745 static int dwcmshc_runtime_resume(struct device *dev)
 746 {
 747         struct sdhci_host *host = dev_get_drvdata(dev);
 748
 749         dwcmshc_enable_card_clk(host);
 750
 751         return 0;
 752 }
 753
 754 #endif
 755
 756 static const struct dev_pm_ops dwcmshc_pmops = {
 757         SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume)
 758         SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend,
 759                            dwcmshc_runtime_resume, NULL)
 760 };
 761
 762 static struct platform_driver sdhci_dwcmshc_driver = {
 763         .driver = {
 764                 .name   = "sdhci-dwcmshc",
 765                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 766                 .of_match_table = sdhci_dwcmshc_dt_ids,
 767                 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
 768                 .pm = &dwcmshc_pmops,
 769         },
 770         .probe  = dwcmshc_probe,
 771         .remove_new = dwcmshc_remove,
 772 };
 773 module_platform_driver(sdhci_dwcmshc_driver);
 774
 775 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
 776 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
 777 MODULE_LICENSE("GPL v2");