drivers/mmc/host/sdhci-of-dwcmshc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
   4  *
   5  * Copyright (C) 2018 Synaptics Incorporated
   6  *
   7  * Author: Jisheng Zhang <jszhang@kernel.org>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/clk.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/reset.h>
  19 #include <linux/sizes.h>
  20
  21 #include "sdhci-pltfm.h"
  22
  23 #define SDHCI_DWCMSHC_ARG2_STUFF        GENMASK(31, 16)
  24
  25 /* DWCMSHC specific Mode Select value */
  26 #define DWCMSHC_CTRL_HS400              0x7
  27
  28 /* DWC IP vendor area 1 pointer */
  29 #define DWCMSHC_P_VENDOR_AREA1          0xe8
  30 #define DWCMSHC_AREA1_MASK              GENMASK(11, 0)
  31 /* Offset inside the  vendor area 1 */
  32 #define DWCMSHC_HOST_CTRL3              0x8
  33 #define DWCMSHC_EMMC_CONTROL            0x2c
  34 #define DWCMSHC_CARD_IS_EMMC            BIT(0)
  35 #define DWCMSHC_ENHANCED_STROBE         BIT(8)
  36 #define DWCMSHC_EMMC_ATCTRL             0x40
  37
  38 /* Rockchip specific Registers */
  39 #define DWCMSHC_EMMC_DLL_CTRL           0x800
  40 #define DWCMSHC_EMMC_DLL_RXCLK          0x804
  41 #define DWCMSHC_EMMC_DLL_TXCLK          0x808
  42 #define DWCMSHC_EMMC_DLL_STRBIN         0x80c
  43 #define DECMSHC_EMMC_DLL_CMDOUT         0x810
  44 #define DWCMSHC_EMMC_DLL_STATUS0        0x840
  45 #define DWCMSHC_EMMC_DLL_START          BIT(0)
  46 #define DWCMSHC_EMMC_DLL_LOCKED         BIT(8)
  47 #define DWCMSHC_EMMC_DLL_TIMEOUT        BIT(9)
  48 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL   29
  49 #define DWCMSHC_EMMC_DLL_START_POINT    16
  50 #define DWCMSHC_EMMC_DLL_INC            8
  51 #define DWCMSHC_EMMC_DLL_DLYENA         BIT(27)
  52 #define DLL_TXCLK_TAPNUM_DEFAULT        0x10
  53 #define DLL_TXCLK_TAPNUM_90_DEGREES     0xA
  54 #define DLL_TXCLK_TAPNUM_FROM_SW        BIT(24)
  55 #define DLL_STRBIN_TAPNUM_DEFAULT       0x8
  56 #define DLL_STRBIN_TAPNUM_FROM_SW       BIT(24)
  57 #define DLL_STRBIN_DELAY_NUM_SEL        BIT(26)
  58 #define DLL_STRBIN_DELAY_NUM_OFFSET     16
  59 #define DLL_STRBIN_DELAY_NUM_DEFAULT    0x16
  60 #define DLL_RXCLK_NO_INVERTER           1
  61 #define DLL_RXCLK_INVERTER              0
  62 #define DLL_CMDOUT_TAPNUM_90_DEGREES    0x8
  63 #define DLL_CMDOUT_TAPNUM_FROM_SW       BIT(24)
  64 #define DLL_CMDOUT_SRC_CLK_NEG          BIT(28)
  65 #define DLL_CMDOUT_EN_SRC_CLK_NEG       BIT(29)
  66
  67 #define DLL_LOCK_WO_TMOUT(x) \
  68         ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
  69         (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
  70 #define RK35xx_MAX_CLKS 3
  71
  72 #define BOUNDARY_OK(addr, len) \
  73         ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
  74
  75 enum dwcmshc_rk_type {
  76         DWCMSHC_RK3568,
  77         DWCMSHC_RK3588,
  78 };
  79
  80 struct rk35xx_priv {
  81         /* Rockchip specified optional clocks */
  82         struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
  83         struct reset_control *reset;
  84         enum dwcmshc_rk_type devtype;
  85         u8 txclk_tapnum;
  86 };
  87
  88 struct dwcmshc_priv {
  89         struct clk      *bus_clk;
  90         int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
  91         void *priv; /* pointer to SoC private stuff */
  92 };
  93
  94 /*
  95  * If DMA addr spans 128MB boundary, we split the DMA transfer into two
  96  * so that each DMA transfer doesn't exceed the boundary.
  97  */
  98 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
  99                                     dma_addr_t addr, int len, unsigned int cmd)
 100 {
 101         int tmplen, offset;
 102
 103         if (likely(!len || BOUNDARY_OK(addr, len))) {
 104                 sdhci_adma_write_desc(host, desc, addr, len, cmd);
 105                 return;
 106         }
 107
 108         offset = addr & (SZ_128M - 1);
 109         tmplen = SZ_128M - offset;
 110         sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
 111
 112         addr += tmplen;
 113         len -= tmplen;
 114         sdhci_adma_write_desc(host, desc, addr, len, cmd);
 115 }
 116
 117 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
 118 {
 119         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 120
 121         if (pltfm_host->clk)
 122                 return sdhci_pltfm_clk_get_max_clock(host);
 123         else
 124                 return pltfm_host->clock;
 125 }
 126
 127 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
 128                                      struct mmc_request *mrq)
 129 {
 130         struct sdhci_host *host = mmc_priv(mmc);
 131
 132         /*
 133          * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
 134          * block count register which doesn't support stuff bits of
 135          * CMD23 argument on dwcmsch host controller.
 136          */
 137         if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
 138                 host->flags &= ~SDHCI_AUTO_CMD23;
 139         else
 140                 host->flags |= SDHCI_AUTO_CMD23;
 141 }
 142
 143 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 144 {
 145         dwcmshc_check_auto_cmd23(mmc, mrq);
 146
 147         sdhci_request(mmc, mrq);
 148 }
 149
 150 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
 151                                       unsigned int timing)
 152 {
 153         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 154         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 155         u16 ctrl, ctrl_2;
 156
 157         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 158         /* Select Bus Speed Mode for host */
 159         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 160         if ((timing == MMC_TIMING_MMC_HS200) ||
 161             (timing == MMC_TIMING_UHS_SDR104))
 162                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 163         else if (timing == MMC_TIMING_UHS_SDR12)
 164                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 165         else if ((timing == MMC_TIMING_UHS_SDR25) ||
 166                  (timing == MMC_TIMING_MMC_HS))
 167                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 168         else if (timing == MMC_TIMING_UHS_SDR50)
 169                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 170         else if ((timing == MMC_TIMING_UHS_DDR50) ||
 171                  (timing == MMC_TIMING_MMC_DDR52))
 172                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 173         else if (timing == MMC_TIMING_MMC_HS400) {
 174                 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
 175                 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
 176                 ctrl |= DWCMSHC_CARD_IS_EMMC;
 177                 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
 178
 179                 ctrl_2 |= DWCMSHC_CTRL_HS400;
 180         }
 181
 182         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 183 }
 184
 185 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
 186                                           struct mmc_ios *ios)
 187 {
 188         u32 vendor;
 189         struct sdhci_host *host = mmc_priv(mmc);
 190         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 191         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 192         int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
 193
 194         vendor = sdhci_readl(host, reg);
 195         if (ios->enhanced_strobe)
 196                 vendor |= DWCMSHC_ENHANCED_STROBE;
 197         else
 198                 vendor &= ~DWCMSHC_ENHANCED_STROBE;
 199
 200         sdhci_writel(host, vendor, reg);
 201 }
 202
 203 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
 204 {
 205         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 206         struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
 207         struct rk35xx_priv *priv = dwc_priv->priv;
 208         u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
 209         u32 extra, reg;
 210         int err;
 211
 212         host->mmc->actual_clock = 0;
 213
 214         if (clock == 0) {
 215                 /* Disable interface clock at initial state. */
 216                 sdhci_set_clock(host, clock);
 217                 return;
 218         }
 219
 220         /* Rockchip platform only support 375KHz for identify mode */
 221         if (clock <= 400000)
 222                 clock = 375000;
 223
 224         err = clk_set_rate(pltfm_host->clk, clock);
 225         if (err)
 226                 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
 227
 228         sdhci_set_clock(host, clock);
 229
 230         /* Disable cmd conflict check */
 231         reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
 232         extra = sdhci_readl(host, reg);
 233         extra &= ~BIT(0);
 234         sdhci_writel(host, extra, reg);
 235
 236         if (clock <= 52000000) {
 237                 /* Disable DLL and reset both of sample and drive clock */
 238                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
 239                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
 240                 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 241                 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
 242                 /*
 243                  * Before switching to hs400es mode, the driver will enable
 244                  * enhanced strobe first. PHY needs to configure the parameters
 245                  * of enhanced strobe first.
 246                  */
 247                 extra = DWCMSHC_EMMC_DLL_DLYENA |
 248                         DLL_STRBIN_DELAY_NUM_SEL |
 249                         DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
 250                 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 251                 return;
 252         }
 253
 254         /* Reset DLL */
 255         sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
 256         udelay(1);
 257         sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
 258
 259         /*
 260          * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
 261          * we must set it in higher speed mode.
 262          */
 263         extra = DWCMSHC_EMMC_DLL_DLYENA;
 264         if (priv->devtype == DWCMSHC_RK3568)
 265                 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 266         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 267
 268         /* Init DLL settings */
 269         extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
 270                 0x2 << DWCMSHC_EMMC_DLL_INC |
 271                 DWCMSHC_EMMC_DLL_START;
 272         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
 273         err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
 274                                  extra, DLL_LOCK_WO_TMOUT(extra), 1,
 275                                  500 * USEC_PER_MSEC);
 276         if (err) {
 277                 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
 278                 return;
 279         }
 280
 281         extra = 0x1 << 16 | /* tune clock stop en */
 282                 0x2 << 17 | /* pre-change delay */
 283                 0x3 << 19;  /* post-change delay */
 284         sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
 285
 286         if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
 287             host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
 288                 txclk_tapnum = priv->txclk_tapnum;
 289
 290         if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
 291                 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
 292
 293                 extra = DLL_CMDOUT_SRC_CLK_NEG |
 294                         DLL_CMDOUT_EN_SRC_CLK_NEG |
 295                         DWCMSHC_EMMC_DLL_DLYENA |
 296                         DLL_CMDOUT_TAPNUM_90_DEGREES |
 297                         DLL_CMDOUT_TAPNUM_FROM_SW;
 298                 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
 299         }
 300
 301         extra = DWCMSHC_EMMC_DLL_DLYENA |
 302                 DLL_TXCLK_TAPNUM_FROM_SW |
 303                 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
 304                 txclk_tapnum;
 305         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
 306
 307         extra = DWCMSHC_EMMC_DLL_DLYENA |
 308                 DLL_STRBIN_TAPNUM_DEFAULT |
 309                 DLL_STRBIN_TAPNUM_FROM_SW;
 310         sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 311 }
 312
 313 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
 314 {
 315         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 316         struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
 317         struct rk35xx_priv *priv = dwc_priv->priv;
 318
 319         if (mask & SDHCI_RESET_ALL && priv->reset) {
 320                 reset_control_assert(priv->reset);
 321                 udelay(1);
 322                 reset_control_deassert(priv->reset);
 323         }
 324
 325         sdhci_reset(host, mask);
 326 }
 327
 328 static const struct sdhci_ops sdhci_dwcmshc_ops = {
 329         .set_clock              = sdhci_set_clock,
 330         .set_bus_width          = sdhci_set_bus_width,
 331         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
 332         .get_max_clock          = dwcmshc_get_max_clock,
 333         .reset                  = sdhci_reset,
 334         .adma_write_desc        = dwcmshc_adma_write_desc,
 335 };
 336
 337 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
 338         .set_clock              = dwcmshc_rk3568_set_clock,
 339         .set_bus_width          = sdhci_set_bus_width,
 340         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
 341         .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
 342         .reset                  = rk35xx_sdhci_reset,
 343         .adma_write_desc        = dwcmshc_adma_write_desc,
 344 };
 345
 346 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
 347         .ops = &sdhci_dwcmshc_ops,
 348         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 349         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 350 };
 351
 352 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
 353         .ops = &sdhci_dwcmshc_rk35xx_ops,
 354         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 355                   SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
 356         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 357                    SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
 358 };
 359
 360 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
 361 {
 362         int err;
 363         struct rk35xx_priv *priv = dwc_priv->priv;
 364
 365         priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
 366         if (IS_ERR(priv->reset)) {
 367                 err = PTR_ERR(priv->reset);
 368                 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
 369                 return err;
 370         }
 371
 372         priv->rockchip_clks[0].id = "axi";
 373         priv->rockchip_clks[1].id = "block";
 374         priv->rockchip_clks[2].id = "timer";
 375         err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
 376                                          priv->rockchip_clks);
 377         if (err) {
 378                 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
 379                 return err;
 380         }
 381
 382         err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
 383         if (err) {
 384                 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
 385                 return err;
 386         }
 387
 388         if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
 389                                 &priv->txclk_tapnum))
 390                 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
 391
 392         /* Disable cmd conflict check */
 393         sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
 394         /* Reset previous settings */
 395         sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 396         sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
 397
 398         return 0;
 399 }
 400
 401 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
 402 {
 403         /*
 404          * Don't support highspeed bus mode with low clk speed as we
 405          * cannot use DLL for this condition.
 406          */
 407         if (host->mmc->f_max <= 52000000) {
 408                 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
 409                          host->mmc->f_max);
 410                 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
 411                 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
 412         }
 413 }
 414
 415 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
 416         {
 417                 .compatible = "rockchip,rk3588-dwcmshc",
 418                 .data = &sdhci_dwcmshc_rk35xx_pdata,
 419         },
 420         {
 421                 .compatible = "rockchip,rk3568-dwcmshc",
 422                 .data = &sdhci_dwcmshc_rk35xx_pdata,
 423         },
 424         {
 425                 .compatible = "snps,dwcmshc-sdhci",
 426                 .data = &sdhci_dwcmshc_pdata,
 427         },
 428         {},
 429 };
 430 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
 431
 432 #ifdef CONFIG_ACPI
 433 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
 434         { .id = "MLNXBF30" },
 435         {}
 436 };
 437 #endif
 438
 439 static int dwcmshc_probe(struct platform_device *pdev)
 440 {
 441         struct device *dev = &pdev->dev;
 442         struct sdhci_pltfm_host *pltfm_host;
 443         struct sdhci_host *host;
 444         struct dwcmshc_priv *priv;
 445         struct rk35xx_priv *rk_priv = NULL;
 446         const struct sdhci_pltfm_data *pltfm_data;
 447         int err;
 448         u32 extra;
 449
 450         pltfm_data = of_device_get_match_data(&pdev->dev);
 451         if (!pltfm_data) {
 452                 dev_err(&pdev->dev, "Error: No device match data found\n");
 453                 return -ENODEV;
 454         }
 455
 456         host = sdhci_pltfm_init(pdev, pltfm_data,
 457                                 sizeof(struct dwcmshc_priv));
 458         if (IS_ERR(host))
 459                 return PTR_ERR(host);
 460
 461         /*
 462          * extra adma table cnt for cross 128M boundary handling.
 463          */
 464         extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
 465         if (extra > SDHCI_MAX_SEGS)
 466                 extra = SDHCI_MAX_SEGS;
 467         host->adma_table_cnt += extra;
 468
 469         pltfm_host = sdhci_priv(host);
 470         priv = sdhci_pltfm_priv(pltfm_host);
 471
 472         if (dev->of_node) {
 473                 pltfm_host->clk = devm_clk_get(dev, "core");
 474                 if (IS_ERR(pltfm_host->clk)) {
 475                         err = PTR_ERR(pltfm_host->clk);
 476                         dev_err(dev, "failed to get core clk: %d\n", err);
 477                         goto free_pltfm;
 478                 }
 479                 err = clk_prepare_enable(pltfm_host->clk);
 480                 if (err)
 481                         goto free_pltfm;
 482
 483                 priv->bus_clk = devm_clk_get(dev, "bus");
 484                 if (!IS_ERR(priv->bus_clk))
 485                         clk_prepare_enable(priv->bus_clk);
 486         }
 487
 488         err = mmc_of_parse(host->mmc);
 489         if (err)
 490                 goto err_clk;
 491
 492         sdhci_get_of_property(pdev);
 493
 494         priv->vendor_specific_area1 =
 495                 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
 496
 497         host->mmc_host_ops.request = dwcmshc_request;
 498         host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
 499
 500         if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) {
 501                 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
 502                 if (!rk_priv) {
 503                         err = -ENOMEM;
 504                         goto err_clk;
 505                 }
 506
 507                 if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
 508                         rk_priv->devtype = DWCMSHC_RK3588;
 509                 else
 510                         rk_priv->devtype = DWCMSHC_RK3568;
 511
 512                 priv->priv = rk_priv;
 513
 514                 err = dwcmshc_rk35xx_init(host, priv);
 515                 if (err)
 516                         goto err_clk;
 517         }
 518
 519         host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
 520
 521         err = sdhci_setup_host(host);
 522         if (err)
 523                 goto err_clk;
 524
 525         if (rk_priv)
 526                 dwcmshc_rk35xx_postinit(host, priv);
 527
 528         err = __sdhci_add_host(host);
 529         if (err)
 530                 goto err_setup_host;
 531
 532         return 0;
 533
 534 err_setup_host:
 535         sdhci_cleanup_host(host);
 536 err_clk:
 537         clk_disable_unprepare(pltfm_host->clk);
 538         clk_disable_unprepare(priv->bus_clk);
 539         if (rk_priv)
 540                 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
 541                                            rk_priv->rockchip_clks);
 542 free_pltfm:
 543         sdhci_pltfm_free(pdev);
 544         return err;
 545 }
 546
 547 static int dwcmshc_remove(struct platform_device *pdev)
 548 {
 549         struct sdhci_host *host = platform_get_drvdata(pdev);
 550         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 551         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 552         struct rk35xx_priv *rk_priv = priv->priv;
 553
 554         sdhci_remove_host(host, 0);
 555
 556         clk_disable_unprepare(pltfm_host->clk);
 557         clk_disable_unprepare(priv->bus_clk);
 558         if (rk_priv)
 559                 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
 560                                            rk_priv->rockchip_clks);
 561         sdhci_pltfm_free(pdev);
 562
 563         return 0;
 564 }
 565
 566 #ifdef CONFIG_PM_SLEEP
 567 static int dwcmshc_suspend(struct device *dev)
 568 {
 569         struct sdhci_host *host = dev_get_drvdata(dev);
 570         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 571         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 572         struct rk35xx_priv *rk_priv = priv->priv;
 573         int ret;
 574
 575         ret = sdhci_suspend_host(host);
 576         if (ret)
 577                 return ret;
 578
 579         clk_disable_unprepare(pltfm_host->clk);
 580         if (!IS_ERR(priv->bus_clk))
 581                 clk_disable_unprepare(priv->bus_clk);
 582
 583         if (rk_priv)
 584                 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
 585                                            rk_priv->rockchip_clks);
 586
 587         return ret;
 588 }
 589
 590 static int dwcmshc_resume(struct device *dev)
 591 {
 592         struct sdhci_host *host = dev_get_drvdata(dev);
 593         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 594         struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 595         struct rk35xx_priv *rk_priv = priv->priv;
 596         int ret;
 597
 598         ret = clk_prepare_enable(pltfm_host->clk);
 599         if (ret)
 600                 return ret;
 601
 602         if (!IS_ERR(priv->bus_clk)) {
 603                 ret = clk_prepare_enable(priv->bus_clk);
 604                 if (ret)
 605                         return ret;
 606         }
 607
 608         if (rk_priv) {
 609                 ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
 610                                               rk_priv->rockchip_clks);
 611                 if (ret)
 612                         return ret;
 613         }
 614
 615         return sdhci_resume_host(host);
 616 }
 617 #endif
 618
 619 static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
 620
 621 static struct platform_driver sdhci_dwcmshc_driver = {
 622         .driver = {
 623                 .name   = "sdhci-dwcmshc",
 624                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 625                 .of_match_table = sdhci_dwcmshc_dt_ids,
 626                 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
 627                 .pm = &dwcmshc_pmops,
 628         },
 629         .probe  = dwcmshc_probe,
 630         .remove = dwcmshc_remove,
 631 };
 632 module_platform_driver(sdhci_dwcmshc_driver);
 633
 634 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
 635 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
 636 MODULE_LICENSE("GPL v2");