1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Arasan Secure Digital Host Controller Interface.
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5 * Copyright (c) 2012 Wind River Systems, Inc.
6 * Copyright (C) 2013 Pengutronix e.K.
7 * Copyright (C) 2013 Xilinx Inc.
9 * Based on sdhci-of-esdhc.c
11 * Copyright (c) 2007 Freescale Semiconductor, Inc.
12 * Copyright (c) 2009 MontaVista Software, Inc.
14 * Authors: Xiaobo Xie <X.Xie@freescale.com>
15 * Anton Vorontsov <avorontsov@ru.mvista.com>
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/regmap.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
30 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
32 #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
33 #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
35 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
36 #define VENDOR_ENHANCED_STROBE BIT(0)
38 #define PHY_CLK_TOO_SLOW_HZ 400000
40 #define SDHCI_ITAPDLY_CHGWIN 0x200
41 #define SDHCI_ITAPDLY_ENABLE 0x100
42 #define SDHCI_OTAPDLY_ENABLE 0x40
44 /* Default settings for ZynqMP Clock Phases */
45 #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
46 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
48 #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
49 #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
52 * On some SoCs the syscon area has a feature where the upper 16-bits of
53 * each 32-bit register act as a write mask for the lower 16-bits. This allows
54 * atomic updates of the register without locking. This macro is used on SoCs
55 * that have that feature.
57 #define HIWORD_UPDATE(val, mask, shift) \
58 ((val) << (shift) | (mask) << ((shift) + 16))
61 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
63 * @reg: Offset within the syscon of the register containing this field
64 * @width: Number of bits for this field
65 * @shift: Bit offset within @reg of this field (or -1 if not avail)
67 struct sdhci_arasan_soc_ctl_field {
74 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
76 * @baseclkfreq: Where to find corecfg_baseclkfreq
77 * @clockmultiplier: Where to find corecfg_clockmultiplier
78 * @support64b: Where to find SUPPORT64B bit
79 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
81 * It's up to the licensee of the Arsan IP block to make these available
82 * somewhere if needed. Presumably these will be scattered somewhere that's
83 * accessible via the syscon API.
85 struct sdhci_arasan_soc_ctl_map {
86 struct sdhci_arasan_soc_ctl_field baseclkfreq;
87 struct sdhci_arasan_soc_ctl_field clockmultiplier;
88 struct sdhci_arasan_soc_ctl_field support64b;
93 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
95 * @sdcardclk_ops: The output clock related operations
96 * @sampleclk_ops: The sample clock related operations
98 struct sdhci_arasan_clk_ops {
99 const struct clk_ops *sdcardclk_ops;
100 const struct clk_ops *sampleclk_ops;
104 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
106 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
107 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
108 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
109 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
110 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
111 * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
112 * @set_clk_delays: Function pointer for setting Clock Delays
113 * @clk_of_data: Platform specific runtime clock data storage pointer
115 struct sdhci_arasan_clk_data {
116 struct clk_hw sdcardclk_hw;
117 struct clk *sdcardclk;
118 struct clk_hw sampleclk_hw;
119 struct clk *sampleclk;
120 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
121 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
122 void (*set_clk_delays)(struct sdhci_host *host);
126 struct sdhci_arasan_zynqmp_clk_data {
127 const struct zynqmp_eemi_ops *eemi_ops;
131 * struct sdhci_arasan_data - Arasan Controller Data
133 * @host: Pointer to the main SDHCI host structure.
134 * @clk_ahb: Pointer to the AHB clock
135 * @phy: Pointer to the generic phy
136 * @is_phy_on: True if the PHY is on; false if not.
137 * @has_cqe: True if controller has command queuing engine.
138 * @clk_data: Struct for the Arasan Controller Clock Data.
139 * @clk_ops: Struct for the Arasan Controller Clock Operations.
140 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
141 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
142 * @quirks: Arasan deviations from spec.
144 struct sdhci_arasan_data {
145 struct sdhci_host *host;
151 struct sdhci_arasan_clk_data clk_data;
152 const struct sdhci_arasan_clk_ops *clk_ops;
154 struct regmap *soc_ctl_base;
155 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
158 /* Controller does not have CD wired and will not function normally without */
159 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
160 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
161 * internal clock even when the clock isn't stable */
162 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
165 struct sdhci_arasan_of_data {
166 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
167 const struct sdhci_pltfm_data *pdata;
168 const struct sdhci_arasan_clk_ops *clk_ops;
171 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
172 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
173 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
174 .hiword_update = true,
177 static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
178 .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
179 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
180 .hiword_update = false,
183 static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
184 .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
185 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
186 .hiword_update = false,
189 static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
190 .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
191 .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
192 .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
193 .hiword_update = false,
197 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
199 * @host: The sdhci_host
200 * @fld: The field to write to
201 * @val: The value to write
203 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
204 * Note that if a field is specified as not available (shift < 0) then
205 * this function will silently return an error code. It will be noisy
206 * and print errors for any other (unexpected) errors.
208 * Return: 0 on success and error value on error
210 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
211 const struct sdhci_arasan_soc_ctl_field *fld,
214 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
215 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
216 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
218 u16 width = fld->width;
219 s16 shift = fld->shift;
223 * Silently return errors for shift < 0 so caller doesn't have
224 * to check for fields which are optional. For fields that
225 * are required then caller needs to do something special
231 if (sdhci_arasan->soc_ctl_map->hiword_update)
232 ret = regmap_write(soc_ctl_base, reg,
233 HIWORD_UPDATE(val, GENMASK(width, 0),
236 ret = regmap_update_bits(soc_ctl_base, reg,
237 GENMASK(shift + width, shift),
240 /* Yell about (unexpected) regmap errors */
242 pr_warn("%s: Regmap write fail: %d\n",
243 mmc_hostname(host->mmc), ret);
248 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
250 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
251 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
252 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
253 bool ctrl_phy = false;
255 if (!IS_ERR(sdhci_arasan->phy)) {
256 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
258 * If PHY off, set clock to max speed and power PHY on.
260 * Although PHY docs apparently suggest power cycling
261 * when changing the clock the PHY doesn't like to be
262 * powered on while at low speeds like those used in ID
263 * mode. Even worse is powering the PHY on while the
266 * To workaround the PHY limitations, the best we can
267 * do is to power it on at a faster speed and then slam
268 * through low speeds without power cycling.
270 sdhci_set_clock(host, host->max_clk);
271 phy_power_on(sdhci_arasan->phy);
272 sdhci_arasan->is_phy_on = true;
275 * We'll now fall through to the below case with
276 * ctrl_phy = false (so we won't turn off/on). The
277 * sdhci_set_clock() will set the real clock.
279 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
281 * At higher clock speeds the PHY is fine being power
282 * cycled and docs say you _should_ power cycle when
283 * changing clock speeds.
289 if (ctrl_phy && sdhci_arasan->is_phy_on) {
290 phy_power_off(sdhci_arasan->phy);
291 sdhci_arasan->is_phy_on = false;
294 /* Set the Input and Output Clock Phase Delays */
295 if (clk_data->set_clk_delays)
296 clk_data->set_clk_delays(host);
298 sdhci_set_clock(host, clock);
300 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
302 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
303 * after enabling the clock even though the clock is not
304 * stable. Trying to use a clock without waiting here results
305 * in EILSEQ while detecting some older/slower cards. The
306 * chosen delay is the maximum delay from sdhci_set_clock.
311 phy_power_on(sdhci_arasan->phy);
312 sdhci_arasan->is_phy_on = true;
316 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
320 struct sdhci_host *host = mmc_priv(mmc);
322 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
323 if (ios->enhanced_strobe)
324 vendor |= VENDOR_ENHANCED_STROBE;
326 vendor &= ~VENDOR_ENHANCED_STROBE;
328 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
331 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
334 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
335 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
337 sdhci_reset(host, mask);
339 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
340 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
341 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
342 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
346 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
349 switch (ios->signal_voltage) {
350 case MMC_SIGNAL_VOLTAGE_180:
352 * Plese don't switch to 1V8 as arasan,5.1 doesn't
353 * actually refer to this setting to indicate the
354 * signal voltage and the state machine will be broken
355 * actually if we force to enable 1V8. That's something
356 * like broken quirk but we could work around here.
359 case MMC_SIGNAL_VOLTAGE_330:
360 case MMC_SIGNAL_VOLTAGE_120:
361 /* We don't support 3V3 and 1V2 */
368 static const struct sdhci_ops sdhci_arasan_ops = {
369 .set_clock = sdhci_arasan_set_clock,
370 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
371 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
372 .set_bus_width = sdhci_set_bus_width,
373 .reset = sdhci_arasan_reset,
374 .set_uhs_signaling = sdhci_set_uhs_signaling,
375 .set_power = sdhci_set_power_and_bus_voltage,
378 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
383 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
386 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
391 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
393 sdhci_dumpregs(mmc_priv(mmc));
396 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
398 struct sdhci_host *host = mmc_priv(mmc);
401 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
402 while (reg & SDHCI_DATA_AVAILABLE) {
403 sdhci_readl(host, SDHCI_BUFFER);
404 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
407 sdhci_cqe_enable(mmc);
410 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
411 .enable = sdhci_arasan_cqe_enable,
412 .disable = sdhci_cqe_disable,
413 .dumpregs = sdhci_arasan_dumpregs,
416 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
417 .set_clock = sdhci_arasan_set_clock,
418 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
419 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
420 .set_bus_width = sdhci_set_bus_width,
421 .reset = sdhci_arasan_reset,
422 .set_uhs_signaling = sdhci_set_uhs_signaling,
423 .set_power = sdhci_set_power_and_bus_voltage,
424 .irq = sdhci_arasan_cqhci_irq,
427 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
428 .ops = &sdhci_arasan_cqe_ops,
429 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
430 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
431 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
434 #ifdef CONFIG_PM_SLEEP
436 * sdhci_arasan_suspend - Suspend method for the driver
437 * @dev: Address of the device structure
439 * Put the device in a low power state.
441 * Return: 0 on success and error value on error
443 static int sdhci_arasan_suspend(struct device *dev)
445 struct sdhci_host *host = dev_get_drvdata(dev);
446 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
447 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
450 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
451 mmc_retune_needed(host->mmc);
453 if (sdhci_arasan->has_cqe) {
454 ret = cqhci_suspend(host->mmc);
459 ret = sdhci_suspend_host(host);
463 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
464 ret = phy_power_off(sdhci_arasan->phy);
466 dev_err(dev, "Cannot power off phy.\n");
467 sdhci_resume_host(host);
470 sdhci_arasan->is_phy_on = false;
473 clk_disable(pltfm_host->clk);
474 clk_disable(sdhci_arasan->clk_ahb);
480 * sdhci_arasan_resume - Resume method for the driver
481 * @dev: Address of the device structure
483 * Resume operation after suspend
485 * Return: 0 on success and error value on error
487 static int sdhci_arasan_resume(struct device *dev)
489 struct sdhci_host *host = dev_get_drvdata(dev);
490 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
491 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
494 ret = clk_enable(sdhci_arasan->clk_ahb);
496 dev_err(dev, "Cannot enable AHB clock.\n");
500 ret = clk_enable(pltfm_host->clk);
502 dev_err(dev, "Cannot enable SD clock.\n");
506 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
507 ret = phy_power_on(sdhci_arasan->phy);
509 dev_err(dev, "Cannot power on phy.\n");
512 sdhci_arasan->is_phy_on = true;
515 ret = sdhci_resume_host(host);
517 dev_err(dev, "Cannot resume host.\n");
521 if (sdhci_arasan->has_cqe)
522 return cqhci_resume(host->mmc);
526 #endif /* ! CONFIG_PM_SLEEP */
528 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
529 sdhci_arasan_resume);
532 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
534 * @hw: Pointer to the hardware clock structure.
535 * @parent_rate: The parent rate (should be rate of clk_xin).
537 * Return the current actual rate of the SD card clock. This can be used
538 * to communicate with out PHY.
540 * Return: The card clock rate.
542 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
543 unsigned long parent_rate)
545 struct sdhci_arasan_clk_data *clk_data =
546 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
547 struct sdhci_arasan_data *sdhci_arasan =
548 container_of(clk_data, struct sdhci_arasan_data, clk_data);
549 struct sdhci_host *host = sdhci_arasan->host;
551 return host->mmc->actual_clock;
554 static const struct clk_ops arasan_sdcardclk_ops = {
555 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
559 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
561 * @hw: Pointer to the hardware clock structure.
562 * @parent_rate: The parent rate (should be rate of clk_xin).
564 * Return the current actual rate of the sampling clock. This can be used
565 * to communicate with out PHY.
567 * Return: The sample clock rate.
569 static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
570 unsigned long parent_rate)
572 struct sdhci_arasan_clk_data *clk_data =
573 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
574 struct sdhci_arasan_data *sdhci_arasan =
575 container_of(clk_data, struct sdhci_arasan_data, clk_data);
576 struct sdhci_host *host = sdhci_arasan->host;
578 return host->mmc->actual_clock;
581 static const struct clk_ops arasan_sampleclk_ops = {
582 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
586 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
588 * @hw: Pointer to the hardware clock structure.
589 * @degrees: The clock phase shift between 0 - 359.
591 * Set the SD Output Clock Tap Delays for Output path
593 * Return: 0 on success and error value on error
595 static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
597 struct sdhci_arasan_clk_data *clk_data =
598 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
599 struct sdhci_arasan_data *sdhci_arasan =
600 container_of(clk_data, struct sdhci_arasan_data, clk_data);
601 struct sdhci_host *host = sdhci_arasan->host;
602 struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
603 clk_data->clk_of_data;
604 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
605 const char *clk_name = clk_hw_get_name(hw);
606 u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
607 u8 tap_delay, tap_max = 0;
611 * This is applicable for SDHCI_SPEC_300 and above
612 * ZynqMP does not set phase for <=25MHz clock.
613 * If degrees is zero, no need to do anything.
615 if (host->version < SDHCI_SPEC_300 ||
616 host->timing == MMC_TIMING_LEGACY ||
617 host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
620 switch (host->timing) {
621 case MMC_TIMING_MMC_HS:
622 case MMC_TIMING_SD_HS:
623 case MMC_TIMING_UHS_SDR25:
624 case MMC_TIMING_UHS_DDR50:
625 case MMC_TIMING_MMC_DDR52:
626 /* For 50MHz clock, 30 Taps are available */
629 case MMC_TIMING_UHS_SDR50:
630 /* For 100MHz clock, 15 Taps are available */
633 case MMC_TIMING_UHS_SDR104:
634 case MMC_TIMING_MMC_HS200:
635 /* For 200MHz clock, 8 Taps are available */
641 tap_delay = (degrees * tap_max) / 360;
643 /* Set the Clock Phase */
644 ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
645 PM_TAPDELAY_OUTPUT, tap_delay, NULL);
647 pr_err("Error setting Output Tap Delay\n");
652 static const struct clk_ops zynqmp_sdcardclk_ops = {
653 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
654 .set_phase = sdhci_zynqmp_sdcardclk_set_phase,
658 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
660 * @hw: Pointer to the hardware clock structure.
661 * @degrees: The clock phase shift between 0 - 359.
663 * Set the SD Input Clock Tap Delays for Input path
665 * Return: 0 on success and error value on error
667 static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
669 struct sdhci_arasan_clk_data *clk_data =
670 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
671 struct sdhci_arasan_data *sdhci_arasan =
672 container_of(clk_data, struct sdhci_arasan_data, clk_data);
673 struct sdhci_host *host = sdhci_arasan->host;
674 struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
675 clk_data->clk_of_data;
676 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
677 const char *clk_name = clk_hw_get_name(hw);
678 u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
679 u8 tap_delay, tap_max = 0;
683 * This is applicable for SDHCI_SPEC_300 and above
684 * ZynqMP does not set phase for <=25MHz clock.
685 * If degrees is zero, no need to do anything.
687 if (host->version < SDHCI_SPEC_300 ||
688 host->timing == MMC_TIMING_LEGACY ||
689 host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
692 switch (host->timing) {
693 case MMC_TIMING_MMC_HS:
694 case MMC_TIMING_SD_HS:
695 case MMC_TIMING_UHS_SDR25:
696 case MMC_TIMING_UHS_DDR50:
697 case MMC_TIMING_MMC_DDR52:
698 /* For 50MHz clock, 120 Taps are available */
701 case MMC_TIMING_UHS_SDR50:
702 /* For 100MHz clock, 60 Taps are available */
705 case MMC_TIMING_UHS_SDR104:
706 case MMC_TIMING_MMC_HS200:
707 /* For 200MHz clock, 30 Taps are available */
713 tap_delay = (degrees * tap_max) / 360;
715 /* Set the Clock Phase */
716 ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
717 PM_TAPDELAY_INPUT, tap_delay, NULL);
719 pr_err("Error setting Input Tap Delay\n");
724 static const struct clk_ops zynqmp_sampleclk_ops = {
725 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
726 .set_phase = sdhci_zynqmp_sampleclk_set_phase,
730 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
732 * @hw: Pointer to the hardware clock structure.
733 * @degrees: The clock phase shift between 0 - 359.
735 * Set the SD Output Clock Tap Delays for Output path
737 * Return: 0 on success and error value on error
739 static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
741 struct sdhci_arasan_clk_data *clk_data =
742 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
743 struct sdhci_arasan_data *sdhci_arasan =
744 container_of(clk_data, struct sdhci_arasan_data, clk_data);
745 struct sdhci_host *host = sdhci_arasan->host;
746 u8 tap_delay, tap_max = 0;
749 * This is applicable for SDHCI_SPEC_300 and above
750 * Versal does not set phase for <=25MHz clock.
751 * If degrees is zero, no need to do anything.
753 if (host->version < SDHCI_SPEC_300 ||
754 host->timing == MMC_TIMING_LEGACY ||
755 host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
758 switch (host->timing) {
759 case MMC_TIMING_MMC_HS:
760 case MMC_TIMING_SD_HS:
761 case MMC_TIMING_UHS_SDR25:
762 case MMC_TIMING_UHS_DDR50:
763 case MMC_TIMING_MMC_DDR52:
764 /* For 50MHz clock, 30 Taps are available */
767 case MMC_TIMING_UHS_SDR50:
768 /* For 100MHz clock, 15 Taps are available */
771 case MMC_TIMING_UHS_SDR104:
772 case MMC_TIMING_MMC_HS200:
773 /* For 200MHz clock, 8 Taps are available */
779 tap_delay = (degrees * tap_max) / 360;
781 /* Set the Clock Phase */
785 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
786 regval |= SDHCI_OTAPDLY_ENABLE;
787 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
789 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
795 static const struct clk_ops versal_sdcardclk_ops = {
796 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
797 .set_phase = sdhci_versal_sdcardclk_set_phase,
801 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
803 * @hw: Pointer to the hardware clock structure.
804 * @degrees: The clock phase shift between 0 - 359.
806 * Set the SD Input Clock Tap Delays for Input path
808 * Return: 0 on success and error value on error
810 static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
812 struct sdhci_arasan_clk_data *clk_data =
813 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
814 struct sdhci_arasan_data *sdhci_arasan =
815 container_of(clk_data, struct sdhci_arasan_data, clk_data);
816 struct sdhci_host *host = sdhci_arasan->host;
817 u8 tap_delay, tap_max = 0;
820 * This is applicable for SDHCI_SPEC_300 and above
821 * Versal does not set phase for <=25MHz clock.
822 * If degrees is zero, no need to do anything.
824 if (host->version < SDHCI_SPEC_300 ||
825 host->timing == MMC_TIMING_LEGACY ||
826 host->timing == MMC_TIMING_UHS_SDR12 || !degrees)
829 switch (host->timing) {
830 case MMC_TIMING_MMC_HS:
831 case MMC_TIMING_SD_HS:
832 case MMC_TIMING_UHS_SDR25:
833 case MMC_TIMING_UHS_DDR50:
834 case MMC_TIMING_MMC_DDR52:
835 /* For 50MHz clock, 120 Taps are available */
838 case MMC_TIMING_UHS_SDR50:
839 /* For 100MHz clock, 60 Taps are available */
842 case MMC_TIMING_UHS_SDR104:
843 case MMC_TIMING_MMC_HS200:
844 /* For 200MHz clock, 30 Taps are available */
850 tap_delay = (degrees * tap_max) / 360;
852 /* Set the Clock Phase */
856 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
857 regval |= SDHCI_ITAPDLY_CHGWIN;
858 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
859 regval |= SDHCI_ITAPDLY_ENABLE;
860 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
862 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
863 regval &= ~SDHCI_ITAPDLY_CHGWIN;
864 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
870 static const struct clk_ops versal_sampleclk_ops = {
871 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
872 .set_phase = sdhci_versal_sampleclk_set_phase,
875 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
877 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
878 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
879 struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
880 sdhci_arasan->clk_data.clk_of_data;
881 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
884 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
885 clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
886 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
888 /* Issue DLL Reset */
889 eemi_ops->ioctl(deviceid, IOCTL_SD_DLL_RESET,
890 PM_DLL_RESET_PULSE, 0, NULL);
892 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
894 sdhci_enable_clk(host, clk);
897 static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
899 struct sdhci_host *host = mmc_priv(mmc);
900 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
901 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
902 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
903 const char *clk_name = clk_hw_get_name(hw);
904 u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
908 arasan_zynqmp_dll_reset(host, device_id);
910 err = sdhci_execute_tuning(mmc, opcode);
914 arasan_zynqmp_dll_reset(host, device_id);
920 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
922 * @host: The sdhci_host
923 * @value: The value to write
925 * The corecfg_clockmultiplier is supposed to contain clock multiplier
926 * value of programmable clock generator.
929 * - Many existing devices don't seem to do this and work fine. To keep
930 * compatibility for old hardware where the device tree doesn't provide a
931 * register map, this function is a noop if a soc_ctl_map hasn't been provided
933 * - The value of corecfg_clockmultiplier should sync with that of corresponding
934 * value reading from sdhci_capability_register. So this function is called
935 * once at probe time and never called again.
937 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
940 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
941 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
942 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
943 sdhci_arasan->soc_ctl_map;
945 /* Having a map is optional */
949 /* If we have a map, we expect to have a syscon */
950 if (!sdhci_arasan->soc_ctl_base) {
951 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
952 mmc_hostname(host->mmc));
956 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
960 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
962 * @host: The sdhci_host
964 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
965 * function can be used to make that happen.
968 * - Many existing devices don't seem to do this and work fine. To keep
969 * compatibility for old hardware where the device tree doesn't provide a
970 * register map, this function is a noop if a soc_ctl_map hasn't been provided
972 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
973 * to achieve lower clock rates. That means that this function is called once
974 * at probe time and never called again.
976 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
978 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
979 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
980 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
981 sdhci_arasan->soc_ctl_map;
982 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
984 /* Having a map is optional */
988 /* If we have a map, we expect to have a syscon */
989 if (!sdhci_arasan->soc_ctl_base) {
990 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
991 mmc_hostname(host->mmc));
995 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
998 static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
1000 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1001 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1002 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1004 clk_set_phase(clk_data->sampleclk,
1005 clk_data->clk_phase_in[host->timing]);
1006 clk_set_phase(clk_data->sdcardclk,
1007 clk_data->clk_phase_out[host->timing]);
1010 static void arasan_dt_read_clk_phase(struct device *dev,
1011 struct sdhci_arasan_clk_data *clk_data,
1012 unsigned int timing, const char *prop)
1014 struct device_node *np = dev->of_node;
1016 int clk_phase[2] = {0};
1019 * Read Tap Delay values from DT, if the DT does not contain the
1020 * Tap Values then use the pre-defined values.
1022 if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
1024 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1025 prop, clk_data->clk_phase_in[timing],
1026 clk_data->clk_phase_out[timing]);
1030 /* The values read are Input and Output Clock Delays in order */
1031 clk_data->clk_phase_in[timing] = clk_phase[0];
1032 clk_data->clk_phase_out[timing] = clk_phase[1];
1036 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1038 * @dev: Pointer to our struct device.
1039 * @clk_data: Pointer to the Clock Data structure
1041 * Called at initialization to parse the values of Clock Delays.
1043 static void arasan_dt_parse_clk_phases(struct device *dev,
1044 struct sdhci_arasan_clk_data *clk_data)
1046 int *iclk_phase, *oclk_phase;
1051 * This has been kept as a pointer and is assigned a function here.
1052 * So that different controller variants can assign their own handling
1055 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1057 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1058 iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ICLK_PHASE;
1059 oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OCLK_PHASE;
1061 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1062 if (mio_bank == 2) {
1063 oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1064 oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1067 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1068 clk_data->clk_phase_in[i] = iclk_phase[i];
1069 clk_data->clk_phase_out[i] = oclk_phase[i];
1073 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1074 iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) VERSAL_ICLK_PHASE;
1075 oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) VERSAL_OCLK_PHASE;
1077 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1078 clk_data->clk_phase_in[i] = iclk_phase[i];
1079 clk_data->clk_phase_out[i] = oclk_phase[i];
1083 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1084 "clk-phase-legacy");
1085 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1086 "clk-phase-mmc-hs");
1087 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1089 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1090 "clk-phase-uhs-sdr12");
1091 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1092 "clk-phase-uhs-sdr25");
1093 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1094 "clk-phase-uhs-sdr50");
1095 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1096 "clk-phase-uhs-sdr104");
1097 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1098 "clk-phase-uhs-ddr50");
1099 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1100 "clk-phase-mmc-ddr52");
1101 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1102 "clk-phase-mmc-hs200");
1103 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1104 "clk-phase-mmc-hs400");
1107 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1108 .ops = &sdhci_arasan_ops,
1109 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1110 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1111 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1112 SDHCI_QUIRK2_STOP_WITH_TC,
1115 static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1116 .sdcardclk_ops = &arasan_sdcardclk_ops,
1117 .sampleclk_ops = &arasan_sampleclk_ops,
1120 static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1121 .pdata = &sdhci_arasan_pdata,
1122 .clk_ops = &arasan_clk_ops,
1125 static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1126 .ops = &sdhci_arasan_cqe_ops,
1127 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1128 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1129 SDHCI_QUIRK_NO_LED |
1130 SDHCI_QUIRK_32BIT_DMA_ADDR |
1131 SDHCI_QUIRK_32BIT_DMA_SIZE |
1132 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1133 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1134 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1135 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1136 SDHCI_QUIRK2_STOP_WITH_TC |
1137 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1140 static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1141 .ops = &sdhci_arasan_ops,
1142 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1143 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1144 SDHCI_QUIRK_NO_LED |
1145 SDHCI_QUIRK_32BIT_DMA_ADDR |
1146 SDHCI_QUIRK_32BIT_DMA_SIZE |
1147 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1148 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1149 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1150 SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1151 SDHCI_QUIRK2_STOP_WITH_TC |
1152 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1155 static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1156 .ops = &sdhci_arasan_ops,
1157 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1158 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1159 SDHCI_QUIRK_NO_LED |
1160 SDHCI_QUIRK_32BIT_DMA_ADDR |
1161 SDHCI_QUIRK_32BIT_DMA_SIZE |
1162 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1163 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1164 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1165 SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1166 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1169 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1170 .soc_ctl_map = &rk3399_soc_ctl_map,
1171 .pdata = &sdhci_arasan_cqe_pdata,
1172 .clk_ops = &arasan_clk_ops,
1175 static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1176 .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1177 .pdata = &sdhci_arasan_cqe_pdata,
1178 .clk_ops = &arasan_clk_ops,
1181 static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1182 .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1183 .pdata = &sdhci_arasan_cqe_pdata,
1184 .clk_ops = &arasan_clk_ops,
1187 static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1188 .ops = &sdhci_arasan_ops,
1189 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1190 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1191 SDHCI_QUIRK2_STOP_WITH_TC,
1194 static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1195 .sdcardclk_ops = &zynqmp_sdcardclk_ops,
1196 .sampleclk_ops = &zynqmp_sampleclk_ops,
1199 static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1200 .pdata = &sdhci_arasan_zynqmp_pdata,
1201 .clk_ops = &zynqmp_clk_ops,
1204 static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1205 .sdcardclk_ops = &versal_sdcardclk_ops,
1206 .sampleclk_ops = &versal_sampleclk_ops,
1209 static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1210 .pdata = &sdhci_arasan_zynqmp_pdata,
1211 .clk_ops = &versal_clk_ops,
1214 static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1215 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1216 .pdata = &sdhci_keembay_emmc_pdata,
1219 static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1220 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1221 .pdata = &sdhci_keembay_sd_pdata,
1224 static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1225 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1226 .pdata = &sdhci_keembay_sdio_pdata,
1229 static const struct of_device_id sdhci_arasan_of_match[] = {
1230 /* SoC-specific compatible strings w/ soc_ctl_map */
1232 .compatible = "rockchip,rk3399-sdhci-5.1",
1233 .data = &sdhci_arasan_rk3399_data,
1236 .compatible = "intel,lgm-sdhci-5.1-emmc",
1237 .data = &intel_lgm_emmc_data,
1240 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1241 .data = &intel_lgm_sdxc_data,
1244 .compatible = "intel,keembay-sdhci-5.1-emmc",
1245 .data = &intel_keembay_emmc_data,
1248 .compatible = "intel,keembay-sdhci-5.1-sd",
1249 .data = &intel_keembay_sd_data,
1252 .compatible = "intel,keembay-sdhci-5.1-sdio",
1253 .data = &intel_keembay_sdio_data,
1255 /* Generic compatible below here */
1257 .compatible = "arasan,sdhci-8.9a",
1258 .data = &sdhci_arasan_generic_data,
1261 .compatible = "arasan,sdhci-5.1",
1262 .data = &sdhci_arasan_generic_data,
1265 .compatible = "arasan,sdhci-4.9a",
1266 .data = &sdhci_arasan_generic_data,
1269 .compatible = "xlnx,zynqmp-8.9a",
1270 .data = &sdhci_arasan_zynqmp_data,
1273 .compatible = "xlnx,versal-8.9a",
1274 .data = &sdhci_arasan_versal_data,
1278 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1281 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1283 * @sdhci_arasan: Our private data structure.
1284 * @clk_xin: Pointer to the functional clock
1285 * @dev: Pointer to our struct device.
1287 * Some PHY devices need to know what the actual card clock is. In order for
1288 * them to find out, we'll provide a clock through the common clock framework
1289 * for them to query.
1291 * Return: 0 on success and error value on error
1294 sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1295 struct clk *clk_xin,
1298 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1299 struct device_node *np = dev->of_node;
1300 struct clk_init_data sdcardclk_init;
1301 const char *parent_clk_name;
1304 ret = of_property_read_string_index(np, "clock-output-names", 0,
1305 &sdcardclk_init.name);
1307 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1311 parent_clk_name = __clk_get_name(clk_xin);
1312 sdcardclk_init.parent_names = &parent_clk_name;
1313 sdcardclk_init.num_parents = 1;
1314 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1315 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1317 clk_data->sdcardclk_hw.init = &sdcardclk_init;
1318 clk_data->sdcardclk =
1319 devm_clk_register(dev, &clk_data->sdcardclk_hw);
1320 clk_data->sdcardclk_hw.init = NULL;
1322 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1323 clk_data->sdcardclk);
1325 dev_err(dev, "Failed to add sdcard clock provider\n");
1331 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1333 * @sdhci_arasan: Our private data structure.
1334 * @clk_xin: Pointer to the functional clock
1335 * @dev: Pointer to our struct device.
1337 * Some PHY devices need to know what the actual card clock is. In order for
1338 * them to find out, we'll provide a clock through the common clock framework
1339 * for them to query.
1341 * Return: 0 on success and error value on error
1344 sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1345 struct clk *clk_xin,
1348 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1349 struct device_node *np = dev->of_node;
1350 struct clk_init_data sampleclk_init;
1351 const char *parent_clk_name;
1354 ret = of_property_read_string_index(np, "clock-output-names", 1,
1355 &sampleclk_init.name);
1357 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1361 parent_clk_name = __clk_get_name(clk_xin);
1362 sampleclk_init.parent_names = &parent_clk_name;
1363 sampleclk_init.num_parents = 1;
1364 sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1365 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1367 clk_data->sampleclk_hw.init = &sampleclk_init;
1368 clk_data->sampleclk =
1369 devm_clk_register(dev, &clk_data->sampleclk_hw);
1370 clk_data->sampleclk_hw.init = NULL;
1372 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1373 clk_data->sampleclk);
1375 dev_err(dev, "Failed to add sample clock provider\n");
1381 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1383 * @dev: Pointer to our struct device.
1385 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1388 static void sdhci_arasan_unregister_sdclk(struct device *dev)
1390 struct device_node *np = dev->of_node;
1392 if (!of_find_property(np, "#clock-cells", NULL))
1395 of_clk_del_provider(dev->of_node);
1399 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1401 * This should be set based on the System Address Bus.
1402 * 0: the Core supports only 32-bit System Address Bus.
1403 * 1: the Core supports 64-bit System Address Bus.
1406 * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1407 * Keem Bay does not support 64-bit access.
1409 * @host The sdhci_host
1411 static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1413 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1414 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1415 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1416 sdhci_arasan->soc_ctl_map;
1418 /* Having a map is optional */
1422 /* If we have a map, we expect to have a syscon */
1423 if (!sdhci_arasan->soc_ctl_base) {
1424 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1425 mmc_hostname(host->mmc));
1429 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1433 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1435 * @sdhci_arasan: Our private data structure.
1436 * @clk_xin: Pointer to the functional clock
1437 * @dev: Pointer to our struct device.
1439 * Some PHY devices need to know what the actual card clock is. In order for
1440 * them to find out, we'll provide a clock through the common clock framework
1441 * for them to query.
1443 * Note: without seriously re-architecting SDHCI's clock code and testing on
1444 * all platforms, there's no way to create a totally beautiful clock here
1445 * with all clock ops implemented. Instead, we'll just create a clock that can
1446 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1447 * framework that we're doing things behind its back. This should be sufficient
1448 * to create nice clean device tree bindings and later (if needed) we can try
1449 * re-architecting SDHCI if we see some benefit to it.
1451 * Return: 0 on success and error value on error
1453 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1454 struct clk *clk_xin,
1457 struct device_node *np = dev->of_node;
1461 /* Providing a clock to the PHY is optional; no error if missing */
1462 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1465 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1470 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1473 sdhci_arasan_unregister_sdclk(dev);
1481 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1483 struct sdhci_host *host = sdhci_arasan->host;
1484 struct cqhci_host *cq_host;
1488 if (!sdhci_arasan->has_cqe)
1489 return sdhci_add_host(host);
1491 ret = sdhci_setup_host(host);
1495 cq_host = devm_kzalloc(host->mmc->parent,
1496 sizeof(*cq_host), GFP_KERNEL);
1502 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1503 cq_host->ops = &sdhci_arasan_cqhci_ops;
1505 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1507 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1509 ret = cqhci_init(cq_host, host->mmc, dma64);
1513 ret = __sdhci_add_host(host);
1520 sdhci_cleanup_host(host);
1524 static int sdhci_arasan_probe(struct platform_device *pdev)
1527 const struct of_device_id *match;
1528 struct device_node *node;
1529 struct clk *clk_xin;
1530 struct sdhci_host *host;
1531 struct sdhci_pltfm_host *pltfm_host;
1532 struct sdhci_arasan_data *sdhci_arasan;
1533 struct device_node *np = pdev->dev.of_node;
1534 const struct sdhci_arasan_of_data *data;
1536 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
1538 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1541 return PTR_ERR(host);
1543 pltfm_host = sdhci_priv(host);
1544 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1545 sdhci_arasan->host = host;
1547 sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1548 sdhci_arasan->clk_ops = data->clk_ops;
1550 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
1552 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1555 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1556 ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
1557 if (ret != -EPROBE_DEFER)
1558 dev_err(&pdev->dev, "Can't get syscon: %d\n",
1560 goto err_pltfm_free;
1564 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
1565 if (IS_ERR(sdhci_arasan->clk_ahb)) {
1566 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
1567 ret = PTR_ERR(sdhci_arasan->clk_ahb);
1568 goto err_pltfm_free;
1571 clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
1572 if (IS_ERR(clk_xin)) {
1573 dev_err(&pdev->dev, "clk_xin clock not found.\n");
1574 ret = PTR_ERR(clk_xin);
1575 goto err_pltfm_free;
1578 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1580 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
1581 goto err_pltfm_free;
1584 ret = clk_prepare_enable(clk_xin);
1586 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
1590 sdhci_get_of_property(pdev);
1592 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1593 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1595 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1596 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1598 pltfm_host->clk = clk_xin;
1600 if (of_device_is_compatible(pdev->dev.of_node,
1601 "rockchip,rk3399-sdhci-5.1"))
1602 sdhci_arasan_update_clockmultiplier(host, 0x0);
1604 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1605 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1606 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
1607 sdhci_arasan_update_clockmultiplier(host, 0x0);
1608 sdhci_arasan_update_support64b(host, 0x0);
1610 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1613 sdhci_arasan_update_baseclkfreq(host);
1615 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
1617 goto clk_disable_all;
1619 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1620 struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data;
1621 const struct zynqmp_eemi_ops *eemi_ops;
1623 zynqmp_clk_data = devm_kzalloc(&pdev->dev,
1624 sizeof(*zynqmp_clk_data),
1626 eemi_ops = zynqmp_pm_get_eemi_ops();
1627 if (IS_ERR(eemi_ops)) {
1628 ret = PTR_ERR(eemi_ops);
1632 zynqmp_clk_data->eemi_ops = eemi_ops;
1633 sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data;
1634 host->mmc_host_ops.execute_tuning =
1635 arasan_zynqmp_execute_tuning;
1638 arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
1640 ret = mmc_of_parse(host->mmc);
1642 if (ret != -EPROBE_DEFER)
1643 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
1647 sdhci_arasan->phy = ERR_PTR(-ENODEV);
1648 if (of_device_is_compatible(pdev->dev.of_node,
1649 "arasan,sdhci-5.1")) {
1650 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
1652 if (IS_ERR(sdhci_arasan->phy)) {
1653 ret = PTR_ERR(sdhci_arasan->phy);
1654 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
1658 ret = phy_init(sdhci_arasan->phy);
1660 dev_err(&pdev->dev, "phy_init err.\n");
1664 host->mmc_host_ops.hs400_enhanced_strobe =
1665 sdhci_arasan_hs400_enhanced_strobe;
1666 host->mmc_host_ops.start_signal_voltage_switch =
1667 sdhci_arasan_voltage_switch;
1668 sdhci_arasan->has_cqe = true;
1669 host->mmc->caps2 |= MMC_CAP2_CQE;
1671 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
1672 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
1675 ret = sdhci_arasan_add_host(sdhci_arasan);
1682 if (!IS_ERR(sdhci_arasan->phy))
1683 phy_exit(sdhci_arasan->phy);
1685 sdhci_arasan_unregister_sdclk(&pdev->dev);
1687 clk_disable_unprepare(clk_xin);
1689 clk_disable_unprepare(sdhci_arasan->clk_ahb);
1691 sdhci_pltfm_free(pdev);
1695 static int sdhci_arasan_remove(struct platform_device *pdev)
1698 struct sdhci_host *host = platform_get_drvdata(pdev);
1699 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1700 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1701 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1703 if (!IS_ERR(sdhci_arasan->phy)) {
1704 if (sdhci_arasan->is_phy_on)
1705 phy_power_off(sdhci_arasan->phy);
1706 phy_exit(sdhci_arasan->phy);
1709 sdhci_arasan_unregister_sdclk(&pdev->dev);
1711 ret = sdhci_pltfm_unregister(pdev);
1713 clk_disable_unprepare(clk_ahb);
1718 static struct platform_driver sdhci_arasan_driver = {
1720 .name = "sdhci-arasan",
1721 .of_match_table = sdhci_arasan_of_match,
1722 .pm = &sdhci_arasan_dev_pm_ops,
1724 .probe = sdhci_arasan_probe,
1725 .remove = sdhci_arasan_remove,
1728 module_platform_driver(sdhci_arasan_driver);
1730 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1731 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1732 MODULE_LICENSE("GPL");