drivers/mmc/host/sdhci-msm.c

   1 /*
   2  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
   3  *
   4  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/of_device.h>
  19 #include <linux/delay.h>
  20 #include <linux/mmc/mmc.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/iopoll.h>
  24
  25 #include "sdhci-pltfm.h"
  26
  27 #define CORE_MCI_VERSION                0x50
  28 #define CORE_VERSION_MAJOR_SHIFT        28
  29 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
  30 #define CORE_VERSION_MINOR_MASK         0xff
  31
  32 #define CORE_MCI_GENERICS               0x70
  33 #define SWITCHABLE_SIGNALING_VOLTAGE    BIT(29)
  34
  35 #define CORE_HC_MODE            0x78
  36 #define HC_MODE_EN              0x1
  37 #define CORE_POWER              0x0
  38 #define CORE_SW_RST             BIT(7)
  39 #define FF_CLK_SW_RST_DIS       BIT(13)
  40
  41 #define CORE_PWRCTL_STATUS      0xdc
  42 #define CORE_PWRCTL_MASK        0xe0
  43 #define CORE_PWRCTL_CLEAR       0xe4
  44 #define CORE_PWRCTL_CTL         0xe8
  45 #define CORE_PWRCTL_BUS_OFF     BIT(0)
  46 #define CORE_PWRCTL_BUS_ON      BIT(1)
  47 #define CORE_PWRCTL_IO_LOW      BIT(2)
  48 #define CORE_PWRCTL_IO_HIGH     BIT(3)
  49 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
  50 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
  51 #define REQ_BUS_OFF             BIT(0)
  52 #define REQ_BUS_ON              BIT(1)
  53 #define REQ_IO_LOW              BIT(2)
  54 #define REQ_IO_HIGH             BIT(3)
  55 #define INT_MASK                0xf
  56 #define MAX_PHASES              16
  57 #define CORE_DLL_LOCK           BIT(7)
  58 #define CORE_DDR_DLL_LOCK       BIT(11)
  59 #define CORE_DLL_EN             BIT(16)
  60 #define CORE_CDR_EN             BIT(17)
  61 #define CORE_CK_OUT_EN          BIT(18)
  62 #define CORE_CDR_EXT_EN         BIT(19)
  63 #define CORE_DLL_PDN            BIT(29)
  64 #define CORE_DLL_RST            BIT(30)
  65 #define CORE_DLL_CONFIG         0x100
  66 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
  67 #define CORE_DLL_STATUS         0x108
  68
  69 #define CORE_DLL_CONFIG_2       0x1b4
  70 #define CORE_DDR_CAL_EN         BIT(0)
  71 #define CORE_FLL_CYCLE_CNT      BIT(18)
  72 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
  73
  74 #define CORE_VENDOR_SPEC        0x10c
  75 #define CORE_VENDOR_SPEC_POR_VAL        0xa1c
  76 #define CORE_CLK_PWRSAVE        BIT(1)
  77 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
  78 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
  79 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
  80 #define CORE_HC_SELECT_IN_EN    BIT(18)
  81 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
  82 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
  83
  84 #define CORE_CSR_CDC_CTLR_CFG0          0x130
  85 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
  86 #define CORE_HW_AUTOCAL_ENA             BIT(17)
  87
  88 #define CORE_CSR_CDC_CTLR_CFG1          0x134
  89 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
  90 #define CORE_TIMER_ENA                  BIT(16)
  91
  92 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
  93 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
  94 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
  95 #define CORE_CDC_OFFSET_CFG             0x14C
  96 #define CORE_CSR_CDC_DELAY_CFG          0x150
  97 #define CORE_CDC_SLAVE_DDA_CFG          0x160
  98 #define CORE_CSR_CDC_STATUS0            0x164
  99 #define CORE_CALIBRATION_DONE           BIT(0)
 100
 101 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
 102
 103 #define CORE_CSR_CDC_GEN_CFG            0x178
 104 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
 105 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
 106
 107 #define CORE_DDR_200_CFG                0x184
 108 #define CORE_CDC_T4_DLY_SEL             BIT(0)
 109 #define CORE_CMDIN_RCLK_EN              BIT(1)
 110 #define CORE_START_CDC_TRAFFIC          BIT(6)
 111 #define CORE_VENDOR_SPEC3       0x1b0
 112 #define CORE_PWRSAVE_DLL        BIT(3)
 113
 114 #define CORE_DDR_CONFIG         0x1b8
 115 #define DDR_CONFIG_POR_VAL      0x80040853
 116
 117 #define CORE_VENDOR_SPEC_CAPABILITIES0  0x11c
 118
 119 #define INVALID_TUNING_PHASE    -1
 120 #define SDHCI_MSM_MIN_CLOCK     400000
 121 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
 122
 123 #define CDR_SELEXT_SHIFT        20
 124 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
 125 #define CMUX_SHIFT_PHASE_SHIFT  24
 126 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
 127
 128 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
 129
 130 /* Timeout value to avoid infinite waiting for pwr_irq */
 131 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
 132
 133 struct sdhci_msm_host {
 134         struct platform_device *pdev;
 135         void __iomem *core_mem; /* MSM SDCC mapped address */
 136         int pwr_irq;            /* power irq */
 137         struct clk *bus_clk;    /* SDHC bus voter clock */
 138         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
 139         struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
 140         unsigned long clk_rate;
 141         struct mmc_host *mmc;
 142         bool use_14lpp_dll_reset;
 143         bool tuning_done;
 144         bool calibration_done;
 145         u8 saved_tuning_phase;
 146         bool use_cdclp533;
 147         u32 curr_pwr_state;
 148         u32 curr_io_level;
 149         wait_queue_head_t pwr_irq_wait;
 150         bool pwr_irq_flag;
 151 };
 152
 153 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
 154                                                     unsigned int clock)
 155 {
 156         struct mmc_ios ios = host->mmc->ios;
 157         /*
 158          * The SDHC requires internal clock frequency to be double the
 159          * actual clock that will be set for DDR mode. The controller
 160          * uses the faster clock(100/400MHz) for some of its parts and
 161          * send the actual required clock (50/200MHz) to the card.
 162          */
 163         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
 164             ios.timing == MMC_TIMING_MMC_DDR52 ||
 165             ios.timing == MMC_TIMING_MMC_HS400 ||
 166             host->flags & SDHCI_HS400_TUNING)
 167                 clock *= 2;
 168         return clock;
 169 }
 170
 171 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
 172                                             unsigned int clock)
 173 {
 174         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 175         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 176         struct mmc_ios curr_ios = host->mmc->ios;
 177         struct clk *core_clk = msm_host->bulk_clks[0].clk;
 178         int rc;
 179
 180         clock = msm_get_clock_rate_for_bus_mode(host, clock);
 181         rc = clk_set_rate(core_clk, clock);
 182         if (rc) {
 183                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
 184                        mmc_hostname(host->mmc), clock,
 185                        curr_ios.timing);
 186                 return;
 187         }
 188         msm_host->clk_rate = clock;
 189         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
 190                  mmc_hostname(host->mmc), clk_get_rate(core_clk),
 191                  curr_ios.timing);
 192 }
 193
 194 /* Platform specific tuning */
 195 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
 196 {
 197         u32 wait_cnt = 50;
 198         u8 ck_out_en;
 199         struct mmc_host *mmc = host->mmc;
 200
 201         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
 202         ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
 203                         CORE_CK_OUT_EN);
 204
 205         while (ck_out_en != poll) {
 206                 if (--wait_cnt == 0) {
 207                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
 208                                mmc_hostname(mmc), poll);
 209                         return -ETIMEDOUT;
 210                 }
 211                 udelay(1);
 212
 213                 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
 214                                 CORE_CK_OUT_EN);
 215         }
 216
 217         return 0;
 218 }
 219
 220 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 221 {
 222         int rc;
 223         static const u8 grey_coded_phase_table[] = {
 224                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 225                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 226         };
 227         unsigned long flags;
 228         u32 config;
 229         struct mmc_host *mmc = host->mmc;
 230
 231         if (phase > 0xf)
 232                 return -EINVAL;
 233
 234         spin_lock_irqsave(&host->lock, flags);
 235
 236         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 237         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 238         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 239         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 240
 241         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 242         rc = msm_dll_poll_ck_out_en(host, 0);
 243         if (rc)
 244                 goto err_out;
 245
 246         /*
 247          * Write the selected DLL clock output phase (0 ... 15)
 248          * to CDR_SELEXT bit field of DLL_CONFIG register.
 249          */
 250         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 251         config &= ~CDR_SELEXT_MASK;
 252         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 253         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 254
 255         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 256         config |= CORE_CK_OUT_EN;
 257         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 258
 259         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 260         rc = msm_dll_poll_ck_out_en(host, 1);
 261         if (rc)
 262                 goto err_out;
 263
 264         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 265         config |= CORE_CDR_EN;
 266         config &= ~CORE_CDR_EXT_EN;
 267         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 268         goto out;
 269
 270 err_out:
 271         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 272                mmc_hostname(mmc), phase);
 273 out:
 274         spin_unlock_irqrestore(&host->lock, flags);
 275         return rc;
 276 }
 277
 278 /*
 279  * Find out the greatest range of consecuitive selected
 280  * DLL clock output phases that can be used as sampling
 281  * setting for SD3.0 UHS-I card read operation (in SDR104
 282  * timing mode) or for eMMC4.5 card read operation (in
 283  * HS400/HS200 timing mode).
 284  * Select the 3/4 of the range and configure the DLL with the
 285  * selected DLL clock output phase.
 286  */
 287
 288 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 289                                            u8 *phase_table, u8 total_phases)
 290 {
 291         int ret;
 292         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 293         u8 phases_per_row[MAX_PHASES] = { 0 };
 294         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 295         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 296         bool phase_0_found = false, phase_15_found = false;
 297         struct mmc_host *mmc = host->mmc;
 298
 299         if (!total_phases || (total_phases > MAX_PHASES)) {
 300                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 301                        mmc_hostname(mmc), total_phases);
 302                 return -EINVAL;
 303         }
 304
 305         for (cnt = 0; cnt < total_phases; cnt++) {
 306                 ranges[row_index][col_index] = phase_table[cnt];
 307                 phases_per_row[row_index] += 1;
 308                 col_index++;
 309
 310                 if ((cnt + 1) == total_phases) {
 311                         continue;
 312                 /* check if next phase in phase_table is consecutive or not */
 313                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 314                         row_index++;
 315                         col_index = 0;
 316                 }
 317         }
 318
 319         if (row_index >= MAX_PHASES)
 320                 return -EINVAL;
 321
 322         /* Check if phase-0 is present in first valid window? */
 323         if (!ranges[0][0]) {
 324                 phase_0_found = true;
 325                 phase_0_raw_index = 0;
 326                 /* Check if cycle exist between 2 valid windows */
 327                 for (cnt = 1; cnt <= row_index; cnt++) {
 328                         if (phases_per_row[cnt]) {
 329                                 for (i = 0; i < phases_per_row[cnt]; i++) {
 330                                         if (ranges[cnt][i] == 15) {
 331                                                 phase_15_found = true;
 332                                                 phase_15_raw_index = cnt;
 333                                                 break;
 334                                         }
 335                                 }
 336                         }
 337                 }
 338         }
 339
 340         /* If 2 valid windows form cycle then merge them as single window */
 341         if (phase_0_found && phase_15_found) {
 342                 /* number of phases in raw where phase 0 is present */
 343                 u8 phases_0 = phases_per_row[phase_0_raw_index];
 344                 /* number of phases in raw where phase 15 is present */
 345                 u8 phases_15 = phases_per_row[phase_15_raw_index];
 346
 347                 if (phases_0 + phases_15 >= MAX_PHASES)
 348                         /*
 349                          * If there are more than 1 phase windows then total
 350                          * number of phases in both the windows should not be
 351                          * more than or equal to MAX_PHASES.
 352                          */
 353                         return -EINVAL;
 354
 355                 /* Merge 2 cyclic windows */
 356                 i = phases_15;
 357                 for (cnt = 0; cnt < phases_0; cnt++) {
 358                         ranges[phase_15_raw_index][i] =
 359                             ranges[phase_0_raw_index][cnt];
 360                         if (++i >= MAX_PHASES)
 361                                 break;
 362                 }
 363
 364                 phases_per_row[phase_0_raw_index] = 0;
 365                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 366         }
 367
 368         for (cnt = 0; cnt <= row_index; cnt++) {
 369                 if (phases_per_row[cnt] > curr_max) {
 370                         curr_max = phases_per_row[cnt];
 371                         selected_row_index = cnt;
 372                 }
 373         }
 374
 375         i = (curr_max * 3) / 4;
 376         if (i)
 377                 i--;
 378
 379         ret = ranges[selected_row_index][i];
 380
 381         if (ret >= MAX_PHASES) {
 382                 ret = -EINVAL;
 383                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 384                        mmc_hostname(mmc), ret);
 385         }
 386
 387         return ret;
 388 }
 389
 390 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 391 {
 392         u32 mclk_freq = 0, config;
 393
 394         /* Program the MCLK value to MCLK_FREQ bit field */
 395         if (host->clock <= 112000000)
 396                 mclk_freq = 0;
 397         else if (host->clock <= 125000000)
 398                 mclk_freq = 1;
 399         else if (host->clock <= 137000000)
 400                 mclk_freq = 2;
 401         else if (host->clock <= 150000000)
 402                 mclk_freq = 3;
 403         else if (host->clock <= 162000000)
 404                 mclk_freq = 4;
 405         else if (host->clock <= 175000000)
 406                 mclk_freq = 5;
 407         else if (host->clock <= 187000000)
 408                 mclk_freq = 6;
 409         else if (host->clock <= 200000000)
 410                 mclk_freq = 7;
 411
 412         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 413         config &= ~CMUX_SHIFT_PHASE_MASK;
 414         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 415         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 416 }
 417
 418 /* Initialize the DLL (Programmable Delay Line) */
 419 static int msm_init_cm_dll(struct sdhci_host *host)
 420 {
 421         struct mmc_host *mmc = host->mmc;
 422         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 423         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 424         int wait_cnt = 50;
 425         unsigned long flags;
 426         u32 config;
 427
 428         spin_lock_irqsave(&host->lock, flags);
 429
 430         /*
 431          * Make sure that clock is always enabled when DLL
 432          * tuning is in progress. Keeping PWRSAVE ON may
 433          * turn off the clock.
 434          */
 435         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 436         config &= ~CORE_CLK_PWRSAVE;
 437         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 438
 439         if (msm_host->use_14lpp_dll_reset) {
 440                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 441                 config &= ~CORE_CK_OUT_EN;
 442                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 443
 444                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 445                 config |= CORE_DLL_CLOCK_DISABLE;
 446                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 447         }
 448
 449         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 450         config |= CORE_DLL_RST;
 451         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 452
 453         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 454         config |= CORE_DLL_PDN;
 455         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 456         msm_cm_dll_set_freq(host);
 457
 458         if (msm_host->use_14lpp_dll_reset &&
 459             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
 460                 u32 mclk_freq = 0;
 461
 462                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 463                 config &= CORE_FLL_CYCLE_CNT;
 464                 if (config)
 465                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
 466                                         clk_get_rate(msm_host->xo_clk));
 467                 else
 468                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
 469                                         clk_get_rate(msm_host->xo_clk));
 470
 471                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 472                 config &= ~(0xFF << 10);
 473                 config |= mclk_freq << 10;
 474
 475                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 476                 /* wait for 5us before enabling DLL clock */
 477                 udelay(5);
 478         }
 479
 480         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 481         config &= ~CORE_DLL_RST;
 482         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 483
 484         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 485         config &= ~CORE_DLL_PDN;
 486         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 487
 488         if (msm_host->use_14lpp_dll_reset) {
 489                 msm_cm_dll_set_freq(host);
 490                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 491                 config &= ~CORE_DLL_CLOCK_DISABLE;
 492                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 493         }
 494
 495         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 496         config |= CORE_DLL_EN;
 497         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 498
 499         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 500         config |= CORE_CK_OUT_EN;
 501         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 502
 503         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 504         while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
 505                  CORE_DLL_LOCK)) {
 506                 /* max. wait for 50us sec for LOCK bit to be set */
 507                 if (--wait_cnt == 0) {
 508                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 509                                mmc_hostname(mmc));
 510                         spin_unlock_irqrestore(&host->lock, flags);
 511                         return -ETIMEDOUT;
 512                 }
 513                 udelay(1);
 514         }
 515
 516         spin_unlock_irqrestore(&host->lock, flags);
 517         return 0;
 518 }
 519
 520 static void msm_hc_select_default(struct sdhci_host *host)
 521 {
 522         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 523         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 524         u32 config;
 525
 526         if (!msm_host->use_cdclp533) {
 527                 config = readl_relaxed(host->ioaddr +
 528                                 CORE_VENDOR_SPEC3);
 529                 config &= ~CORE_PWRSAVE_DLL;
 530                 writel_relaxed(config, host->ioaddr +
 531                                 CORE_VENDOR_SPEC3);
 532         }
 533
 534         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 535         config &= ~CORE_HC_MCLK_SEL_MASK;
 536         config |= CORE_HC_MCLK_SEL_DFLT;
 537         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 538
 539         /*
 540          * Disable HC_SELECT_IN to be able to use the UHS mode select
 541          * configuration from Host Control2 register for all other
 542          * modes.
 543          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
 544          * in VENDOR_SPEC_FUNC
 545          */
 546         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 547         config &= ~CORE_HC_SELECT_IN_EN;
 548         config &= ~CORE_HC_SELECT_IN_MASK;
 549         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 550
 551         /*
 552          * Make sure above writes impacting free running MCLK are completed
 553          * before changing the clk_rate at GCC.
 554          */
 555         wmb();
 556 }
 557
 558 static void msm_hc_select_hs400(struct sdhci_host *host)
 559 {
 560         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 561         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 562         struct mmc_ios ios = host->mmc->ios;
 563         u32 config, dll_lock;
 564         int rc;
 565
 566         /* Select the divided clock (free running MCLK/2) */
 567         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 568         config &= ~CORE_HC_MCLK_SEL_MASK;
 569         config |= CORE_HC_MCLK_SEL_HS400;
 570
 571         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 572         /*
 573          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
 574          * register
 575          */
 576         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
 577             !msm_host->calibration_done) {
 578                 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 579                 config |= CORE_HC_SELECT_IN_HS400;
 580                 config |= CORE_HC_SELECT_IN_EN;
 581                 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 582         }
 583         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
 584                 /*
 585                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
 586                  * CORE_DLL_STATUS to be set.  This should get set
 587                  * within 15 us at 200 MHz.
 588                  */
 589                 rc = readl_relaxed_poll_timeout(host->ioaddr +
 590                                                 CORE_DLL_STATUS,
 591                                                 dll_lock,
 592                                                 (dll_lock &
 593                                                 (CORE_DLL_LOCK |
 594                                                 CORE_DDR_DLL_LOCK)), 10,
 595                                                 1000);
 596                 if (rc == -ETIMEDOUT)
 597                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
 598                                mmc_hostname(host->mmc), dll_lock);
 599         }
 600         /*
 601          * Make sure above writes impacting free running MCLK are completed
 602          * before changing the clk_rate at GCC.
 603          */
 604         wmb();
 605 }
 606
 607 /*
 608  * sdhci_msm_hc_select_mode :- In general all timing modes are
 609  * controlled via UHS mode select in Host Control2 register.
 610  * eMMC specific HS200/HS400 doesn't have their respective modes
 611  * defined here, hence we use these values.
 612  *
 613  * HS200 - SDR104 (Since they both are equivalent in functionality)
 614  * HS400 - This involves multiple configurations
 615  *              Initially SDR104 - when tuning is required as HS200
 616  *              Then when switching to DDR @ 400MHz (HS400) we use
 617  *              the vendor specific HC_SELECT_IN to control the mode.
 618  *
 619  * In addition to controlling the modes we also need to select the
 620  * correct input clock for DLL depending on the mode.
 621  *
 622  * HS400 - divided clock (free running MCLK/2)
 623  * All other modes - default (free running MCLK)
 624  */
 625 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
 626 {
 627         struct mmc_ios ios = host->mmc->ios;
 628
 629         if (ios.timing == MMC_TIMING_MMC_HS400 ||
 630             host->flags & SDHCI_HS400_TUNING)
 631                 msm_hc_select_hs400(host);
 632         else
 633                 msm_hc_select_default(host);
 634 }
 635
 636 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
 637 {
 638         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 639         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 640         u32 config, calib_done;
 641         int ret;
 642
 643         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 644
 645         /*
 646          * Retuning in HS400 (DDR mode) will fail, just reset the
 647          * tuning block and restore the saved tuning phase.
 648          */
 649         ret = msm_init_cm_dll(host);
 650         if (ret)
 651                 goto out;
 652
 653         /* Set the selected phase in delay line hw block */
 654         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
 655         if (ret)
 656                 goto out;
 657
 658         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 659         config |= CORE_CMD_DAT_TRACK_SEL;
 660         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 661
 662         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 663         config &= ~CORE_CDC_T4_DLY_SEL;
 664         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 665
 666         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 667         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
 668         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 669
 670         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 671         config |= CORE_CDC_SWITCH_RC_EN;
 672         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 673
 674         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 675         config &= ~CORE_START_CDC_TRAFFIC;
 676         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 677
 678         /* Perform CDC Register Initialization Sequence */
 679
 680         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 681         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
 682         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 683         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
 684         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
 685         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
 686         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
 687         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
 688         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
 689
 690         /* CDC HW Calibration */
 691
 692         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 693         config |= CORE_SW_TRIG_FULL_CALIB;
 694         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 695
 696         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 697         config &= ~CORE_SW_TRIG_FULL_CALIB;
 698         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 699
 700         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 701         config |= CORE_HW_AUTOCAL_ENA;
 702         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 703
 704         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 705         config |= CORE_TIMER_ENA;
 706         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 707
 708         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
 709                                          calib_done,
 710                                          (calib_done & CORE_CALIBRATION_DONE),
 711                                          1, 50);
 712
 713         if (ret == -ETIMEDOUT) {
 714                 pr_err("%s: %s: CDC calibration was not completed\n",
 715                        mmc_hostname(host->mmc), __func__);
 716                 goto out;
 717         }
 718
 719         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
 720                         & CORE_CDC_ERROR_CODE_MASK;
 721         if (ret) {
 722                 pr_err("%s: %s: CDC error code %d\n",
 723                        mmc_hostname(host->mmc), __func__, ret);
 724                 ret = -EINVAL;
 725                 goto out;
 726         }
 727
 728         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 729         config |= CORE_START_CDC_TRAFFIC;
 730         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 731 out:
 732         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 733                  __func__, ret);
 734         return ret;
 735 }
 736
 737 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
 738 {
 739         struct mmc_host *mmc = host->mmc;
 740         u32 dll_status, config;
 741         int ret;
 742
 743         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 744
 745         /*
 746          * Currently the CORE_DDR_CONFIG register defaults to desired
 747          * configuration on reset. Currently reprogramming the power on
 748          * reset (POR) value in case it might have been modified by
 749          * bootloaders. In the future, if this changes, then the desired
 750          * values will need to be programmed appropriately.
 751          */
 752         writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
 753
 754         if (mmc->ios.enhanced_strobe) {
 755                 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 756                 config |= CORE_CMDIN_RCLK_EN;
 757                 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 758         }
 759
 760         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 761         config |= CORE_DDR_CAL_EN;
 762         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 763
 764         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
 765                                          dll_status,
 766                                          (dll_status & CORE_DDR_DLL_LOCK),
 767                                          10, 1000);
 768
 769         if (ret == -ETIMEDOUT) {
 770                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
 771                        mmc_hostname(host->mmc), __func__);
 772                 goto out;
 773         }
 774
 775         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
 776         config |= CORE_PWRSAVE_DLL;
 777         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
 778
 779         /*
 780          * Drain writebuffer to ensure above DLL calibration
 781          * and PWRSAVE DLL is enabled.
 782          */
 783         wmb();
 784 out:
 785         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 786                  __func__, ret);
 787         return ret;
 788 }
 789
 790 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
 791 {
 792         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 793         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 794         struct mmc_host *mmc = host->mmc;
 795         int ret;
 796         u32 config;
 797
 798         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 799
 800         /*
 801          * Retuning in HS400 (DDR mode) will fail, just reset the
 802          * tuning block and restore the saved tuning phase.
 803          */
 804         ret = msm_init_cm_dll(host);
 805         if (ret)
 806                 goto out;
 807
 808         if (!mmc->ios.enhanced_strobe) {
 809                 /* Set the selected phase in delay line hw block */
 810                 ret = msm_config_cm_dll_phase(host,
 811                                               msm_host->saved_tuning_phase);
 812                 if (ret)
 813                         goto out;
 814                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 815                 config |= CORE_CMD_DAT_TRACK_SEL;
 816                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 817         }
 818
 819         if (msm_host->use_cdclp533)
 820                 ret = sdhci_msm_cdclp533_calibration(host);
 821         else
 822                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
 823 out:
 824         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 825                  __func__, ret);
 826         return ret;
 827 }
 828
 829 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
 830 {
 831         struct sdhci_host *host = mmc_priv(mmc);
 832         int tuning_seq_cnt = 3;
 833         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
 834         int rc;
 835         struct mmc_ios ios = host->mmc->ios;
 836         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 837         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 838
 839         /*
 840          * Tuning is required for SDR104, HS200 and HS400 cards and
 841          * if clock frequency is greater than 100MHz in these modes.
 842          */
 843         if (host->clock <= CORE_FREQ_100MHZ ||
 844             !(ios.timing == MMC_TIMING_MMC_HS400 ||
 845             ios.timing == MMC_TIMING_MMC_HS200 ||
 846             ios.timing == MMC_TIMING_UHS_SDR104))
 847                 return 0;
 848
 849         /*
 850          * For HS400 tuning in HS200 timing requires:
 851          * - select MCLK/2 in VENDOR_SPEC
 852          * - program MCLK to 400MHz (or nearest supported) in GCC
 853          */
 854         if (host->flags & SDHCI_HS400_TUNING) {
 855                 sdhci_msm_hc_select_mode(host);
 856                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
 857                 host->flags &= ~SDHCI_HS400_TUNING;
 858         }
 859
 860 retry:
 861         /* First of all reset the tuning block */
 862         rc = msm_init_cm_dll(host);
 863         if (rc)
 864                 return rc;
 865
 866         phase = 0;
 867         do {
 868                 /* Set the phase in delay line hw block */
 869                 rc = msm_config_cm_dll_phase(host, phase);
 870                 if (rc)
 871                         return rc;
 872
 873                 msm_host->saved_tuning_phase = phase;
 874                 rc = mmc_send_tuning(mmc, opcode, NULL);
 875                 if (!rc) {
 876                         /* Tuning is successful at this tuning point */
 877                         tuned_phases[tuned_phase_cnt++] = phase;
 878                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
 879                                  mmc_hostname(mmc), phase);
 880                 }
 881         } while (++phase < ARRAY_SIZE(tuned_phases));
 882
 883         if (tuned_phase_cnt) {
 884                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
 885                                                      tuned_phase_cnt);
 886                 if (rc < 0)
 887                         return rc;
 888                 else
 889                         phase = rc;
 890
 891                 /*
 892                  * Finally set the selected phase in delay
 893                  * line hw block.
 894                  */
 895                 rc = msm_config_cm_dll_phase(host, phase);
 896                 if (rc)
 897                         return rc;
 898                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
 899                          mmc_hostname(mmc), phase);
 900         } else {
 901                 if (--tuning_seq_cnt)
 902                         goto retry;
 903                 /* Tuning failed */
 904                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
 905                        mmc_hostname(mmc));
 906                 rc = -EIO;
 907         }
 908
 909         if (!rc)
 910                 msm_host->tuning_done = true;
 911         return rc;
 912 }
 913
 914 /*
 915  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
 916  * This needs to be done for both tuning and enhanced_strobe mode.
 917  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
 918  * fixed feedback clock is used.
 919  */
 920 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
 921 {
 922         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 923         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 924         int ret;
 925
 926         if (host->clock > CORE_FREQ_100MHZ &&
 927             (msm_host->tuning_done || ios->enhanced_strobe) &&
 928             !msm_host->calibration_done) {
 929                 ret = sdhci_msm_hs400_dll_calibration(host);
 930                 if (!ret)
 931                         msm_host->calibration_done = true;
 932                 else
 933                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
 934                                mmc_hostname(host->mmc), ret);
 935         }
 936 }
 937
 938 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 939                                         unsigned int uhs)
 940 {
 941         struct mmc_host *mmc = host->mmc;
 942         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 943         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 944         u16 ctrl_2;
 945         u32 config;
 946
 947         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 948         /* Select Bus Speed Mode for host */
 949         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 950         switch (uhs) {
 951         case MMC_TIMING_UHS_SDR12:
 952                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 953                 break;
 954         case MMC_TIMING_UHS_SDR25:
 955                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 956                 break;
 957         case MMC_TIMING_UHS_SDR50:
 958                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 959                 break;
 960         case MMC_TIMING_MMC_HS400:
 961         case MMC_TIMING_MMC_HS200:
 962         case MMC_TIMING_UHS_SDR104:
 963                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 964                 break;
 965         case MMC_TIMING_UHS_DDR50:
 966         case MMC_TIMING_MMC_DDR52:
 967                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 968                 break;
 969         }
 970
 971         /*
 972          * When clock frequency is less than 100MHz, the feedback clock must be
 973          * provided and DLL must not be used so that tuning can be skipped. To
 974          * provide feedback clock, the mode selection can be any value less
 975          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
 976          */
 977         if (host->clock <= CORE_FREQ_100MHZ) {
 978                 if (uhs == MMC_TIMING_MMC_HS400 ||
 979                     uhs == MMC_TIMING_MMC_HS200 ||
 980                     uhs == MMC_TIMING_UHS_SDR104)
 981                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 982                 /*
 983                  * DLL is not required for clock <= 100MHz
 984                  * Thus, make sure DLL it is disabled when not required
 985                  */
 986                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 987                 config |= CORE_DLL_RST;
 988                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 989
 990                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 991                 config |= CORE_DLL_PDN;
 992                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 993
 994                 /*
 995                  * The DLL needs to be restored and CDCLP533 recalibrated
 996                  * when the clock frequency is set back to 400MHz.
 997                  */
 998                 msm_host->calibration_done = false;
 999         }
1000
1001         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1002                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1003         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1004
1005         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1006                 sdhci_msm_hs400(host, &mmc->ios);
1007 }
1008
1009 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1010 {
1011         init_waitqueue_head(&msm_host->pwr_irq_wait);
1012 }
1013
1014 static inline void sdhci_msm_complete_pwr_irq_wait(
1015                 struct sdhci_msm_host *msm_host)
1016 {
1017         wake_up(&msm_host->pwr_irq_wait);
1018 }
1019
1020 /*
1021  * sdhci_msm_check_power_status API should be called when registers writes
1022  * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1023  * To what state the register writes will change the IO lines should be passed
1024  * as the argument req_type. This API will check whether the IO line's state
1025  * is already the expected state and will wait for power irq only if
1026  * power irq is expected to be trigerred based on the current IO line state
1027  * and expected IO line state.
1028  */
1029 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1030 {
1031         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1032         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1033         bool done = false;
1034         u32 val;
1035
1036         pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1037                         mmc_hostname(host->mmc), __func__, req_type,
1038                         msm_host->curr_pwr_state, msm_host->curr_io_level);
1039
1040         /*
1041          * The power interrupt will not be generated for signal voltage
1042          * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1043          */
1044         val = readl(msm_host->core_mem + CORE_MCI_GENERICS);
1045         if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1046             !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1047                 return;
1048         }
1049
1050         /*
1051          * The IRQ for request type IO High/LOW will be generated when -
1052          * there is a state change in 1.8V enable bit (bit 3) of
1053          * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1054          * which indicates 3.3V IO voltage. So, when MMC core layer tries
1055          * to set it to 3.3V before card detection happens, the
1056          * IRQ doesn't get triggered as there is no state change in this bit.
1057          * The driver already handles this case by changing the IO voltage
1058          * level to high as part of controller power up sequence. Hence, check
1059          * for host->pwr to handle a case where IO voltage high request is
1060          * issued even before controller power up.
1061          */
1062         if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1063                 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1064                                 mmc_hostname(host->mmc), req_type);
1065                 return;
1066         }
1067         if ((req_type & msm_host->curr_pwr_state) ||
1068                         (req_type & msm_host->curr_io_level))
1069                 done = true;
1070         /*
1071          * This is needed here to handle cases where register writes will
1072          * not change the current bus state or io level of the controller.
1073          * In this case, no power irq will be triggerred and we should
1074          * not wait.
1075          */
1076         if (!done) {
1077                 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1078                                 msm_host->pwr_irq_flag,
1079                                 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1080                         dev_warn(&msm_host->pdev->dev,
1081                                  "%s: pwr_irq for req: (%d) timed out\n",
1082                                  mmc_hostname(host->mmc), req_type);
1083         }
1084         pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1085                         __func__, req_type);
1086 }
1087
1088 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1089 {
1090         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1091         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1092
1093         pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1094                         mmc_hostname(host->mmc),
1095                         readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS),
1096                         readl_relaxed(msm_host->core_mem + CORE_PWRCTL_MASK),
1097                         readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL));
1098 }
1099
1100 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1101 {
1102         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1103         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1104         u32 irq_status, irq_ack = 0;
1105         int retry = 10;
1106         int pwr_state = 0, io_level = 0;
1107
1108
1109         irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
1110         irq_status &= INT_MASK;
1111
1112         writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
1113
1114         /*
1115          * There is a rare HW scenario where the first clear pulse could be
1116          * lost when actual reset and clear/read of status register is
1117          * happening at a time. Hence, retry for at least 10 times to make
1118          * sure status register is cleared. Otherwise, this will result in
1119          * a spurious power IRQ resulting in system instability.
1120          */
1121         while (irq_status & readl_relaxed(msm_host->core_mem +
1122                                 CORE_PWRCTL_STATUS)) {
1123                 if (retry == 0) {
1124                         pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1125                                         mmc_hostname(host->mmc), irq_status);
1126                         sdhci_msm_dump_pwr_ctrl_regs(host);
1127                         WARN_ON(1);
1128                         break;
1129                 }
1130                 writel_relaxed(irq_status,
1131                                 msm_host->core_mem + CORE_PWRCTL_CLEAR);
1132                 retry--;
1133                 udelay(10);
1134         }
1135
1136         /* Handle BUS ON/OFF*/
1137         if (irq_status & CORE_PWRCTL_BUS_ON) {
1138                 pwr_state = REQ_BUS_ON;
1139                 io_level = REQ_IO_HIGH;
1140                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1141         }
1142         if (irq_status & CORE_PWRCTL_BUS_OFF) {
1143                 pwr_state = REQ_BUS_OFF;
1144                 io_level = REQ_IO_LOW;
1145                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1146         }
1147         /* Handle IO LOW/HIGH */
1148         if (irq_status & CORE_PWRCTL_IO_LOW) {
1149                 io_level = REQ_IO_LOW;
1150                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1151         }
1152         if (irq_status & CORE_PWRCTL_IO_HIGH) {
1153                 io_level = REQ_IO_HIGH;
1154                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1155         }
1156
1157         /*
1158          * The driver has to acknowledge the interrupt, switch voltages and
1159          * report back if it succeded or not to this register. The voltage
1160          * switches are handled by the sdhci core, so just report success.
1161          */
1162         writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
1163
1164         if (pwr_state)
1165                 msm_host->curr_pwr_state = pwr_state;
1166         if (io_level)
1167                 msm_host->curr_io_level = io_level;
1168
1169         pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1170                 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1171                 irq_ack);
1172 }
1173
1174 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1175 {
1176         struct sdhci_host *host = (struct sdhci_host *)data;
1177         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1178         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1179
1180         sdhci_msm_handle_pwr_irq(host, irq);
1181         msm_host->pwr_irq_flag = 1;
1182         sdhci_msm_complete_pwr_irq_wait(msm_host);
1183
1184
1185         return IRQ_HANDLED;
1186 }
1187
1188 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1189 {
1190         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1191         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1192         struct clk *core_clk = msm_host->bulk_clks[0].clk;
1193
1194         return clk_round_rate(core_clk, ULONG_MAX);
1195 }
1196
1197 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1198 {
1199         return SDHCI_MSM_MIN_CLOCK;
1200 }
1201
1202 /**
1203  * __sdhci_msm_set_clock - sdhci_msm clock control.
1204  *
1205  * Description:
1206  * MSM controller does not use internal divider and
1207  * instead directly control the GCC clock as per
1208  * HW recommendation.
1209  **/
1210 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1211 {
1212         u16 clk;
1213         /*
1214          * Keep actual_clock as zero -
1215          * - since there is no divider used so no need of having actual_clock.
1216          * - MSM controller uses SDCLK for data timeout calculation. If
1217          *   actual_clock is zero, host->clock is taken for calculation.
1218          */
1219         host->mmc->actual_clock = 0;
1220
1221         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1222
1223         if (clock == 0)
1224                 return;
1225
1226         /*
1227          * MSM controller do not use clock divider.
1228          * Thus read SDHCI_CLOCK_CONTROL and only enable
1229          * clock with no divider value programmed.
1230          */
1231         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1232         sdhci_enable_clk(host, clk);
1233 }
1234
1235 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1236 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1237 {
1238         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1239         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1240
1241         if (!clock) {
1242                 msm_host->clk_rate = clock;
1243                 goto out;
1244         }
1245
1246         sdhci_msm_hc_select_mode(host);
1247
1248         msm_set_clock_rate_for_bus_mode(host, clock);
1249 out:
1250         __sdhci_msm_set_clock(host, clock);
1251 }
1252
1253 /*
1254  * Platform specific register write functions. This is so that, if any
1255  * register write needs to be followed up by platform specific actions,
1256  * they can be added here. These functions can go to sleep when writes
1257  * to certain registers are done.
1258  * These functions are relying on sdhci_set_ios not using spinlock.
1259  */
1260 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1261 {
1262         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1263         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1264         u32 req_type = 0;
1265
1266         switch (reg) {
1267         case SDHCI_HOST_CONTROL2:
1268                 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1269                         REQ_IO_HIGH;
1270                 break;
1271         case SDHCI_SOFTWARE_RESET:
1272                 if (host->pwr && (val & SDHCI_RESET_ALL))
1273                         req_type = REQ_BUS_OFF;
1274                 break;
1275         case SDHCI_POWER_CONTROL:
1276                 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1277                 break;
1278         }
1279
1280         if (req_type) {
1281                 msm_host->pwr_irq_flag = 0;
1282                 /*
1283                  * Since this register write may trigger a power irq, ensure
1284                  * all previous register writes are complete by this point.
1285                  */
1286                 mb();
1287         }
1288         return req_type;
1289 }
1290
1291 /* This function may sleep*/
1292 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1293 {
1294         u32 req_type = 0;
1295
1296         req_type = __sdhci_msm_check_write(host, val, reg);
1297         writew_relaxed(val, host->ioaddr + reg);
1298
1299         if (req_type)
1300                 sdhci_msm_check_power_status(host, req_type);
1301 }
1302
1303 /* This function may sleep*/
1304 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1305 {
1306         u32 req_type = 0;
1307
1308         req_type = __sdhci_msm_check_write(host, val, reg);
1309
1310         writeb_relaxed(val, host->ioaddr + reg);
1311
1312         if (req_type)
1313                 sdhci_msm_check_power_status(host, req_type);
1314 }
1315
1316 static const struct of_device_id sdhci_msm_dt_match[] = {
1317         { .compatible = "qcom,sdhci-msm-v4" },
1318         {},
1319 };
1320
1321 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1322
1323 static const struct sdhci_ops sdhci_msm_ops = {
1324         .reset = sdhci_reset,
1325         .set_clock = sdhci_msm_set_clock,
1326         .get_min_clock = sdhci_msm_get_min_clock,
1327         .get_max_clock = sdhci_msm_get_max_clock,
1328         .set_bus_width = sdhci_set_bus_width,
1329         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1330         .write_w = sdhci_msm_writew,
1331         .write_b = sdhci_msm_writeb,
1332 };
1333
1334 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1335         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1336                   SDHCI_QUIRK_NO_CARD_NO_RESET |
1337                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1338                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1339         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1340         .ops = &sdhci_msm_ops,
1341 };
1342
1343 static int sdhci_msm_probe(struct platform_device *pdev)
1344 {
1345         struct sdhci_host *host;
1346         struct sdhci_pltfm_host *pltfm_host;
1347         struct sdhci_msm_host *msm_host;
1348         struct resource *core_memres;
1349         struct clk *clk;
1350         int ret;
1351         u16 host_version, core_minor;
1352         u32 core_version, config;
1353         u8 core_major;
1354
1355         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1356         if (IS_ERR(host))
1357                 return PTR_ERR(host);
1358
1359         host->sdma_boundary = 0;
1360         pltfm_host = sdhci_priv(host);
1361         msm_host = sdhci_pltfm_priv(pltfm_host);
1362         msm_host->mmc = host->mmc;
1363         msm_host->pdev = pdev;
1364
1365         ret = mmc_of_parse(host->mmc);
1366         if (ret)
1367                 goto pltfm_free;
1368
1369         sdhci_get_of_property(pdev);
1370
1371         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1372
1373         /* Setup SDCC bus voter clock. */
1374         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1375         if (!IS_ERR(msm_host->bus_clk)) {
1376                 /* Vote for max. clk rate for max. performance */
1377                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1378                 if (ret)
1379                         goto pltfm_free;
1380                 ret = clk_prepare_enable(msm_host->bus_clk);
1381                 if (ret)
1382                         goto pltfm_free;
1383         }
1384
1385         /* Setup main peripheral bus clock */
1386         clk = devm_clk_get(&pdev->dev, "iface");
1387         if (IS_ERR(clk)) {
1388                 ret = PTR_ERR(clk);
1389                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1390                 goto bus_clk_disable;
1391         }
1392         msm_host->bulk_clks[1].clk = clk;
1393
1394         /* Setup SDC MMC clock */
1395         clk = devm_clk_get(&pdev->dev, "core");
1396         if (IS_ERR(clk)) {
1397                 ret = PTR_ERR(clk);
1398                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1399                 goto bus_clk_disable;
1400         }
1401         msm_host->bulk_clks[0].clk = clk;
1402
1403         /* Vote for maximum clock rate for maximum performance */
1404         ret = clk_set_rate(clk, INT_MAX);
1405         if (ret)
1406                 dev_warn(&pdev->dev, "core clock boost failed\n");
1407
1408         clk = devm_clk_get(&pdev->dev, "cal");
1409         if (IS_ERR(clk))
1410                 clk = NULL;
1411         msm_host->bulk_clks[2].clk = clk;
1412
1413         clk = devm_clk_get(&pdev->dev, "sleep");
1414         if (IS_ERR(clk))
1415                 clk = NULL;
1416         msm_host->bulk_clks[3].clk = clk;
1417
1418         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1419                                       msm_host->bulk_clks);
1420         if (ret)
1421                 goto bus_clk_disable;
1422
1423         /*
1424          * xo clock is needed for FLL feature of cm_dll.
1425          * In case if xo clock is not mentioned in DT, warn and proceed.
1426          */
1427         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1428         if (IS_ERR(msm_host->xo_clk)) {
1429                 ret = PTR_ERR(msm_host->xo_clk);
1430                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1431         }
1432
1433         core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1434         msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
1435
1436         if (IS_ERR(msm_host->core_mem)) {
1437                 dev_err(&pdev->dev, "Failed to remap registers\n");
1438                 ret = PTR_ERR(msm_host->core_mem);
1439                 goto clk_disable;
1440         }
1441
1442         /* Reset the vendor spec register to power on reset state */
1443         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1444                        host->ioaddr + CORE_VENDOR_SPEC);
1445
1446         /* Set HC_MODE_EN bit in HC_MODE register */
1447         writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
1448
1449         config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
1450         config |= FF_CLK_SW_RST_DIS;
1451         writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
1452
1453         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1454         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1455                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1456                                SDHCI_VENDOR_VER_SHIFT));
1457
1458         core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
1459         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1460                       CORE_VERSION_MAJOR_SHIFT;
1461         core_minor = core_version & CORE_VERSION_MINOR_MASK;
1462         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1463                 core_version, core_major, core_minor);
1464
1465         if (core_major == 1 && core_minor >= 0x42)
1466                 msm_host->use_14lpp_dll_reset = true;
1467
1468         /*
1469          * SDCC 5 controller with major version 1, minor version 0x34 and later
1470          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1471          */
1472         if (core_major == 1 && core_minor < 0x34)
1473                 msm_host->use_cdclp533 = true;
1474
1475         /*
1476          * Support for some capabilities is not advertised by newer
1477          * controller versions and must be explicitly enabled.
1478          */
1479         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1480                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1481                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1482                 writel_relaxed(config, host->ioaddr +
1483                                CORE_VENDOR_SPEC_CAPABILITIES0);
1484         }
1485
1486         /*
1487          * Power on reset state may trigger power irq if previous status of
1488          * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1489          * interrupt in GIC, any pending power irq interrupt should be
1490          * acknowledged. Otherwise power irq interrupt handler would be
1491          * fired prematurely.
1492          */
1493         sdhci_msm_handle_pwr_irq(host, 0);
1494
1495         /*
1496          * Ensure that above writes are propogated before interrupt enablement
1497          * in GIC.
1498          */
1499         mb();
1500
1501         /* Setup IRQ for handling power/voltage tasks with PMIC */
1502         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1503         if (msm_host->pwr_irq < 0) {
1504                 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1505                         msm_host->pwr_irq);
1506                 ret = msm_host->pwr_irq;
1507                 goto clk_disable;
1508         }
1509
1510         sdhci_msm_init_pwr_irq_wait(msm_host);
1511         /* Enable pwr irq interrupts */
1512         writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);
1513
1514         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1515                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
1516                                         dev_name(&pdev->dev), host);
1517         if (ret) {
1518                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1519                 goto clk_disable;
1520         }
1521
1522         pm_runtime_get_noresume(&pdev->dev);
1523         pm_runtime_set_active(&pdev->dev);
1524         pm_runtime_enable(&pdev->dev);
1525         pm_runtime_set_autosuspend_delay(&pdev->dev,
1526                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
1527         pm_runtime_use_autosuspend(&pdev->dev);
1528
1529         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1530         ret = sdhci_add_host(host);
1531         if (ret)
1532                 goto pm_runtime_disable;
1533
1534         pm_runtime_mark_last_busy(&pdev->dev);
1535         pm_runtime_put_autosuspend(&pdev->dev);
1536
1537         return 0;
1538
1539 pm_runtime_disable:
1540         pm_runtime_disable(&pdev->dev);
1541         pm_runtime_set_suspended(&pdev->dev);
1542         pm_runtime_put_noidle(&pdev->dev);
1543 clk_disable:
1544         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1545                                    msm_host->bulk_clks);
1546 bus_clk_disable:
1547         if (!IS_ERR(msm_host->bus_clk))
1548                 clk_disable_unprepare(msm_host->bus_clk);
1549 pltfm_free:
1550         sdhci_pltfm_free(pdev);
1551         return ret;
1552 }
1553
1554 static int sdhci_msm_remove(struct platform_device *pdev)
1555 {
1556         struct sdhci_host *host = platform_get_drvdata(pdev);
1557         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1558         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1559         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1560                     0xffffffff);
1561
1562         sdhci_remove_host(host, dead);
1563
1564         pm_runtime_get_sync(&pdev->dev);
1565         pm_runtime_disable(&pdev->dev);
1566         pm_runtime_put_noidle(&pdev->dev);
1567
1568         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1569                                    msm_host->bulk_clks);
1570         if (!IS_ERR(msm_host->bus_clk))
1571                 clk_disable_unprepare(msm_host->bus_clk);
1572         sdhci_pltfm_free(pdev);
1573         return 0;
1574 }
1575
1576 #ifdef CONFIG_PM
1577 static int sdhci_msm_runtime_suspend(struct device *dev)
1578 {
1579         struct sdhci_host *host = dev_get_drvdata(dev);
1580         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1581         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1582
1583         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1584                                    msm_host->bulk_clks);
1585
1586         return 0;
1587 }
1588
1589 static int sdhci_msm_runtime_resume(struct device *dev)
1590 {
1591         struct sdhci_host *host = dev_get_drvdata(dev);
1592         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1593         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1594
1595         return clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1596                                        msm_host->bulk_clks);
1597 }
1598 #endif
1599
1600 static const struct dev_pm_ops sdhci_msm_pm_ops = {
1601         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1602                                 pm_runtime_force_resume)
1603         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1604                            sdhci_msm_runtime_resume,
1605                            NULL)
1606 };
1607
1608 static struct platform_driver sdhci_msm_driver = {
1609         .probe = sdhci_msm_probe,
1610         .remove = sdhci_msm_remove,
1611         .driver = {
1612                    .name = "sdhci_msm",
1613                    .of_match_table = sdhci_msm_dt_match,
1614                    .pm = &sdhci_msm_pm_ops,
1615         },
1616 };
1617
1618 module_platform_driver(sdhci_msm_driver);
1619
1620 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1621 MODULE_LICENSE("GPL v2");