2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/iopoll.h>
24 #include <linux/regulator/consumer.h>
26 #include "sdhci-pltfm.h"
28 #define CORE_MCI_VERSION 0x50
29 #define CORE_VERSION_MAJOR_SHIFT 28
30 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
31 #define CORE_VERSION_MINOR_MASK 0xff
33 #define CORE_MCI_GENERICS 0x70
34 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
36 #define HC_MODE_EN 0x1
37 #define CORE_POWER 0x0
38 #define CORE_SW_RST BIT(7)
39 #define FF_CLK_SW_RST_DIS BIT(13)
41 #define CORE_PWRCTL_BUS_OFF BIT(0)
42 #define CORE_PWRCTL_BUS_ON BIT(1)
43 #define CORE_PWRCTL_IO_LOW BIT(2)
44 #define CORE_PWRCTL_IO_HIGH BIT(3)
45 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
46 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
47 #define REQ_BUS_OFF BIT(0)
48 #define REQ_BUS_ON BIT(1)
49 #define REQ_IO_LOW BIT(2)
50 #define REQ_IO_HIGH BIT(3)
53 #define CORE_DLL_LOCK BIT(7)
54 #define CORE_DDR_DLL_LOCK BIT(11)
55 #define CORE_DLL_EN BIT(16)
56 #define CORE_CDR_EN BIT(17)
57 #define CORE_CK_OUT_EN BIT(18)
58 #define CORE_CDR_EXT_EN BIT(19)
59 #define CORE_DLL_PDN BIT(29)
60 #define CORE_DLL_RST BIT(30)
61 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
63 #define CORE_DDR_CAL_EN BIT(0)
64 #define CORE_FLL_CYCLE_CNT BIT(18)
65 #define CORE_DLL_CLOCK_DISABLE BIT(21)
67 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
68 #define CORE_CLK_PWRSAVE BIT(1)
69 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
70 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
71 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
72 #define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
73 #define CORE_IO_PAD_PWR_SWITCH (1 << 16)
74 #define CORE_HC_SELECT_IN_EN BIT(18)
75 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
76 #define CORE_HC_SELECT_IN_MASK (7 << 19)
78 #define CORE_3_0V_SUPPORT (1 << 25)
79 #define CORE_1_8V_SUPPORT (1 << 26)
80 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
82 #define CORE_CSR_CDC_CTLR_CFG0 0x130
83 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
84 #define CORE_HW_AUTOCAL_ENA BIT(17)
86 #define CORE_CSR_CDC_CTLR_CFG1 0x134
87 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
88 #define CORE_TIMER_ENA BIT(16)
90 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
91 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
92 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
93 #define CORE_CDC_OFFSET_CFG 0x14C
94 #define CORE_CSR_CDC_DELAY_CFG 0x150
95 #define CORE_CDC_SLAVE_DDA_CFG 0x160
96 #define CORE_CSR_CDC_STATUS0 0x164
97 #define CORE_CALIBRATION_DONE BIT(0)
99 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
101 #define CORE_CSR_CDC_GEN_CFG 0x178
102 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
103 #define CORE_CDC_SWITCH_RC_EN BIT(1)
105 #define CORE_CDC_T4_DLY_SEL BIT(0)
106 #define CORE_CMDIN_RCLK_EN BIT(1)
107 #define CORE_START_CDC_TRAFFIC BIT(6)
109 #define CORE_PWRSAVE_DLL BIT(3)
111 #define DDR_CONFIG_POR_VAL 0x80040853
114 #define INVALID_TUNING_PHASE -1
115 #define SDHCI_MSM_MIN_CLOCK 400000
116 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
118 #define CDR_SELEXT_SHIFT 20
119 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
120 #define CMUX_SHIFT_PHASE_SHIFT 24
121 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
123 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
125 /* Timeout value to avoid infinite waiting for pwr_irq */
126 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
128 #define msm_host_readl(msm_host, host, offset) \
129 msm_host->var_ops->msm_readl_relaxed(host, offset)
131 #define msm_host_writel(msm_host, val, host, offset) \
132 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
134 struct sdhci_msm_offset {
136 u32 core_mci_data_cnt;
138 u32 core_mci_fifo_cnt;
139 u32 core_mci_version;
141 u32 core_testbus_config;
142 u32 core_testbus_sel2_bit;
143 u32 core_testbus_ena;
144 u32 core_testbus_sel2;
145 u32 core_pwrctl_status;
146 u32 core_pwrctl_mask;
147 u32 core_pwrctl_clear;
149 u32 core_sdcc_debug_reg;
152 u32 core_vendor_spec;
153 u32 core_vendor_spec_adma_err_addr0;
154 u32 core_vendor_spec_adma_err_addr1;
155 u32 core_vendor_spec_func2;
156 u32 core_vendor_spec_capabilities0;
157 u32 core_ddr_200_cfg;
158 u32 core_vendor_spec3;
159 u32 core_dll_config_2;
161 u32 core_ddr_config_2;
164 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
165 .core_mci_data_cnt = 0x35c,
166 .core_mci_status = 0x324,
167 .core_mci_fifo_cnt = 0x308,
168 .core_mci_version = 0x318,
169 .core_generics = 0x320,
170 .core_testbus_config = 0x32c,
171 .core_testbus_sel2_bit = 3,
172 .core_testbus_ena = (1 << 31),
173 .core_testbus_sel2 = (1 << 3),
174 .core_pwrctl_status = 0x240,
175 .core_pwrctl_mask = 0x244,
176 .core_pwrctl_clear = 0x248,
177 .core_pwrctl_ctl = 0x24c,
178 .core_sdcc_debug_reg = 0x358,
179 .core_dll_config = 0x200,
180 .core_dll_status = 0x208,
181 .core_vendor_spec = 0x20c,
182 .core_vendor_spec_adma_err_addr0 = 0x214,
183 .core_vendor_spec_adma_err_addr1 = 0x218,
184 .core_vendor_spec_func2 = 0x210,
185 .core_vendor_spec_capabilities0 = 0x21c,
186 .core_ddr_200_cfg = 0x224,
187 .core_vendor_spec3 = 0x250,
188 .core_dll_config_2 = 0x254,
189 .core_ddr_config = 0x258,
190 .core_ddr_config_2 = 0x25c,
193 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
194 .core_hc_mode = 0x78,
195 .core_mci_data_cnt = 0x30,
196 .core_mci_status = 0x34,
197 .core_mci_fifo_cnt = 0x44,
198 .core_mci_version = 0x050,
199 .core_generics = 0x70,
200 .core_testbus_config = 0x0cc,
201 .core_testbus_sel2_bit = 4,
202 .core_testbus_ena = (1 << 3),
203 .core_testbus_sel2 = (1 << 4),
204 .core_pwrctl_status = 0xdc,
205 .core_pwrctl_mask = 0xe0,
206 .core_pwrctl_clear = 0xe4,
207 .core_pwrctl_ctl = 0xe8,
208 .core_sdcc_debug_reg = 0x124,
209 .core_dll_config = 0x100,
210 .core_dll_status = 0x108,
211 .core_vendor_spec = 0x10c,
212 .core_vendor_spec_adma_err_addr0 = 0x114,
213 .core_vendor_spec_adma_err_addr1 = 0x118,
214 .core_vendor_spec_func2 = 0x110,
215 .core_vendor_spec_capabilities0 = 0x11c,
216 .core_ddr_200_cfg = 0x184,
217 .core_vendor_spec3 = 0x1b0,
218 .core_dll_config_2 = 0x1b4,
219 .core_ddr_config = 0x1b8,
220 .core_ddr_config_2 = 0x1bc,
223 struct sdhci_msm_variant_ops {
224 u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
225 void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
230 * From V5, register spaces have changed. Wrap this info in a structure
231 * and choose the data_structure based on version info mentioned in DT.
233 struct sdhci_msm_variant_info {
235 const struct sdhci_msm_variant_ops *var_ops;
236 const struct sdhci_msm_offset *offset;
239 struct sdhci_msm_host {
240 struct platform_device *pdev;
241 void __iomem *core_mem; /* MSM SDCC mapped address */
242 int pwr_irq; /* power irq */
243 struct clk *bus_clk; /* SDHC bus voter clock */
244 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
245 struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
246 unsigned long clk_rate;
247 struct mmc_host *mmc;
248 bool use_14lpp_dll_reset;
250 bool calibration_done;
251 u8 saved_tuning_phase;
255 wait_queue_head_t pwr_irq_wait;
259 const struct sdhci_msm_variant_ops *var_ops;
260 const struct sdhci_msm_offset *offset;
263 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
265 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
266 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
268 return msm_host->offset;
272 * APIs to read/write to vendor specific registers which were there in the
273 * core_mem region before MCI was removed.
275 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
279 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
281 return readl_relaxed(msm_host->core_mem + offset);
284 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
287 return readl_relaxed(host->ioaddr + offset);
290 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
291 struct sdhci_host *host, u32 offset)
293 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
294 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
296 writel_relaxed(val, msm_host->core_mem + offset);
299 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
300 struct sdhci_host *host, u32 offset)
302 writel_relaxed(val, host->ioaddr + offset);
305 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
308 struct mmc_ios ios = host->mmc->ios;
310 * The SDHC requires internal clock frequency to be double the
311 * actual clock that will be set for DDR mode. The controller
312 * uses the faster clock(100/400MHz) for some of its parts and
313 * send the actual required clock (50/200MHz) to the card.
315 if (ios.timing == MMC_TIMING_UHS_DDR50 ||
316 ios.timing == MMC_TIMING_MMC_DDR52 ||
317 ios.timing == MMC_TIMING_MMC_HS400 ||
318 host->flags & SDHCI_HS400_TUNING)
323 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
326 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
327 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
328 struct mmc_ios curr_ios = host->mmc->ios;
329 struct clk *core_clk = msm_host->bulk_clks[0].clk;
332 clock = msm_get_clock_rate_for_bus_mode(host, clock);
333 rc = clk_set_rate(core_clk, clock);
335 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
336 mmc_hostname(host->mmc), clock,
340 msm_host->clk_rate = clock;
341 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
342 mmc_hostname(host->mmc), clk_get_rate(core_clk),
346 /* Platform specific tuning */
347 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
351 struct mmc_host *mmc = host->mmc;
352 const struct sdhci_msm_offset *msm_offset =
353 sdhci_priv_msm_offset(host);
355 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
356 ck_out_en = !!(readl_relaxed(host->ioaddr +
357 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
359 while (ck_out_en != poll) {
360 if (--wait_cnt == 0) {
361 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
362 mmc_hostname(mmc), poll);
367 ck_out_en = !!(readl_relaxed(host->ioaddr +
368 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
374 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
377 static const u8 grey_coded_phase_table[] = {
378 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
379 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
383 struct mmc_host *mmc = host->mmc;
384 const struct sdhci_msm_offset *msm_offset =
385 sdhci_priv_msm_offset(host);
390 spin_lock_irqsave(&host->lock, flags);
392 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
393 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
394 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
395 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
397 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
398 rc = msm_dll_poll_ck_out_en(host, 0);
403 * Write the selected DLL clock output phase (0 ... 15)
404 * to CDR_SELEXT bit field of DLL_CONFIG register.
406 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
407 config &= ~CDR_SELEXT_MASK;
408 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
409 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
411 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
412 config |= CORE_CK_OUT_EN;
413 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
415 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
416 rc = msm_dll_poll_ck_out_en(host, 1);
420 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
421 config |= CORE_CDR_EN;
422 config &= ~CORE_CDR_EXT_EN;
423 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
427 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
428 mmc_hostname(mmc), phase);
430 spin_unlock_irqrestore(&host->lock, flags);
435 * Find out the greatest range of consecuitive selected
436 * DLL clock output phases that can be used as sampling
437 * setting for SD3.0 UHS-I card read operation (in SDR104
438 * timing mode) or for eMMC4.5 card read operation (in
439 * HS400/HS200 timing mode).
440 * Select the 3/4 of the range and configure the DLL with the
441 * selected DLL clock output phase.
444 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
445 u8 *phase_table, u8 total_phases)
448 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
449 u8 phases_per_row[MAX_PHASES] = { 0 };
450 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
451 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
452 bool phase_0_found = false, phase_15_found = false;
453 struct mmc_host *mmc = host->mmc;
455 if (!total_phases || (total_phases > MAX_PHASES)) {
456 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
457 mmc_hostname(mmc), total_phases);
461 for (cnt = 0; cnt < total_phases; cnt++) {
462 ranges[row_index][col_index] = phase_table[cnt];
463 phases_per_row[row_index] += 1;
466 if ((cnt + 1) == total_phases) {
468 /* check if next phase in phase_table is consecutive or not */
469 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
475 if (row_index >= MAX_PHASES)
478 /* Check if phase-0 is present in first valid window? */
480 phase_0_found = true;
481 phase_0_raw_index = 0;
482 /* Check if cycle exist between 2 valid windows */
483 for (cnt = 1; cnt <= row_index; cnt++) {
484 if (phases_per_row[cnt]) {
485 for (i = 0; i < phases_per_row[cnt]; i++) {
486 if (ranges[cnt][i] == 15) {
487 phase_15_found = true;
488 phase_15_raw_index = cnt;
496 /* If 2 valid windows form cycle then merge them as single window */
497 if (phase_0_found && phase_15_found) {
498 /* number of phases in raw where phase 0 is present */
499 u8 phases_0 = phases_per_row[phase_0_raw_index];
500 /* number of phases in raw where phase 15 is present */
501 u8 phases_15 = phases_per_row[phase_15_raw_index];
503 if (phases_0 + phases_15 >= MAX_PHASES)
505 * If there are more than 1 phase windows then total
506 * number of phases in both the windows should not be
507 * more than or equal to MAX_PHASES.
511 /* Merge 2 cyclic windows */
513 for (cnt = 0; cnt < phases_0; cnt++) {
514 ranges[phase_15_raw_index][i] =
515 ranges[phase_0_raw_index][cnt];
516 if (++i >= MAX_PHASES)
520 phases_per_row[phase_0_raw_index] = 0;
521 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
524 for (cnt = 0; cnt <= row_index; cnt++) {
525 if (phases_per_row[cnt] > curr_max) {
526 curr_max = phases_per_row[cnt];
527 selected_row_index = cnt;
531 i = (curr_max * 3) / 4;
535 ret = ranges[selected_row_index][i];
537 if (ret >= MAX_PHASES) {
539 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
540 mmc_hostname(mmc), ret);
546 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
548 u32 mclk_freq = 0, config;
549 const struct sdhci_msm_offset *msm_offset =
550 sdhci_priv_msm_offset(host);
552 /* Program the MCLK value to MCLK_FREQ bit field */
553 if (host->clock <= 112000000)
555 else if (host->clock <= 125000000)
557 else if (host->clock <= 137000000)
559 else if (host->clock <= 150000000)
561 else if (host->clock <= 162000000)
563 else if (host->clock <= 175000000)
565 else if (host->clock <= 187000000)
567 else if (host->clock <= 200000000)
570 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
571 config &= ~CMUX_SHIFT_PHASE_MASK;
572 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
573 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
576 /* Initialize the DLL (Programmable Delay Line) */
577 static int msm_init_cm_dll(struct sdhci_host *host)
579 struct mmc_host *mmc = host->mmc;
580 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
581 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
585 const struct sdhci_msm_offset *msm_offset =
588 spin_lock_irqsave(&host->lock, flags);
591 * Make sure that clock is always enabled when DLL
592 * tuning is in progress. Keeping PWRSAVE ON may
593 * turn off the clock.
595 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
596 config &= ~CORE_CLK_PWRSAVE;
597 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
599 if (msm_host->use_14lpp_dll_reset) {
600 config = readl_relaxed(host->ioaddr +
601 msm_offset->core_dll_config);
602 config &= ~CORE_CK_OUT_EN;
603 writel_relaxed(config, host->ioaddr +
604 msm_offset->core_dll_config);
606 config = readl_relaxed(host->ioaddr +
607 msm_offset->core_dll_config_2);
608 config |= CORE_DLL_CLOCK_DISABLE;
609 writel_relaxed(config, host->ioaddr +
610 msm_offset->core_dll_config_2);
613 config = readl_relaxed(host->ioaddr +
614 msm_offset->core_dll_config);
615 config |= CORE_DLL_RST;
616 writel_relaxed(config, host->ioaddr +
617 msm_offset->core_dll_config);
619 config = readl_relaxed(host->ioaddr +
620 msm_offset->core_dll_config);
621 config |= CORE_DLL_PDN;
622 writel_relaxed(config, host->ioaddr +
623 msm_offset->core_dll_config);
624 msm_cm_dll_set_freq(host);
626 if (msm_host->use_14lpp_dll_reset &&
627 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
630 config = readl_relaxed(host->ioaddr +
631 msm_offset->core_dll_config_2);
632 config &= CORE_FLL_CYCLE_CNT;
634 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
635 clk_get_rate(msm_host->xo_clk));
637 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
638 clk_get_rate(msm_host->xo_clk));
640 config = readl_relaxed(host->ioaddr +
641 msm_offset->core_dll_config_2);
642 config &= ~(0xFF << 10);
643 config |= mclk_freq << 10;
645 writel_relaxed(config, host->ioaddr +
646 msm_offset->core_dll_config_2);
647 /* wait for 5us before enabling DLL clock */
651 config = readl_relaxed(host->ioaddr +
652 msm_offset->core_dll_config);
653 config &= ~CORE_DLL_RST;
654 writel_relaxed(config, host->ioaddr +
655 msm_offset->core_dll_config);
657 config = readl_relaxed(host->ioaddr +
658 msm_offset->core_dll_config);
659 config &= ~CORE_DLL_PDN;
660 writel_relaxed(config, host->ioaddr +
661 msm_offset->core_dll_config);
663 if (msm_host->use_14lpp_dll_reset) {
664 msm_cm_dll_set_freq(host);
665 config = readl_relaxed(host->ioaddr +
666 msm_offset->core_dll_config_2);
667 config &= ~CORE_DLL_CLOCK_DISABLE;
668 writel_relaxed(config, host->ioaddr +
669 msm_offset->core_dll_config_2);
672 config = readl_relaxed(host->ioaddr +
673 msm_offset->core_dll_config);
674 config |= CORE_DLL_EN;
675 writel_relaxed(config, host->ioaddr +
676 msm_offset->core_dll_config);
678 config = readl_relaxed(host->ioaddr +
679 msm_offset->core_dll_config);
680 config |= CORE_CK_OUT_EN;
681 writel_relaxed(config, host->ioaddr +
682 msm_offset->core_dll_config);
684 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
685 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
687 /* max. wait for 50us sec for LOCK bit to be set */
688 if (--wait_cnt == 0) {
689 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
691 spin_unlock_irqrestore(&host->lock, flags);
697 spin_unlock_irqrestore(&host->lock, flags);
701 static void msm_hc_select_default(struct sdhci_host *host)
703 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
704 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
706 const struct sdhci_msm_offset *msm_offset =
709 if (!msm_host->use_cdclp533) {
710 config = readl_relaxed(host->ioaddr +
711 msm_offset->core_vendor_spec3);
712 config &= ~CORE_PWRSAVE_DLL;
713 writel_relaxed(config, host->ioaddr +
714 msm_offset->core_vendor_spec3);
717 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
718 config &= ~CORE_HC_MCLK_SEL_MASK;
719 config |= CORE_HC_MCLK_SEL_DFLT;
720 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
723 * Disable HC_SELECT_IN to be able to use the UHS mode select
724 * configuration from Host Control2 register for all other
726 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
727 * in VENDOR_SPEC_FUNC
729 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
730 config &= ~CORE_HC_SELECT_IN_EN;
731 config &= ~CORE_HC_SELECT_IN_MASK;
732 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
735 * Make sure above writes impacting free running MCLK are completed
736 * before changing the clk_rate at GCC.
741 static void msm_hc_select_hs400(struct sdhci_host *host)
743 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
744 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
745 struct mmc_ios ios = host->mmc->ios;
746 u32 config, dll_lock;
748 const struct sdhci_msm_offset *msm_offset =
751 /* Select the divided clock (free running MCLK/2) */
752 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
753 config &= ~CORE_HC_MCLK_SEL_MASK;
754 config |= CORE_HC_MCLK_SEL_HS400;
756 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
758 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
761 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
762 !msm_host->calibration_done) {
763 config = readl_relaxed(host->ioaddr +
764 msm_offset->core_vendor_spec);
765 config |= CORE_HC_SELECT_IN_HS400;
766 config |= CORE_HC_SELECT_IN_EN;
767 writel_relaxed(config, host->ioaddr +
768 msm_offset->core_vendor_spec);
770 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
772 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
773 * core_dll_status to be set. This should get set
774 * within 15 us at 200 MHz.
776 rc = readl_relaxed_poll_timeout(host->ioaddr +
777 msm_offset->core_dll_status,
781 CORE_DDR_DLL_LOCK)), 10,
783 if (rc == -ETIMEDOUT)
784 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
785 mmc_hostname(host->mmc), dll_lock);
788 * Make sure above writes impacting free running MCLK are completed
789 * before changing the clk_rate at GCC.
795 * sdhci_msm_hc_select_mode :- In general all timing modes are
796 * controlled via UHS mode select in Host Control2 register.
797 * eMMC specific HS200/HS400 doesn't have their respective modes
798 * defined here, hence we use these values.
800 * HS200 - SDR104 (Since they both are equivalent in functionality)
801 * HS400 - This involves multiple configurations
802 * Initially SDR104 - when tuning is required as HS200
803 * Then when switching to DDR @ 400MHz (HS400) we use
804 * the vendor specific HC_SELECT_IN to control the mode.
806 * In addition to controlling the modes we also need to select the
807 * correct input clock for DLL depending on the mode.
809 * HS400 - divided clock (free running MCLK/2)
810 * All other modes - default (free running MCLK)
812 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
814 struct mmc_ios ios = host->mmc->ios;
816 if (ios.timing == MMC_TIMING_MMC_HS400 ||
817 host->flags & SDHCI_HS400_TUNING)
818 msm_hc_select_hs400(host);
820 msm_hc_select_default(host);
823 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
825 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
826 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
827 u32 config, calib_done;
829 const struct sdhci_msm_offset *msm_offset =
832 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
835 * Retuning in HS400 (DDR mode) will fail, just reset the
836 * tuning block and restore the saved tuning phase.
838 ret = msm_init_cm_dll(host);
842 /* Set the selected phase in delay line hw block */
843 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
847 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
848 config |= CORE_CMD_DAT_TRACK_SEL;
849 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
851 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
852 config &= ~CORE_CDC_T4_DLY_SEL;
853 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
855 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
856 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
857 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
859 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
860 config |= CORE_CDC_SWITCH_RC_EN;
861 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
863 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
864 config &= ~CORE_START_CDC_TRAFFIC;
865 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
867 /* Perform CDC Register Initialization Sequence */
869 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
870 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
871 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
872 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
873 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
874 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
875 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
876 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
877 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
879 /* CDC HW Calibration */
881 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
882 config |= CORE_SW_TRIG_FULL_CALIB;
883 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
885 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
886 config &= ~CORE_SW_TRIG_FULL_CALIB;
887 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
889 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
890 config |= CORE_HW_AUTOCAL_ENA;
891 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
893 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
894 config |= CORE_TIMER_ENA;
895 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
897 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
899 (calib_done & CORE_CALIBRATION_DONE),
902 if (ret == -ETIMEDOUT) {
903 pr_err("%s: %s: CDC calibration was not completed\n",
904 mmc_hostname(host->mmc), __func__);
908 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
909 & CORE_CDC_ERROR_CODE_MASK;
911 pr_err("%s: %s: CDC error code %d\n",
912 mmc_hostname(host->mmc), __func__, ret);
917 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
918 config |= CORE_START_CDC_TRAFFIC;
919 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
921 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
926 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
928 struct mmc_host *mmc = host->mmc;
929 u32 dll_status, config;
931 const struct sdhci_msm_offset *msm_offset =
932 sdhci_priv_msm_offset(host);
934 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
937 * Currently the core_ddr_config register defaults to desired
938 * configuration on reset. Currently reprogramming the power on
939 * reset (POR) value in case it might have been modified by
940 * bootloaders. In the future, if this changes, then the desired
941 * values will need to be programmed appropriately.
943 writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr +
944 msm_offset->core_ddr_config);
946 if (mmc->ios.enhanced_strobe) {
947 config = readl_relaxed(host->ioaddr +
948 msm_offset->core_ddr_200_cfg);
949 config |= CORE_CMDIN_RCLK_EN;
950 writel_relaxed(config, host->ioaddr +
951 msm_offset->core_ddr_200_cfg);
954 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
955 config |= CORE_DDR_CAL_EN;
956 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
958 ret = readl_relaxed_poll_timeout(host->ioaddr +
959 msm_offset->core_dll_status,
961 (dll_status & CORE_DDR_DLL_LOCK),
964 if (ret == -ETIMEDOUT) {
965 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
966 mmc_hostname(host->mmc), __func__);
970 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
971 config |= CORE_PWRSAVE_DLL;
972 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
975 * Drain writebuffer to ensure above DLL calibration
976 * and PWRSAVE DLL is enabled.
980 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
985 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
987 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
988 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
989 struct mmc_host *mmc = host->mmc;
992 const struct sdhci_msm_offset *msm_offset =
995 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
998 * Retuning in HS400 (DDR mode) will fail, just reset the
999 * tuning block and restore the saved tuning phase.
1001 ret = msm_init_cm_dll(host);
1005 if (!mmc->ios.enhanced_strobe) {
1006 /* Set the selected phase in delay line hw block */
1007 ret = msm_config_cm_dll_phase(host,
1008 msm_host->saved_tuning_phase);
1011 config = readl_relaxed(host->ioaddr +
1012 msm_offset->core_dll_config);
1013 config |= CORE_CMD_DAT_TRACK_SEL;
1014 writel_relaxed(config, host->ioaddr +
1015 msm_offset->core_dll_config);
1018 if (msm_host->use_cdclp533)
1019 ret = sdhci_msm_cdclp533_calibration(host);
1021 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1023 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1028 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1030 struct sdhci_host *host = mmc_priv(mmc);
1031 int tuning_seq_cnt = 3;
1032 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1034 struct mmc_ios ios = host->mmc->ios;
1035 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1036 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1039 * Tuning is required for SDR104, HS200 and HS400 cards and
1040 * if clock frequency is greater than 100MHz in these modes.
1042 if (host->clock <= CORE_FREQ_100MHZ ||
1043 !(ios.timing == MMC_TIMING_MMC_HS400 ||
1044 ios.timing == MMC_TIMING_MMC_HS200 ||
1045 ios.timing == MMC_TIMING_UHS_SDR104))
1049 * For HS400 tuning in HS200 timing requires:
1050 * - select MCLK/2 in VENDOR_SPEC
1051 * - program MCLK to 400MHz (or nearest supported) in GCC
1053 if (host->flags & SDHCI_HS400_TUNING) {
1054 sdhci_msm_hc_select_mode(host);
1055 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1056 host->flags &= ~SDHCI_HS400_TUNING;
1060 /* First of all reset the tuning block */
1061 rc = msm_init_cm_dll(host);
1067 /* Set the phase in delay line hw block */
1068 rc = msm_config_cm_dll_phase(host, phase);
1072 msm_host->saved_tuning_phase = phase;
1073 rc = mmc_send_tuning(mmc, opcode, NULL);
1075 /* Tuning is successful at this tuning point */
1076 tuned_phases[tuned_phase_cnt++] = phase;
1077 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1078 mmc_hostname(mmc), phase);
1080 } while (++phase < ARRAY_SIZE(tuned_phases));
1082 if (tuned_phase_cnt) {
1083 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1091 * Finally set the selected phase in delay
1094 rc = msm_config_cm_dll_phase(host, phase);
1097 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1098 mmc_hostname(mmc), phase);
1100 if (--tuning_seq_cnt)
1103 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1109 msm_host->tuning_done = true;
1114 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1115 * This needs to be done for both tuning and enhanced_strobe mode.
1116 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1117 * fixed feedback clock is used.
1119 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1121 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1122 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1125 if (host->clock > CORE_FREQ_100MHZ &&
1126 (msm_host->tuning_done || ios->enhanced_strobe) &&
1127 !msm_host->calibration_done) {
1128 ret = sdhci_msm_hs400_dll_calibration(host);
1130 msm_host->calibration_done = true;
1132 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1133 mmc_hostname(host->mmc), ret);
1137 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1140 struct mmc_host *mmc = host->mmc;
1141 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1142 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1145 const struct sdhci_msm_offset *msm_offset =
1148 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1149 /* Select Bus Speed Mode for host */
1150 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1152 case MMC_TIMING_UHS_SDR12:
1153 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1155 case MMC_TIMING_UHS_SDR25:
1156 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1158 case MMC_TIMING_UHS_SDR50:
1159 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1161 case MMC_TIMING_MMC_HS400:
1162 case MMC_TIMING_MMC_HS200:
1163 case MMC_TIMING_UHS_SDR104:
1164 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1166 case MMC_TIMING_UHS_DDR50:
1167 case MMC_TIMING_MMC_DDR52:
1168 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1173 * When clock frequency is less than 100MHz, the feedback clock must be
1174 * provided and DLL must not be used so that tuning can be skipped. To
1175 * provide feedback clock, the mode selection can be any value less
1176 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1178 if (host->clock <= CORE_FREQ_100MHZ) {
1179 if (uhs == MMC_TIMING_MMC_HS400 ||
1180 uhs == MMC_TIMING_MMC_HS200 ||
1181 uhs == MMC_TIMING_UHS_SDR104)
1182 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1184 * DLL is not required for clock <= 100MHz
1185 * Thus, make sure DLL it is disabled when not required
1187 config = readl_relaxed(host->ioaddr +
1188 msm_offset->core_dll_config);
1189 config |= CORE_DLL_RST;
1190 writel_relaxed(config, host->ioaddr +
1191 msm_offset->core_dll_config);
1193 config = readl_relaxed(host->ioaddr +
1194 msm_offset->core_dll_config);
1195 config |= CORE_DLL_PDN;
1196 writel_relaxed(config, host->ioaddr +
1197 msm_offset->core_dll_config);
1200 * The DLL needs to be restored and CDCLP533 recalibrated
1201 * when the clock frequency is set back to 400MHz.
1203 msm_host->calibration_done = false;
1206 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1207 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1208 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1210 if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1211 sdhci_msm_hs400(host, &mmc->ios);
1214 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1216 init_waitqueue_head(&msm_host->pwr_irq_wait);
1219 static inline void sdhci_msm_complete_pwr_irq_wait(
1220 struct sdhci_msm_host *msm_host)
1222 wake_up(&msm_host->pwr_irq_wait);
1226 * sdhci_msm_check_power_status API should be called when registers writes
1227 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1228 * To what state the register writes will change the IO lines should be passed
1229 * as the argument req_type. This API will check whether the IO line's state
1230 * is already the expected state and will wait for power irq only if
1231 * power irq is expected to be trigerred based on the current IO line state
1232 * and expected IO line state.
1234 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1236 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1237 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1239 u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1240 const struct sdhci_msm_offset *msm_offset =
1243 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1244 mmc_hostname(host->mmc), __func__, req_type,
1245 msm_host->curr_pwr_state, msm_host->curr_io_level);
1248 * The power interrupt will not be generated for signal voltage
1249 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1250 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1253 if (!msm_host->mci_removed)
1254 val = msm_host_readl(msm_host, host,
1255 msm_offset->core_generics);
1256 if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1257 !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1262 * The IRQ for request type IO High/LOW will be generated when -
1263 * there is a state change in 1.8V enable bit (bit 3) of
1264 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1265 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1266 * to set it to 3.3V before card detection happens, the
1267 * IRQ doesn't get triggered as there is no state change in this bit.
1268 * The driver already handles this case by changing the IO voltage
1269 * level to high as part of controller power up sequence. Hence, check
1270 * for host->pwr to handle a case where IO voltage high request is
1271 * issued even before controller power up.
1273 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1274 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1275 mmc_hostname(host->mmc), req_type);
1278 if ((req_type & msm_host->curr_pwr_state) ||
1279 (req_type & msm_host->curr_io_level))
1282 * This is needed here to handle cases where register writes will
1283 * not change the current bus state or io level of the controller.
1284 * In this case, no power irq will be triggerred and we should
1288 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1289 msm_host->pwr_irq_flag,
1290 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1291 dev_warn(&msm_host->pdev->dev,
1292 "%s: pwr_irq for req: (%d) timed out\n",
1293 mmc_hostname(host->mmc), req_type);
1295 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1296 __func__, req_type);
1299 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1301 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1302 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1303 const struct sdhci_msm_offset *msm_offset =
1306 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1307 mmc_hostname(host->mmc),
1308 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1309 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1310 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1313 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1315 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1316 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1317 u32 irq_status, irq_ack = 0;
1319 u32 pwr_state = 0, io_level = 0;
1321 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1323 irq_status = msm_host_readl(msm_host, host,
1324 msm_offset->core_pwrctl_status);
1325 irq_status &= INT_MASK;
1327 msm_host_writel(msm_host, irq_status, host,
1328 msm_offset->core_pwrctl_clear);
1331 * There is a rare HW scenario where the first clear pulse could be
1332 * lost when actual reset and clear/read of status register is
1333 * happening at a time. Hence, retry for at least 10 times to make
1334 * sure status register is cleared. Otherwise, this will result in
1335 * a spurious power IRQ resulting in system instability.
1337 while (irq_status & msm_host_readl(msm_host, host,
1338 msm_offset->core_pwrctl_status)) {
1340 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1341 mmc_hostname(host->mmc), irq_status);
1342 sdhci_msm_dump_pwr_ctrl_regs(host);
1346 msm_host_writel(msm_host, irq_status, host,
1347 msm_offset->core_pwrctl_clear);
1352 /* Handle BUS ON/OFF*/
1353 if (irq_status & CORE_PWRCTL_BUS_ON) {
1354 pwr_state = REQ_BUS_ON;
1355 io_level = REQ_IO_HIGH;
1356 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1358 if (irq_status & CORE_PWRCTL_BUS_OFF) {
1359 pwr_state = REQ_BUS_OFF;
1360 io_level = REQ_IO_LOW;
1361 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1363 /* Handle IO LOW/HIGH */
1364 if (irq_status & CORE_PWRCTL_IO_LOW) {
1365 io_level = REQ_IO_LOW;
1366 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1368 if (irq_status & CORE_PWRCTL_IO_HIGH) {
1369 io_level = REQ_IO_HIGH;
1370 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1374 * The driver has to acknowledge the interrupt, switch voltages and
1375 * report back if it succeded or not to this register. The voltage
1376 * switches are handled by the sdhci core, so just report success.
1378 msm_host_writel(msm_host, irq_ack, host,
1379 msm_offset->core_pwrctl_ctl);
1382 * If we don't have info regarding the voltage levels supported by
1383 * regulators, don't change the IO PAD PWR SWITCH.
1385 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1388 * We should unset IO PAD PWR switch only if the register write
1389 * can set IO lines high and the regulator also switches to 3 V.
1390 * Else, we should keep the IO PAD PWR switch set.
1391 * This is applicable to certain targets where eMMC vccq supply
1392 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1393 * IO PAD PWR switch must be kept set to reflect actual
1394 * regulator voltage. This way, during initialization of
1395 * controllers with only 1.8V, we will set the IO PAD bit
1396 * without waiting for a REQ_IO_LOW.
1398 config = readl_relaxed(host->ioaddr +
1399 msm_offset->core_vendor_spec);
1400 new_config = config;
1402 if ((io_level & REQ_IO_HIGH) &&
1403 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1404 new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1405 else if ((io_level & REQ_IO_LOW) ||
1406 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1407 new_config |= CORE_IO_PAD_PWR_SWITCH;
1409 if (config ^ new_config)
1410 writel_relaxed(new_config, host->ioaddr +
1411 msm_offset->core_vendor_spec);
1415 msm_host->curr_pwr_state = pwr_state;
1417 msm_host->curr_io_level = io_level;
1419 pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1420 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1424 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1426 struct sdhci_host *host = (struct sdhci_host *)data;
1427 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1428 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1430 sdhci_msm_handle_pwr_irq(host, irq);
1431 msm_host->pwr_irq_flag = 1;
1432 sdhci_msm_complete_pwr_irq_wait(msm_host);
1438 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1440 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1441 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1442 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1444 return clk_round_rate(core_clk, ULONG_MAX);
1447 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1449 return SDHCI_MSM_MIN_CLOCK;
1453 * __sdhci_msm_set_clock - sdhci_msm clock control.
1456 * MSM controller does not use internal divider and
1457 * instead directly control the GCC clock as per
1458 * HW recommendation.
1460 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1464 * Keep actual_clock as zero -
1465 * - since there is no divider used so no need of having actual_clock.
1466 * - MSM controller uses SDCLK for data timeout calculation. If
1467 * actual_clock is zero, host->clock is taken for calculation.
1469 host->mmc->actual_clock = 0;
1471 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1477 * MSM controller do not use clock divider.
1478 * Thus read SDHCI_CLOCK_CONTROL and only enable
1479 * clock with no divider value programmed.
1481 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1482 sdhci_enable_clk(host, clk);
1485 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1486 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1488 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1489 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1492 msm_host->clk_rate = clock;
1496 sdhci_msm_hc_select_mode(host);
1498 msm_set_clock_rate_for_bus_mode(host, clock);
1500 __sdhci_msm_set_clock(host, clock);
1504 * Platform specific register write functions. This is so that, if any
1505 * register write needs to be followed up by platform specific actions,
1506 * they can be added here. These functions can go to sleep when writes
1507 * to certain registers are done.
1508 * These functions are relying on sdhci_set_ios not using spinlock.
1510 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1512 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1513 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1517 case SDHCI_HOST_CONTROL2:
1518 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1521 case SDHCI_SOFTWARE_RESET:
1522 if (host->pwr && (val & SDHCI_RESET_ALL))
1523 req_type = REQ_BUS_OFF;
1525 case SDHCI_POWER_CONTROL:
1526 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1531 msm_host->pwr_irq_flag = 0;
1533 * Since this register write may trigger a power irq, ensure
1534 * all previous register writes are complete by this point.
1541 /* This function may sleep*/
1542 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1546 req_type = __sdhci_msm_check_write(host, val, reg);
1547 writew_relaxed(val, host->ioaddr + reg);
1550 sdhci_msm_check_power_status(host, req_type);
1553 /* This function may sleep*/
1554 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1558 req_type = __sdhci_msm_check_write(host, val, reg);
1560 writeb_relaxed(val, host->ioaddr + reg);
1563 sdhci_msm_check_power_status(host, req_type);
1566 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1568 struct mmc_host *mmc = msm_host->mmc;
1569 struct regulator *supply = mmc->supply.vqmmc;
1570 u32 caps = 0, config;
1571 struct sdhci_host *host = mmc_priv(mmc);
1572 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1574 if (!IS_ERR(mmc->supply.vqmmc)) {
1575 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1576 caps |= CORE_1_8V_SUPPORT;
1577 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1578 caps |= CORE_3_0V_SUPPORT;
1581 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1587 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1588 * bit can be used as required later on.
1590 u32 io_level = msm_host->curr_io_level;
1592 config = readl_relaxed(host->ioaddr +
1593 msm_offset->core_vendor_spec);
1594 config |= CORE_IO_PAD_PWR_SWITCH_EN;
1596 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
1597 config &= ~CORE_IO_PAD_PWR_SWITCH;
1598 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
1599 config |= CORE_IO_PAD_PWR_SWITCH;
1601 writel_relaxed(config,
1602 host->ioaddr + msm_offset->core_vendor_spec);
1604 msm_host->caps_0 |= caps;
1605 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1608 static const struct sdhci_msm_variant_ops mci_var_ops = {
1609 .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
1610 .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
1613 static const struct sdhci_msm_variant_ops v5_var_ops = {
1614 .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
1615 .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
1618 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
1619 .mci_removed = false,
1620 .var_ops = &mci_var_ops,
1621 .offset = &sdhci_msm_mci_offset,
1624 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
1625 .mci_removed = true,
1626 .var_ops = &v5_var_ops,
1627 .offset = &sdhci_msm_v5_offset,
1630 static const struct of_device_id sdhci_msm_dt_match[] = {
1631 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
1632 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
1636 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1638 static const struct sdhci_ops sdhci_msm_ops = {
1639 .reset = sdhci_reset,
1640 .set_clock = sdhci_msm_set_clock,
1641 .get_min_clock = sdhci_msm_get_min_clock,
1642 .get_max_clock = sdhci_msm_get_max_clock,
1643 .set_bus_width = sdhci_set_bus_width,
1644 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1645 .write_w = sdhci_msm_writew,
1646 .write_b = sdhci_msm_writeb,
1649 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1650 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1651 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1652 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1653 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1654 .ops = &sdhci_msm_ops,
1657 static int sdhci_msm_probe(struct platform_device *pdev)
1659 struct sdhci_host *host;
1660 struct sdhci_pltfm_host *pltfm_host;
1661 struct sdhci_msm_host *msm_host;
1662 struct resource *core_memres;
1665 u16 host_version, core_minor;
1666 u32 core_version, config;
1668 const struct sdhci_msm_offset *msm_offset;
1669 const struct sdhci_msm_variant_info *var_info;
1671 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1673 return PTR_ERR(host);
1675 host->sdma_boundary = 0;
1676 pltfm_host = sdhci_priv(host);
1677 msm_host = sdhci_pltfm_priv(pltfm_host);
1678 msm_host->mmc = host->mmc;
1679 msm_host->pdev = pdev;
1681 ret = mmc_of_parse(host->mmc);
1686 * Based on the compatible string, load the required msm host info from
1687 * the data associated with the version info.
1689 var_info = of_device_get_match_data(&pdev->dev);
1691 msm_host->mci_removed = var_info->mci_removed;
1692 msm_host->var_ops = var_info->var_ops;
1693 msm_host->offset = var_info->offset;
1695 msm_offset = msm_host->offset;
1697 sdhci_get_of_property(pdev);
1699 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1701 /* Setup SDCC bus voter clock. */
1702 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1703 if (!IS_ERR(msm_host->bus_clk)) {
1704 /* Vote for max. clk rate for max. performance */
1705 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1708 ret = clk_prepare_enable(msm_host->bus_clk);
1713 /* Setup main peripheral bus clock */
1714 clk = devm_clk_get(&pdev->dev, "iface");
1717 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1718 goto bus_clk_disable;
1720 msm_host->bulk_clks[1].clk = clk;
1722 /* Setup SDC MMC clock */
1723 clk = devm_clk_get(&pdev->dev, "core");
1726 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1727 goto bus_clk_disable;
1729 msm_host->bulk_clks[0].clk = clk;
1731 /* Vote for maximum clock rate for maximum performance */
1732 ret = clk_set_rate(clk, INT_MAX);
1734 dev_warn(&pdev->dev, "core clock boost failed\n");
1736 clk = devm_clk_get(&pdev->dev, "cal");
1739 msm_host->bulk_clks[2].clk = clk;
1741 clk = devm_clk_get(&pdev->dev, "sleep");
1744 msm_host->bulk_clks[3].clk = clk;
1746 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1747 msm_host->bulk_clks);
1749 goto bus_clk_disable;
1752 * xo clock is needed for FLL feature of cm_dll.
1753 * In case if xo clock is not mentioned in DT, warn and proceed.
1755 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1756 if (IS_ERR(msm_host->xo_clk)) {
1757 ret = PTR_ERR(msm_host->xo_clk);
1758 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1761 if (!msm_host->mci_removed) {
1762 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1763 msm_host->core_mem = devm_ioremap_resource(&pdev->dev,
1766 if (IS_ERR(msm_host->core_mem)) {
1767 ret = PTR_ERR(msm_host->core_mem);
1772 /* Reset the vendor spec register to power on reset state */
1773 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1774 host->ioaddr + msm_offset->core_vendor_spec);
1776 if (!msm_host->mci_removed) {
1777 /* Set HC_MODE_EN bit in HC_MODE register */
1778 msm_host_writel(msm_host, HC_MODE_EN, host,
1779 msm_offset->core_hc_mode);
1780 config = msm_host_readl(msm_host, host,
1781 msm_offset->core_hc_mode);
1782 config |= FF_CLK_SW_RST_DIS;
1783 msm_host_writel(msm_host, config, host,
1784 msm_offset->core_hc_mode);
1787 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1788 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1789 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1790 SDHCI_VENDOR_VER_SHIFT));
1792 core_version = msm_host_readl(msm_host, host,
1793 msm_offset->core_mci_version);
1794 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1795 CORE_VERSION_MAJOR_SHIFT;
1796 core_minor = core_version & CORE_VERSION_MINOR_MASK;
1797 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1798 core_version, core_major, core_minor);
1800 if (core_major == 1 && core_minor >= 0x42)
1801 msm_host->use_14lpp_dll_reset = true;
1804 * SDCC 5 controller with major version 1, minor version 0x34 and later
1805 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1807 if (core_major == 1 && core_minor < 0x34)
1808 msm_host->use_cdclp533 = true;
1811 * Support for some capabilities is not advertised by newer
1812 * controller versions and must be explicitly enabled.
1814 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1815 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1816 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1817 writel_relaxed(config, host->ioaddr +
1818 msm_offset->core_vendor_spec_capabilities0);
1822 * Power on reset state may trigger power irq if previous status of
1823 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1824 * interrupt in GIC, any pending power irq interrupt should be
1825 * acknowledged. Otherwise power irq interrupt handler would be
1826 * fired prematurely.
1828 sdhci_msm_handle_pwr_irq(host, 0);
1831 * Ensure that above writes are propogated before interrupt enablement
1836 /* Setup IRQ for handling power/voltage tasks with PMIC */
1837 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1838 if (msm_host->pwr_irq < 0) {
1839 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1841 ret = msm_host->pwr_irq;
1845 sdhci_msm_init_pwr_irq_wait(msm_host);
1846 /* Enable pwr irq interrupts */
1847 msm_host_writel(msm_host, INT_MASK, host,
1848 msm_offset->core_pwrctl_mask);
1850 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1851 sdhci_msm_pwr_irq, IRQF_ONESHOT,
1852 dev_name(&pdev->dev), host);
1854 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1858 pm_runtime_get_noresume(&pdev->dev);
1859 pm_runtime_set_active(&pdev->dev);
1860 pm_runtime_enable(&pdev->dev);
1861 pm_runtime_set_autosuspend_delay(&pdev->dev,
1862 MSM_MMC_AUTOSUSPEND_DELAY_MS);
1863 pm_runtime_use_autosuspend(&pdev->dev);
1865 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1866 ret = sdhci_add_host(host);
1868 goto pm_runtime_disable;
1869 sdhci_msm_set_regulator_caps(msm_host);
1871 pm_runtime_mark_last_busy(&pdev->dev);
1872 pm_runtime_put_autosuspend(&pdev->dev);
1877 pm_runtime_disable(&pdev->dev);
1878 pm_runtime_set_suspended(&pdev->dev);
1879 pm_runtime_put_noidle(&pdev->dev);
1881 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1882 msm_host->bulk_clks);
1884 if (!IS_ERR(msm_host->bus_clk))
1885 clk_disable_unprepare(msm_host->bus_clk);
1887 sdhci_pltfm_free(pdev);
1891 static int sdhci_msm_remove(struct platform_device *pdev)
1893 struct sdhci_host *host = platform_get_drvdata(pdev);
1894 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1895 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1896 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1899 sdhci_remove_host(host, dead);
1901 pm_runtime_get_sync(&pdev->dev);
1902 pm_runtime_disable(&pdev->dev);
1903 pm_runtime_put_noidle(&pdev->dev);
1905 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1906 msm_host->bulk_clks);
1907 if (!IS_ERR(msm_host->bus_clk))
1908 clk_disable_unprepare(msm_host->bus_clk);
1909 sdhci_pltfm_free(pdev);
1914 static int sdhci_msm_runtime_suspend(struct device *dev)
1916 struct sdhci_host *host = dev_get_drvdata(dev);
1917 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1918 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1920 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1921 msm_host->bulk_clks);
1926 static int sdhci_msm_runtime_resume(struct device *dev)
1928 struct sdhci_host *host = dev_get_drvdata(dev);
1929 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1930 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1932 return clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1933 msm_host->bulk_clks);
1937 static const struct dev_pm_ops sdhci_msm_pm_ops = {
1938 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1939 pm_runtime_force_resume)
1940 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1941 sdhci_msm_runtime_resume,
1945 static struct platform_driver sdhci_msm_driver = {
1946 .probe = sdhci_msm_probe,
1947 .remove = sdhci_msm_remove,
1949 .name = "sdhci_msm",
1950 .of_match_table = sdhci_msm_dt_match,
1951 .pm = &sdhci_msm_pm_ops,
1955 module_platform_driver(sdhci_msm_driver);
1957 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1958 MODULE_LICENSE("GPL v2");